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author | Daniel Berlin <dberlin@dberlin.org> | 2007-09-11 22:58:27 +0000 |
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committer | Daniel Berlin <dberlin@dberlin.org> | 2007-09-11 22:58:27 +0000 |
commit | a3bba5ce20afba15722f806a8d17709ef13f698a (patch) | |
tree | ab97c706488b69a6ca300cedb361ba6bd06996cc | |
parent | Sometimes a MI can define a register as well as defining a super-register at the (diff) | |
download | llvm-project-a3bba5ce20afba15722f806a8d17709ef13f698a.tar.gz llvm-project-a3bba5ce20afba15722f806a8d17709ef13f698a.tar.bz2 llvm-project-a3bba5ce20afba15722f806a8d17709ef13f698a.zip |
Move dump out of class, use "\n" instead of endl
llvm-svn: 41872
-rw-r--r-- | llvm/include/llvm/ADT/SparseBitVector.h | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/llvm/include/llvm/ADT/SparseBitVector.h b/llvm/include/llvm/ADT/SparseBitVector.h index 3a2fb1f234f7..cfa57f408f47 100644 --- a/llvm/include/llvm/ADT/SparseBitVector.h +++ b/llvm/include/llvm/ADT/SparseBitVector.h @@ -796,16 +796,6 @@ public: return iterator(this, ~0); } - // Dump our bits to stderr - void dump(llvm::OStream &out) const { - out << "[ "; - for (iterator bi = begin(); - bi != end(); - ++bi) { - out << *bi << " "; - } - out << std::endl; - } }; // Convenience functions to allow Or and And without dereferencing in the user @@ -834,6 +824,19 @@ inline bool operator &=(SparseBitVector<ElementSize> &LHS, const SparseBitVector<ElementSize> *RHS) { return LHS &= (*RHS); } + + +// Dump a SparseBitVector to a stream +template <unsigned ElementSize> +void dump(const SparseBitVector<ElementSize> &LHS, llvm::OStream &out) { + out << "[ "; + + typename SparseBitVector<ElementSize>::iterator bi; + for (bi = LHS.begin(); bi != LHS.end(); ++bi) { + out << *bi << " "; + } + out << "\n"; +} } |