[Hexagon] Round 3 of selection pattern simplifications

Remove unnecessary C++ functions for SDNode transforms. Move more
pat frags to files where they are used.

llvm-svn: 286077

1 files changed, 0 insertions, 47 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonOperands.td b/llvm/lib/Target/Hexagon/HexagonOperands.td
index 559a488e110d..80af52c603ba 100644
--- a/llvm/lib/Target/Hexagon/HexagonOperands.td
+++ b/llvm/lib/Target/Hexagon/HexagonOperands.td
@@ -196,12 +196,6 @@ def u8_0ImmPred  : PatLeaf<(i32 imm), [{
   return isUInt<8>(v);
 }]>;
 
-def u7_0StrictPosImmPred : ImmLeaf<i32, [{
-  // u7_0StrictPosImmPred predicate - True if the immediate fits in an 7-bit
-  // unsigned field and is strictly greater than 0.
-  return isUInt<7>(Imm) && Imm > 0;
-}]>;
-
 def u6_0ImmPred  : PatLeaf<(i32 imm), [{
   int64_t v = (int64_t)N->getSExtValue();
   return isUInt<6>(v);
@@ -237,28 +231,6 @@ def u2_0ImmPred  : PatLeaf<(i32 imm), [{
   return isUInt<2>(v);
 }]>;
 
-def m5_0ImmPred  : PatLeaf<(i32 imm), [{
-  // m5_0ImmPred predicate - True if the number is in range -1 .. -31
-  // and will fit in a 5 bit field when made positive, for use in memops.
-  int64_t v = (int64_t)N->getSExtValue();
-  return (-31 <= v && v <= -1);
-}]>;
-
-//InN means negative integers in [-(2^N - 1), 0]
-def n8_0ImmPred  : PatLeaf<(i32 imm), [{
-  // n8_0ImmPred predicate - True if the immediate fits in a 8-bit signed
-  // field.
-  int64_t v = (int64_t)N->getSExtValue();
-  return (-255 <= v && v <= 0);
-}]>;
-
-def nOneImmPred  : PatLeaf<(i32 imm), [{
-  // nOneImmPred predicate - True if the immediate is -1.
-  int64_t v = (int64_t)N->getSExtValue();
-  return (-1 == v);
-}]>;
-
-
 // Extendable immediate operands.
 def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; }
 def s16_0ExtOperand : AsmOperandClass { let Name = "s16_0Ext"; }
@@ -320,25 +292,6 @@ let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand",
 }
 
 
-def s4_7ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  if (HST->hasV60TOps())
-    // Return true if the immediate can fit in a 10-bit sign extended field and
-    // is 128-byte aligned.
-    return isShiftedInt<4,7>(v);
-  return false;
-}]>;
-
-def s4_6ImmPred  : PatLeaf<(i32 imm), [{
-  int64_t v = (int64_t)N->getSExtValue();
-  if (HST->hasV60TOps())
-    // Return true if the immediate can fit in a 10-bit sign extended field and
-    // is 64-byte aligned.
-    return isShiftedInt<4,6>(v);
-  return false;
-}]>;
-
-
 // This complex pattern exists only to create a machine instruction operand
 // of type "frame index". There doesn't seem to be a way to do that directly
 // in the patterns.