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author | Tim Northover <tnorthover@apple.com> | 2014-05-24 12:50:23 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-05-24 12:50:23 +0000 |
commit | 3b0846e8f76899815159389be96d7184ad015a8a (patch) | |
tree | 3ff48b9a41b3bf5d19039bc8e0a2907b13fc4047 /llvm/test/CodeGen/AArch64/arm64-unaligned_ldst.ll | |
parent | AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. (diff) | |
download | llvm-project-3b0846e8f76899815159389be96d7184ad015a8a.tar.gz llvm-project-3b0846e8f76899815159389be96d7184ad015a8a.tar.bz2 llvm-project-3b0846e8f76899815159389be96d7184ad015a8a.zip |
AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.
"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.
This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.
llvm-svn: 209577
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-unaligned_ldst.ll')
-rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-unaligned_ldst.ll | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-unaligned_ldst.ll b/llvm/test/CodeGen/AArch64/arm64-unaligned_ldst.ll new file mode 100644 index 000000000000..20b80c09f72f --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-unaligned_ldst.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -march=arm64 | FileCheck %s +; rdar://r11231896 + +define void @t1(i8* nocapture %a, i8* nocapture %b) nounwind { +entry: +; CHECK-LABEL: t1: +; CHECK-NOT: orr +; CHECK: ldr [[X0:x[0-9]+]], [x1] +; CHECK: str [[X0]], [x0] + %tmp1 = bitcast i8* %b to i64* + %tmp2 = bitcast i8* %a to i64* + %tmp3 = load i64* %tmp1, align 1 + store i64 %tmp3, i64* %tmp2, align 1 + ret void +} + +define void @t2(i8* nocapture %a, i8* nocapture %b) nounwind { +entry: +; CHECK-LABEL: t2: +; CHECK-NOT: orr +; CHECK: ldr [[W0:w[0-9]+]], [x1] +; CHECK: str [[W0]], [x0] + %tmp1 = bitcast i8* %b to i32* + %tmp2 = bitcast i8* %a to i32* + %tmp3 = load i32* %tmp1, align 1 + store i32 %tmp3, i32* %tmp2, align 1 + ret void +} + +define void @t3(i8* nocapture %a, i8* nocapture %b) nounwind { +entry: +; CHECK-LABEL: t3: +; CHECK-NOT: orr +; CHECK: ldrh [[W0:w[0-9]+]], [x1] +; CHECK: strh [[W0]], [x0] + %tmp1 = bitcast i8* %b to i16* + %tmp2 = bitcast i8* %a to i16* + %tmp3 = load i16* %tmp1, align 1 + store i16 %tmp3, i16* %tmp2, align 1 + ret void +} |