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| author |   Jessica Paquette <jpaquette@apple.com> | 2018-12-21 17:05:26 +0000 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2018-12-21 17:05:26 +0000 |
| commit | 453ab1db5bb6ddee7d42d8d52c7455b6f5eba325 (patch) | |
| tree | 64f2dbbe5718b0766f9b31c9dd951ca16bc0f9a0 /llvm/test/CodeGen/AArch64/f16-instructions.ll | |
| parent | Don't duplicate the logic that detects if a section can/should be loaded (NFC) (diff) | |
| download | llvm-project-453ab1db5bb6ddee7d42d8d52c7455b6f5eba325.tar.gz llvm-project-453ab1db5bb6ddee7d42d8d52c7455b6f5eba325.tar.bz2 llvm-project-453ab1db5bb6ddee7d42d8d52c7455b6f5eba325.zip | |
[GlobalISel][AArch64] Add support for widening G_FCEIL
This adds support for widening G_FCEIL in LegalizerHelper and
AArch64LegalizerInfo. More specifically, it teaches the AArch64 legalizer to
widen G_FCEIL from a 16-bit float to a 32-bit float when the subtarget doesn't
support full FP 16.
This also updates AArch64/f16-instructions.ll to show that we perform the
correct transformation.
llvm-svn: 349927
Diffstat (limited to 'llvm/test/CodeGen/AArch64/f16-instructions.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/f16-instructions.ll | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll index 352a27539032..13e518a865f2 100644 --- a/llvm/test/CodeGen/AArch64/f16-instructions.ll +++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll @@ -1,6 +1,17 @@ ; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -disable-fp-elim | FileCheck %s --check-prefix=CHECK-CVT --check-prefix=CHECK-COMMON ; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -disable-fp-elim | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-FP16 +; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple \ +; RUN: -asm-verbose=false -disable-post-ra -disable-fp-elim -global-isel \ +; RUN: -global-isel-abort=2 -pass-remarks-missed=gisel-* 2>&1 | FileCheck %s \ +; RUN: --check-prefixes=FALLBACK,GISEL-CVT + +; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 \ +; RUN: -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra \ +; RUN: -disable-fp-elim -global-isel -global-isel-abort=2 \ +; RUN: -pass-remarks-missed=gisel-* 2>&1 | FileCheck %s \ +; RUN: --check-prefixes=FALLBACK-FP16,GISEL-FP16 + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" ; CHECK-CVT-LABEL: test_fadd: @@ -1071,6 +1082,18 @@ define half @test_floor(half %a) #0 { ; CHECK-FP16-NEXT: frintp h0, h0 ; CHECK-FP16-NEXT: ret +; FALLBACK-NOT: remark:{{.*}}test_ceil +; FALLBACK-FP16-NOT: remark:{{.*}}test_ceil + +; GISEL-CVT-LABEL: test_ceil: +; GISEL-CVT-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0 +; GISEL-CVT-NEXT: frintp [[INT32:s[0-9]+]], [[FLOAT32]] +; GISEL-CVT-NEXT: fcvt h0, [[INT32]] +; GISEL-CVT-NEXT: ret + +; GISEL-FP16-LABEL: test_ceil: +; GISEL-FP16-NEXT: frintp h0, h0 +; GISEL-FP16-NEXT: ret define half @test_ceil(half %a) #0 { %r = call half @llvm.ceil.f16(half %a) ret half %r |