diff options
Diffstat (limited to 'clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c')
| -rw-r--r-- | clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c | 1118 |
1 files changed, 1118 insertions, 0 deletions
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c new file mode 100644 index 000000000000..ae01b1e7f34b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c @@ -0,0 +1,1118 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s + +// ASM-NOT: warning +#include <riscv_vector.h> + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i32(<vscale x 1 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] +// +vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2(vint16mf4_t src, size_t vl) { + return vfwcvt_f_x_v_f32mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16.i32(<vscale x 2 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwcvt_f_x_v_f32m1(vint16mf2_t src, size_t vl) { + return vfwcvt_f_x_v_f32m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16.i32(<vscale x 4 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_x_v_f32m2(vint16m1_t src, size_t vl) { + return vfwcvt_f_x_v_f32m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16.i32(<vscale x 8 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_x_v_f32m4(vint16m2_t src, size_t vl) { + return vfwcvt_f_x_v_f32m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16.i32(<vscale x 16 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_x_v_f32m8(vint16m4_t src, size_t vl) { + return vfwcvt_f_x_v_f32m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16.i32(<vscale x 1 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] +// +vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2(vuint16mf4_t src, size_t vl) { + return vfwcvt_f_xu_v_f32mf2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16.i32(<vscale x 2 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwcvt_f_xu_v_f32m1(vuint16mf2_t src, size_t vl) { + return vfwcvt_f_xu_v_f32m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16.i32(<vscale x 4 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_xu_v_f32m2(vuint16m1_t src, size_t vl) { + return vfwcvt_f_xu_v_f32m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16.i32(<vscale x 8 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_xu_v_f32m4(vuint16m2_t src, size_t vl) { + return vfwcvt_f_xu_v_f32m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16.i32(<vscale x 16 x i16> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_xu_v_f32m8(vuint16m4_t src, size_t vl) { + return vfwcvt_f_xu_v_f32m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_x_f_v_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32.i32(<vscale x 1 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +vint64m1_t test_vfwcvt_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) { + return vfwcvt_x_f_v_i64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_x_f_v_i64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i32(<vscale x 1 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) { + return vfwcvt_rtz_x_f_v_i64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_x_f_v_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32.i32(<vscale x 2 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +vint64m2_t test_vfwcvt_x_f_v_i64m2(vfloat32m1_t src, size_t vl) { + return vfwcvt_x_f_v_i64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_x_f_v_i64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i32(<vscale x 2 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2(vfloat32m1_t src, size_t vl) { + return vfwcvt_rtz_x_f_v_i64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_x_f_v_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32.i32(<vscale x 4 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +vint64m4_t test_vfwcvt_x_f_v_i64m4(vfloat32m2_t src, size_t vl) { + return vfwcvt_x_f_v_i64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_x_f_v_i64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32.i32(<vscale x 4 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4(vfloat32m2_t src, size_t vl) { + return vfwcvt_rtz_x_f_v_i64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_x_f_v_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32.i32(<vscale x 8 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +vint64m8_t test_vfwcvt_x_f_v_i64m8(vfloat32m4_t src, size_t vl) { + return vfwcvt_x_f_v_i64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_x_f_v_i64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32.i32(<vscale x 8 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8(vfloat32m4_t src, size_t vl) { + return vfwcvt_rtz_x_f_v_i64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_xu_f_v_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32.i32(<vscale x 1 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +vuint64m1_t test_vfwcvt_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) { + return vfwcvt_xu_f_v_u64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32.i32(<vscale x 1 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) { + return vfwcvt_rtz_xu_f_v_u64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_xu_f_v_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i32(<vscale x 2 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +vuint64m2_t test_vfwcvt_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) { + return vfwcvt_xu_f_v_u64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32.i32(<vscale x 2 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) { + return vfwcvt_rtz_xu_f_v_u64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_xu_f_v_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i32(<vscale x 4 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +vuint64m4_t test_vfwcvt_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) { + return vfwcvt_xu_f_v_u64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32.i32(<vscale x 4 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) { + return vfwcvt_rtz_xu_f_v_u64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_xu_f_v_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i32(<vscale x 8 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +vuint64m8_t test_vfwcvt_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) { + return vfwcvt_xu_f_v_u64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32.i32(<vscale x 8 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) { + return vfwcvt_rtz_xu_f_v_u64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32.i32(<vscale x 1 x i32> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwcvt_f_x_v_f64m1(vint32mf2_t src, size_t vl) { + return vfwcvt_f_x_v_f64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32.i32(<vscale x 2 x i32> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_x_v_f64m2(vint32m1_t src, size_t vl) { + return vfwcvt_f_x_v_f64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32.i32(<vscale x 4 x i32> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_x_v_f64m4(vint32m2_t src, size_t vl) { + return vfwcvt_f_x_v_f64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32.i32(<vscale x 8 x i32> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_x_v_f64m8(vint32m4_t src, size_t vl) { + return vfwcvt_f_x_v_f64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32.i32(<vscale x 1 x i32> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwcvt_f_xu_v_f64m1(vuint32mf2_t src, size_t vl) { + return vfwcvt_f_xu_v_f64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32.i32(<vscale x 2 x i32> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_xu_v_f64m2(vuint32m1_t src, size_t vl) { + return vfwcvt_f_xu_v_f64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32.i32(<vscale x 4 x i32> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_xu_v_f64m4(vuint32m2_t src, size_t vl) { + return vfwcvt_f_xu_v_f64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32.i32(<vscale x 8 x i32> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_xu_v_f64m8(vuint32m4_t src, size_t vl) { + return vfwcvt_f_xu_v_f64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_f_v_f64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i32(<vscale x 1 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwcvt_f_f_v_f64m1(vfloat32mf2_t src, size_t vl) { + return vfwcvt_f_f_v_f64m1(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_f_v_f64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i32(<vscale x 2 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_f_v_f64m2(vfloat32m1_t src, size_t vl) { + return vfwcvt_f_f_v_f64m2(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_f_v_f64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i32(<vscale x 4 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_f_v_f64m4(vfloat32m2_t src, size_t vl) { + return vfwcvt_f_f_v_f64m4(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_f_v_f64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i32(<vscale x 8 x float> [[SRC:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_f_v_f64m8(vfloat32m4_t src, size_t vl) { + return vfwcvt_f_f_v_f64m8(src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32mf2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16.i32(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] +// +vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2_m(vbool64_t mask, + vfloat32mf2_t maskedoff, + vint16mf4_t src, size_t vl) { + return vfwcvt_f_x_v_f32mf2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16.i32(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwcvt_f_x_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff, + vint16mf2_t src, size_t vl) { + return vfwcvt_f_x_v_f32m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16.i32(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_x_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff, + vint16m1_t src, size_t vl) { + return vfwcvt_f_x_v_f32m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16.i32(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_x_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff, + vint16m2_t src, size_t vl) { + return vfwcvt_f_x_v_f32m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16.i32(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_x_v_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff, + vint16m4_t src, size_t vl) { + return vfwcvt_f_x_v_f32m8_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32mf2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16.i32(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32mf2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] +// +vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2_m(vbool64_t mask, + vfloat32mf2_t maskedoff, + vuint16mf4_t src, size_t vl) { + return vfwcvt_f_xu_v_f32mf2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16.i32(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwcvt_f_xu_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff, + vuint16mf2_t src, size_t vl) { + return vfwcvt_f_xu_v_f32m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16.i32(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_xu_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff, + vuint16m1_t src, size_t vl) { + return vfwcvt_f_xu_v_f32m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16.i32(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_xu_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff, + vuint16m2_t src, size_t vl) { + return vfwcvt_f_xu_v_f32m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f32m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16.i32(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_xu_v_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff, + vuint16m4_t src, size_t vl) { + return vfwcvt_f_xu_v_f32m8_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_x_f_v_i64m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32.i32(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +vint64m1_t test_vfwcvt_x_f_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, + vfloat32mf2_t src, size_t vl) { + return vfwcvt_x_f_v_i64m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_x_f_v_i64m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i64.nxv1f32.i32(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, + vfloat32mf2_t src, size_t vl) { + return vfwcvt_rtz_x_f_v_i64m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_x_f_v_i64m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i32(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +vint64m2_t test_vfwcvt_x_f_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, + vfloat32m1_t src, size_t vl) { + return vfwcvt_x_f_v_i64m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_x_f_v_i64m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i64.nxv2f32.i32(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, + vfloat32m1_t src, size_t vl) { + return vfwcvt_rtz_x_f_v_i64m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_x_f_v_i64m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i32(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +vint64m4_t test_vfwcvt_x_f_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, + vfloat32m2_t src, size_t vl) { + return vfwcvt_x_f_v_i64m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_x_f_v_i64m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i64.nxv4f32.i32(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, + vfloat32m2_t src, size_t vl) { + return vfwcvt_rtz_x_f_v_i64m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_x_f_v_i64m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i32(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +vint64m8_t test_vfwcvt_x_f_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, + vfloat32m4_t src, size_t vl) { + return vfwcvt_x_f_v_i64m8_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_x_f_v_i64m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i64.nxv8f32.i32(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, + vfloat32m4_t src, size_t vl) { + return vfwcvt_rtz_x_f_v_i64m8_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_xu_f_v_u64m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32.i32(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +vuint64m1_t test_vfwcvt_xu_f_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, + vfloat32mf2_t src, size_t vl) { + return vfwcvt_xu_f_v_u64m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f32.i32(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] +// +vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1_m(vbool64_t mask, + vuint64m1_t maskedoff, + vfloat32mf2_t src, size_t vl) { + return vfwcvt_rtz_xu_f_v_u64m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_xu_f_v_u64m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i32(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +vuint64m2_t test_vfwcvt_xu_f_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, + vfloat32m1_t src, size_t vl) { + return vfwcvt_xu_f_v_u64m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f32.i32(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] +// +vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2_m(vbool32_t mask, + vuint64m2_t maskedoff, + vfloat32m1_t src, size_t vl) { + return vfwcvt_rtz_xu_f_v_u64m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_xu_f_v_u64m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i32(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +vuint64m4_t test_vfwcvt_xu_f_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, + vfloat32m2_t src, size_t vl) { + return vfwcvt_xu_f_v_u64m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f32.i32(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] +// +vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4_m(vbool16_t mask, + vuint64m4_t maskedoff, + vfloat32m2_t src, size_t vl) { + return vfwcvt_rtz_xu_f_v_u64m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_xu_f_v_u64m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i32(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +vuint64m8_t test_vfwcvt_xu_f_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, + vfloat32m4_t src, size_t vl) { + return vfwcvt_xu_f_v_u64m8_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f32.i32(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] +// +vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, + vfloat32m4_t src, size_t vl) { + return vfwcvt_rtz_xu_f_v_u64m8_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f64m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32.i32(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwcvt_f_x_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff, + vint32mf2_t src, size_t vl) { + return vfwcvt_f_x_v_f64m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f64m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32.i32(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_x_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff, + vint32m1_t src, size_t vl) { + return vfwcvt_f_x_v_f64m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f64m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32.i32(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_x_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, + vint32m2_t src, size_t vl) { + return vfwcvt_f_x_v_f64m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f64m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32.i32(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_x_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, + vint32m4_t src, size_t vl) { + return vfwcvt_f_x_v_f64m8_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f64m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32.i32(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwcvt_f_xu_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff, + vuint32mf2_t src, size_t vl) { + return vfwcvt_f_xu_v_f64m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f64m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32.i32(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_xu_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff, + vuint32m1_t src, size_t vl) { + return vfwcvt_f_xu_v_f64m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f64m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32.i32(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_xu_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, + vuint32m2_t src, size_t vl) { + return vfwcvt_f_xu_v_f64m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_xu_v_f64m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32.i32(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_xu_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, + vuint32m4_t src, size_t vl) { + return vfwcvt_f_xu_v_f64m8_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_f_v_f64m1_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32.i32(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwcvt_f_f_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff, + vfloat32mf2_t src, size_t vl) { + return vfwcvt_f_f_v_f64m1_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_f_v_f64m2_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32.i32(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m2_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_f_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff, + vfloat32m1_t src, size_t vl) { + return vfwcvt_f_f_v_f64m2_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_f_v_f64m4_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32.i32(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m4_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_f_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, + vfloat32m2_t src, size_t vl) { + return vfwcvt_f_f_v_f64m4_m(mask, maskedoff, src, vl); +} + +// CHECK-RV32-LABEL: @test_vfwcvt_f_f_v_f64m8_m( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32.i32(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m8_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_f_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, + vfloat32m4_t src, size_t vl) { + return vfwcvt_f_f_v_f64m8_m(mask, maskedoff, src, vl); +} |