Get Gentoo!
gentoo.org sites
gentoo.org Wiki Bugs Forums Packages
Planet Archives Sources
Infra Status
aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll45
1 files changed, 15 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
index 604cf9b9abcf..1e83630630c9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
@@ -688,8 +688,7 @@ define <vscale x 1 x i16> @intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT: vwsubu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8(
@@ -733,8 +732,7 @@ define <vscale x 2 x i16> @intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT: vwsubu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8(
@@ -778,8 +776,7 @@ define <vscale x 4 x i16> @intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT: vwsubu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.i8(
@@ -823,8 +820,7 @@ define <vscale x 8 x i16> @intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT: vwsubu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.i8(
@@ -868,8 +864,7 @@ define <vscale x 16 x i16> @intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8(<vscale x
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT: vwsubu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.i8(
@@ -913,8 +908,7 @@ define <vscale x 32 x i16> @intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8(<vscale x
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT: vwsubu.wx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.i8(
@@ -958,8 +952,7 @@ define <vscale x 1 x i32> @intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT: vwsubu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.i16(
@@ -1003,8 +996,7 @@ define <vscale x 2 x i32> @intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT: vwsubu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.i16(
@@ -1048,8 +1040,7 @@ define <vscale x 4 x i32> @intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT: vwsubu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.i16(
@@ -1093,8 +1084,7 @@ define <vscale x 8 x i32> @intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT: vwsubu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.i16(
@@ -1138,8 +1128,7 @@ define <vscale x 16 x i32> @intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT: vwsubu.wx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.i16(
@@ -1183,8 +1172,7 @@ define <vscale x 1 x i64> @intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT: vwsubu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.i32(
@@ -1228,8 +1216,7 @@ define <vscale x 2 x i64> @intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT: vwsubu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.i32(
@@ -1273,8 +1260,7 @@ define <vscale x 4 x i64> @intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT: vwsubu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.i32(
@@ -1318,8 +1304,7 @@ define <vscale x 8 x i64> @intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT: vwsubu.wx v16, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.i32(