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path: root/llvm/lib/Target/PowerPC
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* [PowerPC] Disable relative lookup table converter pass for AIXJinsong Ji2021-04-192-1/+9
* [TargetLowering] move "o" and "X" constraint handling to base classNick Desaulniers2021-04-191-2/+0
* Normalize interaction with boolean attributesSerge Guelton2021-04-171-2/+1
* [PowerPC] Minor improvement for insert_vector_elt codegenNemanja Ivanovic2021-04-162-4/+14
* [PowerPC] Add ROP Protection Instructions for PowerPCStefan Pintilie2021-04-1510-0/+112
* [TTI] NFC: Change getArithmeticInstrCost to return InstructionCostSander de Smalen2021-04-142-13/+10
* [TTI] NFC: Change getVectorInstrCost to return InstructionCostSander de Smalen2021-04-142-7/+9
* [TTI] NFC: Change getShuffleCost to return InstructionCostSander de Smalen2021-04-142-7/+7
* [TTI] NFC: Change getCFInstrCost to return InstructionCostSander de Smalen2021-04-142-4/+5
* [AIX] Allow safe for 32bit P8 VSX pattern matchingZarko Todorovski2021-04-141-4/+28
* [PowerPC] Fix incorrect subreg typo from 0148bf53f0a0Nemanja Ivanovic2021-04-141-1/+1
* [PowerPC] Use correct node to get a super register from a subregNemanja Ivanovic2021-04-131-71/+69
* [TTI] NFC: Change get[Interleaved]MemoryOpCost to return InstructionCostSander de Smalen2021-04-132-15/+15
* [TTI] NFC: Change getCmpSelInstrCost to return InstructionCostSander de Smalen2021-04-132-10/+11
* [TTI] NFC: Change getCastInstrCost and getExtractWithExtendCost to return Ins...Sander de Smalen2021-04-132-19/+25
* [PowerPC] stop reverse mem op generation for some cases.Chen Zheng2021-04-121-0/+11
* [PowerPC] Lower f128 SETCC/SELECT_CC as libcall if p9vector disabledQiu Chaofan2021-04-122-18/+64
* [AMDGPU][CostModel] Refine cost model for control-flow instructions.dfukalov2021-04-102-3/+5
* Revert "[PowerPC] Add ROP Protection Instructions for PowerPC"Mitch Phillips2021-04-0910-112/+0
* Add correct types to the xxsplti32dx pattern.Stefan Pintilie2021-04-091-2/+2
* [PowerPC] Add ROP Protection Instructions for PowerPCStefan Pintilie2021-04-0910-0/+112
* [PowerPC] fixup killed flags for ri + addi to ri transformationChen Zheng2021-04-071-1/+6
* [PowerPC] Fix use check of swap-reductionQiu Chaofan2021-04-071-5/+8
* [PowerPC] Materialize 34-bit constants with pli directlyAmy Kwan2021-04-061-7/+5
* [FastISel] Remove kill trackingNikita Popov2021-04-031-15/+9
* [PowerPC] [MLICM] Enable hoisting of caller preserved registers on AIXShimin Cui2021-03-311-9/+7
* NFC: Change getIntrinsicInstrCost to return InstructionCostSander de Smalen2021-03-312-4/+5
* NFC: Change getUserCost to return InstructionCostSander de Smalen2021-03-312-5/+5
* [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functionsTomas Matheson2021-03-301-1/+1
* [PowerPC] Exploit xxsplti32dx (constant materialization) for scalarsAlbion Fung2021-03-245-12/+66
* [TTI] Return a TypeSize from getRegisterBitWidth.Sander de Smalen2021-03-242-9/+11
* [PowerPC] Add mprivileged optionStefan Pintilie2021-03-243-0/+7
* [PowerPC] Change option to mrop-protectStefan Pintilie2021-03-243-8/+7
* [PowerPC][NFC] Do not enter prefix selection if it cannot do better.Stefan Pintilie2021-03-221-1/+4
* [PowerPC] Enable redundant TOC save removal on AIXQiu Chaofan2021-03-222-24/+29
* [PowerPC][NFC] Do not produce i64 constants in 32-bit modeNemanja Ivanovic2021-03-192-10/+10
* [NFC] [PowerPC] Determine Endianness in PPCTargetMachineAnshil Gandhi2021-03-193-5/+19
* [PowerPC] Fix the check for 16-bit signed field in peepholeNemanja Ivanovic2021-03-191-9/+5
* [TTI] Add a Mask to getShuffleCostDavid Green2021-03-172-3/+4
* Change void getNoop(MCInst &NopInst) to MCInst getNop()Fangrui Song2021-03-152-3/+5
* [PPC] Fix UBSAN warning about out of range shift. NFCI.Simon Pilgrim2021-03-121-1/+1
* [PPC] Fix static analyzer / UBSAN warnings about out of range shifts. NFCI.Simon Pilgrim2021-03-121-3/+3
* [PowerPC] Exploit paddi instruction on Power 10 for constant materializationStefan Pintilie2021-03-111-2/+107
* [PowerPC] Fix multi-use case for swap reductionQiu Chaofan2021-03-111-1/+1
* [PowerPC] Fix infinite loop in peephole CR optimization (PR49509)Nikita Popov2021-03-111-0/+6
* [PowerPC] Implement patterns for PC-Rel zextload/extload byte loadsAmy Kwan2021-03-101-0/+8
* [PowerPC] Reduce symmetrical swaps for lane-insensitive vector opsQiu Chaofan2021-03-101-0/+99
* [P10] [Power PC] Exploiting new load rightmost vector element instructions.Albion Fung2021-03-092-6/+40
* [AIX][TLS] Generate 64-bit general-dynamic access code sequenceLei Huang2021-03-084-6/+34
* [PowerPC] Removing _massv place holderMasoud Ataei2021-03-081-2/+2