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* [AArch64] Combine UADDVs to generate vector addVinay Madhusudan2020-10-151-8/+4
* [AArch64] Add more addv testsVinay Madhusudan2020-10-141-13/+111
* [llvm][mlir] Promote the experimental reduction intrinsics to be first class ...Amara Emerson2020-10-071-12/+12
* [AArch64] Expand some vector of i64 reductions on NEONCameron McInally2020-09-231-0/+1
* Improve reduction intrinsics by overloading result value.Sander de Smalen2019-06-131-12/+12
* Re-commit r302678, fixing PR33053.Amara Emerson2017-05-161-46/+17
* Revert r302678 "[AArch64] Enable use of reduction intrinsics."Hans Wennborg2017-05-151-17/+46
* [AArch64] Enable use of reduction intrinsics.Amara Emerson2017-05-101-46/+17
* [AARCH64] Enable AARCH64 lit tests on windows dev machinesSimon Pilgrim2016-07-191-1/+1
* [AArch64] Implement vector splitting on UADDV.Charlie Turner2015-10-161-0/+45
* Improve ISel using across lane min/max reductionJun Bum Lim2015-09-141-8/+8
* Fix the testcase in r246790Steven Wu2015-09-041-1/+1
* [AArch64] Improve ISel using across lane addition reduction.Chad Rosier2015-09-031-0/+53