| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [clang][llvm] Obsolete Exynos M1 and M2 |   Evandro Menezes | 2019-10-30 | 1 | -2/+2 |
| * | [AArch64] Improve single vector lane unscaled stores | Evandro Menezes | 2018-05-15 | 1 | -53/+74 |
| * | [AArch64] Improve single vector lane stores | Evandro Menezes | 2018-05-14 | 1 | -0/+205 |
| * | [AArch64] Avoid SIMD interleaved store instruction for Exynos. |   Abderrazek Zaafrani | 2017-12-08 | 1 | -0/+107 |
| * | [AARCH64] Enable AARCH64 lit tests on windows dev machines |   Simon Pilgrim | 2016-07-19 | 1 | -1/+1 |
| * | Add a bunch of CHECK missing colons in tests. NFC. |   Ahmed Bougacha | 2015-03-14 | 1 | -24/+25 |
| * | [opaque pointer type] Add textual IR support for explicit type parameter to g... |   David Blaikie | 2015-02-27 | 1 | -20/+20 |
| * | [AArch64] Improve codegen of store lane instructions by avoiding GPR usage. | Ahmed Bougacha | 2015-01-05 | 1 | -4/+104 |
| * | [AArch64] Improve codegen of store lane 0 instructions by directly storing th... | Ahmed Bougacha | 2015-01-05 | 1 | -0/+92 |
| * | AArch64/ARM64: move ARM64 into AArch64's place |   Tim Northover | 2014-05-24 | 1 | -0/+676 |
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