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path: root/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
Commit message (Expand)AuthorAgeFilesLines
* [AArch64] Add some missing Neoverse featuresSjoerd Meijer2021-02-191-0/+4
* [AArch64] Add Cortex CPU subtarget features for instruction fusion.Sjoerd Meijer2021-01-251-0/+6
* [MachineScheduler] Update available queue on the first mop of a new cycleDavid Green2020-06-091-2/+2
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-2/+0
* Adjust MachineScheduler to use ProcResource countsMomchil Velikov2019-05-101-1/+3
* [AArch64, ARM] Add support for Exynos M5Evandro Menezes2019-03-221-0/+1
* [AArch64, ARM] Add support for Samsung Exynos M4Evandro Menezes2018-06-061-0/+1
* [AArch64] Add pipeline model for Exynos M3Evandro Menezes2018-01-301-0/+1
* [AArch64] Add Exynos M2 feature test (NFC)Evandro Menezes2017-08-021-0/+1
* [AArch64] Tie source and destination operands for AESMC/AESIMC. Florian Hahn2017-07-291-83/+47
* [AArch64] Enable FeatureFuseAES for the generic processor model.Florian Hahn2017-06-151-36/+41
* [AArch64] Enable FeatureFuseAES on Cortex-A53.Florian Hahn2017-05-311-0/+1
* [AArch64] Enable FeatureFuseAES on Cortex-A73.Florian Hahn2017-05-311-34/+35
* [AArch64] Make instruction fusion more aggressive. Florian Hahn2017-05-231-74/+71
* [AArch64] Enable FeatureFuseAES on Cortex-A72.Florian Hahn2017-05-151-0/+33
* [AArch64] Add test case for fusion of AES crypto operationsEvandro Menezes2017-02-211-0/+207