diff options
| author |   eisnerd <eisnerd@localhost> | 2009-10-18 09:19:16 +0000 |
|---|---|---|
| committer | eisnerd <eisnerd@localhost> | 2009-10-18 09:19:16 +0000 |
| commit | 8bb5ff1b10dac99dae00e459b26e3f85b4c837a0 (patch) | |
| tree | 295494aae7857b96ac49b263d049ecf5347da6c8 | |
| parent | fix nls doins in headless mode (diff) | |
| download | jokey-8bb5ff1b10dac99dae00e459b26e3f85b4c837a0.tar.gz jokey-8bb5ff1b10dac99dae00e459b26e3f85b4c837a0.tar.bz2 jokey-8bb5ff1b10dac99dae00e459b26e3f85b4c837a0.zip | |
sys-kernel/thinkpad-sources: Bump to 2.6.31, cleaning all older versions, it is a incomplete inbetween release, so please inform me if you miss something. The ~* -r1 version applies some drm-next patches, really experimental, I may get some newer patches if some one like to have them
svn path=/trunk/; revision=736
19 files changed, 88959 insertions, 5016 deletions
diff --git a/sys-kernel/thinkpad-sources/ChangeLog b/sys-kernel/thinkpad-sources/ChangeLog index d97ef38..e527870 100644 --- a/sys-kernel/thinkpad-sources/ChangeLog +++ b/sys-kernel/thinkpad-sources/ChangeLog @@ -2,6 +2,33 @@ # Copyright 1999-2009 Gentoo Foundation; Distributed under the GPL v2 # $Header: $ + 18 Oct 2009; Florian Manschwetus <florianmanschwetus@gmx.de> + -files/2.6.27/colored-printk-2.6.26.patch, + -files/configs/config-for-core-2.6.27, -thinkpad-sources-2.6.27-r2.ebuild, + -files/2.6.27, -files/2.6.28/01-mac80211_2.6.28-rc4-wl_frag+ack_v2.patch, + +files/2.6.31, -files/2.6.28/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch, + +files/2.6.31/mac80211.compat08082009.wl_frag+ack_v1.patch, + +files/2.6.31/linux-phc-0.3.2-2.6.31.patch, + +files/2.6.31/thinkpad-acpi-0.23-20090920-fix1.patch.gz, + -files/2.6.27/01-disk-protect-for-2.6.27.2.patch, + +files/2.6.31/02-ipw2200-inject-for-2.6.27.patch, + -files/2.6.28/02-ipw2200-inject-for-2.6.27.patch, + -thinkpad-sources-2.6.28-r1.ebuild, -files/2.6.28, + -files/configs/config-for-core-2.6.28-r1, + -thinkpad-sources-2.6.28-r2.ebuild, + -files/2.6.28/power-off-unused-ports.patch, +files/2.6.31/drm-next.patch, + -files/2.6.28/colored-printk-2.6.26.patch, + -files/2.6.27/02-ipw2200-inject-for-2.6.27.patch, + +files/2.6.31/colored-printk-2.6.30.patch, + +files/configs/config-for-core-2.6.31, +thinkpad-sources-2.6.31.ebuild, + -files/2.6.27/power-off-unused-ports.patch, + -files/2.6.27/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch, + +thinkpad-sources-2.6.31-r1.ebuild: + Bump to 2.6.31, cleaning all older versions, it is a incomplete inbetween + release, so please inform me if you miss something. The ~* -r1 version + applies some drm-next patches, really experimental, I may get some newer + patches if some one like to have them + 05 Feb 2009; Florian Manschwetus <florianmanschwetus@gmx.de> +thinkpad-sources-2.6.28-r2.ebuild: pumb to 2.6.28-r2 diff --git a/sys-kernel/thinkpad-sources/Manifest b/sys-kernel/thinkpad-sources/Manifest index be15142..3843219 100644 --- a/sys-kernel/thinkpad-sources/Manifest +++ b/sys-kernel/thinkpad-sources/Manifest @@ -1,30 +1,16 @@ -AUX 2.6.27/01-disk-protect-for-2.6.27.2.patch 32538 RMD160 fbe408c71c006dc5f344f20ef1cfa886191ea91c SHA1 e927b4ecb17b74a0a6b0809d3d8facac251f9ee1 SHA256 bc4690bc2fb40fb82765a68d47288134e0fc62770db8b058b4c8eb9ca7d63be6 -AUX 2.6.27/02-ipw2200-inject-for-2.6.27.patch 2376 RMD160 4856f02093faa941a51dafe54d34c27b6c4a21db SHA1 328c8947089c84fb3ce78fe20400ad03f51ac381 SHA256 01b4f715de58660ab779abc0e28398d348fe31344c300bdd9eaeca73c6090cb0 -AUX 2.6.27/colored-printk-2.6.26.patch 11265 RMD160 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thinkpad-sources-2.6.27-r2.ebuild 2764 RMD160 f6de699f826f9aef3c21743ee1f0e8edb877334e SHA1 2d41c152d66ff8ada20c7983e151442119420e0a SHA256 893b3f085fbaf198bbfe8af2ea66c4f8dfd8c3d1b815c8de172a6b3711310f21 -EBUILD thinkpad-sources-2.6.28-r1.ebuild 2775 RMD160 49fef15362cd11abcc9a430507b6bcb663d7810d SHA1 c3f17582050d0f2836bd3ce3b7d34aef64ee5c60 SHA256 2d10cd69b484001db36f33c03272a84e2cc757c5d4f89ffd07c81f0a725bcd22 -EBUILD thinkpad-sources-2.6.28-r2.ebuild 2759 RMD160 c904dfcc600287c3700bfddb7101cc363f6d48d4 SHA1 618b20d45d8533d3a7b57068ed749b37a5ca8cd0 SHA256 d7329515d6e8a0d45c722ab245f5a5ad3ec21b7153ca80f1e53825ff6d3afd51 -MISC ChangeLog 1481 RMD160 7348e30065a1383af4cd3479cb6b5289e1e1c27e SHA1 f14fe6fe0cef252160b5b93612ea485b85d04f98 SHA256 136ff6bd719547ce65c7e5a06c5237a4ac7cf5f871c1685794480d467bebeaa4 +AUX 2.6.31/02-ipw2200-inject-for-2.6.27.patch 2376 RMD160 4856f02093faa941a51dafe54d34c27b6c4a21db SHA1 328c8947089c84fb3ce78fe20400ad03f51ac381 SHA256 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ad111e0117f15d54a514add96a08bb15db6726fb19085e27a9d270e36e458c1d +DIST linux-2.6.31.tar.bz2 61494822 RMD160 c0d88e63740abf0d4f9d82557260a31643f5a01b SHA1 c6e0e6b473ba2b80d164e37cfabf294e783c03d9 SHA256 0acd83f7b85db7ee18c2b0b7505e1ba6fd722c36f49a8870a831c851660e3512 +DIST thinkpad-acpi-0.23-20090920_v2.6.31.patch.gz 15913 RMD160 737d633b36a33a52b71d0380dfb636ece5223454 SHA1 305e5675379685dd738541d79d3a677b14412ba5 SHA256 7288c5708f2a87e8d9711c3332d5958a5b074adf7acbcd0778897aa15b244364 +EBUILD thinkpad-sources-2.6.31-r1.ebuild 2827 RMD160 877e3a92cc781b32d641928d6d8b61e5386e8c6c SHA1 fe7e832f2d092606e2c5c16a86935f66048c9783 SHA256 dca41105b0c1e2010ce2e6c37f5c144b8481ed6f733aff375ee00f3c70543bf4 +EBUILD thinkpad-sources-2.6.31.ebuild 2777 RMD160 01daee397a75c2cd574de7d654d1b049864d86c6 SHA1 a4f4ff243df7429c8359a716b8d35dc9688fa7c9 SHA256 8f53c3578c08bfbaf63d5b218e62d62cdd95beb6d3efcce79399a91f2e3408a9 +MISC ChangeLog 2978 RMD160 1d4107081e039c972c158ca2c0953bb578eef35f SHA1 b65d5072ee152cbc15f41cb5d2659cc2cf7296dd SHA256 185ca0ff22b19b0f5a4a82682884de6bfdd0a8ffd942c6ced5956916560fb8bf MISC metadata.xml 284 RMD160 5062b08f804b7eaf9e1765c0d38b7fc95bc467e4 SHA1 687ba9103e597aad8a7231ff9a470d841f7121df SHA256 6ca83c8927bd3516baac49bc9ea82ddbeeddbe38a5a98b637d6eb1f1d436c84a diff --git a/sys-kernel/thinkpad-sources/files/2.6.27/01-disk-protect-for-2.6.27.2.patch b/sys-kernel/thinkpad-sources/files/2.6.27/01-disk-protect-for-2.6.27.2.patch deleted file mode 100644 index 2be4a67..0000000 --- a/sys-kernel/thinkpad-sources/files/2.6.27/01-disk-protect-for-2.6.27.2.patch +++ /dev/null @@ -1,966 +0,0 @@ ---- - - Documentation/laptops/disk-shock-protection.txt | 149 +++++++++++++++++++++++ - drivers/ata/ahci.c | 1 - drivers/ata/libata-core.c | 1 - drivers/ata/libata-eh.c | 126 +++++++++++++++++++ - drivers/ata/libata-scsi.c | 109 +++++++++++++++++ - drivers/ide/Makefile | 2 - drivers/ide/ide-io.c | 27 ++++ - drivers/ide/ide-iops.c | 28 ++++ - drivers/ide/ide-park.c | 120 +++++++++++++++++++ - drivers/ide/ide-probe.c | 5 + - drivers/ide/ide-taskfile.c | 34 +++++ - drivers/ide/ide.c | 1 - include/linux/ata.h | 9 + - include/linux/ide.h | 12 ++ - include/linux/libata.h | 13 ++ - 15 files changed, 631 insertions(+), 6 deletions(-) - create mode 100644 Documentation/laptops/disk-shock-protection.txt - create mode 100644 drivers/ide/ide-park.c - -diff --git a/Documentation/laptops/disk-shock-protection.txt b/Documentation/laptops/disk-shock-protection.txt -new file mode 100644 -index 0000000..0e6ba26 ---- /dev/null -+++ b/Documentation/laptops/disk-shock-protection.txt -@@ -0,0 +1,149 @@ -+Hard disk shock protection -+========================== -+ -+Author: Elias Oltmanns <eo@nebensachen.de> -+Last modified: 2008-10-03 -+ -+ -+0. Contents -+----------- -+ -+1. Intro -+2. The interface -+3. References -+4. CREDITS -+ -+ -+1. Intro -+-------- -+ -+ATA/ATAPI-7 specifies the IDLE IMMEDIATE command with unload feature. -+Issuing this command should cause the drive to switch to idle mode and -+unload disk heads. This feature is being used in modern laptops in -+conjunction with accelerometers and appropriate software to implement -+a shock protection facility. The idea is to stop all I/O operations on -+the internal hard drive and park its heads on the ramp when critical -+situations are anticipated. The desire to have such a feature -+available on GNU/Linux systems has been the original motivation to -+implement a generic disk head parking interface in the Linux kernel. -+Please note, however, that other components have to be set up on your -+system in order to get disk shock protection working (see -+section 3. References below for pointers to more information about -+that). -+ -+ -+2. The interface -+---------------- -+ -+For each ATA device, the kernel exports the file -+block/*/device/unload_heads in sysfs (here assumed to be mounted under -+/sys). Access to /sys/block/*/device/unload_heads is denied with -+-EOPNOTSUPP if the device does not support the unload feature. -+Otherwise, writing an integer value to this file will take the heads -+of the respective drive off the platter and block all I/O operations -+for the specified number of milliseconds. When the timeout expires and -+no further disk head park request has been issued in the meantime, -+normal operation will be resumed. The maximal value accepted for a -+timeout is 30000 milliseconds. Exceeding this limit will return -+-EOVERFLOW, but heads will be parked anyway and the timeout will be -+set to 30 seconds. However, you can always change a timeout to any -+value between 0 and 30000 by issuing a subsequent head park request -+before the timeout of the previous one has expired. In particular, the -+total timeout can exceed 30 seconds and, more importantly, you can -+cancel a previously set timeout and resume normal operation -+immediately by specifying a timeout of 0. Values below -2 are rejected -+with -EINVAL (see below for the special meaning of -1 and -2). If the -+timeout specified for a recent head park request has not yet expired, -+reading from /sys/block/*/device/unload_heads will report the number -+of milliseconds remaining until normal operation will be resumed; -+otherwise, reading the unload_heads attribute will return 0. -+ -+For example, do the following in order to park the heads of drive -+/dev/sda and stop all I/O operations for five seconds: -+ -+# echo 5000 > /sys/block/sda/device/unload_heads -+ -+A simple -+ -+# cat /sys/block/sda/device/unload_heads -+ -+will show you how many milliseconds are left before normal operation -+will be resumed. -+ -+A word of caution: The fact that the interface operates on a basis of -+milliseconds may raise expectations that cannot be satisfied in -+reality. In fact, the ATA specs clearly state that the time for an -+unload operation to complete is vendor specific. The hint in ATA-7 -+that this will typically be within 500 milliseconds apparently has -+been dropped in ATA-8. -+ -+There is a technical detail of this implementation that may cause some -+confusion and should be discussed here. When a head park request has -+been issued to a device successfully, all I/O operations on the -+controller port this device is attached to will be deferred. That is -+to say, any other device that may be connected to the same port will -+be affected too. The only exception is that a subsequent head unload -+request to that other device will be executed immediately. Further -+operations on that port will be deferred until the timeout specified -+for either device on the port has expired. As far as PATA (old style -+IDE) configurations are concerned, there can only be two devices -+attached to any single port. In SATA world we have port multipliers -+which means that a user-issued head parking request to one device may -+actually result in stopping I/O to a whole bunch of devices. However, -+since this feature is supposed to be used on laptops and does not seem -+to be very useful in any other environment, there will be mostly one -+device per port. Even if the CD/DVD writer happens to be connected to -+the same port as the hard drive, it generally *should* recover just -+fine from the occasional buffer under-run incurred by a head park -+request to the HD. Actually, when you are using an ide driver rather -+than its libata counterpart (i.e. your disk is called /dev/hda -+instead of /dev/sda), then parking the heads of one drive (drive X) -+will generally not affect the mode of operation of another drive -+(drive Y) on the same port as described above. It is only when a port -+reset is required to recover from an exception on drive Y that further -+I/O operations on that drive (and the reset itself) will be delayed -+until drive X is no longer in the parked state. -+ -+Finally, there are some hard drives that only comply with an earlier -+version of the ATA standard than ATA-7, but do support the unload -+feature nonetheless. Unfortunately, there is no safe way Linux can -+detect these devices, so you won't be able to write to the -+unload_heads attribute. If you know that your device really does -+support the unload feature (for instance, because the vendor of your -+laptop or the hard drive itself told you so), then you can tell the -+kernel to enable the usage of this feature for that drive by writing -+the special value -1 to the unload_heads attribute: -+ -+# echo -1 > /sys/block/sda/device/unload_heads -+ -+will enable the feature for /dev/sda, and giving -2 instead of -1 will -+disable it again. -+ -+ -+3. References -+------------- -+ -+There are several laptops from different vendors featuring shock -+protection capabilities. As manufacturers have refused to support open -+source development of the required software components so far, Linux -+support for shock protection varies considerably between different -+hardware implementations. Ideally, this section should contain a list -+of pointers at different projects aiming at an implementation of shock -+protection on different systems. Unfortunately, I only know of a -+single project which, although still considered experimental, is fit -+for use. Please feel free to add projects that have been the victims -+of my ignorance. -+ -+- http://www.thinkwiki.org/wiki/HDAPS -+ See this page for information about Linux support of the hard disk -+ active protection system as implemented in IBM/Lenovo Thinkpads. -+ -+ -+4. CREDITS -+---------- -+ -+This implementation of disk head parking has been inspired by a patch -+originally published by Jon Escombe <lists@dresco.co.uk>. My efforts -+to develop an implementation of this feature that is fit to be merged -+into mainline have been aided by various kernel developers, in -+particular by Tejun Heo and Bartlomiej Zolnierkiewicz. -diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c -index 2e1a7cb..fd813fa 100644 ---- a/drivers/ata/ahci.c -+++ b/drivers/ata/ahci.c -@@ -316,6 +316,7 @@ static struct device_attribute *ahci_shost_attrs[] = { - - static struct device_attribute *ahci_sdev_attrs[] = { - &dev_attr_sw_activity, -+ &dev_attr_unload_heads, - NULL - }; - -diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c -index 79e3a8e..b8102d7 100644 ---- a/drivers/ata/libata-core.c -+++ b/drivers/ata/libata-core.c -@@ -5264,6 +5264,7 @@ struct ata_port *ata_port_alloc(struct ata_host *host) - INIT_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan); - INIT_LIST_HEAD(&ap->eh_done_q); - init_waitqueue_head(&ap->eh_wait_q); -+ init_completion(&ap->park_req_pending); - init_timer_deferrable(&ap->fastdrain_timer); - ap->fastdrain_timer.function = ata_eh_fastdrain_timerfn; - ap->fastdrain_timer.data = (unsigned long)ap; -diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c -index c1db2f2..2efe3ae 100644 ---- a/drivers/ata/libata-eh.c -+++ b/drivers/ata/libata-eh.c -@@ -2446,6 +2446,80 @@ int ata_eh_reset(struct ata_link *link, int classify, - goto retry; - } - -+static inline void ata_eh_pull_park_action(struct ata_port *ap) -+{ -+ struct ata_link *link; -+ struct ata_device *dev; -+ unsigned long flags; -+ -+ /* -+ * This function can be thought of as an extended version of -+ * ata_eh_about_to_do() specially crafted to accommodate the -+ * requirements of ATA_EH_PARK handling. Since the EH thread -+ * does not leave the do {} while () loop in ata_eh_recover as -+ * long as the timeout for a park request to *one* device on -+ * the port has not expired, and since we still want to pick -+ * up park requests to other devices on the same port or -+ * timeout updates for the same device, we have to pull -+ * ATA_EH_PARK actions from eh_info into eh_context.i -+ * ourselves at the beginning of each pass over the loop. -+ * -+ * Additionally, all write accesses to &ap->park_req_pending -+ * through INIT_COMPLETION() (see below) or complete_all() -+ * (see ata_scsi_park_store()) are protected by the host lock. -+ * As a result we have that park_req_pending.done is zero on -+ * exit from this function, i.e. when ATA_EH_PARK actions for -+ * *all* devices on port ap have been pulled into the -+ * respective eh_context structs. If, and only if, -+ * park_req_pending.done is non-zero by the time we reach -+ * wait_for_completion_timeout(), another ATA_EH_PARK action -+ * has been scheduled for at least one of the devices on port -+ * ap and we have to cycle over the do {} while () loop in -+ * ata_eh_recover() again. -+ */ -+ -+ spin_lock_irqsave(ap->lock, flags); -+ INIT_COMPLETION(ap->park_req_pending); -+ ata_port_for_each_link(link, ap) { -+ ata_link_for_each_dev(dev, link) { -+ struct ata_eh_info *ehi = &link->eh_info; -+ -+ link->eh_context.i.dev_action[dev->devno] |= -+ ehi->dev_action[dev->devno] & ATA_EH_PARK; -+ ata_eh_clear_action(link, dev, ehi, ATA_EH_PARK); -+ } -+ } -+ spin_unlock_irqrestore(ap->lock, flags); -+} -+ -+static void ata_eh_park_issue_cmd(struct ata_device *dev, int park) -+{ -+ struct ata_eh_context *ehc = &dev->link->eh_context; -+ struct ata_taskfile tf; -+ unsigned int err_mask; -+ -+ ata_tf_init(dev, &tf); -+ if (park) { -+ ehc->unloaded_mask |= 1 << dev->devno; -+ tf.command = ATA_CMD_IDLEIMMEDIATE; -+ tf.feature = 0x44; -+ tf.lbal = 0x4c; -+ tf.lbam = 0x4e; -+ tf.lbah = 0x55; -+ } else { -+ ehc->unloaded_mask &= ~(1 << dev->devno); -+ tf.command = ATA_CMD_CHK_POWER; -+ } -+ -+ tf.flags |= ATA_TFLAG_DEVICE | ATA_TFLAG_ISADDR; -+ tf.protocol |= ATA_PROT_NODATA; -+ err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0); -+ if (park && (err_mask || tf.lbal != 0xc4)) { -+ ata_dev_printk(dev, KERN_ERR, "head unload failed!\n"); -+ ehc->unloaded_mask &= ~(1 << dev->devno); -+ } -+} -+ - static int ata_eh_revalidate_and_attach(struct ata_link *link, - struct ata_device **r_failed_dev) - { -@@ -2755,7 +2829,7 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset, - struct ata_device *dev; - int nr_failed_devs; - int rc; -- unsigned long flags; -+ unsigned long flags, deadline; - - DPRINTK("ENTER\n"); - -@@ -2829,6 +2903,56 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset, - } - } - -+ do { -+ unsigned long now; -+ -+ /* -+ * clears ATA_EH_PARK in eh_info and resets -+ * ap->park_req_pending -+ */ -+ ata_eh_pull_park_action(ap); -+ -+ deadline = jiffies; -+ ata_port_for_each_link(link, ap) { -+ ata_link_for_each_dev(dev, link) { -+ struct ata_eh_context *ehc = &link->eh_context; -+ unsigned long tmp; -+ -+ if (dev->class != ATA_DEV_ATA) -+ continue; -+ if (!(ehc->i.dev_action[dev->devno] & -+ ATA_EH_PARK)) -+ continue; -+ tmp = dev->unpark_deadline; -+ if (time_before(deadline, tmp)) -+ deadline = tmp; -+ else if (time_before_eq(tmp, jiffies)) -+ continue; -+ if (ehc->unloaded_mask & (1 << dev->devno)) -+ continue; -+ -+ ata_eh_park_issue_cmd(dev, 1); -+ } -+ } -+ -+ now = jiffies; -+ if (time_before_eq(deadline, now)) -+ break; -+ -+ deadline = wait_for_completion_timeout(&ap->park_req_pending, -+ deadline - now); -+ } while (deadline); -+ ata_port_for_each_link(link, ap) { -+ ata_link_for_each_dev(dev, link) { -+ if (!(link->eh_context.unloaded_mask & -+ (1 << dev->devno))) -+ continue; -+ -+ ata_eh_park_issue_cmd(dev, 0); -+ ata_eh_done(link, dev, ATA_EH_PARK); -+ } -+ } -+ - /* the rest */ - ata_port_for_each_link(link, ap) { - struct ata_eh_context *ehc = &link->eh_context; -diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c -index b9d3ba4..e1f916f 100644 ---- a/drivers/ata/libata-scsi.c -+++ b/drivers/ata/libata-scsi.c -@@ -183,6 +183,106 @@ DEVICE_ATTR(link_power_management_policy, S_IRUGO | S_IWUSR, - ata_scsi_lpm_show, ata_scsi_lpm_put); - EXPORT_SYMBOL_GPL(dev_attr_link_power_management_policy); - -+static ssize_t ata_scsi_park_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct scsi_device *sdev = to_scsi_device(device); -+ struct ata_port *ap; -+ struct ata_link *link; -+ struct ata_device *dev; -+ unsigned long flags, now; -+ unsigned int uninitialized_var(msecs); -+ int rc = 0; -+ -+ ap = ata_shost_to_port(sdev->host); -+ -+ spin_lock_irqsave(ap->lock, flags); -+ dev = ata_scsi_find_dev(ap, sdev); -+ if (!dev) { -+ rc = -ENODEV; -+ goto unlock; -+ } -+ if (dev->flags & ATA_DFLAG_NO_UNLOAD) { -+ rc = -EOPNOTSUPP; -+ goto unlock; -+ } -+ -+ link = dev->link; -+ now = jiffies; -+ if (ap->pflags & ATA_PFLAG_EH_IN_PROGRESS && -+ link->eh_context.unloaded_mask & (1 << dev->devno) && -+ time_after(dev->unpark_deadline, now)) -+ msecs = jiffies_to_msecs(dev->unpark_deadline - now); -+ else -+ msecs = 0; -+ -+unlock: -+ spin_unlock_irq(ap->lock); -+ -+ return rc ? rc : snprintf(buf, 20, "%u\n", msecs); -+} -+ -+static ssize_t ata_scsi_park_store(struct device *device, -+ struct device_attribute *attr, -+ const char *buf, size_t len) -+{ -+ struct scsi_device *sdev = to_scsi_device(device); -+ struct ata_port *ap; -+ struct ata_device *dev; -+ long int input; -+ unsigned long flags; -+ int rc; -+ -+ rc = strict_strtol(buf, 10, &input); -+ if (rc || input < -2) -+ return -EINVAL; -+ if (input > ATA_TMOUT_MAX_PARK) { -+ rc = -EOVERFLOW; -+ input = ATA_TMOUT_MAX_PARK; -+ } -+ -+ ap = ata_shost_to_port(sdev->host); -+ -+ spin_lock_irqsave(ap->lock, flags); -+ dev = ata_scsi_find_dev(ap, sdev); -+ if (unlikely(!dev)) { -+ rc = -ENODEV; -+ goto unlock; -+ } -+ if (dev->class != ATA_DEV_ATA) { -+ rc = -EOPNOTSUPP; -+ goto unlock; -+ } -+ -+ if (input >= 0) { -+ if (dev->flags & ATA_DFLAG_NO_UNLOAD) { -+ rc = -EOPNOTSUPP; -+ goto unlock; -+ } -+ -+ dev->unpark_deadline = ata_deadline(jiffies, input); -+ dev->link->eh_info.dev_action[dev->devno] |= ATA_EH_PARK; -+ ata_port_schedule_eh(ap); -+ complete(&ap->park_req_pending); -+ } else { -+ switch (input) { -+ case -1: -+ dev->flags &= ~ATA_DFLAG_NO_UNLOAD; -+ break; -+ case -2: -+ dev->flags |= ATA_DFLAG_NO_UNLOAD; -+ break; -+ } -+ } -+unlock: -+ spin_unlock_irqrestore(ap->lock, flags); -+ -+ return rc ? rc : len; -+} -+DEVICE_ATTR(unload_heads, S_IRUGO | S_IWUSR, -+ ata_scsi_park_show, ata_scsi_park_store); -+EXPORT_SYMBOL_GPL(dev_attr_unload_heads); -+ - static void ata_scsi_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq) - { - cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; -@@ -269,6 +369,12 @@ DEVICE_ATTR(sw_activity, S_IWUGO | S_IRUGO, ata_scsi_activity_show, - ata_scsi_activity_store); - EXPORT_SYMBOL_GPL(dev_attr_sw_activity); - -+struct device_attribute *ata_common_sdev_attrs[] = { -+ &dev_attr_unload_heads, -+ NULL -+}; -+EXPORT_SYMBOL_GPL(ata_common_sdev_attrs); -+ - static void ata_scsi_invalid_field(struct scsi_cmnd *cmd, - void (*done)(struct scsi_cmnd *)) - { -@@ -954,6 +1060,9 @@ static int atapi_drain_needed(struct request *rq) - static int ata_scsi_dev_config(struct scsi_device *sdev, - struct ata_device *dev) - { -+ if (!ata_id_has_unload(dev->id)) -+ dev->flags |= ATA_DFLAG_NO_UNLOAD; -+ - /* configure max sectors */ - blk_queue_max_sectors(sdev->request_queue, dev->max_sectors); - -diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile -index 64e0ecd..564bf9d 100644 ---- a/drivers/ide/Makefile -+++ b/drivers/ide/Makefile -@@ -5,7 +5,7 @@ - EXTRA_CFLAGS += -Idrivers/ide - - ide-core-y += ide.o ide-io.o ide-iops.o ide-lib.o ide-probe.o ide-taskfile.o \ -- ide-pio-blacklist.o -+ ide-park.o ide-pio-blacklist.o - - # core IDE code - ide-core-$(CONFIG_IDE_TIMINGS) += ide-timings.o -diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c -index a896a28..c83e9f0 100644 ---- a/drivers/ide/ide-io.c -+++ b/drivers/ide/ide-io.c -@@ -718,7 +718,31 @@ static ide_startstop_t execute_drive_cmd (ide_drive_t *drive, - - static ide_startstop_t ide_special_rq(ide_drive_t *drive, struct request *rq) - { -- switch (rq->cmd[0]) { -+ u8 cmd = rq->cmd[0]; -+ -+ if (cmd == REQ_PARK_HEADS || cmd == REQ_UNPARK_HEADS) { -+ ide_task_t task; -+ struct ide_taskfile *tf = &task.tf; -+ -+ memset(&task, 0, sizeof(task)); -+ if (cmd == REQ_PARK_HEADS) { -+ drive->sleep = *(unsigned long *)rq->special; -+ drive->sleeping = 1; -+ tf->command = WIN_IDLEIMMEDIATE; -+ tf->feature = 0x44; -+ tf->lbal = 0x4c; -+ tf->lbam = 0x4e; -+ tf->lbah = 0x55; -+ } else /* cmd == REQ_UNPARK_HEADS */ -+ tf->command = WIN_CHECKPOWERMODE1; -+ -+ task.tf_flags = IDE_TFLAG_TF | IDE_TFLAG_DEVICE | -+ IDE_TFLAG_CUSTOM_HANDLER; -+ drive->hwif->data_phase = task.data_phase = TASKFILE_NO_DATA; -+ return do_rw_taskfile(drive, &task); -+ } -+ -+ switch (cmd) { - case REQ_DRIVE_RESET: - return ide_do_reset(drive); - default: -@@ -1047,6 +1071,7 @@ static void ide_do_request (ide_hwgroup_t *hwgroup, int masked_irq) - hwgroup->hwif = hwif; - hwgroup->drive = drive; - drive->sleeping = 0; -+ drive->parked = 0; - drive->service_start = jiffies; - - if (blk_queue_plugged(drive->queue)) { -diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c -index 2cbadff..446ec28 100644 ---- a/drivers/ide/ide-iops.c -+++ b/drivers/ide/ide-iops.c -@@ -1108,6 +1108,7 @@ static void ide_disk_pre_reset(ide_drive_t *drive) - drive->special.b.set_geometry = legacy; - drive->special.b.recalibrate = legacy; - drive->mult_count = 0; -+ drive->parked = 0; - if (!drive->keep_settings && !drive->using_dma) - drive->mult_req = 0; - if (drive->mult_req != drive->mult_count) -@@ -1164,12 +1165,13 @@ static void pre_reset(ide_drive_t *drive) - static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi) - { - unsigned int unit; -- unsigned long flags; -+ unsigned long flags, timeout; - ide_hwif_t *hwif; - ide_hwgroup_t *hwgroup; - struct ide_io_ports *io_ports; - const struct ide_tp_ops *tp_ops; - const struct ide_port_ops *port_ops; -+ DEFINE_WAIT(wait); - - spin_lock_irqsave(&ide_lock, flags); - hwif = HWIF(drive); -@@ -1196,6 +1198,30 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi) - return ide_started; - } - -+ /* We must not disturb devices in the parked state. */ -+ do { -+ unsigned long now; -+ -+ prepare_to_wait(&ide_park_wq, &wait, TASK_UNINTERRUPTIBLE); -+ timeout = jiffies; -+ for (unit = 0; unit < MAX_DRIVES; unit++) { -+ ide_drive_t *tdrive = &hwif->drives[unit]; -+ -+ if (tdrive->present && tdrive->parked && -+ time_after(tdrive->sleep, timeout)) -+ timeout = tdrive->sleep; -+ } -+ -+ now = jiffies; -+ if (time_before_eq(timeout, now)) -+ break; -+ -+ spin_unlock_irqrestore(&ide_lock, flags); -+ timeout = schedule_timeout_uninterruptible(timeout - now); -+ spin_lock_irqsave(&ide_lock, flags); -+ } while (timeout); -+ finish_wait(&ide_park_wq, &wait); -+ - /* - * First, reset any device state data we were maintaining - * for any of the drives on this interface. -diff --git a/drivers/ide/ide-park.c b/drivers/ide/ide-park.c -new file mode 100644 -index 0000000..18adda6 ---- /dev/null -+++ b/drivers/ide/ide-park.c -@@ -0,0 +1,120 @@ -+#include <linux/kernel.h> -+#include <linux/ide.h> -+#include <linux/jiffies.h> -+#include <linux/blkdev.h> -+ -+DECLARE_WAIT_QUEUE_HEAD(ide_park_wq); -+ -+static void issue_park_cmd(ide_drive_t *drive, unsigned long timeout) -+{ -+ struct request_queue *q = drive->queue; -+ struct request *rq; -+ int rc; -+ -+ timeout += jiffies; -+ spin_lock_irq(&ide_lock); -+ if (drive->parked) { -+ ide_hwgroup_t *hwgroup = drive->hwif->hwgroup; -+ int reset_timer; -+ -+ reset_timer = time_before(timeout, drive->sleep); -+ drive->sleep = timeout; -+ wake_up_all(&ide_park_wq); -+ if (reset_timer && hwgroup->sleeping && -+ del_timer(&hwgroup->timer)) { -+ hwgroup->sleeping = 0; -+ hwgroup->busy = 0; -+ blk_start_queueing(q); -+ } -+ spin_unlock_irq(&ide_lock); -+ return; -+ } -+ spin_unlock_irq(&ide_lock); -+ -+ rq = blk_get_request(q, READ, __GFP_WAIT); -+ rq->cmd[0] = REQ_PARK_HEADS; -+ rq->cmd_len = 1; -+ rq->cmd_type = REQ_TYPE_SPECIAL; -+ rq->special = &timeout; -+ rc = blk_execute_rq(q, NULL, rq, 1); -+ blk_put_request(rq); -+ if (rc) -+ goto out; -+ -+ /* -+ * Make sure that *some* command is sent to the drive after the -+ * timeout has expired, so power management will be reenabled. -+ */ -+ rq = blk_get_request(q, READ, GFP_NOWAIT); -+ if (unlikely(!rq)) -+ goto out; -+ -+ rq->cmd[0] = REQ_UNPARK_HEADS; -+ rq->cmd_len = 1; -+ rq->cmd_type = REQ_TYPE_SPECIAL; -+ elv_add_request(q, rq, ELEVATOR_INSERT_FRONT, 1); -+ -+out: -+ return; -+} -+ -+ssize_t ide_park_show(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ide_drive_t *drive = to_ide_device(dev); -+ unsigned long now; -+ unsigned int msecs; -+ -+ if (drive->no_unload) -+ return -EOPNOTSUPP; -+ -+ spin_lock_irq(&ide_lock); -+ now = jiffies; -+ if (drive->parked && time_after(drive->sleep, now)) -+ msecs = jiffies_to_msecs(drive->sleep - now); -+ else -+ msecs = 0; -+ spin_unlock_irq(&ide_lock); -+ -+ return snprintf(buf, 20, "%u\n", msecs); -+} -+ -+ssize_t ide_park_store(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t len) -+{ -+#define MAX_PARK_TIMEOUT 30000 -+ ide_drive_t *drive = to_ide_device(dev); -+ long int input; -+ int rc; -+ -+ rc = strict_strtol(buf, 10, &input); -+ if (rc || input < -2) -+ return -EINVAL; -+ if (input > MAX_PARK_TIMEOUT) { -+ input = MAX_PARK_TIMEOUT; -+ rc = -EOVERFLOW; -+ } -+ -+ mutex_lock(&ide_setting_mtx); -+ if (input >= 0) { -+ if (drive->no_unload) -+ rc = -EOPNOTSUPP; -+ else if (input || drive->parked) -+ issue_park_cmd(drive, msecs_to_jiffies(input)); -+ } else { -+ if (drive->media == ide_disk) -+ switch (input) { -+ case -1: -+ drive->no_unload = 0; -+ break; -+ case -2: -+ drive->no_unload = 1; -+ break; -+ } -+ else -+ rc = -EOPNOTSUPP; -+ } -+ mutex_unlock(&ide_setting_mtx); -+ -+ return rc ? rc : len; -+} -diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c -index a51a30e..0df3c91 100644 ---- a/drivers/ide/ide-probe.c -+++ b/drivers/ide/ide-probe.c -@@ -210,6 +210,8 @@ static inline void do_identify (ide_drive_t *drive, u8 cmd) - drive->media = type; - /* an ATAPI device ignores DRDY */ - drive->ready_stat = 0; -+ /* we don't do head unloading on ATAPI devices */ -+ drive->no_unload = 1; - return; - } - -@@ -227,6 +229,9 @@ static inline void do_identify (ide_drive_t *drive, u8 cmd) - - drive->media = ide_disk; - -+ if (!ata_id_has_unload((const u16 *)drive->id)) -+ drive->no_unload = 1; -+ - printk(KERN_CONT "%s DISK drive\n", - (id->config == 0x848a) ? "CFA" : "ATA"); - -diff --git a/drivers/ide/ide-taskfile.c b/drivers/ide/ide-taskfile.c -index 7fb6f1c..255c960 100644 ---- a/drivers/ide/ide-taskfile.c -+++ b/drivers/ide/ide-taskfile.c -@@ -56,6 +56,7 @@ static ide_startstop_t task_no_data_intr(ide_drive_t *); - static ide_startstop_t set_geometry_intr(ide_drive_t *); - static ide_startstop_t recal_intr(ide_drive_t *); - static ide_startstop_t set_multmode_intr(ide_drive_t *); -+static ide_startstop_t park_intr(ide_drive_t *); - static ide_startstop_t pre_task_out_intr(ide_drive_t *, struct request *); - static ide_startstop_t task_in_intr(ide_drive_t *); - -@@ -105,6 +106,8 @@ ide_startstop_t do_rw_taskfile (ide_drive_t *drive, ide_task_t *task) - case WIN_SPECIFY: handler = set_geometry_intr; break; - case WIN_RESTORE: handler = recal_intr; break; - case WIN_SETMULT: handler = set_multmode_intr; break; -+ case WIN_IDLEIMMEDIATE: /* fall through */ -+ case WIN_CHECKPOWERMODE1: handler = park_intr; break; - } - } - ide_execute_command(drive, tf->command, handler, -@@ -186,6 +189,37 @@ static ide_startstop_t recal_intr(ide_drive_t *drive) - } - - /* -+ * park_intr() is invoked on completion of a REQ_PARK_HEADS cmd. -+ */ -+static ide_startstop_t park_intr(ide_drive_t *drive) -+{ -+ ide_hwif_t *hwif = drive->hwif; -+ u8 stat; -+ -+ local_irq_enable_in_hardirq(); -+ stat = hwif->tp_ops->read_status(hwif); -+ -+ if (!OK_STAT(stat, READY_STAT, BAD_STAT)) -+ return ide_error(drive, "park_intr", stat); -+ -+ if (hwif->hwgroup->rq->cmd[0] == REQ_PARK_HEADS) { -+ ide_task_t task; -+ -+ task.tf_flags = IDE_TFLAG_TF | IDE_TFLAG_DEVICE; -+ hwif->tp_ops->tf_read(drive, &task); -+ if (task.tf.lbal != 0xc4) { -+ printk(KERN_ERR "%s: head unload failed!\n", -+ drive->name); -+ ide_tf_dump(drive->name, &task.tf); -+ } else -+ drive->parked = 1; -+ } -+ -+ ide_end_drive_cmd(drive, stat, ide_read_error(drive)); -+ return ide_stopped; -+} -+ -+/* - * Handler for commands without a data phase - */ - static ide_startstop_t task_no_data_intr(ide_drive_t *drive) -diff --git a/drivers/ide/ide.c b/drivers/ide/ide.c -index 7724516..9416ffb 100644 ---- a/drivers/ide/ide.c -+++ b/drivers/ide/ide.c -@@ -734,6 +734,7 @@ static struct device_attribute ide_dev_attrs[] = { - __ATTR_RO(model), - __ATTR_RO(firmware), - __ATTR(serial, 0400, serial_show, NULL), -+ __ATTR(unload_heads, 0644, ide_park_show, ide_park_store), - __ATTR_NULL - }; - -diff --git a/include/linux/ata.h b/include/linux/ata.h -index 8a12d71..a26ebd2 100644 ---- a/include/linux/ata.h -+++ b/include/linux/ata.h -@@ -667,6 +667,15 @@ static inline int ata_id_has_dword_io(const u16 *id) - return 0; - } - -+static inline int ata_id_has_unload(const u16 *id) -+{ -+ if (ata_id_major_version(id) >= 7 && -+ (id[ATA_ID_CFSSE] & 0xC000) == 0x4000 && -+ id[ATA_ID_CFSSE] & (1 << 13)) -+ return 1; -+ return 0; -+} -+ - static inline int ata_id_current_chs_valid(const u16 *id) - { - /* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command -diff --git a/include/linux/ide.h b/include/linux/ide.h -index 6514db8..03b6dea 100644 ---- a/include/linux/ide.h -+++ b/include/linux/ide.h -@@ -143,6 +143,8 @@ struct ide_io_ports { - * Values should be in the range of 0x20 to 0x3f. - */ - #define REQ_DRIVE_RESET 0x20 -+#define REQ_PARK_HEADS 0x22 -+#define REQ_UNPARK_HEADS 0x23 - - /* - * Check for an interrupt and acknowledge the interrupt status -@@ -423,6 +425,8 @@ struct ide_drive_s { - unsigned sleeping : 1; /* 1=sleeping & sleep field valid */ - unsigned post_reset : 1; - unsigned udma33_warned : 1; -+ unsigned no_unload : 1; /* no support for unload feature */ -+ unsigned parked : 1; /* device parked, heads unloaded */ - - u8 addressing; /* 0=28-bit, 1=48-bit, 2=48-bit doing 28-bit */ - u8 quirk_list; /* considered quirky, set for a specific host */ -@@ -1061,6 +1065,7 @@ extern int drive_is_ready(ide_drive_t *); - - void ide_pktcmd_tf_load(ide_drive_t *, u32, u16, u8); - -+ - ide_startstop_t ide_pc_intr(ide_drive_t *drive, struct ide_atapi_pc *pc, - ide_handler_t *handler, unsigned int timeout, ide_expiry_t *expiry, - void (*update_buffers)(ide_drive_t *, struct ide_atapi_pc *), -@@ -1072,6 +1077,13 @@ ide_startstop_t ide_transfer_pc(ide_drive_t *, struct ide_atapi_pc *, - ide_startstop_t ide_issue_pc(ide_drive_t *, struct ide_atapi_pc *, - ide_handler_t *, unsigned int, ide_expiry_t *); - -+/* Disk head parking */ -+extern wait_queue_head_t ide_park_wq; -+ssize_t ide_park_show(struct device *dev, struct device_attribute *attr, -+ char *buf); -+ssize_t ide_park_store(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t len); -+ - ide_startstop_t do_rw_taskfile(ide_drive_t *, ide_task_t *); - - void task_end_request(ide_drive_t *, struct request *, u8); -diff --git a/include/linux/libata.h b/include/linux/libata.h -index 225bfc5..adc16cf 100644 ---- a/include/linux/libata.h -+++ b/include/linux/libata.h -@@ -146,6 +146,7 @@ enum { - ATA_DFLAG_SPUNDOWN = (1 << 14), /* XXX: for spindown_compat */ - ATA_DFLAG_SLEEPING = (1 << 15), /* device is sleeping */ - ATA_DFLAG_DUBIOUS_XFER = (1 << 16), /* data transfer not verified */ -+ ATA_DFLAG_NO_UNLOAD = (1 << 17), /* device doesn't support unload */ - ATA_DFLAG_INIT_MASK = (1 << 24) - 1, - - ATA_DFLAG_DETACH = (1 << 24), -@@ -244,6 +245,7 @@ enum { - ATA_TMOUT_BOOT = 30000, /* heuristic */ - ATA_TMOUT_BOOT_QUICK = 7000, /* heuristic */ - ATA_TMOUT_INTERNAL_QUICK = 5000, -+ ATA_TMOUT_MAX_PARK = 30000, - - /* FIXME: GoVault needs 2s but we can't afford that without - * parallel probing. 800ms is enough for iVDR disk -@@ -319,8 +321,9 @@ enum { - ATA_EH_RESET = ATA_EH_SOFTRESET | ATA_EH_HARDRESET, - ATA_EH_ENABLE_LINK = (1 << 3), - ATA_EH_LPM = (1 << 4), /* link power management action */ -+ ATA_EH_PARK = (1 << 5), /* unload heads and stop I/O */ - -- ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE, -+ ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE | ATA_EH_PARK, - - /* ata_eh_info->flags */ - ATA_EHI_HOTPLUGGED = (1 << 0), /* could have been hotplugged */ -@@ -452,6 +455,7 @@ enum link_pm { - MEDIUM_POWER, - }; - extern struct device_attribute dev_attr_link_power_management_policy; -+extern struct device_attribute dev_attr_unload_heads; - extern struct device_attribute dev_attr_em_message_type; - extern struct device_attribute dev_attr_em_message; - extern struct device_attribute dev_attr_sw_activity; -@@ -564,6 +568,7 @@ struct ata_device { - /* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */ - u64 n_sectors; /* size of device, if ATA */ - unsigned int class; /* ATA_DEV_xxx */ -+ unsigned long unpark_deadline; - - u8 pio_mode; - u8 dma_mode; -@@ -621,6 +626,7 @@ struct ata_eh_context { - [ATA_EH_CMD_TIMEOUT_TABLE_SIZE]; - unsigned int classes[ATA_MAX_DEVICES]; - unsigned int did_probe_mask; -+ unsigned int unloaded_mask; - unsigned int saved_ncq_enabled; - u8 saved_xfer_mode[ATA_MAX_DEVICES]; - /* timestamp for the last reset attempt or success */ -@@ -709,6 +715,7 @@ struct ata_port { - struct list_head eh_done_q; - wait_queue_head_t eh_wait_q; - int eh_tries; -+ struct completion park_req_pending; - - pm_message_t pm_mesg; - int *pm_result; -@@ -1098,6 +1105,7 @@ extern void ata_std_error_handler(struct ata_port *ap); - */ - extern const struct ata_port_operations ata_base_port_ops; - extern const struct ata_port_operations sata_port_ops; -+extern struct device_attribute *ata_common_sdev_attrs[]; - - #define ATA_BASE_SHT(drv_name) \ - .module = THIS_MODULE, \ -@@ -1112,7 +1120,8 @@ extern const struct ata_port_operations sata_port_ops; - .proc_name = drv_name, \ - .slave_configure = ata_scsi_slave_config, \ - .slave_destroy = ata_scsi_slave_destroy, \ -- .bios_param = ata_std_bios_param -+ .bios_param = ata_std_bios_param, \ -+ .sdev_attrs = ata_common_sdev_attrs - - #define ATA_NCQ_SHT(drv_name) \ - ATA_BASE_SHT(drv_name), \ diff --git a/sys-kernel/thinkpad-sources/files/2.6.27/colored-printk-2.6.26.patch b/sys-kernel/thinkpad-sources/files/2.6.27/colored-printk-2.6.26.patch deleted file mode 100644 index dc97636..0000000 --- a/sys-kernel/thinkpad-sources/files/2.6.27/colored-printk-2.6.26.patch +++ /dev/null @@ -1,355 +0,0 @@ -diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c -index 643fd86..837f3c2 100644 ---- a/arch/x86/kernel/early_printk.c -+++ b/arch/x86/kernel/early_printk.c -@@ -15,7 +15,8 @@ - static int max_ypos = 25, max_xpos = 80; - static int current_ypos = 25, current_xpos; - --static void early_vga_write(struct console *con, const char *str, unsigned n) -+static void early_vga_write(struct console *con, const char *str, unsigned n, -+ unsigned int loglevel) - { - char c; - int i, k, j; -@@ -84,7 +85,8 @@ static int early_serial_putc(unsigned char ch) - return timeout ? 0 : -1; - } - --static void early_serial_write(struct console *con, const char *s, unsigned n) -+static void early_serial_write(struct console *con, const char *s, unsigned n, -+ unsigned int loglevel) - { - while (*s && n-- > 0) { - if (*s == '\n') -@@ -180,7 +182,8 @@ static void __init simnow_init(char *str) - simnow_fd = simnow(XOPEN, (unsigned long)fn, O_WRONLY|O_APPEND|O_CREAT, 0644); - } - --static void simnow_write(struct console *con, const char *s, unsigned n) -+static void simnow_write(struct console *con, const char *s, unsigned n, -+ unsigned int loglevel) - { - simnow(XWRITE, simnow_fd, (unsigned long)s, n); - } -@@ -204,7 +207,7 @@ void early_printk(const char *fmt, ...) - - va_start(ap, fmt); - n = vscnprintf(buf, 512, fmt, ap); -- early_console->write(early_console, buf, n); -+ early_console->write(early_console, buf, n, 0); - va_end(ap); - } - -diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig -index 57ba5c2..10556dd 100644 ---- a/drivers/char/Kconfig -+++ b/drivers/char/Kconfig -@@ -71,6 +71,111 @@ config NR_TTY_DEVICES - - If unsure, say 63. - -+menuconfig VT_CKO -+ bool "Colored kernel message output" -+ depends on VT_CONSOLE -+ ---help--- -+ This option enables kernel messages to be emitted in -+ colors other than the default. -+ -+ The color value you need to enter is composed (OR-ed) -+ of a foreground and a background color. -+ -+ Foreground: -+ 0x00 = black, 0x08 = dark gray, -+ 0x01 = red, 0x09 = light red, -+ 0x02 = green, 0x0A = light green, -+ 0x03 = brown, 0x0B = yellow, -+ 0x04 = blue, 0x0C = light blue, -+ 0x05 = magenta, 0x0D = light magenta, -+ 0x06 = cyan, 0x0E = light cyan, -+ 0x07 = gray, 0x0F = white, -+ -+ (Foreground colors 0x08 to 0x0F do not work when a VGA -+ console font with 512 glyphs is used.) -+ -+ Background: -+ 0x00 = black, 0x40 = blue, -+ 0x10 = red, 0x50 = magenta, -+ 0x20 = green, 0x60 = cyan, -+ 0x30 = brown, 0x70 = gray, -+ -+ For example, 0x1F would yield white on red. -+ -+ If unsure, say N. -+ -+config VT_PRINTK_EMERG_COLOR -+ hex "Emergency messages color" -+ range 0x00 0xFF -+ depends on VT_CKO -+ default 0x07 -+ ---help--- -+ This option defines with which color kernel emergency messages will -+ be printed to the console. -+ -+config VT_PRINTK_ALERT_COLOR -+ hex "Alert messages color" -+ range 0x00 0xFF -+ depends on VT_CKO -+ default 0x07 -+ ---help--- -+ This option defines with which color kernel alert messages will -+ be printed to the console. -+ -+config VT_PRINTK_CRIT_COLOR -+ hex "Critical messages color" -+ range 0x00 0xFF -+ depends on VT_CKO -+ default 0x07 -+ ---help--- -+ This option defines with which color kernel critical messages will -+ be printed to the console. -+ -+config VT_PRINTK_ERR_COLOR -+ hex "Error messages color" -+ range 0x00 0xFF -+ depends on VT_CKO -+ default 0x07 -+ ---help--- -+ This option defines with which color kernel error messages will -+ be printed to the console. -+ -+config VT_PRINTK_WARNING_COLOR -+ hex "Warning messages color" -+ range 0x00 0xFF -+ depends on VT_CKO -+ default 0x07 -+ ---help--- -+ This option defines with which color kernel warning messages will -+ be printed to the console. -+ -+config VT_PRINTK_NOTICE_COLOR -+ hex "Notice messages color" -+ range 0x00 0xFF -+ depends on VT_CKO -+ default 0x07 -+ ---help--- -+ This option defines with which color kernel notice messages will -+ be printed to the console. -+ -+config VT_PRINTK_INFO_COLOR -+ hex "Information messages color" -+ range 0x00 0xFF -+ depends on VT_CKO -+ default 0x07 -+ ---help--- -+ This option defines with which color kernel information messages will -+ be printed to the console. -+ -+config VT_PRINTK_DEBUG_COLOR -+ hex "Debug messages color" -+ range 0x00 0xFF -+ depends on VT_CKO -+ default 0x07 -+ ---help--- -+ This option defines with which color kernel debug messages will -+ be printed to the console. -+ - config HW_CONSOLE - bool - depends on VT && !S390 && !UML -diff --git a/drivers/char/vt.c b/drivers/char/vt.c -index 935f1c2..1fee2dc 100644 ---- a/drivers/char/vt.c -+++ b/drivers/char/vt.c -@@ -73,6 +73,7 @@ - */ - - #include <linux/module.h> -+#include <linux/moduleparam.h> - #include <linux/types.h> - #include <linux/sched.h> - #include <linux/tty.h> -@@ -2409,17 +2410,45 @@ struct tty_driver *console_driver; - - #ifdef CONFIG_VT_CONSOLE - -+#ifdef CONFIG_VT_CKO -+static unsigned int printk_color[8] __read_mostly = { -+ CONFIG_VT_PRINTK_EMERG_COLOR, /* KERN_EMERG */ -+ CONFIG_VT_PRINTK_ALERT_COLOR, /* KERN_ALERT */ -+ CONFIG_VT_PRINTK_CRIT_COLOR, /* KERN_CRIT */ -+ CONFIG_VT_PRINTK_ERR_COLOR, /* KERN_ERR */ -+ CONFIG_VT_PRINTK_WARNING_COLOR, /* KERN_WARNING */ -+ CONFIG_VT_PRINTK_NOTICE_COLOR, /* KERN_NOTICE */ -+ CONFIG_VT_PRINTK_INFO_COLOR, /* KERN_INFO */ -+ CONFIG_VT_PRINTK_DEBUG_COLOR, /* KERN_DEBUG */ -+}; -+module_param_array(printk_color, uint, NULL, S_IRUGO | S_IWUSR); -+ -+static inline void vc_set_color(struct vc_data *vc, unsigned char color) -+{ -+ vc->vc_color = color_table[color & 0xF] | -+ (color_table[(color >> 4) & 0x7] << 4) | -+ (color & 0x80); -+ update_attr(vc); -+} -+#else -+static unsigned int printk_color[8]; -+static inline void vc_set_color(const struct vc_data *vc, unsigned char c) -+{ -+} -+#endif -+ - /* - * Console on virtual terminal - * - * The console must be locked when we get here. - */ - --static void vt_console_print(struct console *co, const char *b, unsigned count) -+static void vt_console_print(struct console *co, const char *b, unsigned count, -+ unsigned int loglevel) - { - struct vc_data *vc = vc_cons[fg_console].d; -- unsigned char c; - static DEFINE_SPINLOCK(printing_lock); -+ unsigned char current_color, c; - const ushort *start; - ushort cnt = 0; - ushort myx; -@@ -2452,11 +2481,19 @@ static void vt_console_print(struct console *co, const char *b, unsigned count) - - start = (ushort *)vc->vc_pos; - -+ /* -+ * We always get a valid loglevel - <8> and "no level" is transformed -+ * to <4> in the typical kernel. -+ */ -+ current_color = printk_color[loglevel]; -+ vc_set_color(vc, current_color); -+ - /* Contrived structure to try to emulate original need_wrap behaviour - * Problems caused when we have need_wrap set on '\n' character */ - while (count--) { - c = *b++; - if (c == 10 || c == 13 || c == 8 || vc->vc_need_wrap) { -+ vc_set_color(vc, vc->vc_def_color); - if (cnt > 0) { - if (CON_IS_VISIBLE(vc)) - vc->vc_sw->con_putcs(vc, start, cnt, vc->vc_y, vc->vc_x); -@@ -2469,6 +2506,7 @@ static void vt_console_print(struct console *co, const char *b, unsigned count) - bs(vc); - start = (ushort *)vc->vc_pos; - myx = vc->vc_x; -+ vc_set_color(vc, current_color); - continue; - } - if (c != 13) -@@ -2476,6 +2514,7 @@ static void vt_console_print(struct console *co, const char *b, unsigned count) - cr(vc); - start = (ushort *)vc->vc_pos; - myx = vc->vc_x; -+ vc_set_color(vc, current_color); - if (c == 10 || c == 13) - continue; - } -@@ -2498,6 +2537,7 @@ static void vt_console_print(struct console *co, const char *b, unsigned count) - vc->vc_need_wrap = 1; - } - } -+ vc_set_color(vc, vc->vc_def_color); - set_cursor(vc); - notify_update(vc); - -diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c -index 665341e..4c27de8 100644 ---- a/drivers/net/netconsole.c -+++ b/drivers/net/netconsole.c -@@ -694,7 +694,8 @@ static struct notifier_block netconsole_netdev_notifier = { - .notifier_call = netconsole_netdev_event, - }; - --static void write_msg(struct console *con, const char *msg, unsigned int len) -+static void write_msg(struct console *con, const char *msg, unsigned int len, -+ unsigned int loglevel) - { - int frag, left; - unsigned long flags; -diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c -index 1bc00b7..b4f1b6f 100644 ---- a/drivers/serial/8250.c -+++ b/drivers/serial/8250.c -@@ -2527,7 +2527,8 @@ static void serial8250_console_putchar(struct uart_port *port, int ch) - * The console_lock must be held when we get here. - */ - static void --serial8250_console_write(struct console *co, const char *s, unsigned int count) -+serial8250_console_write(struct console *co, const char *s, unsigned int count, -+ unsigned int loglevel) - { - struct uart_8250_port *up = &serial8250_ports[co->index]; - unsigned long flags; -diff --git a/drivers/serial/8250_early.c b/drivers/serial/8250_early.c -index f279745..2a928bd 100644 ---- a/drivers/serial/8250_early.c -+++ b/drivers/serial/8250_early.c -@@ -83,7 +83,7 @@ static void __init serial_putc(struct uart_port *port, int c) - } - - static void __init early_serial8250_write(struct console *console, -- const char *s, unsigned int count) -+ const char *s, unsigned int count, unsigned int loglevel) - { - struct uart_port *port = &early_device.port; - unsigned int ier; -diff --git a/include/linux/console.h b/include/linux/console.h -index a4f27fb..46fcfd3 100644 ---- a/include/linux/console.h -+++ b/include/linux/console.h -@@ -95,7 +95,7 @@ void give_up_console(const struct consw *sw); - - struct console { - char name[16]; -- void (*write)(struct console *, const char *, unsigned); -+ void (*write)(struct console *, const char *, unsigned, unsigned int); - int (*read)(struct console *, char *, unsigned); - struct tty_driver *(*device)(struct console *, int *); - void (*unblank)(void); -diff --git a/kernel/printk.c b/kernel/printk.c -index 6e920ce..a1aaa3f 100644 ---- a/kernel/printk.c -+++ b/kernel/printk.c -@@ -444,7 +444,8 @@ asmlinkage long sys_syslog(int type, char __user *buf, int len) - /* - * Call the console drivers on a range of log_buf - */ --static void __call_console_drivers(unsigned start, unsigned end) -+static void __call_console_drivers(unsigned start, unsigned end, -+ unsigned int loglevel) - { - struct console *con; - -@@ -452,7 +453,7 @@ static void __call_console_drivers(unsigned start, unsigned end) - if ((con->flags & CON_ENABLED) && con->write && - (cpu_online(smp_processor_id()) || - (con->flags & CON_ANYTIME))) -- con->write(con, &LOG_BUF(start), end - start); -+ con->write(con, &LOG_BUF(start), end - start, loglevel); - } - } - -@@ -479,10 +480,11 @@ static void _call_console_drivers(unsigned start, - if ((start & LOG_BUF_MASK) > (end & LOG_BUF_MASK)) { - /* wrapped write */ - __call_console_drivers(start & LOG_BUF_MASK, -- log_buf_len); -- __call_console_drivers(0, end & LOG_BUF_MASK); -+ log_buf_len, msg_log_level); -+ __call_console_drivers(0, end & LOG_BUF_MASK, -+ msg_log_level); - } else { -- __call_console_drivers(start, end); -+ __call_console_drivers(start, end, msg_log_level); - } - } - } diff --git a/sys-kernel/thinkpad-sources/files/2.6.27/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch b/sys-kernel/thinkpad-sources/files/2.6.27/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch deleted file mode 100644 index 4a4db8b..0000000 --- a/sys-kernel/thinkpad-sources/files/2.6.27/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch +++ /dev/null @@ -1,554 +0,0 @@ -diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c linux-source-2.6.26-rc9-custom8/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c ---- linux-source-2.6.26-rc9_orig/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c 2008-07-09 16:59:37.000000000 +0200 -+++ linux-source-2.6.26-rc9-custom8/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c 2008-07-09 12:41:37.000000000 +0200 -@@ -23,10 +23,14 @@ - * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. - * - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - */ - -+/* This file has been patched with Linux PHC: http://phc.athousandnights.de -+ * Patch version: linux-phc-0.3.1-kernel-vanilla-2.6.26.patch -+ */ -+ - #include <linux/kernel.h> - #include <linux/module.h> - #include <linux/init.h> - #include <linux/smp.h> - #include <linux/sched.h> -@@ -56,17 +60,22 @@ - SYSTEM_IO_CAPABLE, - }; - - #define INTEL_MSR_RANGE (0xffff) - #define CPUID_6_ECX_APERFMPERF_CAPABILITY (0x1) -+#define INTEL_MSR_VID_MASK (0x00ff) -+#define INTEL_MSR_FID_MASK (0xff00) -+#define INTEL_MSR_FID_SHIFT (0x8) -+#define PHC_VERSION_STRING "0.3.2:1" - - struct acpi_cpufreq_data { - struct acpi_processor_performance *acpi_data; - struct cpufreq_frequency_table *freq_table; - unsigned int max_freq; - unsigned int resume; - unsigned int cpu_feature; -+ acpi_integer *original_controls; - }; - - static DEFINE_PER_CPU(struct acpi_cpufreq_data *, drv_data); - - /* acpi_perf_data is a pointer to percpu data. */ -@@ -102,17 +111,18 @@ - } - - static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) - { - int i; -+ u32 fid; - struct acpi_processor_performance *perf; - -- msr &= INTEL_MSR_RANGE; -+ fid = msr & INTEL_MSR_FID_MASK; - perf = data->acpi_data; - - for (i=0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { -- if (msr == perf->states[data->freq_table[i].index].status) -+ if (fid == (perf->states[data->freq_table[i].index].status & INTEL_MSR_FID_MASK)) - return data->freq_table[i].frequency; - } - return data->freq_table[0].frequency; - } - -@@ -740,10 +750,12 @@ - if (data) { - cpufreq_frequency_table_put_attr(policy->cpu); - per_cpu(drv_data, policy->cpu) = NULL; - acpi_processor_unregister_performance(data->acpi_data, - policy->cpu); -+ if (data->original_controls) -+ kfree(data->original_controls); - kfree(data); - } - - return 0; - } -@@ -757,12 +769,477 @@ - data->resume = 1; - - return 0; - } - -+ -+ -+ -+/* sysfs interface to change operating points voltages */ -+ -+static unsigned int extract_fid_from_control(unsigned int control) -+{ -+ return ((control & INTEL_MSR_FID_MASK) >> INTEL_MSR_FID_SHIFT); -+} -+ -+static unsigned int extract_vid_from_control(unsigned int control) -+{ -+ return (control & INTEL_MSR_VID_MASK); -+} -+ -+ -+static bool check_cpu_control_capability(struct acpi_cpufreq_data *data) { -+ /* check if the cpu we are running on is capable of setting new control data -+ * -+ */ -+ if (unlikely(data == NULL || -+ data->acpi_data == NULL || -+ data->freq_table == NULL || -+ data->cpu_feature != SYSTEM_INTEL_MSR_CAPABLE)) { -+ return false; -+ } else { -+ return true; -+ }; -+} -+ -+ -+static ssize_t check_origial_table (struct acpi_cpufreq_data *data) -+{ -+ -+ struct acpi_processor_performance *acpi_data; -+ struct cpufreq_frequency_table *freq_table; -+ unsigned int state_index; -+ -+ acpi_data = data->acpi_data; -+ freq_table = data->freq_table; -+ -+ if (data->original_controls == NULL) { -+ // Backup original control values -+ data->original_controls = kcalloc(acpi_data->state_count, -+ sizeof(acpi_integer), GFP_KERNEL); -+ if (data->original_controls == NULL) { -+ printk("failed to allocate memory for original control values\n"); -+ return -ENOMEM; -+ } -+ for (state_index = 0; state_index < acpi_data->state_count; state_index++) { -+ data->original_controls[state_index] = acpi_data->states[state_index].control; -+ } -+ } -+ return 0; -+} -+ -+static ssize_t show_freq_attr_vids(struct cpufreq_policy *policy, char *buf) -+ /* display phc's voltage id's -+ * -+ */ -+{ -+ struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu); -+ struct acpi_processor_performance *acpi_data; -+ struct cpufreq_frequency_table *freq_table; -+ unsigned int i; -+ unsigned int vid; -+ ssize_t count = 0; -+ -+ if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls -+ -+ acpi_data = data->acpi_data; -+ freq_table = data->freq_table; -+ -+ for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { -+ vid = extract_vid_from_control(acpi_data->states[freq_table[i].index].control); -+ count += sprintf(&buf[count], "%u ", vid); -+ } -+ count += sprintf(&buf[count], "\n"); -+ -+ return count; -+} -+ -+static ssize_t show_freq_attr_default_vids(struct cpufreq_policy *policy, char *buf) -+ /* display acpi's default voltage id's -+ * -+ */ -+{ -+ struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu); -+ struct cpufreq_frequency_table *freq_table; -+ unsigned int i; -+ unsigned int vid; -+ ssize_t count = 0; -+ ssize_t retval; -+ -+ if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls -+ -+ retval = check_origial_table(data); -+ if (0 != retval) -+ return retval; -+ -+ freq_table = data->freq_table; -+ -+ for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { -+ vid = extract_vid_from_control(data->original_controls[freq_table[i].index]); -+ count += sprintf(&buf[count], "%u ", vid); -+ } -+ count += sprintf(&buf[count], "\n"); -+ -+ return count; -+} -+ -+static ssize_t show_freq_attr_fids(struct cpufreq_policy *policy, char *buf) -+ /* display phc's frequeny id's -+ * -+ */ -+{ -+ struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu); -+ struct acpi_processor_performance *acpi_data; -+ struct cpufreq_frequency_table *freq_table; -+ unsigned int i; -+ unsigned int fid; -+ ssize_t count = 0; -+ -+ if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls -+ -+ acpi_data = data->acpi_data; -+ freq_table = data->freq_table; -+ -+ for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { -+ fid = extract_fid_from_control(acpi_data->states[freq_table[i].index].control); -+ count += sprintf(&buf[count], "%u ", fid); -+ } -+ count += sprintf(&buf[count], "\n"); -+ -+ return count; -+} -+ -+static ssize_t show_freq_attr_controls(struct cpufreq_policy *policy, char *buf) -+ /* display phc's controls for the cpu (frequency id's and related voltage id's) -+ * -+ */ -+{ -+ struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu); -+ struct acpi_processor_performance *acpi_data; -+ struct cpufreq_frequency_table *freq_table; -+ unsigned int i; -+ unsigned int fid; -+ unsigned int vid; -+ ssize_t count = 0; -+ -+ if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls -+ -+ acpi_data = data->acpi_data; -+ freq_table = data->freq_table; -+ -+ for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { -+ fid = extract_fid_from_control(acpi_data->states[freq_table[i].index].control); -+ vid = extract_vid_from_control(acpi_data->states[freq_table[i].index].control); -+ count += sprintf(&buf[count], "%u:%u ", fid, vid); -+ } -+ count += sprintf(&buf[count], "\n"); -+ -+ return count; -+} -+ -+static ssize_t show_freq_attr_default_controls(struct cpufreq_policy *policy, char *buf) -+ /* display acpi's default controls for the cpu (frequency id's and related voltage id's) -+ * -+ */ -+{ -+ struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu); -+ struct cpufreq_frequency_table *freq_table; -+ unsigned int i; -+ unsigned int fid; -+ unsigned int vid; -+ ssize_t count = 0; -+ ssize_t retval; -+ -+ if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls -+ -+ retval = check_origial_table(data); -+ if (0 != retval) -+ return retval; -+ -+ freq_table = data->freq_table; -+ -+ for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { -+ fid = extract_fid_from_control(data->original_controls[freq_table[i].index]); -+ vid = extract_vid_from_control(data->original_controls[freq_table[i].index]); -+ count += sprintf(&buf[count], "%u:%u ", fid, vid); -+ } -+ count += sprintf(&buf[count], "\n"); -+ -+ return count; -+} -+ -+ -+static ssize_t store_freq_attr_vids(struct cpufreq_policy *policy, const char *buf, size_t count) -+ /* store the voltage id's for the related frequency -+ * We are going to do some sanity checks here to prevent users -+ * from setting higher voltages than the default one. -+ */ -+{ -+ struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu); -+ struct acpi_processor_performance *acpi_data; -+ struct cpufreq_frequency_table *freq_table; -+ unsigned int freq_index; -+ unsigned int state_index; -+ unsigned int new_vid; -+ unsigned int original_vid; -+ unsigned int new_control; -+ unsigned int original_control; -+ const char *curr_buf = buf; -+ char *next_buf; -+ ssize_t retval; -+ -+ if (!check_cpu_control_capability(data)) return -ENODEV; //check if CPU is capable of changing controls -+ -+ retval = check_origial_table(data); -+ if (0 != retval) -+ return retval; -+ -+ acpi_data = data->acpi_data; -+ freq_table = data->freq_table; -+ -+ /* for each value taken from the sysfs interfalce (phc_vids) get entrys and convert them to unsigned long integers*/ -+ for (freq_index = 0; freq_table[freq_index].frequency != CPUFREQ_TABLE_END; freq_index++) { -+ new_vid = simple_strtoul(curr_buf, &next_buf, 10); -+ if (next_buf == curr_buf) { -+ if ((curr_buf - buf == count - 1) && (*curr_buf == '\n')) { //end of line? -+ curr_buf++; -+ break; -+ } -+ //if we didn't got end of line but there is nothing more to read something went wrong... -+ printk("failed to parse vid value at %i (%s)\n", freq_index, curr_buf); -+ return -EINVAL; -+ } -+ -+ state_index = freq_table[freq_index].index; -+ original_control = data->original_controls[state_index]; -+ original_vid = original_control & INTEL_MSR_VID_MASK; -+ -+ /* before we store the values we do some checks to prevent -+ * users to set up values higher than the default one -+ */ -+ if (new_vid <= original_vid) { -+ new_control = (original_control & ~INTEL_MSR_VID_MASK) | new_vid; -+ dprintk("setting control at %i to %x (default is %x)\n", -+ freq_index, new_control, original_control); -+ acpi_data->states[state_index].control = new_control; -+ -+ } else { -+ printk("skipping vid at %i, %u is greater than default %u\n", -+ freq_index, new_vid, original_vid); -+ } -+ -+ curr_buf = next_buf; -+ /* jump over value seperators (space or comma). -+ * There could be more than one space or comma character -+ * to separate two values so we better do it using a loop. -+ */ -+ while ((curr_buf - buf < count) && ((*curr_buf == ' ') || (*curr_buf == ','))) { -+ curr_buf++; -+ } -+ } -+ -+ /* set new voltage for current frequency */ -+ data->resume = 1; -+ acpi_cpufreq_target(policy, get_cur_freq_on_cpu(policy->cpu), CPUFREQ_RELATION_L); -+ -+ return curr_buf - buf; -+} -+ -+static ssize_t store_freq_attr_controls(struct cpufreq_policy *policy, const char *buf, size_t count) -+ /* store the controls (frequency id's and related voltage id's) -+ * We are going to do some sanity checks here to prevent users -+ * from setting higher voltages than the default one. -+ */ -+{ -+ struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu); -+ struct acpi_processor_performance *acpi_data; -+ struct cpufreq_frequency_table *freq_table; -+ const char *curr_buf; -+ unsigned int op_count; -+ unsigned int state_index; -+ int isok; -+ char *next_buf; -+ ssize_t retval; -+ unsigned int new_vid; -+ unsigned int original_vid; -+ unsigned int new_fid; -+ unsigned int old_fid; -+ unsigned int original_control; -+ unsigned int old_control; -+ unsigned int new_control; -+ int found; -+ -+ if (!check_cpu_control_capability(data)) return -ENODEV; -+ -+ retval = check_origial_table(data); -+ if (0 != retval) -+ return retval; -+ -+ acpi_data = data->acpi_data; -+ freq_table = data->freq_table; -+ -+ op_count = 0; -+ curr_buf = buf; -+ next_buf = NULL; -+ isok = 1; -+ -+ while ( (isok) && (curr_buf != NULL) ) -+ { -+ op_count++; -+ // Parse fid -+ new_fid = simple_strtoul(curr_buf, &next_buf, 10); -+ if ((next_buf != curr_buf) && (next_buf != NULL)) -+ { -+ // Parse separator between frequency and voltage -+ curr_buf = next_buf; -+ next_buf = NULL; -+ if (*curr_buf==':') -+ { -+ curr_buf++; -+ // Parse vid -+ new_vid = simple_strtoul(curr_buf, &next_buf, 10); -+ if ((next_buf != curr_buf) && (next_buf != NULL)) -+ { -+ found = 0; -+ for (state_index = 0; state_index < acpi_data->state_count; state_index++) { -+ old_control = acpi_data->states[state_index].control; -+ old_fid = extract_fid_from_control(old_control); -+ if (new_fid == old_fid) -+ { -+ found = 1; -+ original_control = data->original_controls[state_index]; -+ original_vid = extract_vid_from_control(original_control); -+ if (new_vid <= original_vid) -+ { -+ new_control = (original_control & ~INTEL_MSR_VID_MASK) | new_vid; -+ dprintk("setting control at %i to %x (default is %x)\n", -+ state_index, new_control, original_control); -+ acpi_data->states[state_index].control = new_control; -+ -+ } else { -+ printk("skipping vid at %i, %u is greater than default %u\n", -+ state_index, new_vid, original_vid); -+ } -+ } -+ } -+ -+ if (found == 0) -+ { -+ printk("operating point # %u not found (FID = %u)\n", op_count, new_fid); -+ isok = 0; -+ } -+ -+ // Parse seprator before next operating point, if any -+ curr_buf = next_buf; -+ next_buf = NULL; -+ if ((*curr_buf == ',') || (*curr_buf == ' ')) -+ curr_buf++; -+ else -+ curr_buf = NULL; -+ } -+ else -+ { -+ printk("failed to parse VID of operating point # %u (%s)\n", op_count, curr_buf); -+ isok = 0; -+ } -+ } -+ else -+ { -+ printk("failed to parse operating point # %u (%s)\n", op_count, curr_buf); -+ isok = 0; -+ } -+ } -+ else -+ { -+ printk("failed to parse FID of operating point # %u (%s)\n", op_count, curr_buf); -+ isok = 0; -+ } -+ } -+ -+ if (isok) -+ { -+ retval = count; -+ /* set new voltage at current frequency */ -+ data->resume = 1; -+ acpi_cpufreq_target(policy, get_cur_freq_on_cpu(policy->cpu), CPUFREQ_RELATION_L); -+ } -+ else -+ { -+ retval = -EINVAL; -+ } -+ -+ return retval; -+} -+ -+static ssize_t show_freq_attr_phc_version(struct cpufreq_policy *policy, char *buf) -+ /* print out the phc version string set at the beginning of that file -+ */ -+{ -+ ssize_t count = 0; -+ count += sprintf(&buf[count], "%s\n", PHC_VERSION_STRING); -+ return count; -+} -+ -+ -+ -+static struct freq_attr cpufreq_freq_attr_phc_version = -+{ -+ /*display phc's version string*/ -+ .attr = { .name = "phc_version", .mode = 0444, .owner = THIS_MODULE }, -+ .show = show_freq_attr_phc_version, -+ .store = NULL, -+}; -+ -+static struct freq_attr cpufreq_freq_attr_vids = -+{ -+ /*display phc's voltage id's for the cpu*/ -+ .attr = { .name = "phc_vids", .mode = 0644, .owner = THIS_MODULE }, -+ .show = show_freq_attr_vids, -+ .store = store_freq_attr_vids, -+}; -+ -+static struct freq_attr cpufreq_freq_attr_default_vids = -+{ -+ /*display acpi's default frequency id's for the cpu*/ -+ .attr = { .name = "phc_default_vids", .mode = 0444, .owner = THIS_MODULE }, -+ .show = show_freq_attr_default_vids, -+ .store = NULL, -+}; -+ -+static struct freq_attr cpufreq_freq_attr_fids = -+{ -+ /*display phc's default frequency id's for the cpu*/ -+ .attr = { .name = "phc_fids", .mode = 0444, .owner = THIS_MODULE }, -+ .show = show_freq_attr_fids, -+ .store = NULL, -+}; -+ -+static struct freq_attr cpufreq_freq_attr_controls = -+{ -+ /*display phc's current voltage/frequency controls for the cpu*/ -+ .attr = { .name = "phc_controls", .mode = 0644, .owner = THIS_MODULE }, -+ .show = show_freq_attr_controls, -+ .store = store_freq_attr_controls, -+}; -+ -+static struct freq_attr cpufreq_freq_attr_default_controls = -+{ -+ /*display acpi's default voltage/frequency controls for the cpu*/ -+ .attr = { .name = "phc_default_controls", .mode = 0444, .owner = THIS_MODULE }, -+ .show = show_freq_attr_default_controls, -+ .store = NULL, -+}; -+ -+ - static struct freq_attr *acpi_cpufreq_attr[] = { -- &cpufreq_freq_attr_scaling_available_freqs, -+ &cpufreq_freq_attr_phc_version, -+ &cpufreq_freq_attr_scaling_available_freqs, -+ &cpufreq_freq_attr_vids, -+ &cpufreq_freq_attr_default_vids, -+ &cpufreq_freq_attr_fids, -+ &cpufreq_freq_attr_controls, -+ &cpufreq_freq_attr_default_controls, - NULL, - }; - - static struct cpufreq_driver acpi_cpufreq_driver = { - .verify = acpi_cpufreq_verify, diff --git a/sys-kernel/thinkpad-sources/files/2.6.27/power-off-unused-ports.patch b/sys-kernel/thinkpad-sources/files/2.6.27/power-off-unused-ports.patch deleted file mode 100644 index d7225a2..0000000 --- a/sys-kernel/thinkpad-sources/files/2.6.27/power-off-unused-ports.patch +++ /dev/null @@ -1,133 +0,0 @@ - drivers/ata/ahci.c | 21 +++++++++++++++++++++ - drivers/ata/libata-core.c | 24 ++++++++++++++++++++++++ - include/linux/libata.h | 1 + - 3 files changed, 46 insertions(+) - -Index: linux-ahci-phy/drivers/ata/ahci.c -=================================================================== ---- linux-ahci-phy.orig/drivers/ata/ahci.c 2008-05-08 14:29:02.000000000 -0700 -+++ linux-ahci-phy/drivers/ata/ahci.c 2008-05-08 14:31:05.000000000 -0700 -@@ -53,14 +53,18 @@ static int ahci_skip_host_reset; - module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); - MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); - -+static int ahci_power_save = 1; -+module_param_named(power_save, ahci_power_save, int, 0444); -+MODULE_PARM_DESC(power_save, "Power off unused ports (0=don't power off, 1=power off)"); - static int ahci_enable_alpm(struct ata_port *ap, - enum link_pm policy); - static void ahci_disable_alpm(struct ata_port *ap); - static ssize_t ahci_led_show(struct ata_port *ap, char *buf); - static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, - size_t size); - static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, - ssize_t size); -+static int ahci_is_hotplug_capable(struct ata_port *ap); - #define MAX_SLOTS 8 - - enum { -@@ -166,6 +170,8 @@ enum { - PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ - PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ - PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ -+ PORT_CMD_ESP = (1 << 21), /* External SATA Port */ -+ PORT_CMD_HPCP = (1 << 18), /* port is hot plug capable */ - PORT_CMD_PMP = (1 << 17), /* PMP attached */ - PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ - PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ -@@ -1900,6 +1906,18 @@ static int ahci_pci_device_resume(struct - } - #endif - -+static int ahci_is_hotplug_capable(struct ata_port *ap) -+{ -+ void __iomem *port_mmio = ahci_port_base(ap); -+ u8 cmd; -+ -+ if (!ahci_power_save) -+ return 1; -+ -+ cmd = readl(port_mmio + PORT_CMD); -+ return ((cmd & PORT_CMD_HPCP) || (cmd & PORT_CMD_ESP)); -+} -+ - static int ahci_port_start(struct ata_port *ap) - { - struct device *dev = ap->host->dev; -@@ -1951,6 +1969,9 @@ static int ahci_port_start(struct ata_po - - ap->private_data = pp; - -+ /* set some flags based on port capabilities */ -+ if (!ahci_is_hotplug_capable(ap)) -+ ap->flags |= ATA_FLAG_NO_HOTPLUG; - /* engage engines, captain */ - return ahci_port_resume(ap); - } -Index: linux-ahci-phy/drivers/ata/libata-core.c -=================================================================== ---- linux-ahci-phy.orig/drivers/ata/libata-core.c 2008-05-08 14:28:57.000000000 -0700 -+++ linux-ahci-phy/drivers/ata/libata-core.c 2008-05-08 14:29:50.000000000 -0700 -@@ -162,6 +162,19 @@ MODULE_DESCRIPTION("Library module for A - MODULE_LICENSE("GPL"); - MODULE_VERSION(DRV_VERSION); - -+static void ata_phy_offline(struct ata_link *link) -+{ -+ u32 scontrol; -+ int rc; -+ -+ /* set DET to 4 */ -+ rc = sata_scr_read(link, SCR_CONTROL, &scontrol); -+ if (rc) -+ return; -+ scontrol &= ~0xf; -+ scontrol |= (1 << 2); -+ sata_scr_write(link, SCR_CONTROL, scontrol); -+} - - /** - * ata_force_cbl - force cable type according to libata.force -@@ -2671,6 +2684,7 @@ void ata_port_disable(struct ata_port *a - ap->link.device[0].class = ATA_DEV_NONE; - ap->link.device[1].class = ATA_DEV_NONE; - ap->flags |= ATA_FLAG_DISABLED; -+ ata_phy_offline(&ap->link); - } - - /** -@@ -5609,6 +5623,8 @@ int ata_host_register(struct ata_host *h - if (ap->ops->error_handler) { - struct ata_eh_info *ehi = &ap->link.eh_info; - unsigned long flags; -+ int device_attached = 0; -+ struct ata_device *dev; - - ata_port_probe(ap); - -@@ -5627,6 +5643,14 @@ int ata_host_register(struct ata_host *h - - /* wait for EH to finish */ - ata_port_wait_eh(ap); -+ ata_link_for_each_dev(dev, &ap->link) -+ if (ata_dev_enabled(dev)) -+ device_attached++; -+ if (!device_attached && -+ (ap->flags & ATA_FLAG_NO_HOTPLUG)) { -+ /* no device present, disable port */ -+ ata_port_disable(ap); -+ } - } else { - DPRINTK("ata%u: bus probe begin\n", ap->print_id); - rc = ata_bus_probe(ap); -Index: linux-ahci-phy/include/linux/libata.h -=================================================================== ---- linux-ahci-phy.orig/include/linux/libata.h 2008-05-08 14:28:57.000000000 -0700 -+++ linux-ahci-phy/include/linux/libata.h 2008-05-08 14:29:50.000000000 -0700 -@@ -207,4 +207,6 @@ ATA_FLAG_DISABLED = (1 << 23), /* port is disabled, ignore it */ - - /* bits 24:31 of ap->flags are reserved for LLD specific flags */ -+ -+ ATA_FLAG_NO_HOTPLUG = (1 << 32), /* port doesn't support HP */ - - /* struct ata_port pflags */ diff --git a/sys-kernel/thinkpad-sources/files/2.6.28/02-ipw2200-inject-for-2.6.27.patch b/sys-kernel/thinkpad-sources/files/2.6.28/02-ipw2200-inject-for-2.6.27.patch deleted file mode 100644 index ec44f16..0000000 --- a/sys-kernel/thinkpad-sources/files/2.6.28/02-ipw2200-inject-for-2.6.27.patch +++ /dev/null @@ -1,86 +0,0 @@ ---- a/drivers/net/wireless/ipw2200.c 2007-10-07 12:41:29.000000000 +0200 -+++ b/drivers/net/wireless/ipw2200.c 2007-10-07 12:50:43.000000000 +0200 -@@ -31,7 +31,7 @@ - ******************************************************************************/ - - #include "ipw2200.h" -- -+#include <linux/version.h> - - #ifndef KBUILD_EXTMOD - #define VK "k" -@@ -1862,6 +1862,66 @@ - static DEVICE_ATTR(net_stats, S_IWUSR | S_IRUGO, - show_net_stats, store_net_stats); - -+static int ipw_tx_skb(struct ipw_priv *priv, struct ieee80211_txb *txb, int pri); -+ -+/* SYSFS INJECT */ -+static ssize_t store_inject(struct device *d, -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12) -+ struct device_attribute *attr, -+#endif -+ const char *buf, size_t count) -+{ -+ struct ipw_priv *priv = (struct ipw_priv *)d->driver_data; -+ struct ieee80211_device *ieee = priv->ieee; -+ struct ieee80211_txb * txb; -+ struct sk_buff *skb_frag; -+ unsigned char * newbuf; -+ unsigned long flags; -+ -+ // should test (ieee->is_queue_full) -+ -+ // Fw only accepts data, so avoid accidental fw errors. -+ if ( (buf[0]&0x0c) != '\x08') { -+ //printk("ipw2200: inject: discarding non-data frame (type=%02X)\n",(int)(unsigned char)buf[0]); -+ return count; -+ } -+ -+ if (count>1500) { -+ count=1500; -+ printk("ipw2200: inject: cutting down frame to 1500 bytes\n"); -+ } -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ -+ // Create a txb with one skb -+ txb = kmalloc(sizeof(struct ieee80211_txb) + sizeof(u8 *), GFP_ATOMIC); -+ if (!txb) -+ goto nosepuede; -+ txb->nr_frags=1; -+ txb->frag_size = ieee->tx_headroom; -+ txb->fragments[0]=__dev_alloc_skb(count + ieee->tx_headroom, GFP_ATOMIC); -+ if (!txb->fragments[0]) { -+ kfree(txb); -+ goto nosepuede; -+ } -+ skb_reserve(txb->fragments[0], ieee->tx_headroom); -+ txb->encrypted=0; -+ txb->payload_size=count; -+ skb_frag = txb->fragments[0]; -+ newbuf=skb_put(skb_frag, count); -+ -+ // copy data into txb->skb and send it -+ memcpy(newbuf, buf, count); -+ -+ ipw_tx_skb(priv, txb, 0); -+ -+nosepuede: -+ spin_unlock_irqrestore(&priv->lock, flags); -+ return count; -+} -+ -+static DEVICE_ATTR(inject, S_IWUSR, NULL, store_inject); -+ - static ssize_t show_channels(struct device *d, - struct device_attribute *attr, - char *buf) -@@ -11478,6 +11538,7 @@ - #ifdef CONFIG_IPW2200_PROMISCUOUS - &dev_attr_rtap_iface.attr, - &dev_attr_rtap_filter.attr, -+ &dev_attr_inject.attr, - #endif - NULL - }; diff --git a/sys-kernel/thinkpad-sources/files/2.6.28/power-off-unused-ports.patch b/sys-kernel/thinkpad-sources/files/2.6.28/power-off-unused-ports.patch deleted file mode 100644 index d7225a2..0000000 --- a/sys-kernel/thinkpad-sources/files/2.6.28/power-off-unused-ports.patch +++ /dev/null @@ -1,133 +0,0 @@ - drivers/ata/ahci.c | 21 +++++++++++++++++++++ - drivers/ata/libata-core.c | 24 ++++++++++++++++++++++++ - include/linux/libata.h | 1 + - 3 files changed, 46 insertions(+) - -Index: linux-ahci-phy/drivers/ata/ahci.c -=================================================================== ---- linux-ahci-phy.orig/drivers/ata/ahci.c 2008-05-08 14:29:02.000000000 -0700 -+++ linux-ahci-phy/drivers/ata/ahci.c 2008-05-08 14:31:05.000000000 -0700 -@@ -53,14 +53,18 @@ static int ahci_skip_host_reset; - module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); - MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); - -+static int ahci_power_save = 1; -+module_param_named(power_save, ahci_power_save, int, 0444); -+MODULE_PARM_DESC(power_save, "Power off unused ports (0=don't power off, 1=power off)"); - static int ahci_enable_alpm(struct ata_port *ap, - enum link_pm policy); - static void ahci_disable_alpm(struct ata_port *ap); - static ssize_t ahci_led_show(struct ata_port *ap, char *buf); - static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, - size_t size); - static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, - ssize_t size); -+static int ahci_is_hotplug_capable(struct ata_port *ap); - #define MAX_SLOTS 8 - - enum { -@@ -166,6 +170,8 @@ enum { - PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ - PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ - PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ -+ PORT_CMD_ESP = (1 << 21), /* External SATA Port */ -+ PORT_CMD_HPCP = (1 << 18), /* port is hot plug capable */ - PORT_CMD_PMP = (1 << 17), /* PMP attached */ - PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ - PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ -@@ -1900,6 +1906,18 @@ static int ahci_pci_device_resume(struct - } - #endif - -+static int ahci_is_hotplug_capable(struct ata_port *ap) -+{ -+ void __iomem *port_mmio = ahci_port_base(ap); -+ u8 cmd; -+ -+ if (!ahci_power_save) -+ return 1; -+ -+ cmd = readl(port_mmio + PORT_CMD); -+ return ((cmd & PORT_CMD_HPCP) || (cmd & PORT_CMD_ESP)); -+} -+ - static int ahci_port_start(struct ata_port *ap) - { - struct device *dev = ap->host->dev; -@@ -1951,6 +1969,9 @@ static int ahci_port_start(struct ata_po - - ap->private_data = pp; - -+ /* set some flags based on port capabilities */ -+ if (!ahci_is_hotplug_capable(ap)) -+ ap->flags |= ATA_FLAG_NO_HOTPLUG; - /* engage engines, captain */ - return ahci_port_resume(ap); - } -Index: linux-ahci-phy/drivers/ata/libata-core.c -=================================================================== ---- linux-ahci-phy.orig/drivers/ata/libata-core.c 2008-05-08 14:28:57.000000000 -0700 -+++ linux-ahci-phy/drivers/ata/libata-core.c 2008-05-08 14:29:50.000000000 -0700 -@@ -162,6 +162,19 @@ MODULE_DESCRIPTION("Library module for A - MODULE_LICENSE("GPL"); - MODULE_VERSION(DRV_VERSION); - -+static void ata_phy_offline(struct ata_link *link) -+{ -+ u32 scontrol; -+ int rc; -+ -+ /* set DET to 4 */ -+ rc = sata_scr_read(link, SCR_CONTROL, &scontrol); -+ if (rc) -+ return; -+ scontrol &= ~0xf; -+ scontrol |= (1 << 2); -+ sata_scr_write(link, SCR_CONTROL, scontrol); -+} - - /** - * ata_force_cbl - force cable type according to libata.force -@@ -2671,6 +2684,7 @@ void ata_port_disable(struct ata_port *a - ap->link.device[0].class = ATA_DEV_NONE; - ap->link.device[1].class = ATA_DEV_NONE; - ap->flags |= ATA_FLAG_DISABLED; -+ ata_phy_offline(&ap->link); - } - - /** -@@ -5609,6 +5623,8 @@ int ata_host_register(struct ata_host *h - if (ap->ops->error_handler) { - struct ata_eh_info *ehi = &ap->link.eh_info; - unsigned long flags; -+ int device_attached = 0; -+ struct ata_device *dev; - - ata_port_probe(ap); - -@@ -5627,6 +5643,14 @@ int ata_host_register(struct ata_host *h - - /* wait for EH to finish */ - ata_port_wait_eh(ap); -+ ata_link_for_each_dev(dev, &ap->link) -+ if (ata_dev_enabled(dev)) -+ device_attached++; -+ if (!device_attached && -+ (ap->flags & ATA_FLAG_NO_HOTPLUG)) { -+ /* no device present, disable port */ -+ ata_port_disable(ap); -+ } - } else { - DPRINTK("ata%u: bus probe begin\n", ap->print_id); - rc = ata_bus_probe(ap); -Index: linux-ahci-phy/include/linux/libata.h -=================================================================== ---- linux-ahci-phy.orig/include/linux/libata.h 2008-05-08 14:28:57.000000000 -0700 -+++ linux-ahci-phy/include/linux/libata.h 2008-05-08 14:29:50.000000000 -0700 -@@ -207,4 +207,6 @@ ATA_FLAG_DISABLED = (1 << 23), /* port is disabled, ignore it */ - - /* bits 24:31 of ap->flags are reserved for LLD specific flags */ -+ -+ ATA_FLAG_NO_HOTPLUG = (1 << 32), /* port doesn't support HP */ - - /* struct ata_port pflags */ diff --git a/sys-kernel/thinkpad-sources/files/2.6.27/02-ipw2200-inject-for-2.6.27.patch b/sys-kernel/thinkpad-sources/files/2.6.31/02-ipw2200-inject-for-2.6.27.patch index ec44f16..ec44f16 100644 --- a/sys-kernel/thinkpad-sources/files/2.6.27/02-ipw2200-inject-for-2.6.27.patch +++ b/sys-kernel/thinkpad-sources/files/2.6.31/02-ipw2200-inject-for-2.6.27.patch diff --git a/sys-kernel/thinkpad-sources/files/2.6.28/colored-printk-2.6.26.patch b/sys-kernel/thinkpad-sources/files/2.6.31/colored-printk-2.6.30.patch index dc97636..d48f769 100644 --- a/sys-kernel/thinkpad-sources/files/2.6.28/colored-printk-2.6.26.patch +++ b/sys-kernel/thinkpad-sources/files/2.6.31/colored-printk-2.6.30.patch @@ -1,8 +1,7 @@ -diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c -index 643fd86..837f3c2 100644 ---- a/arch/x86/kernel/early_printk.c -+++ b/arch/x86/kernel/early_printk.c -@@ -15,7 +15,8 @@ +diff -pruN -X linux/Documentation/dontdiff linux-2.6.29.3/arch/x86/kernel/early_printk.c linux-2.6.29.3-cprintk/arch/x86/kernel/early_printk.c +--- a/arch/x86/kernel/early_printk.c 2009-03-24 00:12:14.000000000 +0100 ++++ b/arch/x86/kernel/early_printk.c 2009-05-09 16:10:36.000000000 +0200 +@@ -23,7 +23,8 @@ static int max_ypos = 25, max_xpos = 80; static int current_ypos = 25, current_xpos; @@ -12,7 +11,7 @@ index 643fd86..837f3c2 100644 { char c; int i, k, j; -@@ -84,7 +85,8 @@ static int early_serial_putc(unsigned char ch) +@@ -93,7 +94,8 @@ static int early_serial_putc(unsigned ch return timeout ? 0 : -1; } @@ -22,32 +21,21 @@ index 643fd86..837f3c2 100644 { while (*s && n-- > 0) { if (*s == '\n') -@@ -180,7 +182,8 @@ static void __init simnow_init(char *str) - simnow_fd = simnow(XOPEN, (unsigned long)fn, O_WRONLY|O_APPEND|O_CREAT, 0644); - } - --static void simnow_write(struct console *con, const char *s, unsigned n) -+static void simnow_write(struct console *con, const char *s, unsigned n, -+ unsigned int loglevel) - { - simnow(XWRITE, simnow_fd, (unsigned long)s, n); - } -@@ -204,7 +207,7 @@ void early_printk(const char *fmt, ...) +@@ -887,7 +889,7 @@ asmlinkage void early_printk(const char va_start(ap, fmt); - n = vscnprintf(buf, 512, fmt, ap); + n = vscnprintf(buf, sizeof(buf), fmt, ap); - early_console->write(early_console, buf, n); + early_console->write(early_console, buf, n, 0); va_end(ap); } -diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig -index 57ba5c2..10556dd 100644 ---- a/drivers/char/Kconfig -+++ b/drivers/char/Kconfig -@@ -71,6 +71,111 @@ config NR_TTY_DEVICES +diff -pruN -X linux/Documentation/dontdiff linux-2.6.29.3/drivers/char/Kconfig linux-2.6.29.3-cprintk/drivers/char/Kconfig +--- a/drivers/char/Kconfig 2009-03-24 00:12:14.000000000 +0100 ++++ b/drivers/char/Kconfig 2009-05-09 14:43:48.000000000 +0200 +@@ -66,6 +66,111 @@ config VT_CONSOLE - If unsure, say 63. + If unsure, say Y. +menuconfig VT_CKO + bool "Colored kernel message output" @@ -157,10 +145,9 @@ index 57ba5c2..10556dd 100644 config HW_CONSOLE bool depends on VT && !S390 && !UML -diff --git a/drivers/char/vt.c b/drivers/char/vt.c -index 935f1c2..1fee2dc 100644 ---- a/drivers/char/vt.c -+++ b/drivers/char/vt.c +diff -pruN -X linux/Documentation/dontdiff linux-2.6.29.3/drivers/char/vt.c linux-2.6.29.3-cprintk/drivers/char/vt.c +--- a/drivers/char/vt.c 2009-05-09 10:46:57.000000000 +0200 ++++ b/drivers/char/vt.c 2009-05-09 14:43:48.000000000 +0200 @@ -73,6 +73,7 @@ */ @@ -169,7 +156,7 @@ index 935f1c2..1fee2dc 100644 #include <linux/types.h> #include <linux/sched.h> #include <linux/tty.h> -@@ -2409,17 +2410,45 @@ struct tty_driver *console_driver; +@@ -2431,17 +2432,45 @@ struct tty_driver *console_driver; #ifdef CONFIG_VT_CONSOLE @@ -217,7 +204,7 @@ index 935f1c2..1fee2dc 100644 const ushort *start; ushort cnt = 0; ushort myx; -@@ -2452,11 +2481,19 @@ static void vt_console_print(struct console *co, const char *b, unsigned count) +@@ -2474,11 +2503,19 @@ static void vt_console_print(struct cons start = (ushort *)vc->vc_pos; @@ -237,7 +224,7 @@ index 935f1c2..1fee2dc 100644 if (cnt > 0) { if (CON_IS_VISIBLE(vc)) vc->vc_sw->con_putcs(vc, start, cnt, vc->vc_y, vc->vc_x); -@@ -2469,6 +2506,7 @@ static void vt_console_print(struct console *co, const char *b, unsigned count) +@@ -2491,6 +2528,7 @@ static void vt_console_print(struct cons bs(vc); start = (ushort *)vc->vc_pos; myx = vc->vc_x; @@ -245,7 +232,7 @@ index 935f1c2..1fee2dc 100644 continue; } if (c != 13) -@@ -2476,6 +2514,7 @@ static void vt_console_print(struct console *co, const char *b, unsigned count) +@@ -2498,6 +2536,7 @@ static void vt_console_print(struct cons cr(vc); start = (ushort *)vc->vc_pos; myx = vc->vc_x; @@ -253,7 +240,7 @@ index 935f1c2..1fee2dc 100644 if (c == 10 || c == 13) continue; } -@@ -2498,6 +2537,7 @@ static void vt_console_print(struct console *co, const char *b, unsigned count) +@@ -2520,6 +2559,7 @@ static void vt_console_print(struct cons vc->vc_need_wrap = 1; } } @@ -261,11 +248,10 @@ index 935f1c2..1fee2dc 100644 set_cursor(vc); notify_update(vc); -diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c -index 665341e..4c27de8 100644 ---- a/drivers/net/netconsole.c -+++ b/drivers/net/netconsole.c -@@ -694,7 +694,8 @@ static struct notifier_block netconsole_netdev_notifier = { +diff -pruN -X linux/Documentation/dontdiff linux-2.6.29.3/drivers/net/netconsole.c linux-2.6.29.3-cprintk/drivers/net/netconsole.c +--- a/drivers/net/netconsole.c 2009-03-24 00:12:14.000000000 +0100 ++++ b/drivers/net/netconsole.c 2009-05-09 14:43:48.000000000 +0200 +@@ -691,7 +691,8 @@ static struct notifier_block netconsole_ .notifier_call = netconsole_netdev_event, }; @@ -275,11 +261,10 @@ index 665341e..4c27de8 100644 { int frag, left; unsigned long flags; -diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c -index 1bc00b7..b4f1b6f 100644 ---- a/drivers/serial/8250.c -+++ b/drivers/serial/8250.c -@@ -2527,7 +2527,8 @@ static void serial8250_console_putchar(struct uart_port *port, int ch) +diff -pruN -X linux/Documentation/dontdiff linux-2.6.29.3/drivers/serial/8250.c linux-2.6.29.3-cprintk/drivers/serial/8250.c +--- a/drivers/serial/8250.c 2009-03-24 00:12:14.000000000 +0100 ++++ b/drivers/serial/8250.c 2009-05-09 14:43:48.000000000 +0200 +@@ -2698,7 +2698,8 @@ static void serial8250_console_putchar(s * The console_lock must be held when we get here. */ static void @@ -289,11 +274,10 @@ index 1bc00b7..b4f1b6f 100644 { struct uart_8250_port *up = &serial8250_ports[co->index]; unsigned long flags; -diff --git a/drivers/serial/8250_early.c b/drivers/serial/8250_early.c -index f279745..2a928bd 100644 ---- a/drivers/serial/8250_early.c -+++ b/drivers/serial/8250_early.c -@@ -83,7 +83,7 @@ static void __init serial_putc(struct uart_port *port, int c) +diff -pruN -X linux/Documentation/dontdiff linux-2.6.29.3/drivers/serial/8250_early.c linux-2.6.29.3-cprintk/drivers/serial/8250_early.c +--- a/drivers/serial/8250_early.c 2009-03-24 00:12:14.000000000 +0100 ++++ b/drivers/serial/8250_early.c 2009-05-09 14:43:48.000000000 +0200 +@@ -83,7 +83,7 @@ static void __init serial_putc(struct ua } static void __init early_serial8250_write(struct console *console, @@ -302,11 +286,10 @@ index f279745..2a928bd 100644 { struct uart_port *port = &early_device.port; unsigned int ier; -diff --git a/include/linux/console.h b/include/linux/console.h -index a4f27fb..46fcfd3 100644 ---- a/include/linux/console.h -+++ b/include/linux/console.h -@@ -95,7 +95,7 @@ void give_up_console(const struct consw *sw); +diff -pruN -X linux/Documentation/dontdiff linux-2.6.29.3/include/linux/console.h linux-2.6.29.3-cprintk/include/linux/console.h +--- a/include/linux/console.h 2009-03-24 00:12:14.000000000 +0100 ++++ b/include/linux/console.h 2009-05-09 14:43:48.000000000 +0200 +@@ -95,7 +95,7 @@ void give_up_console(const struct consw struct console { char name[16]; @@ -315,11 +298,10 @@ index a4f27fb..46fcfd3 100644 int (*read)(struct console *, char *, unsigned); struct tty_driver *(*device)(struct console *, int *); void (*unblank)(void); -diff --git a/kernel/printk.c b/kernel/printk.c -index 6e920ce..a1aaa3f 100644 ---- a/kernel/printk.c -+++ b/kernel/printk.c -@@ -444,7 +444,8 @@ asmlinkage long sys_syslog(int type, char __user *buf, int len) +diff -pruN -X linux/Documentation/dontdiff linux-2.6.29.3/kernel/printk.c linux-2.6.29.3-cprintk/kernel/printk.c +--- a/kernel/printk.c 2009-03-24 00:12:14.000000000 +0100 ++++ b/kernel/printk.c 2009-05-09 14:43:48.000000000 +0200 +@@ -389,7 +389,8 @@ SYSCALL_DEFINE3(syslog, int, type, char /* * Call the console drivers on a range of log_buf */ @@ -329,7 +311,7 @@ index 6e920ce..a1aaa3f 100644 { struct console *con; -@@ -452,7 +453,7 @@ static void __call_console_drivers(unsigned start, unsigned end) +@@ -397,7 +398,7 @@ static void __call_console_drivers(unsig if ((con->flags & CON_ENABLED) && con->write && (cpu_online(smp_processor_id()) || (con->flags & CON_ANYTIME))) @@ -338,7 +320,7 @@ index 6e920ce..a1aaa3f 100644 } } -@@ -479,10 +480,11 @@ static void _call_console_drivers(unsigned start, +@@ -424,10 +425,11 @@ static void _call_console_drivers(unsign if ((start & LOG_BUF_MASK) > (end & LOG_BUF_MASK)) { /* wrapped write */ __call_console_drivers(start & LOG_BUF_MASK, diff --git a/sys-kernel/thinkpad-sources/files/2.6.31/drm-next.patch b/sys-kernel/thinkpad-sources/files/2.6.31/drm-next.patch new file mode 100644 index 0000000..5bb0323 --- /dev/null +++ b/sys-kernel/thinkpad-sources/files/2.6.31/drm-next.patch @@ -0,0 +1,88389 @@ +diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig +index 39b393d..e4d971c 100644 +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -18,6 +18,14 @@ menuconfig DRM + details. You should also select and configure AGP + (/dev/agpgart) support. + ++config DRM_KMS_HELPER ++ tristate ++ depends on DRM ++ select FB ++ select FRAMEBUFFER_CONSOLE if !EMBEDDED ++ help ++ FB and CRTC helpers for KMS drivers. ++ + config DRM_TTM + tristate + depends on DRM +@@ -36,6 +44,7 @@ config DRM_TDFX + config DRM_R128 + tristate "ATI Rage 128" + depends on DRM && PCI ++ select FW_LOADER + help + Choose this option if you have an ATI Rage 128 graphics card. If M + is selected, the module will be called r128. AGP support for +@@ -47,8 +56,9 @@ config DRM_RADEON + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT +- select FB +- select FRAMEBUFFER_CONSOLE if !EMBEDDED ++ select FW_LOADER ++ select DRM_KMS_HELPER ++ select DRM_TTM + help + Choose this option if you have an ATI Radeon graphics card. There + are both PCI and AGP versions. You don't need to choose this to +@@ -82,11 +92,10 @@ config DRM_I830 + config DRM_I915 + tristate "i915 driver" + depends on AGP_INTEL ++ select DRM_KMS_HELPER + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT +- select FB +- select FRAMEBUFFER_CONSOLE if !EMBEDDED + # i915 depends on ACPI_VIDEO when ACPI is enabled + # but for select to work, need to select ACPI_VIDEO's dependencies, ick + select VIDEO_OUTPUT_CONTROL if ACPI +@@ -116,6 +125,7 @@ endchoice + config DRM_MGA + tristate "Matrox g200/g400" + depends on DRM ++ select FW_LOADER + help + Choose this option if you have a Matrox G200, G400 or G450 graphics + card. If M is selected, the module will be called mga. AGP +diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile +index fe23f29..3c8827a 100644 +--- a/drivers/gpu/drm/Makefile ++++ b/drivers/gpu/drm/Makefile +@@ -10,11 +10,15 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ + drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \ + drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \ + drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \ +- drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \ +- drm_info.o drm_debugfs.o ++ drm_crtc.o drm_modes.o drm_edid.o \ ++ drm_info.o drm_debugfs.o drm_encoder_slave.o + + drm-$(CONFIG_COMPAT) += drm_ioc32.o + ++drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o ++ ++obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o ++ + obj-$(CONFIG_DRM) += drm.o + obj-$(CONFIG_DRM_TTM) += ttm/ + obj-$(CONFIG_DRM_TDFX) += tdfx/ +diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c +index 6246e3f..3d09e30 100644 +--- a/drivers/gpu/drm/drm_bufs.c ++++ b/drivers/gpu/drm/drm_bufs.c +@@ -310,10 +310,10 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset, + (unsigned long long)map->offset, map->size); + + break; ++ } + case _DRM_GEM: +- DRM_ERROR("tried to rmmap GEM object\n"); ++ DRM_ERROR("tried to addmap GEM object\n"); + break; +- } + case _DRM_SCATTER_GATHER: + if (!dev->sg) { + kfree(map); +diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c +index 0e994a0..0e3bd5b 100644 +--- a/drivers/gpu/drm/drm_cache.c ++++ b/drivers/gpu/drm/drm_cache.c +@@ -45,6 +45,23 @@ drm_clflush_page(struct page *page) + clflush(page_virtual + i); + kunmap_atomic(page_virtual, KM_USER0); + } ++ ++static void drm_cache_flush_clflush(struct page *pages[], ++ unsigned long num_pages) ++{ ++ unsigned long i; ++ ++ mb(); ++ for (i = 0; i < num_pages; i++) ++ drm_clflush_page(*pages++); ++ mb(); ++} ++ ++static void ++drm_clflush_ipi_handler(void *null) ++{ ++ wbinvd(); ++} + #endif + + void +@@ -53,17 +70,30 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages) + + #if defined(CONFIG_X86) + if (cpu_has_clflush) { +- unsigned long i; +- +- mb(); +- for (i = 0; i < num_pages; ++i) +- drm_clflush_page(*pages++); +- mb(); +- ++ drm_cache_flush_clflush(pages, num_pages); + return; + } + +- wbinvd(); ++ if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) ++ printk(KERN_ERR "Timed out waiting for cache flush.\n"); ++ ++#elif defined(__powerpc__) ++ unsigned long i; ++ for (i = 0; i < num_pages; i++) { ++ struct page *page = pages[i]; ++ void *page_virtual; ++ ++ if (unlikely(page == NULL)) ++ continue; ++ ++ page_virtual = kmap_atomic(page, KM_USER0); ++ flush_dcache_range((unsigned long)page_virtual, ++ (unsigned long)page_virtual + PAGE_SIZE); ++ kunmap_atomic(page_virtual, KM_USER0); ++ } ++#else ++ printk(KERN_ERR "Architecture has no drm_cache.c support\n"); ++ WARN_ON_ONCE(1); + #endif + } + EXPORT_SYMBOL(drm_clflush_pages); +diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c +index 2f631c7..8e7b0eb 100644 +--- a/drivers/gpu/drm/drm_crtc.c ++++ b/drivers/gpu/drm/drm_crtc.c +@@ -68,10 +68,10 @@ DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list) + */ + static struct drm_prop_enum_list drm_scaling_mode_enum_list[] = + { +- { DRM_MODE_SCALE_NON_GPU, "Non-GPU" }, +- { DRM_MODE_SCALE_FULLSCREEN, "Fullscreen" }, +- { DRM_MODE_SCALE_NO_SCALE, "No scale" }, +- { DRM_MODE_SCALE_ASPECT, "Aspect" }, ++ { DRM_MODE_SCALE_NONE, "None" }, ++ { DRM_MODE_SCALE_FULLSCREEN, "Full" }, ++ { DRM_MODE_SCALE_CENTER, "Center" }, ++ { DRM_MODE_SCALE_ASPECT, "Full aspect" }, + }; + + static struct drm_prop_enum_list drm_dithering_mode_enum_list[] = +@@ -108,6 +108,7 @@ static struct drm_prop_enum_list drm_tv_select_enum_list[] = + { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ + { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */ + { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */ ++ { DRM_MODE_SUBCONNECTOR_SCART, "SCART" }, /* TV-out */ + }; + + DRM_ENUM_NAME_FN(drm_get_tv_select_name, drm_tv_select_enum_list) +@@ -118,6 +119,7 @@ static struct drm_prop_enum_list drm_tv_subconnector_enum_list[] = + { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ + { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */ + { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */ ++ { DRM_MODE_SUBCONNECTOR_SCART, "SCART" }, /* TV-out */ + }; + + DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, +@@ -146,6 +148,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] = + { DRM_MODE_CONNECTOR_DisplayPort, "DisplayPort", 0 }, + { DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 }, + { DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 }, ++ { DRM_MODE_CONNECTOR_TV, "TV", 0 }, + }; + + static struct drm_prop_enum_list drm_encoder_enum_list[] = +@@ -165,6 +168,7 @@ char *drm_get_encoder_name(struct drm_encoder *encoder) + encoder->base.id); + return buf; + } ++EXPORT_SYMBOL(drm_get_encoder_name); + + char *drm_get_connector_name(struct drm_connector *connector) + { +@@ -478,6 +482,7 @@ void drm_connector_cleanup(struct drm_connector *connector) + list_for_each_entry_safe(mode, t, &connector->user_modes, head) + drm_mode_remove(connector, mode); + ++ kfree(connector->fb_helper_private); + mutex_lock(&dev->mode_config.mutex); + drm_mode_object_put(dev, &connector->base); + list_del(&connector->head); +@@ -699,6 +704,42 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes, + drm_property_add_enum(dev->mode_config.tv_mode_property, i, + i, modes[i]); + ++ dev->mode_config.tv_brightness_property = ++ drm_property_create(dev, DRM_MODE_PROP_RANGE, ++ "brightness", 2); ++ dev->mode_config.tv_brightness_property->values[0] = 0; ++ dev->mode_config.tv_brightness_property->values[1] = 100; ++ ++ dev->mode_config.tv_contrast_property = ++ drm_property_create(dev, DRM_MODE_PROP_RANGE, ++ "contrast", 2); ++ dev->mode_config.tv_contrast_property->values[0] = 0; ++ dev->mode_config.tv_contrast_property->values[1] = 100; ++ ++ dev->mode_config.tv_flicker_reduction_property = ++ drm_property_create(dev, DRM_MODE_PROP_RANGE, ++ "flicker reduction", 2); ++ dev->mode_config.tv_flicker_reduction_property->values[0] = 0; ++ dev->mode_config.tv_flicker_reduction_property->values[1] = 100; ++ ++ dev->mode_config.tv_overscan_property = ++ drm_property_create(dev, DRM_MODE_PROP_RANGE, ++ "overscan", 2); ++ dev->mode_config.tv_overscan_property->values[0] = 0; ++ dev->mode_config.tv_overscan_property->values[1] = 100; ++ ++ dev->mode_config.tv_saturation_property = ++ drm_property_create(dev, DRM_MODE_PROP_RANGE, ++ "saturation", 2); ++ dev->mode_config.tv_saturation_property->values[0] = 0; ++ dev->mode_config.tv_saturation_property->values[1] = 100; ++ ++ dev->mode_config.tv_hue_property = ++ drm_property_create(dev, DRM_MODE_PROP_RANGE, ++ "hue", 2); ++ dev->mode_config.tv_hue_property->values[0] = 0; ++ dev->mode_config.tv_hue_property->values[1] = 100; ++ + return 0; + } + EXPORT_SYMBOL(drm_mode_create_tv_properties); +@@ -1044,7 +1085,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, + if (file_priv->master->minor->type == DRM_MINOR_CONTROL) { + list_for_each_entry(crtc, &dev->mode_config.crtc_list, + head) { +- DRM_DEBUG("CRTC ID is %d\n", crtc->base.id); ++ DRM_DEBUG_KMS("CRTC ID is %d\n", crtc->base.id); + if (put_user(crtc->base.id, crtc_id + copied)) { + ret = -EFAULT; + goto out; +@@ -1072,7 +1113,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, + list_for_each_entry(encoder, + &dev->mode_config.encoder_list, + head) { +- DRM_DEBUG("ENCODER ID is %d\n", ++ DRM_DEBUG_KMS("ENCODER ID is %d\n", + encoder->base.id); + if (put_user(encoder->base.id, encoder_id + + copied)) { +@@ -1103,7 +1144,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, + list_for_each_entry(connector, + &dev->mode_config.connector_list, + head) { +- DRM_DEBUG("CONNECTOR ID is %d\n", ++ DRM_DEBUG_KMS("CONNECTOR ID is %d\n", + connector->base.id); + if (put_user(connector->base.id, + connector_id + copied)) { +@@ -1127,7 +1168,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, + } + card_res->count_connectors = connector_count; + +- DRM_DEBUG("Counted %d %d %d\n", card_res->count_crtcs, ++ DRM_DEBUG_KMS("Counted %d %d %d\n", card_res->count_crtcs, + card_res->count_connectors, card_res->count_encoders); + + out: +@@ -1230,7 +1271,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, + + memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo)); + +- DRM_DEBUG("connector id %d:\n", out_resp->connector_id); ++ DRM_DEBUG_KMS("connector id %d:\n", out_resp->connector_id); + + mutex_lock(&dev->mode_config.mutex); + +@@ -1406,7 +1447,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, + obj = drm_mode_object_find(dev, crtc_req->crtc_id, + DRM_MODE_OBJECT_CRTC); + if (!obj) { +- DRM_DEBUG("Unknown CRTC ID %d\n", crtc_req->crtc_id); ++ DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_req->crtc_id); + ret = -EINVAL; + goto out; + } +@@ -1419,7 +1460,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, + list_for_each_entry(crtcfb, + &dev->mode_config.crtc_list, head) { + if (crtcfb == crtc) { +- DRM_DEBUG("Using current fb for setmode\n"); ++ DRM_DEBUG_KMS("Using current fb for " ++ "setmode\n"); + fb = crtc->fb; + } + } +@@ -1427,7 +1469,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, + obj = drm_mode_object_find(dev, crtc_req->fb_id, + DRM_MODE_OBJECT_FB); + if (!obj) { +- DRM_DEBUG("Unknown FB ID%d\n", crtc_req->fb_id); ++ DRM_DEBUG_KMS("Unknown FB ID%d\n", ++ crtc_req->fb_id); + ret = -EINVAL; + goto out; + } +@@ -1440,13 +1483,13 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, + } + + if (crtc_req->count_connectors == 0 && mode) { +- DRM_DEBUG("Count connectors is 0 but mode set\n"); ++ DRM_DEBUG_KMS("Count connectors is 0 but mode set\n"); + ret = -EINVAL; + goto out; + } + + if (crtc_req->count_connectors > 0 && (!mode || !fb)) { +- DRM_DEBUG("Count connectors is %d but no mode or fb set\n", ++ DRM_DEBUG_KMS("Count connectors is %d but no mode or fb set\n", + crtc_req->count_connectors); + ret = -EINVAL; + goto out; +@@ -1479,7 +1522,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, + obj = drm_mode_object_find(dev, out_id, + DRM_MODE_OBJECT_CONNECTOR); + if (!obj) { +- DRM_DEBUG("Connector id %d unknown\n", out_id); ++ DRM_DEBUG_KMS("Connector id %d unknown\n", ++ out_id); + ret = -EINVAL; + goto out; + } +@@ -1512,7 +1556,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev, + struct drm_crtc *crtc; + int ret = 0; + +- DRM_DEBUG("\n"); ++ DRM_DEBUG_KMS("\n"); + + if (!req->flags) { + DRM_ERROR("no operation set\n"); +@@ -1522,7 +1566,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev, + mutex_lock(&dev->mode_config.mutex); + obj = drm_mode_object_find(dev, req->crtc_id, DRM_MODE_OBJECT_CRTC); + if (!obj) { +- DRM_DEBUG("Unknown CRTC ID %d\n", req->crtc_id); ++ DRM_DEBUG_KMS("Unknown CRTC ID %d\n", req->crtc_id); + ret = -EINVAL; + goto out; + } +diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c +index 6aaa2cb..1fe4e1d 100644 +--- a/drivers/gpu/drm/drm_crtc_helper.c ++++ b/drivers/gpu/drm/drm_crtc_helper.c +@@ -32,15 +32,7 @@ + #include "drmP.h" + #include "drm_crtc.h" + #include "drm_crtc_helper.h" +- +-/* +- * Detailed mode info for 800x600@60Hz +- */ +-static struct drm_display_mode std_modes[] = { +- { DRM_MODE("800x600", DRM_MODE_TYPE_DEFAULT, 40000, 800, 840, +- 968, 1056, 0, 600, 601, 605, 628, 0, +- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, +-}; ++#include "drm_fb_helper.h" + + static void drm_mode_validate_flag(struct drm_connector *connector, + int flags) +@@ -94,23 +86,33 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, + int count = 0; + int mode_flags = 0; + +- DRM_DEBUG("%s\n", drm_get_connector_name(connector)); ++ DRM_DEBUG_KMS("%s\n", drm_get_connector_name(connector)); + /* set all modes to the unverified state */ + list_for_each_entry_safe(mode, t, &connector->modes, head) + mode->status = MODE_UNVERIFIED; + +- connector->status = connector->funcs->detect(connector); ++ if (connector->force) { ++ if (connector->force == DRM_FORCE_ON) ++ connector->status = connector_status_connected; ++ else ++ connector->status = connector_status_disconnected; ++ if (connector->funcs->force) ++ connector->funcs->force(connector); ++ } else ++ connector->status = connector->funcs->detect(connector); + + if (connector->status == connector_status_disconnected) { +- DRM_DEBUG("%s is disconnected\n", ++ DRM_DEBUG_KMS("%s is disconnected\n", + drm_get_connector_name(connector)); +- /* TODO set EDID to NULL */ +- return 0; ++ goto prune; + } + + count = (*connector_funcs->get_modes)(connector); +- if (!count) +- return 0; ++ if (!count) { ++ count = drm_add_modes_noedid(connector, 800, 600); ++ if (!count) ++ return 0; ++ } + + drm_mode_connector_list_update(connector); + +@@ -130,7 +132,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, + mode); + } + +- ++prune: + drm_mode_prune_invalid(dev, &connector->modes, true); + + if (list_empty(&connector->modes)) +@@ -138,7 +140,8 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, + + drm_mode_sort(&connector->modes); + +- DRM_DEBUG("Probed modes for %s\n", drm_get_connector_name(connector)); ++ DRM_DEBUG_KMS("Probed modes for %s\n", ++ drm_get_connector_name(connector)); + list_for_each_entry_safe(mode, t, &connector->modes, head) { + mode->vrefresh = drm_mode_vrefresh(mode); + +@@ -165,39 +168,6 @@ int drm_helper_probe_connector_modes(struct drm_device *dev, uint32_t maxX, + } + EXPORT_SYMBOL(drm_helper_probe_connector_modes); + +-static void drm_helper_add_std_modes(struct drm_device *dev, +- struct drm_connector *connector) +-{ +- struct drm_display_mode *mode, *t; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(std_modes); i++) { +- struct drm_display_mode *stdmode; +- +- /* +- * When no valid EDID modes are available we end up +- * here and bailed in the past, now we add some standard +- * modes and move on. +- */ +- stdmode = drm_mode_duplicate(dev, &std_modes[i]); +- drm_mode_probed_add(connector, stdmode); +- drm_mode_list_concat(&connector->probed_modes, +- &connector->modes); +- +- DRM_DEBUG("Adding mode %s to %s\n", stdmode->name, +- drm_get_connector_name(connector)); +- } +- drm_mode_sort(&connector->modes); +- +- DRM_DEBUG("Added std modes on %s\n", drm_get_connector_name(connector)); +- list_for_each_entry_safe(mode, t, &connector->modes, head) { +- mode->vrefresh = drm_mode_vrefresh(mode); +- +- drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); +- drm_mode_debug_printmodeline(mode); +- } +-} +- + /** + * drm_helper_encoder_in_use - check if a given encoder is in use + * @encoder: encoder to check +@@ -258,13 +228,27 @@ EXPORT_SYMBOL(drm_helper_crtc_in_use); + void drm_helper_disable_unused_functions(struct drm_device *dev) + { + struct drm_encoder *encoder; ++ struct drm_connector *connector; + struct drm_encoder_helper_funcs *encoder_funcs; + struct drm_crtc *crtc; + ++ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { ++ if (!connector->encoder) ++ continue; ++ if (connector->status == connector_status_disconnected) ++ connector->encoder = NULL; ++ } ++ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + encoder_funcs = encoder->helper_private; +- if (!drm_helper_encoder_in_use(encoder)) +- (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); ++ if (!drm_helper_encoder_in_use(encoder)) { ++ if (encoder_funcs->disable) ++ (*encoder_funcs->disable)(encoder); ++ else ++ (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); ++ /* disconnector encoder from any connector */ ++ encoder->crtc = NULL; ++ } + } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +@@ -292,6 +276,65 @@ static struct drm_display_mode *drm_has_preferred_mode(struct drm_connector *con + return NULL; + } + ++static bool drm_has_cmdline_mode(struct drm_connector *connector) ++{ ++ struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; ++ struct drm_fb_helper_cmdline_mode *cmdline_mode; ++ ++ if (!fb_help_conn) ++ return false; ++ ++ cmdline_mode = &fb_help_conn->cmdline_mode; ++ return cmdline_mode->specified; ++} ++ ++static struct drm_display_mode *drm_pick_cmdline_mode(struct drm_connector *connector, int width, int height) ++{ ++ struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; ++ struct drm_fb_helper_cmdline_mode *cmdline_mode; ++ struct drm_display_mode *mode = NULL; ++ ++ if (!fb_help_conn) ++ return mode; ++ ++ cmdline_mode = &fb_help_conn->cmdline_mode; ++ if (cmdline_mode->specified == false) ++ return mode; ++ ++ /* attempt to find a matching mode in the list of modes ++ * we have gotten so far, if not add a CVT mode that conforms ++ */ ++ if (cmdline_mode->rb || cmdline_mode->margins) ++ goto create_mode; ++ ++ list_for_each_entry(mode, &connector->modes, head) { ++ /* check width/height */ ++ if (mode->hdisplay != cmdline_mode->xres || ++ mode->vdisplay != cmdline_mode->yres) ++ continue; ++ ++ if (cmdline_mode->refresh_specified) { ++ if (mode->vrefresh != cmdline_mode->refresh) ++ continue; ++ } ++ ++ if (cmdline_mode->interlace) { ++ if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) ++ continue; ++ } ++ return mode; ++ } ++ ++create_mode: ++ mode = drm_cvt_mode(connector->dev, cmdline_mode->xres, ++ cmdline_mode->yres, ++ cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60, ++ cmdline_mode->rb, cmdline_mode->interlace, ++ cmdline_mode->margins); ++ list_add(&mode->head, &connector->modes); ++ return mode; ++} ++ + static bool drm_connector_enabled(struct drm_connector *connector, bool strict) + { + bool enable; +@@ -312,7 +355,7 @@ static void drm_enable_connectors(struct drm_device *dev, bool *enabled) + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + enabled[i] = drm_connector_enabled(connector, true); +- DRM_DEBUG("connector %d enabled? %s\n", connector->base.id, ++ DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id, + enabled[i] ? "yes" : "no"); + any_enabled |= enabled[i]; + i++; +@@ -342,16 +385,22 @@ static bool drm_target_preferred(struct drm_device *dev, + continue; + } + +- DRM_DEBUG("looking for preferred mode on connector %d\n", +- connector->base.id); ++ DRM_DEBUG_KMS("looking for cmdline mode on connector %d\n", ++ connector->base.id); + +- modes[i] = drm_has_preferred_mode(connector, width, height); ++ /* got for command line mode first */ ++ modes[i] = drm_pick_cmdline_mode(connector, width, height); ++ if (!modes[i]) { ++ DRM_DEBUG_KMS("looking for preferred mode on connector %d\n", ++ connector->base.id); ++ modes[i] = drm_has_preferred_mode(connector, width, height); ++ } + /* No preferred modes, pick one off the list */ + if (!modes[i] && !list_empty(&connector->modes)) { + list_for_each_entry(modes[i], &connector->modes, head) + break; + } +- DRM_DEBUG("found mode %s\n", modes[i] ? modes[i]->name : ++ DRM_DEBUG_KMS("found mode %s\n", modes[i] ? modes[i]->name : + "none"); + i++; + } +@@ -394,6 +443,8 @@ static int drm_pick_crtcs(struct drm_device *dev, + my_score = 1; + if (connector->status == connector_status_connected) + my_score++; ++ if (drm_has_cmdline_mode(connector)) ++ my_score++; + if (drm_has_preferred_mode(connector, width, height)) + my_score++; + +@@ -409,7 +460,7 @@ static int drm_pick_crtcs(struct drm_device *dev, + c = 0; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + +- if ((connector->encoder->possible_crtcs & (1 << c)) == 0) { ++ if ((encoder->possible_crtcs & (1 << c)) == 0) { + c++; + continue; + } +@@ -452,7 +503,7 @@ static void drm_setup_crtcs(struct drm_device *dev) + int width, height; + int i, ret; + +- DRM_DEBUG("\n"); ++ DRM_DEBUG_KMS("\n"); + + width = dev->mode_config.max_width; + height = dev->mode_config.max_height; +@@ -475,7 +526,7 @@ static void drm_setup_crtcs(struct drm_device *dev) + if (!ret) + DRM_ERROR("Unable to find initial modes\n"); + +- DRM_DEBUG("picking CRTCs for %dx%d config\n", width, height); ++ DRM_DEBUG_KMS("picking CRTCs for %dx%d config\n", width, height); + + drm_pick_crtcs(dev, crtcs, modes, 0, width, height); + +@@ -490,12 +541,14 @@ static void drm_setup_crtcs(struct drm_device *dev) + } + + if (mode && crtc) { +- DRM_DEBUG("desired mode %s set on crtc %d\n", ++ DRM_DEBUG_KMS("desired mode %s set on crtc %d\n", + mode->name, crtc->base.id); + crtc->desired_mode = mode; + connector->encoder->crtc = crtc; +- } else ++ } else { + connector->encoder->crtc = NULL; ++ connector->encoder = NULL; ++ } + i++; + } + +@@ -702,18 +755,17 @@ EXPORT_SYMBOL(drm_crtc_helper_set_mode); + int drm_crtc_helper_set_config(struct drm_mode_set *set) + { + struct drm_device *dev; +- struct drm_crtc **save_crtcs, *new_crtc; +- struct drm_encoder **save_encoders, *new_encoder; ++ struct drm_crtc *save_crtcs, *new_crtc, *crtc; ++ struct drm_encoder *save_encoders, *new_encoder, *encoder; + struct drm_framebuffer *old_fb = NULL; +- bool save_enabled; + bool mode_changed = false; /* if true do a full mode set */ + bool fb_changed = false; /* if true and !mode_changed just do a flip */ +- struct drm_connector *connector; ++ struct drm_connector *save_connectors, *connector; + int count = 0, ro, fail = 0; + struct drm_crtc_helper_funcs *crtc_funcs; + int ret = 0; + +- DRM_DEBUG("\n"); ++ DRM_DEBUG_KMS("\n"); + + if (!set) + return -EINVAL; +@@ -726,37 +778,60 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + + crtc_funcs = set->crtc->helper_private; + +- DRM_DEBUG("crtc: %p %d fb: %p connectors: %p num_connectors: %d (x, y) (%i, %i)\n", ++ DRM_DEBUG_KMS("crtc: %p %d fb: %p connectors: %p num_connectors:" ++ " %d (x, y) (%i, %i)\n", + set->crtc, set->crtc->base.id, set->fb, set->connectors, + (int)set->num_connectors, set->x, set->y); + + dev = set->crtc->dev; + +- /* save previous config */ +- save_enabled = set->crtc->enabled; +- +- /* +- * We do mode_config.num_connectors here since we'll look at the +- * CRTC and encoder associated with each connector later. +- */ +- save_crtcs = kzalloc(dev->mode_config.num_connector * +- sizeof(struct drm_crtc *), GFP_KERNEL); ++ /* Allocate space for the backup of all (non-pointer) crtc, encoder and ++ * connector data. */ ++ save_crtcs = kzalloc(dev->mode_config.num_crtc * ++ sizeof(struct drm_crtc), GFP_KERNEL); + if (!save_crtcs) + return -ENOMEM; + +- save_encoders = kzalloc(dev->mode_config.num_connector * +- sizeof(struct drm_encoders *), GFP_KERNEL); ++ save_encoders = kzalloc(dev->mode_config.num_encoder * ++ sizeof(struct drm_encoder), GFP_KERNEL); + if (!save_encoders) { + kfree(save_crtcs); + return -ENOMEM; + } + ++ save_connectors = kzalloc(dev->mode_config.num_connector * ++ sizeof(struct drm_connector), GFP_KERNEL); ++ if (!save_connectors) { ++ kfree(save_crtcs); ++ kfree(save_encoders); ++ return -ENOMEM; ++ } ++ ++ /* Copy data. Note that driver private data is not affected. ++ * Should anything bad happen only the expected state is ++ * restored, not the drivers personal bookkeeping. ++ */ ++ count = 0; ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ save_crtcs[count++] = *crtc; ++ } ++ ++ count = 0; ++ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ++ save_encoders[count++] = *encoder; ++ } ++ ++ count = 0; ++ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { ++ save_connectors[count++] = *connector; ++ } ++ + /* We should be able to check here if the fb has the same properties + * and then just flip_or_move it */ + if (set->crtc->fb != set->fb) { + /* If we have no fb then treat it as a full mode set */ + if (set->crtc->fb == NULL) { +- DRM_DEBUG("crtc has no fb, full mode set\n"); ++ DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); + mode_changed = true; + } else if (set->fb == NULL) { + mode_changed = true; +@@ -772,7 +847,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + fb_changed = true; + + if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { +- DRM_DEBUG("modes are different, full mode set\n"); ++ DRM_DEBUG_KMS("modes are different, full mode set\n"); + drm_mode_debug_printmodeline(&set->crtc->mode); + drm_mode_debug_printmodeline(set->mode); + mode_changed = true; +@@ -783,7 +858,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + struct drm_connector_helper_funcs *connector_funcs = + connector->helper_private; +- save_encoders[count++] = connector->encoder; + new_encoder = connector->encoder; + for (ro = 0; ro < set->num_connectors; ro++) { + if (set->connectors[ro] == connector) { +@@ -798,15 +872,20 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + } + + if (new_encoder != connector->encoder) { +- DRM_DEBUG("encoder changed, full mode switch\n"); ++ DRM_DEBUG_KMS("encoder changed, full mode switch\n"); + mode_changed = true; ++ /* If the encoder is reused for another connector, then ++ * the appropriate crtc will be set later. ++ */ ++ if (connector->encoder) ++ connector->encoder->crtc = NULL; + connector->encoder = new_encoder; + } + } + + if (fail) { + ret = -EINVAL; +- goto fail_no_encoder; ++ goto fail; + } + + count = 0; +@@ -814,8 +893,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + if (!connector->encoder) + continue; + +- save_crtcs[count++] = connector->encoder->crtc; +- + if (connector->encoder->crtc == set->crtc) + new_crtc = NULL; + else +@@ -830,14 +907,14 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + if (new_crtc && + !drm_encoder_crtc_ok(connector->encoder, new_crtc)) { + ret = -EINVAL; +- goto fail_set_mode; ++ goto fail; + } + if (new_crtc != connector->encoder->crtc) { +- DRM_DEBUG("crtc changed, full mode switch\n"); ++ DRM_DEBUG_KMS("crtc changed, full mode switch\n"); + mode_changed = true; + connector->encoder->crtc = new_crtc; + } +- DRM_DEBUG("setting connector %d crtc to %p\n", ++ DRM_DEBUG_KMS("setting connector %d crtc to %p\n", + connector->base.id, new_crtc); + } + +@@ -850,7 +927,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + set->crtc->fb = set->fb; + set->crtc->enabled = (set->mode != NULL); + if (set->mode != NULL) { +- DRM_DEBUG("attempting to set mode from userspace\n"); ++ DRM_DEBUG_KMS("attempting to set mode from" ++ " userspace\n"); + drm_mode_debug_printmodeline(set->mode); + if (!drm_crtc_helper_set_mode(set->crtc, set->mode, + set->x, set->y, +@@ -858,7 +936,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + DRM_ERROR("failed to set mode on crtc %p\n", + set->crtc); + ret = -EINVAL; +- goto fail_set_mode; ++ goto fail; + } + /* TODO are these needed? */ + set->crtc->desired_x = set->x; +@@ -867,43 +945,50 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) + } + drm_helper_disable_unused_functions(dev); + } else if (fb_changed) { ++ set->crtc->x = set->x; ++ set->crtc->y = set->y; ++ + old_fb = set->crtc->fb; + if (set->crtc->fb != set->fb) + set->crtc->fb = set->fb; + ret = crtc_funcs->mode_set_base(set->crtc, + set->x, set->y, old_fb); + if (ret != 0) +- goto fail_set_mode; ++ goto fail; + } + ++ kfree(save_connectors); + kfree(save_encoders); + kfree(save_crtcs); + return 0; + +-fail_set_mode: +- set->crtc->enabled = save_enabled; +- set->crtc->fb = old_fb; ++fail: ++ /* Restore all previous data. */ + count = 0; +- list_for_each_entry(connector, &dev->mode_config.connector_list, head) { +- if (!connector->encoder) +- continue; ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ *crtc = save_crtcs[count++]; ++ } + +- connector->encoder->crtc = save_crtcs[count++]; ++ count = 0; ++ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ++ *encoder = save_encoders[count++]; + } +-fail_no_encoder: +- kfree(save_crtcs); ++ + count = 0; + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { +- connector->encoder = save_encoders[count++]; ++ *connector = save_connectors[count++]; + } ++ ++ kfree(save_connectors); + kfree(save_encoders); ++ kfree(save_crtcs); + return ret; + } + EXPORT_SYMBOL(drm_crtc_helper_set_config); + + bool drm_helper_plugged_event(struct drm_device *dev) + { +- DRM_DEBUG("\n"); ++ DRM_DEBUG_KMS("\n"); + + drm_helper_probe_connector_modes(dev, dev->mode_config.max_width, + dev->mode_config.max_height); +@@ -932,24 +1017,18 @@ bool drm_helper_plugged_event(struct drm_device *dev) + */ + bool drm_helper_initial_config(struct drm_device *dev) + { +- struct drm_connector *connector; + int count = 0; + ++ drm_fb_helper_parse_command_line(dev); ++ + count = drm_helper_probe_connector_modes(dev, + dev->mode_config.max_width, + dev->mode_config.max_height); + + /* +- * None of the available connectors had any modes, so add some +- * and try to light them up anyway ++ * we shouldn't end up with no modes here. + */ +- if (!count) { +- DRM_ERROR("connectors have no modes, using standard modes\n"); +- list_for_each_entry(connector, +- &dev->mode_config.connector_list, +- head) +- drm_helper_add_std_modes(dev, connector); +- } ++ WARN(!count, "No connectors reported connected with modes\n"); + + drm_setup_crtcs(dev); + +diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c +index b39d7bf..a75ca63 100644 +--- a/drivers/gpu/drm/drm_drv.c ++++ b/drivers/gpu/drm/drm_drv.c +@@ -63,12 +63,12 @@ static struct drm_ioctl_desc drm_ioctls[] = { + DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, 0), + DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, 0), + DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, 0), +- DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER|DRM_ROOT_ONLY), ++ DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER), + + DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), +- DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), ++ DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER), + + DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_rmmap_ioctl, DRM_AUTH), +diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c +index 7f2728b..3c0d2b3 100644 +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -60,6 +60,12 @@ + #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) + /* use +hsync +vsync for detailed mode */ + #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) ++/* define the number of Extension EDID block */ ++#define MAX_EDID_EXT_NUM 4 ++ ++#define LEVEL_DMT 0 ++#define LEVEL_GTF 1 ++#define LEVEL_CVT 2 + + static struct edid_quirk { + char *vendor; +@@ -103,7 +109,9 @@ static struct edid_quirk { + + + /* Valid EDID header has these bytes */ +-static u8 edid_header[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; ++static const u8 edid_header[] = { ++ 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 ++}; + + /** + * edid_is_valid - sanity check EDID data +@@ -237,39 +245,345 @@ static void edid_fixup_preferred(struct drm_connector *connector, + preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; + } + ++/* ++ * Add the Autogenerated from the DMT spec. ++ * This table is copied from xfree86/modes/xf86EdidModes.c. ++ * But the mode with Reduced blank feature is deleted. ++ */ ++static struct drm_display_mode drm_dmt_modes[] = { ++ /* 640x350@85Hz */ ++ { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, ++ 736, 832, 0, 350, 382, 385, 445, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 640x400@85Hz */ ++ { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, ++ 736, 832, 0, 400, 401, 404, 445, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 720x400@85Hz */ ++ { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, ++ 828, 936, 0, 400, 401, 404, 446, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 640x480@60Hz */ ++ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, ++ 752, 800, 0, 480, 489, 492, 525, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 640x480@72Hz */ ++ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, ++ 704, 832, 0, 480, 489, 492, 520, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 640x480@75Hz */ ++ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, ++ 720, 840, 0, 480, 481, 484, 500, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 640x480@85Hz */ ++ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, ++ 752, 832, 0, 480, 481, 484, 509, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 800x600@56Hz */ ++ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, ++ 896, 1024, 0, 600, 601, 603, 625, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 800x600@60Hz */ ++ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, ++ 968, 1056, 0, 600, 601, 605, 628, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 800x600@72Hz */ ++ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, ++ 976, 1040, 0, 600, 637, 643, 666, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 800x600@75Hz */ ++ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, ++ 896, 1056, 0, 600, 601, 604, 625, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 800x600@85Hz */ ++ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, ++ 896, 1048, 0, 600, 601, 604, 631, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 848x480@60Hz */ ++ { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, ++ 976, 1088, 0, 480, 486, 494, 517, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1024x768@43Hz, interlace */ ++ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, ++ 1208, 1264, 0, 768, 768, 772, 817, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | ++ DRM_MODE_FLAG_INTERLACE) }, ++ /* 1024x768@60Hz */ ++ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, ++ 1184, 1344, 0, 768, 771, 777, 806, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 1024x768@70Hz */ ++ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, ++ 1184, 1328, 0, 768, 771, 777, 806, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 1024x768@75Hz */ ++ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, ++ 1136, 1312, 0, 768, 769, 772, 800, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1024x768@85Hz */ ++ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, ++ 1072, 1376, 0, 768, 769, 772, 808, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1152x864@75Hz */ ++ { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, ++ 1344, 1600, 0, 864, 865, 868, 900, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x768@60Hz */ ++ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, ++ 1472, 1664, 0, 768, 771, 778, 798, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x768@75Hz */ ++ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, ++ 1488, 1696, 0, 768, 771, 778, 805, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 1280x768@85Hz */ ++ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, ++ 1496, 1712, 0, 768, 771, 778, 809, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x800@60Hz */ ++ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, ++ 1480, 1680, 0, 800, 803, 809, 831, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, ++ /* 1280x800@75Hz */ ++ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, ++ 1488, 1696, 0, 800, 803, 809, 838, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x800@85Hz */ ++ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, ++ 1496, 1712, 0, 800, 803, 809, 843, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x960@60Hz */ ++ { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, ++ 1488, 1800, 0, 960, 961, 964, 1000, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x960@85Hz */ ++ { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, ++ 1504, 1728, 0, 960, 961, 964, 1011, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x1024@60Hz */ ++ { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, ++ 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x1024@75Hz */ ++ { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, ++ 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1280x1024@85Hz */ ++ { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, ++ 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1360x768@60Hz */ ++ { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, ++ 1536, 1792, 0, 768, 771, 777, 795, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1440x1050@60Hz */ ++ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, ++ 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1440x1050@75Hz */ ++ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, ++ 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1440x1050@85Hz */ ++ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, ++ 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1440x900@60Hz */ ++ { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, ++ 1672, 1904, 0, 900, 903, 909, 934, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1440x900@75Hz */ ++ { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, ++ 1688, 1936, 0, 900, 903, 909, 942, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1440x900@85Hz */ ++ { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, ++ 1696, 1952, 0, 900, 903, 909, 948, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1600x1200@60Hz */ ++ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, ++ 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1600x1200@65Hz */ ++ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, ++ 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1600x1200@70Hz */ ++ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, ++ 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1600x1200@75Hz */ ++ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664, ++ 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1600x1200@85Hz */ ++ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, ++ 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1680x1050@60Hz */ ++ { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, ++ 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1680x1050@75Hz */ ++ { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, ++ 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1680x1050@85Hz */ ++ { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, ++ 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1792x1344@60Hz */ ++ { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, ++ 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1729x1344@75Hz */ ++ { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, ++ 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1853x1392@60Hz */ ++ { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, ++ 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1856x1392@75Hz */ ++ { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, ++ 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1920x1200@60Hz */ ++ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, ++ 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1920x1200@75Hz */ ++ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, ++ 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1920x1200@85Hz */ ++ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, ++ 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1920x1440@60Hz */ ++ { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, ++ 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 1920x1440@75Hz */ ++ { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, ++ 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 2560x1600@60Hz */ ++ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, ++ 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 2560x1600@75HZ */ ++ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, ++ 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++ /* 2560x1600@85HZ */ ++ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, ++ 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, ++}; ++ ++static struct drm_display_mode *drm_find_dmt(struct drm_device *dev, ++ int hsize, int vsize, int fresh) ++{ ++ int i, count; ++ struct drm_display_mode *ptr, *mode; ++ ++ count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); ++ mode = NULL; ++ for (i = 0; i < count; i++) { ++ ptr = &drm_dmt_modes[i]; ++ if (hsize == ptr->hdisplay && ++ vsize == ptr->vdisplay && ++ fresh == drm_mode_vrefresh(ptr)) { ++ /* get the expected default mode */ ++ mode = drm_mode_duplicate(dev, ptr); ++ break; ++ } ++ } ++ return mode; ++} ++ ++/* ++ * 0 is reserved. The spec says 0x01 fill for unused timings. Some old ++ * monitors fill with ascii space (0x20) instead. ++ */ ++static int ++bad_std_timing(u8 a, u8 b) ++{ ++ return (a == 0x00 && b == 0x00) || ++ (a == 0x01 && b == 0x01) || ++ (a == 0x20 && b == 0x20); ++} ++ + /** + * drm_mode_std - convert standard mode info (width, height, refresh) into mode + * @t: standard timing params ++ * @timing_level: standard timing level + * + * Take the standard timing params (in this case width, aspect, and refresh) +- * and convert them into a real mode using CVT. ++ * and convert them into a real mode using CVT/GTF/DMT. + * + * Punts for now, but should eventually use the FB layer's CVT based mode + * generation code. + */ + struct drm_display_mode *drm_mode_std(struct drm_device *dev, +- struct std_timing *t) ++ struct std_timing *t, ++ int revision, ++ int timing_level) + { + struct drm_display_mode *mode; +- int hsize = t->hsize * 8 + 248, vsize; ++ int hsize, vsize; ++ int vrefresh_rate; + unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) + >> EDID_TIMING_ASPECT_SHIFT; ++ unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) ++ >> EDID_TIMING_VFREQ_SHIFT; + +- mode = drm_mode_create(dev); +- if (!mode) ++ if (bad_std_timing(t->hsize, t->vfreq_aspect)) + return NULL; + +- if (aspect_ratio == 0) +- vsize = (hsize * 10) / 16; +- else if (aspect_ratio == 1) ++ /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ ++ hsize = t->hsize * 8 + 248; ++ /* vrefresh_rate = vfreq + 60 */ ++ vrefresh_rate = vfreq + 60; ++ /* the vdisplay is calculated based on the aspect ratio */ ++ if (aspect_ratio == 0) { ++ if (revision < 3) ++ vsize = hsize; ++ else ++ vsize = (hsize * 10) / 16; ++ } else if (aspect_ratio == 1) + vsize = (hsize * 3) / 4; + else if (aspect_ratio == 2) + vsize = (hsize * 4) / 5; + else + vsize = (hsize * 9) / 16; +- +- drm_mode_set_name(mode); +- ++ /* HDTV hack */ ++ if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) { ++ mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, ++ false); ++ mode->hdisplay = 1366; ++ mode->vsync_start = mode->vsync_start - 1; ++ mode->vsync_end = mode->vsync_end - 1; ++ return mode; ++ } ++ mode = NULL; ++ /* check whether it can be found in default mode table */ ++ mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate); ++ if (mode) ++ return mode; ++ ++ switch (timing_level) { ++ case LEVEL_DMT: ++ break; ++ case LEVEL_GTF: ++ mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); ++ break; ++ case LEVEL_CVT: ++ mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, ++ false); ++ break; ++ } + return mode; + } + +@@ -451,6 +765,19 @@ static int add_established_modes(struct drm_connector *connector, struct edid *e + + return modes; + } ++/** ++ * stanard_timing_level - get std. timing level(CVT/GTF/DMT) ++ * @edid: EDID block to scan ++ */ ++static int standard_timing_level(struct edid *edid) ++{ ++ if (edid->revision >= 2) { ++ if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) ++ return LEVEL_CVT; ++ return LEVEL_GTF; ++ } ++ return LEVEL_DMT; ++} + + /** + * add_standard_modes - get std. modes from EDID and add them +@@ -463,6 +790,9 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid + { + struct drm_device *dev = connector->dev; + int i, modes = 0; ++ int timing_level; ++ ++ timing_level = standard_timing_level(edid); + + for (i = 0; i < EDID_STD_TIMINGS; i++) { + struct std_timing *t = &edid->standard_timings[i]; +@@ -472,7 +802,8 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid + if (t->hsize == 1 && t->vfreq_aspect == 1) + continue; + +- newmode = drm_mode_std(dev, &edid->standard_timings[i]); ++ newmode = drm_mode_std(dev, &edid->standard_timings[i], ++ edid->revision, timing_level); + if (newmode) { + drm_mode_probed_add(connector, newmode); + modes++; +@@ -496,6 +827,9 @@ static int add_detailed_info(struct drm_connector *connector, + { + struct drm_device *dev = connector->dev; + int i, j, modes = 0; ++ int timing_level; ++ ++ timing_level = standard_timing_level(edid); + + for (i = 0; i < EDID_DETAILED_TIMINGS; i++) { + struct detailed_timing *timing = &edid->detailed_timings[i]; +@@ -519,13 +853,14 @@ static int add_detailed_info(struct drm_connector *connector, + case EDID_DETAIL_MONITOR_CPDATA: + break; + case EDID_DETAIL_STD_MODES: +- /* Five modes per detailed section */ +- for (j = 0; j < 5; i++) { ++ for (j = 0; j < 6; i++) { + struct std_timing *std; + struct drm_display_mode *newmode; + + std = &data->data.timings[j]; +- newmode = drm_mode_std(dev, std); ++ newmode = drm_mode_std(dev, std, ++ edid->revision, ++ timing_level); + if (newmode) { + drm_mode_probed_add(connector, newmode); + modes++; +@@ -551,6 +886,124 @@ static int add_detailed_info(struct drm_connector *connector, + + return modes; + } ++/** ++ * add_detailed_mode_eedid - get detailed mode info from addtional timing ++ * EDID block ++ * @connector: attached connector ++ * @edid: EDID block to scan(It is only to get addtional timing EDID block) ++ * @quirks: quirks to apply ++ * ++ * Some of the detailed timing sections may contain mode information. Grab ++ * it and add it to the list. ++ */ ++static int add_detailed_info_eedid(struct drm_connector *connector, ++ struct edid *edid, u32 quirks) ++{ ++ struct drm_device *dev = connector->dev; ++ int i, j, modes = 0; ++ char *edid_ext = NULL; ++ struct detailed_timing *timing; ++ struct detailed_non_pixel *data; ++ struct drm_display_mode *newmode; ++ int edid_ext_num; ++ int start_offset, end_offset; ++ int timing_level; ++ ++ if (edid->version == 1 && edid->revision < 3) { ++ /* If the EDID version is less than 1.3, there is no ++ * extension EDID. ++ */ ++ return 0; ++ } ++ if (!edid->extensions) { ++ /* if there is no extension EDID, it is unnecessary to ++ * parse the E-EDID to get detailed info ++ */ ++ return 0; ++ } ++ ++ /* Chose real EDID extension number */ ++ edid_ext_num = edid->extensions > MAX_EDID_EXT_NUM ? ++ MAX_EDID_EXT_NUM : edid->extensions; ++ ++ /* Find CEA extension */ ++ for (i = 0; i < edid_ext_num; i++) { ++ edid_ext = (char *)edid + EDID_LENGTH * (i + 1); ++ /* This block is CEA extension */ ++ if (edid_ext[0] == 0x02) ++ break; ++ } ++ ++ if (i == edid_ext_num) { ++ /* if there is no additional timing EDID block, return */ ++ return 0; ++ } ++ ++ /* Get the start offset of detailed timing block */ ++ start_offset = edid_ext[2]; ++ if (start_offset == 0) { ++ /* If the start_offset is zero, it means that neither detailed ++ * info nor data block exist. In such case it is also ++ * unnecessary to parse the detailed timing info. ++ */ ++ return 0; ++ } ++ ++ timing_level = standard_timing_level(edid); ++ end_offset = EDID_LENGTH; ++ end_offset -= sizeof(struct detailed_timing); ++ for (i = start_offset; i < end_offset; ++ i += sizeof(struct detailed_timing)) { ++ timing = (struct detailed_timing *)(edid_ext + i); ++ data = &timing->data.other_data; ++ /* Detailed mode timing */ ++ if (timing->pixel_clock) { ++ newmode = drm_mode_detailed(dev, edid, timing, quirks); ++ if (!newmode) ++ continue; ++ ++ drm_mode_probed_add(connector, newmode); ++ ++ modes++; ++ continue; ++ } ++ ++ /* Other timing or info */ ++ switch (data->type) { ++ case EDID_DETAIL_MONITOR_SERIAL: ++ break; ++ case EDID_DETAIL_MONITOR_STRING: ++ break; ++ case EDID_DETAIL_MONITOR_RANGE: ++ /* Get monitor range data */ ++ break; ++ case EDID_DETAIL_MONITOR_NAME: ++ break; ++ case EDID_DETAIL_MONITOR_CPDATA: ++ break; ++ case EDID_DETAIL_STD_MODES: ++ /* Five modes per detailed section */ ++ for (j = 0; j < 5; i++) { ++ struct std_timing *std; ++ struct drm_display_mode *newmode; ++ ++ std = &data->data.timings[j]; ++ newmode = drm_mode_std(dev, std, ++ edid->revision, ++ timing_level); ++ if (newmode) { ++ drm_mode_probed_add(connector, newmode); ++ modes++; ++ } ++ } ++ break; ++ default: ++ break; ++ } ++ } ++ ++ return modes; ++} + + #define DDC_ADDR 0x50 + /** +@@ -584,7 +1037,6 @@ int drm_do_probe_ddc_edid(struct i2c_adapter *adapter, + if (i2c_transfer(adapter, msgs, 2) == 2) + return 0; + +- dev_info(&adapter->dev, "unable to read EDID block.\n"); + return -1; + } + EXPORT_SYMBOL(drm_do_probe_ddc_edid); +@@ -597,8 +1049,6 @@ static int drm_ddc_read_edid(struct drm_connector *connector, + + ret = drm_do_probe_ddc_edid(adapter, buf, len); + if (ret != 0) { +- dev_info(&connector->dev->pdev->dev, "%s: no EDID data\n", +- drm_get_connector_name(connector)); + goto end; + } + if (!edid_is_valid((struct edid *)buf)) { +@@ -610,7 +1060,6 @@ end: + return ret; + } + +-#define MAX_EDID_EXT_NUM 4 + /** + * drm_get_edid - get EDID data, if available + * @connector: connector we're probing +@@ -763,6 +1212,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) + num_modes += add_established_modes(connector, edid); + num_modes += add_standard_modes(connector, edid); + num_modes += add_detailed_info(connector, edid, quirks); ++ num_modes += add_detailed_info_eedid(connector, edid, quirks); + + if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) + edid_fixup_preferred(connector, quirks); +@@ -788,3 +1238,49 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) + return num_modes; + } + EXPORT_SYMBOL(drm_add_edid_modes); ++ ++/** ++ * drm_add_modes_noedid - add modes for the connectors without EDID ++ * @connector: connector we're probing ++ * @hdisplay: the horizontal display limit ++ * @vdisplay: the vertical display limit ++ * ++ * Add the specified modes to the connector's mode list. Only when the ++ * hdisplay/vdisplay is not beyond the given limit, it will be added. ++ * ++ * Return number of modes added or 0 if we couldn't find any. ++ */ ++int drm_add_modes_noedid(struct drm_connector *connector, ++ int hdisplay, int vdisplay) ++{ ++ int i, count, num_modes = 0; ++ struct drm_display_mode *mode, *ptr; ++ struct drm_device *dev = connector->dev; ++ ++ count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); ++ if (hdisplay < 0) ++ hdisplay = 0; ++ if (vdisplay < 0) ++ vdisplay = 0; ++ ++ for (i = 0; i < count; i++) { ++ ptr = &drm_dmt_modes[i]; ++ if (hdisplay && vdisplay) { ++ /* ++ * Only when two are valid, they will be used to check ++ * whether the mode should be added to the mode list of ++ * the connector. ++ */ ++ if (ptr->hdisplay > hdisplay || ++ ptr->vdisplay > vdisplay) ++ continue; ++ } ++ mode = drm_mode_duplicate(dev, ptr); ++ if (mode) { ++ drm_mode_probed_add(connector, mode); ++ num_modes++; ++ } ++ } ++ return num_modes; ++} ++EXPORT_SYMBOL(drm_add_modes_noedid); +diff --git a/drivers/gpu/drm/drm_encoder_slave.c b/drivers/gpu/drm/drm_encoder_slave.c +new file mode 100644 +index 0000000..f018469 +--- /dev/null ++++ b/drivers/gpu/drm/drm_encoder_slave.c +@@ -0,0 +1,116 @@ ++/* ++ * Copyright (C) 2009 Francisco Jerez. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining ++ * a copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sublicense, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial ++ * portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE ++ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION ++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#include "drm_encoder_slave.h" ++ ++/** ++ * drm_i2c_encoder_init - Initialize an I2C slave encoder ++ * @dev: DRM device. ++ * @encoder: Encoder to be attached to the I2C device. You aren't ++ * required to have called drm_encoder_init() before. ++ * @adap: I2C adapter that will be used to communicate with ++ * the device. ++ * @info: Information that will be used to create the I2C device. ++ * Required fields are @addr and @type. ++ * ++ * Create an I2C device on the specified bus (the module containing its ++ * driver is transparently loaded) and attach it to the specified ++ * &drm_encoder_slave. The @slave_funcs field will be initialized with ++ * the hooks provided by the slave driver. ++ * ++ * Returns 0 on success or a negative errno on failure, in particular, ++ * -ENODEV is returned when no matching driver is found. ++ */ ++int drm_i2c_encoder_init(struct drm_device *dev, ++ struct drm_encoder_slave *encoder, ++ struct i2c_adapter *adap, ++ const struct i2c_board_info *info) ++{ ++ char modalias[sizeof(I2C_MODULE_PREFIX) ++ + I2C_NAME_SIZE]; ++ struct module *module = NULL; ++ struct i2c_client *client; ++ struct drm_i2c_encoder_driver *encoder_drv; ++ int err = 0; ++ ++ snprintf(modalias, sizeof(modalias), ++ "%s%s", I2C_MODULE_PREFIX, info->type); ++ request_module(modalias); ++ ++ client = i2c_new_device(adap, info); ++ if (!client) { ++ err = -ENOMEM; ++ goto fail; ++ } ++ ++ if (!client->driver) { ++ err = -ENODEV; ++ goto fail_unregister; ++ } ++ ++ module = client->driver->driver.owner; ++ if (!try_module_get(module)) { ++ err = -ENODEV; ++ goto fail_unregister; ++ } ++ ++ encoder->bus_priv = client; ++ ++ encoder_drv = to_drm_i2c_encoder_driver(client->driver); ++ ++ err = encoder_drv->encoder_init(client, dev, encoder); ++ if (err) ++ goto fail_unregister; ++ ++ return 0; ++ ++fail_unregister: ++ i2c_unregister_device(client); ++ module_put(module); ++fail: ++ return err; ++} ++EXPORT_SYMBOL(drm_i2c_encoder_init); ++ ++/** ++ * drm_i2c_encoder_destroy - Unregister the I2C device backing an encoder ++ * @drm_encoder: Encoder to be unregistered. ++ * ++ * This should be called from the @destroy method of an I2C slave ++ * encoder driver once I2C access is no longer needed. ++ */ ++void drm_i2c_encoder_destroy(struct drm_encoder *drm_encoder) ++{ ++ struct drm_encoder_slave *encoder = to_encoder_slave(drm_encoder); ++ struct i2c_client *client = drm_i2c_encoder_get_client(drm_encoder); ++ struct module *module = client->driver->driver.owner; ++ ++ i2c_unregister_device(client); ++ encoder->bus_priv = NULL; ++ ++ module_put(module); ++} ++EXPORT_SYMBOL(drm_i2c_encoder_destroy); +diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c +new file mode 100644 +index 0000000..819ddcb +--- /dev/null ++++ b/drivers/gpu/drm/drm_fb_helper.c +@@ -0,0 +1,940 @@ ++/* ++ * Copyright (c) 2006-2009 Red Hat Inc. ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> ++ * ++ * DRM framebuffer helper functions ++ * ++ * Permission to use, copy, modify, distribute, and sell this software and its ++ * documentation for any purpose is hereby granted without fee, provided that ++ * the above copyright notice appear in all copies and that both that copyright ++ * notice and this permission notice appear in supporting documentation, and ++ * that the name of the copyright holders not be used in advertising or ++ * publicity pertaining to distribution of the software without specific, ++ * written prior permission. The copyright holders make no representations ++ * about the suitability of this software for any purpose. It is provided "as ++ * is" without express or implied warranty. ++ * ++ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, ++ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO ++ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR ++ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, ++ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER ++ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE ++ * OF THIS SOFTWARE. ++ * ++ * Authors: ++ * Dave Airlie <airlied@linux.ie> ++ * Jesse Barnes <jesse.barnes@intel.com> ++ */ ++#include <linux/sysrq.h> ++#include <linux/fb.h> ++#include "drmP.h" ++#include "drm_crtc.h" ++#include "drm_fb_helper.h" ++#include "drm_crtc_helper.h" ++ ++MODULE_AUTHOR("David Airlie, Jesse Barnes"); ++MODULE_DESCRIPTION("DRM KMS helper"); ++MODULE_LICENSE("GPL and additional rights"); ++ ++static LIST_HEAD(kernel_fb_helper_list); ++ ++int drm_fb_helper_add_connector(struct drm_connector *connector) ++{ ++ connector->fb_helper_private = kzalloc(sizeof(struct drm_fb_helper_connector), GFP_KERNEL); ++ if (!connector->fb_helper_private) ++ return -ENOMEM; ++ ++ return 0; ++} ++EXPORT_SYMBOL(drm_fb_helper_add_connector); ++ ++static int my_atoi(const char *name) ++{ ++ int val = 0; ++ ++ for (;; name++) { ++ switch (*name) { ++ case '0' ... '9': ++ val = 10*val+(*name-'0'); ++ break; ++ default: ++ return val; ++ } ++ } ++} ++ ++/** ++ * drm_fb_helper_connector_parse_command_line - parse command line for connector ++ * @connector - connector to parse line for ++ * @mode_option - per connector mode option ++ * ++ * This parses the connector specific then generic command lines for ++ * modes and options to configure the connector. ++ * ++ * This uses the same parameters as the fb modedb.c, except for extra ++ * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd] ++ * ++ * enable/enable Digital/disable bit at the end ++ */ ++static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *connector, ++ const char *mode_option) ++{ ++ const char *name; ++ unsigned int namelen; ++ int res_specified = 0, bpp_specified = 0, refresh_specified = 0; ++ unsigned int xres = 0, yres = 0, bpp = 32, refresh = 0; ++ int yres_specified = 0, cvt = 0, rb = 0, interlace = 0, margins = 0; ++ int i; ++ enum drm_connector_force force = DRM_FORCE_UNSPECIFIED; ++ struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; ++ struct drm_fb_helper_cmdline_mode *cmdline_mode; ++ ++ if (!fb_help_conn) ++ return false; ++ ++ cmdline_mode = &fb_help_conn->cmdline_mode; ++ if (!mode_option) ++ mode_option = fb_mode_option; ++ ++ if (!mode_option) { ++ cmdline_mode->specified = false; ++ return false; ++ } ++ ++ name = mode_option; ++ namelen = strlen(name); ++ for (i = namelen-1; i >= 0; i--) { ++ switch (name[i]) { ++ case '@': ++ namelen = i; ++ if (!refresh_specified && !bpp_specified && ++ !yres_specified) { ++ refresh = my_atoi(&name[i+1]); ++ refresh_specified = 1; ++ if (cvt || rb) ++ cvt = 0; ++ } else ++ goto done; ++ break; ++ case '-': ++ namelen = i; ++ if (!bpp_specified && !yres_specified) { ++ bpp = my_atoi(&name[i+1]); ++ bpp_specified = 1; ++ if (cvt || rb) ++ cvt = 0; ++ } else ++ goto done; ++ break; ++ case 'x': ++ if (!yres_specified) { ++ yres = my_atoi(&name[i+1]); ++ yres_specified = 1; ++ } else ++ goto done; ++ case '0' ... '9': ++ break; ++ case 'M': ++ if (!yres_specified) ++ cvt = 1; ++ break; ++ case 'R': ++ if (!cvt) ++ rb = 1; ++ break; ++ case 'm': ++ if (!cvt) ++ margins = 1; ++ break; ++ case 'i': ++ if (!cvt) ++ interlace = 1; ++ break; ++ case 'e': ++ force = DRM_FORCE_ON; ++ break; ++ case 'D': ++ if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) || ++ (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB)) ++ force = DRM_FORCE_ON; ++ else ++ force = DRM_FORCE_ON_DIGITAL; ++ break; ++ case 'd': ++ force = DRM_FORCE_OFF; ++ break; ++ default: ++ goto done; ++ } ++ } ++ if (i < 0 && yres_specified) { ++ xres = my_atoi(name); ++ res_specified = 1; ++ } ++done: ++ ++ DRM_DEBUG_KMS("cmdline mode for connector %s %dx%d@%dHz%s%s%s\n", ++ drm_get_connector_name(connector), xres, yres, ++ (refresh) ? refresh : 60, (rb) ? " reduced blanking" : ++ "", (margins) ? " with margins" : "", (interlace) ? ++ " interlaced" : ""); ++ ++ if (force) { ++ const char *s; ++ switch (force) { ++ case DRM_FORCE_OFF: s = "OFF"; break; ++ case DRM_FORCE_ON_DIGITAL: s = "ON - dig"; break; ++ default: ++ case DRM_FORCE_ON: s = "ON"; break; ++ } ++ ++ DRM_INFO("forcing %s connector %s\n", ++ drm_get_connector_name(connector), s); ++ connector->force = force; ++ } ++ ++ if (res_specified) { ++ cmdline_mode->specified = true; ++ cmdline_mode->xres = xres; ++ cmdline_mode->yres = yres; ++ } ++ ++ if (refresh_specified) { ++ cmdline_mode->refresh_specified = true; ++ cmdline_mode->refresh = refresh; ++ } ++ ++ if (bpp_specified) { ++ cmdline_mode->bpp_specified = true; ++ cmdline_mode->bpp = bpp; ++ } ++ cmdline_mode->rb = rb ? true : false; ++ cmdline_mode->cvt = cvt ? true : false; ++ cmdline_mode->interlace = interlace ? true : false; ++ ++ return true; ++} ++ ++int drm_fb_helper_parse_command_line(struct drm_device *dev) ++{ ++ struct drm_connector *connector; ++ ++ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { ++ char *option = NULL; ++ ++ /* do something on return - turn off connector maybe */ ++ if (fb_get_options(drm_get_connector_name(connector), &option)) ++ continue; ++ ++ drm_fb_helper_connector_parse_command_line(connector, option); ++ } ++ return 0; ++} ++ ++bool drm_fb_helper_force_kernel_mode(void) ++{ ++ int i = 0; ++ bool ret, error = false; ++ struct drm_fb_helper *helper; ++ ++ if (list_empty(&kernel_fb_helper_list)) ++ return false; ++ ++ list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) { ++ for (i = 0; i < helper->crtc_count; i++) { ++ struct drm_mode_set *mode_set = &helper->crtc_info[i].mode_set; ++ ret = drm_crtc_helper_set_config(mode_set); ++ if (ret) ++ error = true; ++ } ++ } ++ return error; ++} ++ ++int drm_fb_helper_panic(struct notifier_block *n, unsigned long ununsed, ++ void *panic_str) ++{ ++ DRM_ERROR("panic occurred, switching back to text console\n"); ++ return drm_fb_helper_force_kernel_mode(); ++ return 0; ++} ++EXPORT_SYMBOL(drm_fb_helper_panic); ++ ++static struct notifier_block paniced = { ++ .notifier_call = drm_fb_helper_panic, ++}; ++ ++/** ++ * drm_fb_helper_restore - restore the framebuffer console (kernel) config ++ * ++ * Restore's the kernel's fbcon mode, used for lastclose & panic paths. ++ */ ++void drm_fb_helper_restore(void) ++{ ++ bool ret; ++ ret = drm_fb_helper_force_kernel_mode(); ++ if (ret == true) ++ DRM_ERROR("Failed to restore crtc configuration\n"); ++} ++EXPORT_SYMBOL(drm_fb_helper_restore); ++ ++#ifdef CONFIG_MAGIC_SYSRQ ++static void drm_fb_helper_restore_work_fn(struct work_struct *ignored) ++{ ++ drm_fb_helper_restore(); ++} ++static DECLARE_WORK(drm_fb_helper_restore_work, drm_fb_helper_restore_work_fn); ++ ++static void drm_fb_helper_sysrq(int dummy1, struct tty_struct *dummy3) ++{ ++ schedule_work(&drm_fb_helper_restore_work); ++} ++ ++static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { ++ .handler = drm_fb_helper_sysrq, ++ .help_msg = "force-fb(V)", ++ .action_msg = "Restore framebuffer console", ++}; ++#endif ++ ++static void drm_fb_helper_on(struct fb_info *info) ++{ ++ struct drm_fb_helper *fb_helper = info->par; ++ struct drm_device *dev = fb_helper->dev; ++ struct drm_crtc *crtc; ++ struct drm_encoder *encoder; ++ int i; ++ ++ /* ++ * For each CRTC in this fb, turn the crtc on then, ++ * find all associated encoders and turn them on. ++ */ ++ for (i = 0; i < fb_helper->crtc_count; i++) { ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ struct drm_crtc_helper_funcs *crtc_funcs = ++ crtc->helper_private; ++ ++ /* Only mess with CRTCs in this fb */ ++ if (crtc->base.id != fb_helper->crtc_info[i].crtc_id || ++ !crtc->enabled) ++ continue; ++ ++ mutex_lock(&dev->mode_config.mutex); ++ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); ++ mutex_unlock(&dev->mode_config.mutex); ++ ++ /* Found a CRTC on this fb, now find encoders */ ++ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ++ if (encoder->crtc == crtc) { ++ struct drm_encoder_helper_funcs *encoder_funcs; ++ ++ encoder_funcs = encoder->helper_private; ++ mutex_lock(&dev->mode_config.mutex); ++ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); ++ mutex_unlock(&dev->mode_config.mutex); ++ } ++ } ++ } ++ } ++} ++ ++static void drm_fb_helper_off(struct fb_info *info, int dpms_mode) ++{ ++ struct drm_fb_helper *fb_helper = info->par; ++ struct drm_device *dev = fb_helper->dev; ++ struct drm_crtc *crtc; ++ struct drm_encoder *encoder; ++ int i; ++ ++ /* ++ * For each CRTC in this fb, find all associated encoders ++ * and turn them off, then turn off the CRTC. ++ */ ++ for (i = 0; i < fb_helper->crtc_count; i++) { ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ struct drm_crtc_helper_funcs *crtc_funcs = ++ crtc->helper_private; ++ ++ /* Only mess with CRTCs in this fb */ ++ if (crtc->base.id != fb_helper->crtc_info[i].crtc_id || ++ !crtc->enabled) ++ continue; ++ ++ /* Found a CRTC on this fb, now find encoders */ ++ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ++ if (encoder->crtc == crtc) { ++ struct drm_encoder_helper_funcs *encoder_funcs; ++ ++ encoder_funcs = encoder->helper_private; ++ mutex_lock(&dev->mode_config.mutex); ++ encoder_funcs->dpms(encoder, dpms_mode); ++ mutex_unlock(&dev->mode_config.mutex); ++ } ++ } ++ if (dpms_mode == DRM_MODE_DPMS_OFF) { ++ mutex_lock(&dev->mode_config.mutex); ++ crtc_funcs->dpms(crtc, dpms_mode); ++ mutex_unlock(&dev->mode_config.mutex); ++ } ++ } ++ } ++} ++ ++int drm_fb_helper_blank(int blank, struct fb_info *info) ++{ ++ switch (blank) { ++ case FB_BLANK_UNBLANK: ++ drm_fb_helper_on(info); ++ break; ++ case FB_BLANK_NORMAL: ++ drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY); ++ break; ++ case FB_BLANK_HSYNC_SUSPEND: ++ drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY); ++ break; ++ case FB_BLANK_VSYNC_SUSPEND: ++ drm_fb_helper_off(info, DRM_MODE_DPMS_SUSPEND); ++ break; ++ case FB_BLANK_POWERDOWN: ++ drm_fb_helper_off(info, DRM_MODE_DPMS_OFF); ++ break; ++ } ++ return 0; ++} ++EXPORT_SYMBOL(drm_fb_helper_blank); ++ ++static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper) ++{ ++ int i; ++ ++ for (i = 0; i < helper->crtc_count; i++) ++ kfree(helper->crtc_info[i].mode_set.connectors); ++ kfree(helper->crtc_info); ++} ++ ++int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count, int max_conn_count) ++{ ++ struct drm_device *dev = helper->dev; ++ struct drm_crtc *crtc; ++ int ret = 0; ++ int i; ++ ++ helper->crtc_info = kcalloc(crtc_count, sizeof(struct drm_fb_helper_crtc), GFP_KERNEL); ++ if (!helper->crtc_info) ++ return -ENOMEM; ++ ++ helper->crtc_count = crtc_count; ++ ++ for (i = 0; i < crtc_count; i++) { ++ helper->crtc_info[i].mode_set.connectors = ++ kcalloc(max_conn_count, ++ sizeof(struct drm_connector *), ++ GFP_KERNEL); ++ ++ if (!helper->crtc_info[i].mode_set.connectors) { ++ ret = -ENOMEM; ++ goto out_free; ++ } ++ helper->crtc_info[i].mode_set.num_connectors = 0; ++ } ++ ++ i = 0; ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ helper->crtc_info[i].crtc_id = crtc->base.id; ++ helper->crtc_info[i].mode_set.crtc = crtc; ++ i++; ++ } ++ helper->conn_limit = max_conn_count; ++ return 0; ++out_free: ++ drm_fb_helper_crtc_free(helper); ++ return -ENOMEM; ++} ++EXPORT_SYMBOL(drm_fb_helper_init_crtc_count); ++ ++int drm_fb_helper_setcolreg(unsigned regno, ++ unsigned red, ++ unsigned green, ++ unsigned blue, ++ unsigned transp, ++ struct fb_info *info) ++{ ++ struct drm_fb_helper *fb_helper = info->par; ++ struct drm_device *dev = fb_helper->dev; ++ struct drm_crtc *crtc; ++ int i; ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ struct drm_framebuffer *fb = fb_helper->fb; ++ ++ for (i = 0; i < fb_helper->crtc_count; i++) { ++ if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) ++ break; ++ } ++ if (i == fb_helper->crtc_count) ++ continue; ++ ++ if (regno > 255) ++ return 1; ++ ++ if (fb->depth == 8) { ++ fb_helper->funcs->gamma_set(crtc, red, green, blue, regno); ++ return 0; ++ } ++ ++ if (regno < 16) { ++ switch (fb->depth) { ++ case 15: ++ fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | ++ ((green & 0xf800) >> 6) | ++ ((blue & 0xf800) >> 11); ++ break; ++ case 16: ++ fb->pseudo_palette[regno] = (red & 0xf800) | ++ ((green & 0xfc00) >> 5) | ++ ((blue & 0xf800) >> 11); ++ break; ++ case 24: ++ case 32: ++ fb->pseudo_palette[regno] = ++ (((red >> 8) & 0xff) << info->var.red.offset) | ++ (((green >> 8) & 0xff) << info->var.green.offset) | ++ (((blue >> 8) & 0xff) << info->var.blue.offset); ++ break; ++ } ++ } ++ } ++ return 0; ++} ++EXPORT_SYMBOL(drm_fb_helper_setcolreg); ++ ++int drm_fb_helper_check_var(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ struct drm_fb_helper *fb_helper = info->par; ++ struct drm_framebuffer *fb = fb_helper->fb; ++ int depth; ++ ++ if (var->pixclock == -1 || !var->pixclock) ++ return -EINVAL; ++ ++ /* Need to resize the fb object !!! */ ++ if (var->xres > fb->width || var->yres > fb->height) { ++ DRM_ERROR("Requested width/height is greater than current fb " ++ "object %dx%d > %dx%d\n", var->xres, var->yres, ++ fb->width, fb->height); ++ DRM_ERROR("Need resizing code.\n"); ++ return -EINVAL; ++ } ++ ++ switch (var->bits_per_pixel) { ++ case 16: ++ depth = (var->green.length == 6) ? 16 : 15; ++ break; ++ case 32: ++ depth = (var->transp.length > 0) ? 32 : 24; ++ break; ++ default: ++ depth = var->bits_per_pixel; ++ break; ++ } ++ ++ switch (depth) { ++ case 8: ++ var->red.offset = 0; ++ var->green.offset = 0; ++ var->blue.offset = 0; ++ var->red.length = 8; ++ var->green.length = 8; ++ var->blue.length = 8; ++ var->transp.length = 0; ++ var->transp.offset = 0; ++ break; ++ case 15: ++ var->red.offset = 10; ++ var->green.offset = 5; ++ var->blue.offset = 0; ++ var->red.length = 5; ++ var->green.length = 5; ++ var->blue.length = 5; ++ var->transp.length = 1; ++ var->transp.offset = 15; ++ break; ++ case 16: ++ var->red.offset = 11; ++ var->green.offset = 5; ++ var->blue.offset = 0; ++ var->red.length = 5; ++ var->green.length = 6; ++ var->blue.length = 5; ++ var->transp.length = 0; ++ var->transp.offset = 0; ++ break; ++ case 24: ++ var->red.offset = 16; ++ var->green.offset = 8; ++ var->blue.offset = 0; ++ var->red.length = 8; ++ var->green.length = 8; ++ var->blue.length = 8; ++ var->transp.length = 0; ++ var->transp.offset = 0; ++ break; ++ case 32: ++ var->red.offset = 16; ++ var->green.offset = 8; ++ var->blue.offset = 0; ++ var->red.length = 8; ++ var->green.length = 8; ++ var->blue.length = 8; ++ var->transp.length = 8; ++ var->transp.offset = 24; ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++EXPORT_SYMBOL(drm_fb_helper_check_var); ++ ++/* this will let fbcon do the mode init */ ++int drm_fb_helper_set_par(struct fb_info *info) ++{ ++ struct drm_fb_helper *fb_helper = info->par; ++ struct drm_device *dev = fb_helper->dev; ++ struct fb_var_screeninfo *var = &info->var; ++ struct drm_crtc *crtc; ++ int ret; ++ int i; ++ ++ if (var->pixclock != -1) { ++ DRM_ERROR("PIXEL CLCOK SET\n"); ++ return -EINVAL; ++ } ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ ++ for (i = 0; i < fb_helper->crtc_count; i++) { ++ if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) ++ break; ++ } ++ if (i == fb_helper->crtc_count) ++ continue; ++ ++ if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) { ++ mutex_lock(&dev->mode_config.mutex); ++ ret = crtc->funcs->set_config(&fb_helper->crtc_info->mode_set); ++ mutex_unlock(&dev->mode_config.mutex); ++ if (ret) ++ return ret; ++ } ++ } ++ return 0; ++} ++EXPORT_SYMBOL(drm_fb_helper_set_par); ++ ++int drm_fb_helper_pan_display(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ struct drm_fb_helper *fb_helper = info->par; ++ struct drm_device *dev = fb_helper->dev; ++ struct drm_mode_set *modeset; ++ struct drm_crtc *crtc; ++ int ret = 0; ++ int i; ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ for (i = 0; i < fb_helper->crtc_count; i++) { ++ if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) ++ break; ++ } ++ ++ if (i == fb_helper->crtc_count) ++ continue; ++ ++ modeset = &fb_helper->crtc_info[i].mode_set; ++ ++ modeset->x = var->xoffset; ++ modeset->y = var->yoffset; ++ ++ if (modeset->num_connectors) { ++ mutex_lock(&dev->mode_config.mutex); ++ ret = crtc->funcs->set_config(modeset); ++ mutex_unlock(&dev->mode_config.mutex); ++ if (!ret) { ++ info->var.xoffset = var->xoffset; ++ info->var.yoffset = var->yoffset; ++ } ++ } ++ } ++ return ret; ++} ++EXPORT_SYMBOL(drm_fb_helper_pan_display); ++ ++int drm_fb_helper_single_fb_probe(struct drm_device *dev, ++ int (*fb_create)(struct drm_device *dev, ++ uint32_t fb_width, ++ uint32_t fb_height, ++ uint32_t surface_width, ++ uint32_t surface_height, ++ uint32_t surface_depth, ++ uint32_t surface_bpp, ++ struct drm_framebuffer **fb_ptr)) ++{ ++ struct drm_crtc *crtc; ++ struct drm_connector *connector; ++ unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; ++ unsigned int surface_width = 0, surface_height = 0; ++ int new_fb = 0; ++ int crtc_count = 0; ++ int ret, i, conn_count = 0; ++ struct fb_info *info; ++ struct drm_framebuffer *fb; ++ struct drm_mode_set *modeset = NULL; ++ struct drm_fb_helper *fb_helper; ++ uint32_t surface_depth = 24, surface_bpp = 32; ++ ++ /* first up get a count of crtcs now in use and new min/maxes width/heights */ ++ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { ++ struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; ++ ++ struct drm_fb_helper_cmdline_mode *cmdline_mode; ++ ++ if (!fb_help_conn) ++ continue; ++ ++ cmdline_mode = &fb_help_conn->cmdline_mode; ++ ++ if (cmdline_mode->bpp_specified) { ++ switch (cmdline_mode->bpp) { ++ case 8: ++ surface_depth = surface_bpp = 8; ++ break; ++ case 15: ++ surface_depth = 15; ++ surface_bpp = 16; ++ break; ++ case 16: ++ surface_depth = surface_bpp = 16; ++ break; ++ case 24: ++ surface_depth = surface_bpp = 24; ++ break; ++ case 32: ++ surface_depth = 24; ++ surface_bpp = 32; ++ break; ++ } ++ break; ++ } ++ } ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ if (drm_helper_crtc_in_use(crtc)) { ++ if (crtc->desired_mode) { ++ if (crtc->desired_mode->hdisplay < fb_width) ++ fb_width = crtc->desired_mode->hdisplay; ++ ++ if (crtc->desired_mode->vdisplay < fb_height) ++ fb_height = crtc->desired_mode->vdisplay; ++ ++ if (crtc->desired_mode->hdisplay > surface_width) ++ surface_width = crtc->desired_mode->hdisplay; ++ ++ if (crtc->desired_mode->vdisplay > surface_height) ++ surface_height = crtc->desired_mode->vdisplay; ++ } ++ crtc_count++; ++ } ++ } ++ ++ if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { ++ /* hmm everyone went away - assume VGA cable just fell out ++ and will come back later. */ ++ return 0; ++ } ++ ++ /* do we have an fb already? */ ++ if (list_empty(&dev->mode_config.fb_kernel_list)) { ++ ret = (*fb_create)(dev, fb_width, fb_height, surface_width, ++ surface_height, surface_depth, surface_bpp, ++ &fb); ++ if (ret) ++ return -EINVAL; ++ new_fb = 1; ++ } else { ++ fb = list_first_entry(&dev->mode_config.fb_kernel_list, ++ struct drm_framebuffer, filp_head); ++ ++ /* if someone hotplugs something bigger than we have already allocated, we are pwned. ++ As really we can't resize an fbdev that is in the wild currently due to fbdev ++ not really being designed for the lower layers moving stuff around under it. ++ - so in the grand style of things - punt. */ ++ if ((fb->width < surface_width) || ++ (fb->height < surface_height)) { ++ DRM_ERROR("Framebuffer not large enough to scale console onto.\n"); ++ return -EINVAL; ++ } ++ } ++ ++ info = fb->fbdev; ++ fb_helper = info->par; ++ ++ crtc_count = 0; ++ /* okay we need to setup new connector sets in the crtcs */ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ modeset = &fb_helper->crtc_info[crtc_count].mode_set; ++ modeset->fb = fb; ++ conn_count = 0; ++ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { ++ if (connector->encoder) ++ if (connector->encoder->crtc == modeset->crtc) { ++ modeset->connectors[conn_count] = connector; ++ conn_count++; ++ if (conn_count > fb_helper->conn_limit) ++ BUG(); ++ } ++ } ++ ++ for (i = conn_count; i < fb_helper->conn_limit; i++) ++ modeset->connectors[i] = NULL; ++ ++ modeset->crtc = crtc; ++ crtc_count++; ++ ++ modeset->num_connectors = conn_count; ++ if (modeset->crtc->desired_mode) { ++ if (modeset->mode) ++ drm_mode_destroy(dev, modeset->mode); ++ modeset->mode = drm_mode_duplicate(dev, ++ modeset->crtc->desired_mode); ++ } ++ } ++ fb_helper->crtc_count = crtc_count; ++ fb_helper->fb = fb; ++ ++ if (new_fb) { ++ info->var.pixclock = -1; ++ if (register_framebuffer(info) < 0) ++ return -EINVAL; ++ } else { ++ drm_fb_helper_set_par(info); ++ } ++ printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, ++ info->fix.id); ++ ++ /* Switch back to kernel console on panic */ ++ /* multi card linked list maybe */ ++ if (list_empty(&kernel_fb_helper_list)) { ++ printk(KERN_INFO "registered panic notifier\n"); ++ atomic_notifier_chain_register(&panic_notifier_list, ++ &paniced); ++ register_sysrq_key('v', &sysrq_drm_fb_helper_restore_op); ++ } ++ list_add(&fb_helper->kernel_fb_list, &kernel_fb_helper_list); ++ return 0; ++} ++EXPORT_SYMBOL(drm_fb_helper_single_fb_probe); ++ ++void drm_fb_helper_free(struct drm_fb_helper *helper) ++{ ++ list_del(&helper->kernel_fb_list); ++ if (list_empty(&kernel_fb_helper_list)) { ++ printk(KERN_INFO "unregistered panic notifier\n"); ++ atomic_notifier_chain_unregister(&panic_notifier_list, ++ &paniced); ++ unregister_sysrq_key('v', &sysrq_drm_fb_helper_restore_op); ++ } ++ drm_fb_helper_crtc_free(helper); ++} ++EXPORT_SYMBOL(drm_fb_helper_free); ++ ++void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch) ++{ ++ info->fix.type = FB_TYPE_PACKED_PIXELS; ++ info->fix.visual = FB_VISUAL_TRUECOLOR; ++ info->fix.type_aux = 0; ++ info->fix.xpanstep = 1; /* doing it in hw */ ++ info->fix.ypanstep = 1; /* doing it in hw */ ++ info->fix.ywrapstep = 0; ++ info->fix.accel = FB_ACCEL_NONE; ++ info->fix.type_aux = 0; ++ ++ info->fix.line_length = pitch; ++ return; ++} ++EXPORT_SYMBOL(drm_fb_helper_fill_fix); ++ ++void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb, ++ uint32_t fb_width, uint32_t fb_height) ++{ ++ info->pseudo_palette = fb->pseudo_palette; ++ info->var.xres_virtual = fb->width; ++ info->var.yres_virtual = fb->height; ++ info->var.bits_per_pixel = fb->bits_per_pixel; ++ info->var.xoffset = 0; ++ info->var.yoffset = 0; ++ info->var.activate = FB_ACTIVATE_NOW; ++ info->var.height = -1; ++ info->var.width = -1; ++ ++ switch (fb->depth) { ++ case 8: ++ info->var.red.offset = 0; ++ info->var.green.offset = 0; ++ info->var.blue.offset = 0; ++ info->var.red.length = 8; /* 8bit DAC */ ++ info->var.green.length = 8; ++ info->var.blue.length = 8; ++ info->var.transp.offset = 0; ++ info->var.transp.length = 0; ++ break; ++ case 15: ++ info->var.red.offset = 10; ++ info->var.green.offset = 5; ++ info->var.blue.offset = 0; ++ info->var.red.length = 5; ++ info->var.green.length = 5; ++ info->var.blue.length = 5; ++ info->var.transp.offset = 15; ++ info->var.transp.length = 1; ++ break; ++ case 16: ++ info->var.red.offset = 11; ++ info->var.green.offset = 5; ++ info->var.blue.offset = 0; ++ info->var.red.length = 5; ++ info->var.green.length = 6; ++ info->var.blue.length = 5; ++ info->var.transp.offset = 0; ++ break; ++ case 24: ++ info->var.red.offset = 16; ++ info->var.green.offset = 8; ++ info->var.blue.offset = 0; ++ info->var.red.length = 8; ++ info->var.green.length = 8; ++ info->var.blue.length = 8; ++ info->var.transp.offset = 0; ++ info->var.transp.length = 0; ++ break; ++ case 32: ++ info->var.red.offset = 16; ++ info->var.green.offset = 8; ++ info->var.blue.offset = 0; ++ info->var.red.length = 8; ++ info->var.green.length = 8; ++ info->var.blue.length = 8; ++ info->var.transp.offset = 24; ++ info->var.transp.length = 8; ++ break; ++ default: ++ break; ++ } ++ ++ info->var.xres = fb_width; ++ info->var.yres = fb_height; ++} ++EXPORT_SYMBOL(drm_fb_helper_fill_var); +diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c +index ffe8f43..230c9ff 100644 +--- a/drivers/gpu/drm/drm_gem.c ++++ b/drivers/gpu/drm/drm_gem.c +@@ -164,7 +164,7 @@ EXPORT_SYMBOL(drm_gem_object_alloc); + * Removes the mapping from handle to filp for this object. + */ + static int +-drm_gem_handle_delete(struct drm_file *filp, int handle) ++drm_gem_handle_delete(struct drm_file *filp, u32 handle) + { + struct drm_device *dev; + struct drm_gem_object *obj; +@@ -207,7 +207,7 @@ drm_gem_handle_delete(struct drm_file *filp, int handle) + int + drm_gem_handle_create(struct drm_file *file_priv, + struct drm_gem_object *obj, +- int *handlep) ++ u32 *handlep) + { + int ret; + +@@ -221,7 +221,7 @@ again: + + /* do the allocation under our spinlock */ + spin_lock(&file_priv->table_lock); +- ret = idr_get_new_above(&file_priv->object_idr, obj, 1, handlep); ++ ret = idr_get_new_above(&file_priv->object_idr, obj, 1, (int *)handlep); + spin_unlock(&file_priv->table_lock); + if (ret == -EAGAIN) + goto again; +@@ -237,7 +237,7 @@ EXPORT_SYMBOL(drm_gem_handle_create); + /** Returns a reference to the object named by the handle. */ + struct drm_gem_object * + drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, +- int handle) ++ u32 handle) + { + struct drm_gem_object *obj; + +@@ -344,7 +344,7 @@ drm_gem_open_ioctl(struct drm_device *dev, void *data, + struct drm_gem_open *args = data; + struct drm_gem_object *obj; + int ret; +- int handle; ++ u32 handle; + + if (!(dev->driver->driver_features & DRIVER_GEM)) + return -ENODEV; +@@ -539,7 +539,6 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) + vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND; + vma->vm_ops = obj->dev->driver->gem_vm_ops; + vma->vm_private_data = map->handle; +- /* FIXME: use pgprot_writecombine when available */ + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + /* Take a ref for this mapping of the object, so that the fault +diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c +index 3e47869..c861d80 100644 +--- a/drivers/gpu/drm/drm_mm.c ++++ b/drivers/gpu/drm/drm_mm.c +@@ -44,6 +44,7 @@ + #include "drmP.h" + #include "drm_mm.h" + #include <linux/slab.h> ++#include <linux/seq_file.h> + + #define MM_UNUSED_TARGET 4 + +@@ -370,3 +371,23 @@ void drm_mm_takedown(struct drm_mm * mm) + BUG_ON(mm->num_unused != 0); + } + EXPORT_SYMBOL(drm_mm_takedown); ++ ++#if defined(CONFIG_DEBUG_FS) ++int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm) ++{ ++ struct drm_mm_node *entry; ++ int total_used = 0, total_free = 0, total = 0; ++ ++ list_for_each_entry(entry, &mm->ml_entry, ml_entry) { ++ seq_printf(m, "0x%08lx-0x%08lx: 0x%08lx: %s\n", entry->start, entry->start + entry->size, entry->size, entry->free ? "free" : "used"); ++ total += entry->size; ++ if (entry->free) ++ total_free += entry->size; ++ else ++ total_used += entry->size; ++ } ++ seq_printf(m, "total: %d, used %d free %d\n", total, total_free, total_used); ++ return 0; ++} ++EXPORT_SYMBOL(drm_mm_dump_table); ++#endif +diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c +index 7914097..51f6772 100644 +--- a/drivers/gpu/drm/drm_modes.c ++++ b/drivers/gpu/drm/drm_modes.c +@@ -8,6 +8,8 @@ + * Copyright © 2007 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes <jesse.barnes@intel.com> ++ * Copyright 2005-2006 Luc Verhaegen ++ * Copyright (c) 2001, Andy Ritger aritger@nvidia.com + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), +@@ -38,7 +40,6 @@ + #include "drm.h" + #include "drm_crtc.h" + +-#define DRM_MODESET_DEBUG "drm_mode" + /** + * drm_mode_debug_printmodeline - debug print a mode + * @dev: DRM device +@@ -51,8 +52,8 @@ + */ + void drm_mode_debug_printmodeline(struct drm_display_mode *mode) + { +- DRM_DEBUG_MODE(DRM_MODESET_DEBUG, +- "Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n", ++ DRM_DEBUG_KMS("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d " ++ "0x%x 0x%x\n", + mode->base.id, mode->name, mode->vrefresh, mode->clock, + mode->hdisplay, mode->hsync_start, + mode->hsync_end, mode->htotal, +@@ -62,6 +63,419 @@ void drm_mode_debug_printmodeline(struct drm_display_mode *mode) + EXPORT_SYMBOL(drm_mode_debug_printmodeline); + + /** ++ * drm_cvt_mode -create a modeline based on CVT algorithm ++ * @dev: DRM device ++ * @hdisplay: hdisplay size ++ * @vdisplay: vdisplay size ++ * @vrefresh : vrefresh rate ++ * @reduced : Whether the GTF calculation is simplified ++ * @interlaced:Whether the interlace is supported ++ * ++ * LOCKING: ++ * none. ++ * ++ * return the modeline based on CVT algorithm ++ * ++ * This function is called to generate the modeline based on CVT algorithm ++ * according to the hdisplay, vdisplay, vrefresh. ++ * It is based from the VESA(TM) Coordinated Video Timing Generator by ++ * Graham Loveridge April 9, 2003 available at ++ * http://www.vesa.org/public/CVT/CVTd6r1.xls ++ * ++ * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. ++ * What I have done is to translate it by using integer calculation. ++ */ ++#define HV_FACTOR 1000 ++struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, ++ int vdisplay, int vrefresh, ++ bool reduced, bool interlaced, bool margins) ++{ ++ /* 1) top/bottom margin size (% of height) - default: 1.8, */ ++#define CVT_MARGIN_PERCENTAGE 18 ++ /* 2) character cell horizontal granularity (pixels) - default 8 */ ++#define CVT_H_GRANULARITY 8 ++ /* 3) Minimum vertical porch (lines) - default 3 */ ++#define CVT_MIN_V_PORCH 3 ++ /* 4) Minimum number of vertical back porch lines - default 6 */ ++#define CVT_MIN_V_BPORCH 6 ++ /* Pixel Clock step (kHz) */ ++#define CVT_CLOCK_STEP 250 ++ struct drm_display_mode *drm_mode; ++ unsigned int vfieldrate, hperiod; ++ int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; ++ int interlace; ++ ++ /* allocate the drm_display_mode structure. If failure, we will ++ * return directly ++ */ ++ drm_mode = drm_mode_create(dev); ++ if (!drm_mode) ++ return NULL; ++ ++ /* the CVT default refresh rate is 60Hz */ ++ if (!vrefresh) ++ vrefresh = 60; ++ ++ /* the required field fresh rate */ ++ if (interlaced) ++ vfieldrate = vrefresh * 2; ++ else ++ vfieldrate = vrefresh; ++ ++ /* horizontal pixels */ ++ hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); ++ ++ /* determine the left&right borders */ ++ hmargin = 0; ++ if (margins) { ++ hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; ++ hmargin -= hmargin % CVT_H_GRANULARITY; ++ } ++ /* find the total active pixels */ ++ drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; ++ ++ /* find the number of lines per field */ ++ if (interlaced) ++ vdisplay_rnd = vdisplay / 2; ++ else ++ vdisplay_rnd = vdisplay; ++ ++ /* find the top & bottom borders */ ++ vmargin = 0; ++ if (margins) ++ vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; ++ ++ drm_mode->vdisplay = vdisplay + 2 * vmargin; ++ ++ /* Interlaced */ ++ if (interlaced) ++ interlace = 1; ++ else ++ interlace = 0; ++ ++ /* Determine VSync Width from aspect ratio */ ++ if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) ++ vsync = 4; ++ else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) ++ vsync = 5; ++ else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) ++ vsync = 6; ++ else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) ++ vsync = 7; ++ else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) ++ vsync = 7; ++ else /* custom */ ++ vsync = 10; ++ ++ if (!reduced) { ++ /* simplify the GTF calculation */ ++ /* 4) Minimum time of vertical sync + back porch interval (µs) ++ * default 550.0 ++ */ ++ int tmp1, tmp2; ++#define CVT_MIN_VSYNC_BP 550 ++ /* 3) Nominal HSync width (% of line period) - default 8 */ ++#define CVT_HSYNC_PERCENTAGE 8 ++ unsigned int hblank_percentage; ++ int vsyncandback_porch, vback_porch, hblank; ++ ++ /* estimated the horizontal period */ ++ tmp1 = HV_FACTOR * 1000000 - ++ CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; ++ tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + ++ interlace; ++ hperiod = tmp1 * 2 / (tmp2 * vfieldrate); ++ ++ tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; ++ /* 9. Find number of lines in sync + backporch */ ++ if (tmp1 < (vsync + CVT_MIN_V_PORCH)) ++ vsyncandback_porch = vsync + CVT_MIN_V_PORCH; ++ else ++ vsyncandback_porch = tmp1; ++ /* 10. Find number of lines in back porch */ ++ vback_porch = vsyncandback_porch - vsync; ++ drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + ++ vsyncandback_porch + CVT_MIN_V_PORCH; ++ /* 5) Definition of Horizontal blanking time limitation */ ++ /* Gradient (%/kHz) - default 600 */ ++#define CVT_M_FACTOR 600 ++ /* Offset (%) - default 40 */ ++#define CVT_C_FACTOR 40 ++ /* Blanking time scaling factor - default 128 */ ++#define CVT_K_FACTOR 128 ++ /* Scaling factor weighting - default 20 */ ++#define CVT_J_FACTOR 20 ++#define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) ++#define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ ++ CVT_J_FACTOR) ++ /* 12. Find ideal blanking duty cycle from formula */ ++ hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * ++ hperiod / 1000; ++ /* 13. Blanking time */ ++ if (hblank_percentage < 20 * HV_FACTOR) ++ hblank_percentage = 20 * HV_FACTOR; ++ hblank = drm_mode->hdisplay * hblank_percentage / ++ (100 * HV_FACTOR - hblank_percentage); ++ hblank -= hblank % (2 * CVT_H_GRANULARITY); ++ /* 14. find the total pixes per line */ ++ drm_mode->htotal = drm_mode->hdisplay + hblank; ++ drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; ++ drm_mode->hsync_start = drm_mode->hsync_end - ++ (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; ++ drm_mode->hsync_start += CVT_H_GRANULARITY - ++ drm_mode->hsync_start % CVT_H_GRANULARITY; ++ /* fill the Vsync values */ ++ drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; ++ drm_mode->vsync_end = drm_mode->vsync_start + vsync; ++ } else { ++ /* Reduced blanking */ ++ /* Minimum vertical blanking interval time (µs)- default 460 */ ++#define CVT_RB_MIN_VBLANK 460 ++ /* Fixed number of clocks for horizontal sync */ ++#define CVT_RB_H_SYNC 32 ++ /* Fixed number of clocks for horizontal blanking */ ++#define CVT_RB_H_BLANK 160 ++ /* Fixed number of lines for vertical front porch - default 3*/ ++#define CVT_RB_VFPORCH 3 ++ int vbilines; ++ int tmp1, tmp2; ++ /* 8. Estimate Horizontal period. */ ++ tmp1 = HV_FACTOR * 1000000 - ++ CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; ++ tmp2 = vdisplay_rnd + 2 * vmargin; ++ hperiod = tmp1 / (tmp2 * vfieldrate); ++ /* 9. Find number of lines in vertical blanking */ ++ vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; ++ /* 10. Check if vertical blanking is sufficient */ ++ if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) ++ vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; ++ /* 11. Find total number of lines in vertical field */ ++ drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; ++ /* 12. Find total number of pixels in a line */ ++ drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; ++ /* Fill in HSync values */ ++ drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; ++ drm_mode->hsync_start = drm_mode->hsync_end = CVT_RB_H_SYNC; ++ } ++ /* 15/13. Find pixel clock frequency (kHz for xf86) */ ++ drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; ++ drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; ++ /* 18/16. Find actual vertical frame frequency */ ++ /* ignore - just set the mode flag for interlaced */ ++ if (interlaced) ++ drm_mode->vtotal *= 2; ++ /* Fill the mode line name */ ++ drm_mode_set_name(drm_mode); ++ if (reduced) ++ drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | ++ DRM_MODE_FLAG_NVSYNC); ++ else ++ drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | ++ DRM_MODE_FLAG_NHSYNC); ++ if (interlaced) ++ drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; ++ ++ return drm_mode; ++} ++EXPORT_SYMBOL(drm_cvt_mode); ++ ++/** ++ * drm_gtf_mode - create the modeline based on GTF algorithm ++ * ++ * @dev :drm device ++ * @hdisplay :hdisplay size ++ * @vdisplay :vdisplay size ++ * @vrefresh :vrefresh rate. ++ * @interlaced :whether the interlace is supported ++ * @margins :whether the margin is supported ++ * ++ * LOCKING. ++ * none. ++ * ++ * return the modeline based on GTF algorithm ++ * ++ * This function is to create the modeline based on the GTF algorithm. ++ * Generalized Timing Formula is derived from: ++ * GTF Spreadsheet by Andy Morrish (1/5/97) ++ * available at http://www.vesa.org ++ * ++ * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. ++ * What I have done is to translate it by using integer calculation. ++ * I also refer to the function of fb_get_mode in the file of ++ * drivers/video/fbmon.c ++ */ ++struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, int hdisplay, ++ int vdisplay, int vrefresh, ++ bool interlaced, int margins) ++{ ++ /* 1) top/bottom margin size (% of height) - default: 1.8, */ ++#define GTF_MARGIN_PERCENTAGE 18 ++ /* 2) character cell horizontal granularity (pixels) - default 8 */ ++#define GTF_CELL_GRAN 8 ++ /* 3) Minimum vertical porch (lines) - default 3 */ ++#define GTF_MIN_V_PORCH 1 ++ /* width of vsync in lines */ ++#define V_SYNC_RQD 3 ++ /* width of hsync as % of total line */ ++#define H_SYNC_PERCENT 8 ++ /* min time of vsync + back porch (microsec) */ ++#define MIN_VSYNC_PLUS_BP 550 ++ /* blanking formula gradient */ ++#define GTF_M 600 ++ /* blanking formula offset */ ++#define GTF_C 40 ++ /* blanking formula scaling factor */ ++#define GTF_K 128 ++ /* blanking formula scaling factor */ ++#define GTF_J 20 ++ /* C' and M' are part of the Blanking Duty Cycle computation */ ++#define GTF_C_PRIME (((GTF_C - GTF_J) * GTF_K / 256) + GTF_J) ++#define GTF_M_PRIME (GTF_K * GTF_M / 256) ++ struct drm_display_mode *drm_mode; ++ unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; ++ int top_margin, bottom_margin; ++ int interlace; ++ unsigned int hfreq_est; ++ int vsync_plus_bp, vback_porch; ++ unsigned int vtotal_lines, vfieldrate_est, hperiod; ++ unsigned int vfield_rate, vframe_rate; ++ int left_margin, right_margin; ++ unsigned int total_active_pixels, ideal_duty_cycle; ++ unsigned int hblank, total_pixels, pixel_freq; ++ int hsync, hfront_porch, vodd_front_porch_lines; ++ unsigned int tmp1, tmp2; ++ ++ drm_mode = drm_mode_create(dev); ++ if (!drm_mode) ++ return NULL; ++ ++ /* 1. In order to give correct results, the number of horizontal ++ * pixels requested is first processed to ensure that it is divisible ++ * by the character size, by rounding it to the nearest character ++ * cell boundary: ++ */ ++ hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; ++ hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; ++ ++ /* 2. If interlace is requested, the number of vertical lines assumed ++ * by the calculation must be halved, as the computation calculates ++ * the number of vertical lines per field. ++ */ ++ if (interlaced) ++ vdisplay_rnd = vdisplay / 2; ++ else ++ vdisplay_rnd = vdisplay; ++ ++ /* 3. Find the frame rate required: */ ++ if (interlaced) ++ vfieldrate_rqd = vrefresh * 2; ++ else ++ vfieldrate_rqd = vrefresh; ++ ++ /* 4. Find number of lines in Top margin: */ ++ top_margin = 0; ++ if (margins) ++ top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / ++ 1000; ++ /* 5. Find number of lines in bottom margin: */ ++ bottom_margin = top_margin; ++ ++ /* 6. If interlace is required, then set variable interlace: */ ++ if (interlaced) ++ interlace = 1; ++ else ++ interlace = 0; ++ ++ /* 7. Estimate the Horizontal frequency */ ++ { ++ tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; ++ tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * ++ 2 + interlace; ++ hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; ++ } ++ ++ /* 8. Find the number of lines in V sync + back porch */ ++ /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ ++ vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; ++ vsync_plus_bp = (vsync_plus_bp + 500) / 1000; ++ /* 9. Find the number of lines in V back porch alone: */ ++ vback_porch = vsync_plus_bp - V_SYNC_RQD; ++ /* 10. Find the total number of lines in Vertical field period: */ ++ vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + ++ vsync_plus_bp + GTF_MIN_V_PORCH; ++ /* 11. Estimate the Vertical field frequency: */ ++ vfieldrate_est = hfreq_est / vtotal_lines; ++ /* 12. Find the actual horizontal period: */ ++ hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); ++ ++ /* 13. Find the actual Vertical field frequency: */ ++ vfield_rate = hfreq_est / vtotal_lines; ++ /* 14. Find the Vertical frame frequency: */ ++ if (interlaced) ++ vframe_rate = vfield_rate / 2; ++ else ++ vframe_rate = vfield_rate; ++ /* 15. Find number of pixels in left margin: */ ++ if (margins) ++ left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / ++ 1000; ++ else ++ left_margin = 0; ++ ++ /* 16.Find number of pixels in right margin: */ ++ right_margin = left_margin; ++ /* 17.Find total number of active pixels in image and left and right */ ++ total_active_pixels = hdisplay_rnd + left_margin + right_margin; ++ /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ ++ ideal_duty_cycle = GTF_C_PRIME * 1000 - ++ (GTF_M_PRIME * 1000000 / hfreq_est); ++ /* 19.Find the number of pixels in the blanking time to the nearest ++ * double character cell: */ ++ hblank = total_active_pixels * ideal_duty_cycle / ++ (100000 - ideal_duty_cycle); ++ hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); ++ hblank = hblank * 2 * GTF_CELL_GRAN; ++ /* 20.Find total number of pixels: */ ++ total_pixels = total_active_pixels + hblank; ++ /* 21.Find pixel clock frequency: */ ++ pixel_freq = total_pixels * hfreq_est / 1000; ++ /* Stage 1 computations are now complete; I should really pass ++ * the results to another function and do the Stage 2 computations, ++ * but I only need a few more values so I'll just append the ++ * computations here for now */ ++ /* 17. Find the number of pixels in the horizontal sync period: */ ++ hsync = H_SYNC_PERCENT * total_pixels / 100; ++ hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; ++ hsync = hsync * GTF_CELL_GRAN; ++ /* 18. Find the number of pixels in horizontal front porch period */ ++ hfront_porch = hblank / 2 - hsync; ++ /* 36. Find the number of lines in the odd front porch period: */ ++ vodd_front_porch_lines = GTF_MIN_V_PORCH ; ++ ++ /* finally, pack the results in the mode struct */ ++ drm_mode->hdisplay = hdisplay_rnd; ++ drm_mode->hsync_start = hdisplay_rnd + hfront_porch; ++ drm_mode->hsync_end = drm_mode->hsync_start + hsync; ++ drm_mode->htotal = total_pixels; ++ drm_mode->vdisplay = vdisplay_rnd; ++ drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; ++ drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; ++ drm_mode->vtotal = vtotal_lines; ++ ++ drm_mode->clock = pixel_freq; ++ ++ drm_mode_set_name(drm_mode); ++ drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; ++ ++ if (interlaced) { ++ drm_mode->vtotal *= 2; ++ drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; ++ } ++ ++ return drm_mode; ++} ++EXPORT_SYMBOL(drm_gtf_mode); ++/** + * drm_mode_set_name - set the name on a mode + * @mode: name will be set in this mode + * +@@ -151,7 +565,9 @@ EXPORT_SYMBOL(drm_mode_height); + * FIXME: why is this needed? shouldn't vrefresh be set already? + * + * RETURNS: +- * Vertical refresh rate of @mode x 1000. For precision reasons. ++ * Vertical refresh rate. It will be the result of actual value plus 0.5. ++ * If it is 70.288, it will return 70Hz. ++ * If it is 59.6, it will return 60Hz. + */ + int drm_mode_vrefresh(struct drm_display_mode *mode) + { +@@ -161,14 +577,13 @@ int drm_mode_vrefresh(struct drm_display_mode *mode) + if (mode->vrefresh > 0) + refresh = mode->vrefresh; + else if (mode->htotal > 0 && mode->vtotal > 0) { ++ int vtotal; ++ vtotal = mode->vtotal; + /* work out vrefresh the value will be x1000 */ + calc_val = (mode->clock * 1000); +- + calc_val /= mode->htotal; +- calc_val *= 1000; +- calc_val /= mode->vtotal; ++ refresh = (calc_val + vtotal / 2) / vtotal; + +- refresh = calc_val; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + refresh *= 2; + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +@@ -403,8 +818,7 @@ void drm_mode_prune_invalid(struct drm_device *dev, + list_del(&mode->head); + if (verbose) { + drm_mode_debug_printmodeline(mode); +- DRM_DEBUG_MODE(DRM_MODESET_DEBUG, +- "Not using %s mode %d\n", ++ DRM_DEBUG_KMS("Not using %s mode %d\n", + mode->name, mode->status); + } + drm_mode_destroy(dev, mode); +diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c +index bbd4b3d..d379c4f 100644 +--- a/drivers/gpu/drm/drm_proc.c ++++ b/drivers/gpu/drm/drm_proc.c +@@ -106,20 +106,25 @@ int drm_proc_create_files(struct drm_info_list *files, int count, + continue; + + tmp = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); +- ent = create_proc_entry(files[i].name, S_IFREG | S_IRUGO, root); ++ if (tmp == NULL) { ++ ret = -1; ++ goto fail; ++ } ++ tmp->minor = minor; ++ tmp->info_ent = &files[i]; ++ list_add(&tmp->list, &minor->proc_nodes.list); ++ ++ ent = proc_create_data(files[i].name, S_IRUGO, root, ++ &drm_proc_fops, tmp); + if (!ent) { + DRM_ERROR("Cannot create /proc/dri/%s/%s\n", + name, files[i].name); ++ list_del(&tmp->list); + kfree(tmp); + ret = -1; + goto fail; + } + +- ent->proc_fops = &drm_proc_fops; +- ent->data = tmp; +- tmp->minor = minor; +- tmp->info_ent = &files[i]; +- list_add(&(tmp->list), &(minor->proc_nodes.list)); + } + return 0; + +diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c +index f7a615b..5161172 100644 +--- a/drivers/gpu/drm/drm_sysfs.c ++++ b/drivers/gpu/drm/drm_sysfs.c +@@ -16,6 +16,7 @@ + #include <linux/kdev_t.h> + #include <linux/err.h> + ++#include "drm_sysfs.h" + #include "drm_core.h" + #include "drmP.h" + +@@ -253,6 +254,7 @@ static ssize_t subconnector_show(struct device *device, + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_Component: ++ case DRM_MODE_CONNECTOR_TV: + prop = dev->mode_config.tv_subconnector_property; + is_tv = 1; + break; +@@ -293,6 +295,7 @@ static ssize_t select_subconnector_show(struct device *device, + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_Component: ++ case DRM_MODE_CONNECTOR_TV: + prop = dev->mode_config.tv_select_subconnector_property; + is_tv = 1; + break; +@@ -391,6 +394,7 @@ int drm_sysfs_connector_add(struct drm_connector *connector) + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_Component: ++ case DRM_MODE_CONNECTOR_TV: + for (i = 0; i < ARRAY_SIZE(connector_attrs_opt1); i++) { + ret = device_create_file(&connector->kdev, &connector_attrs_opt1[i]); + if (ret) +@@ -519,3 +523,27 @@ void drm_sysfs_device_remove(struct drm_minor *minor) + { + device_unregister(&minor->kdev); + } ++ ++ ++/** ++ * drm_class_device_register - Register a struct device in the drm class. ++ * ++ * @dev: pointer to struct device to register. ++ * ++ * @dev should have all relevant members pre-filled with the exception ++ * of the class member. In particular, the device_type member must ++ * be set. ++ */ ++ ++int drm_class_device_register(struct device *dev) ++{ ++ dev->class = drm_class; ++ return device_register(dev); ++} ++EXPORT_SYMBOL_GPL(drm_class_device_register); ++ ++void drm_class_device_unregister(struct device *dev) ++{ ++ return device_unregister(dev); ++} ++EXPORT_SYMBOL_GPL(drm_class_device_unregister); +diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile +index 30d6b99..5269dfa 100644 +--- a/drivers/gpu/drm/i915/Makefile ++++ b/drivers/gpu/drm/i915/Makefile +@@ -4,10 +4,10 @@ + + ccflags-y := -Iinclude/drm + i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ ++ i915_debugfs.o \ + i915_suspend.o \ + i915_gem.o \ + i915_gem_debug.o \ +- i915_gem_debugfs.o \ + i915_gem_tiling.o \ + intel_display.o \ + intel_crt.o \ +diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c +new file mode 100644 +index 0000000..1e3bdce +--- /dev/null ++++ b/drivers/gpu/drm/i915/i915_debugfs.c +@@ -0,0 +1,445 @@ ++/* ++ * Copyright © 2008 Intel Corporation ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++ * IN THE SOFTWARE. ++ * ++ * Authors: ++ * Eric Anholt <eric@anholt.net> ++ * Keith Packard <keithp@keithp.com> ++ * ++ */ ++ ++#include <linux/seq_file.h> ++#include "drmP.h" ++#include "drm.h" ++#include "i915_drm.h" ++#include "i915_drv.h" ++ ++#define DRM_I915_RING_DEBUG 1 ++ ++ ++#if defined(CONFIG_DEBUG_FS) ++ ++#define ACTIVE_LIST 1 ++#define FLUSHING_LIST 2 ++#define INACTIVE_LIST 3 ++ ++static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv) ++{ ++ if (obj_priv->user_pin_count > 0) ++ return "P"; ++ else if (obj_priv->pin_count > 0) ++ return "p"; ++ else ++ return " "; ++} ++ ++static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv) ++{ ++ switch (obj_priv->tiling_mode) { ++ default: ++ case I915_TILING_NONE: return " "; ++ case I915_TILING_X: return "X"; ++ case I915_TILING_Y: return "Y"; ++ } ++} ++ ++static int i915_gem_object_list_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ uintptr_t list = (uintptr_t) node->info_ent->data; ++ struct list_head *head; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ struct drm_i915_gem_object *obj_priv; ++ spinlock_t *lock = NULL; ++ ++ switch (list) { ++ case ACTIVE_LIST: ++ seq_printf(m, "Active:\n"); ++ lock = &dev_priv->mm.active_list_lock; ++ head = &dev_priv->mm.active_list; ++ break; ++ case INACTIVE_LIST: ++ seq_printf(m, "Inactive:\n"); ++ head = &dev_priv->mm.inactive_list; ++ break; ++ case FLUSHING_LIST: ++ seq_printf(m, "Flushing:\n"); ++ head = &dev_priv->mm.flushing_list; ++ break; ++ default: ++ DRM_INFO("Ooops, unexpected list\n"); ++ return 0; ++ } ++ ++ if (lock) ++ spin_lock(lock); ++ list_for_each_entry(obj_priv, head, list) ++ { ++ struct drm_gem_object *obj = obj_priv->obj; ++ ++ seq_printf(m, " %p: %s %08x %08x %d", ++ obj, ++ get_pin_flag(obj_priv), ++ obj->read_domains, obj->write_domain, ++ obj_priv->last_rendering_seqno); ++ ++ if (obj->name) ++ seq_printf(m, " (name: %d)", obj->name); ++ if (obj_priv->fence_reg != I915_FENCE_REG_NONE) ++ seq_printf(m, " (fence: %d)", obj_priv->fence_reg); ++ if (obj_priv->gtt_space != NULL) ++ seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset); ++ ++ seq_printf(m, "\n"); ++ } ++ ++ if (lock) ++ spin_unlock(lock); ++ return 0; ++} ++ ++static int i915_gem_request_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ struct drm_i915_gem_request *gem_request; ++ ++ seq_printf(m, "Request:\n"); ++ list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) { ++ seq_printf(m, " %d @ %d\n", ++ gem_request->seqno, ++ (int) (jiffies - gem_request->emitted_jiffies)); ++ } ++ return 0; ++} ++ ++static int i915_gem_seqno_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ ++ if (dev_priv->hw_status_page != NULL) { ++ seq_printf(m, "Current sequence: %d\n", ++ i915_get_gem_seqno(dev)); ++ } else { ++ seq_printf(m, "Current sequence: hws uninitialized\n"); ++ } ++ seq_printf(m, "Waiter sequence: %d\n", ++ dev_priv->mm.waiting_gem_seqno); ++ seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno); ++ return 0; ++} ++ ++ ++static int i915_interrupt_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ ++ if (!IS_IGDNG(dev)) { ++ seq_printf(m, "Interrupt enable: %08x\n", ++ I915_READ(IER)); ++ seq_printf(m, "Interrupt identity: %08x\n", ++ I915_READ(IIR)); ++ seq_printf(m, "Interrupt mask: %08x\n", ++ I915_READ(IMR)); ++ seq_printf(m, "Pipe A stat: %08x\n", ++ I915_READ(PIPEASTAT)); ++ seq_printf(m, "Pipe B stat: %08x\n", ++ I915_READ(PIPEBSTAT)); ++ } else { ++ seq_printf(m, "North Display Interrupt enable: %08x\n", ++ I915_READ(DEIER)); ++ seq_printf(m, "North Display Interrupt identity: %08x\n", ++ I915_READ(DEIIR)); ++ seq_printf(m, "North Display Interrupt mask: %08x\n", ++ I915_READ(DEIMR)); ++ seq_printf(m, "South Display Interrupt enable: %08x\n", ++ I915_READ(SDEIER)); ++ seq_printf(m, "South Display Interrupt identity: %08x\n", ++ I915_READ(SDEIIR)); ++ seq_printf(m, "South Display Interrupt mask: %08x\n", ++ I915_READ(SDEIMR)); ++ seq_printf(m, "Graphics Interrupt enable: %08x\n", ++ I915_READ(GTIER)); ++ seq_printf(m, "Graphics Interrupt identity: %08x\n", ++ I915_READ(GTIIR)); ++ seq_printf(m, "Graphics Interrupt mask: %08x\n", ++ I915_READ(GTIMR)); ++ } ++ seq_printf(m, "Interrupts received: %d\n", ++ atomic_read(&dev_priv->irq_received)); ++ if (dev_priv->hw_status_page != NULL) { ++ seq_printf(m, "Current sequence: %d\n", ++ i915_get_gem_seqno(dev)); ++ } else { ++ seq_printf(m, "Current sequence: hws uninitialized\n"); ++ } ++ seq_printf(m, "Waiter sequence: %d\n", ++ dev_priv->mm.waiting_gem_seqno); ++ seq_printf(m, "IRQ sequence: %d\n", ++ dev_priv->mm.irq_gem_seqno); ++ return 0; ++} ++ ++static int i915_gem_fence_regs_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ int i; ++ ++ seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); ++ seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); ++ for (i = 0; i < dev_priv->num_fence_regs; i++) { ++ struct drm_gem_object *obj = dev_priv->fence_regs[i].obj; ++ ++ if (obj == NULL) { ++ seq_printf(m, "Fenced object[%2d] = unused\n", i); ++ } else { ++ struct drm_i915_gem_object *obj_priv; ++ ++ obj_priv = obj->driver_private; ++ seq_printf(m, "Fenced object[%2d] = %p: %s " ++ "%08x %08zx %08x %s %08x %08x %d", ++ i, obj, get_pin_flag(obj_priv), ++ obj_priv->gtt_offset, ++ obj->size, obj_priv->stride, ++ get_tiling_flag(obj_priv), ++ obj->read_domains, obj->write_domain, ++ obj_priv->last_rendering_seqno); ++ if (obj->name) ++ seq_printf(m, " (name: %d)", obj->name); ++ seq_printf(m, "\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static int i915_hws_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ int i; ++ volatile u32 *hws; ++ ++ hws = (volatile u32 *)dev_priv->hw_status_page; ++ if (hws == NULL) ++ return 0; ++ ++ for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { ++ seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ i * 4, ++ hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); ++ } ++ return 0; ++} ++ ++static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count) ++{ ++ int page, i; ++ uint32_t *mem; ++ ++ for (page = 0; page < page_count; page++) { ++ mem = kmap(pages[page]); ++ for (i = 0; i < PAGE_SIZE; i += 4) ++ seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); ++ kunmap(pages[page]); ++ } ++} ++ ++static int i915_batchbuffer_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ struct drm_gem_object *obj; ++ struct drm_i915_gem_object *obj_priv; ++ int ret; ++ ++ spin_lock(&dev_priv->mm.active_list_lock); ++ ++ list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { ++ obj = obj_priv->obj; ++ if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) { ++ ret = i915_gem_object_get_pages(obj); ++ if (ret) { ++ DRM_ERROR("Failed to get pages: %d\n", ret); ++ spin_unlock(&dev_priv->mm.active_list_lock); ++ return ret; ++ } ++ ++ seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset); ++ i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE); ++ ++ i915_gem_object_put_pages(obj); ++ } ++ } ++ ++ spin_unlock(&dev_priv->mm.active_list_lock); ++ ++ return 0; ++} ++ ++static int i915_ringbuffer_data(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ u8 *virt; ++ uint32_t *ptr, off; ++ ++ if (!dev_priv->ring.ring_obj) { ++ seq_printf(m, "No ringbuffer setup\n"); ++ return 0; ++ } ++ ++ virt = dev_priv->ring.virtual_start; ++ ++ for (off = 0; off < dev_priv->ring.Size; off += 4) { ++ ptr = (uint32_t *)(virt + off); ++ seq_printf(m, "%08x : %08x\n", off, *ptr); ++ } ++ ++ return 0; ++} ++ ++static int i915_ringbuffer_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ unsigned int head, tail; ++ ++ head = I915_READ(PRB0_HEAD) & HEAD_ADDR; ++ tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; ++ ++ seq_printf(m, "RingHead : %08x\n", head); ++ seq_printf(m, "RingTail : %08x\n", tail); ++ seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size); ++ seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); ++ ++ return 0; ++} ++ ++static int i915_error_state(struct seq_file *m, void *unused) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ struct drm_i915_error_state *error; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dev_priv->error_lock, flags); ++ if (!dev_priv->first_error) { ++ seq_printf(m, "no error state collected\n"); ++ goto out; ++ } ++ ++ error = dev_priv->first_error; ++ ++ seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, ++ error->time.tv_usec); ++ seq_printf(m, "EIR: 0x%08x\n", error->eir); ++ seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er); ++ seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); ++ seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); ++ seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); ++ seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); ++ seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); ++ if (IS_I965G(dev)) { ++ seq_printf(m, " INSTPS: 0x%08x\n", error->instps); ++ seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); ++ } ++ ++out: ++ spin_unlock_irqrestore(&dev_priv->error_lock, flags); ++ ++ return 0; ++} ++ ++static int i915_registers_info(struct seq_file *m, void *data) { ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ uint32_t reg; ++ ++#define DUMP_RANGE(start, end) \ ++ for (reg=start; reg < end; reg += 4) \ ++ seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg)); ++ ++ DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */ ++ DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */ ++ DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */ ++ DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */ ++ DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */ ++ DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */ ++ DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */ ++ DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */ ++ DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */ ++ DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */ ++ DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */ ++ DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */ ++ DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */ ++ DUMP_RANGE(0x73000, 0x73fff); /* performance counters */ ++ ++ return 0; ++} ++ ++ ++static struct drm_info_list i915_debugfs_list[] = { ++ {"i915_regs", i915_registers_info, 0}, ++ {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, ++ {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, ++ {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, ++ {"i915_gem_request", i915_gem_request_info, 0}, ++ {"i915_gem_seqno", i915_gem_seqno_info, 0}, ++ {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, ++ {"i915_gem_interrupt", i915_interrupt_info, 0}, ++ {"i915_gem_hws", i915_hws_info, 0}, ++ {"i915_ringbuffer_data", i915_ringbuffer_data, 0}, ++ {"i915_ringbuffer_info", i915_ringbuffer_info, 0}, ++ {"i915_batchbuffers", i915_batchbuffer_info, 0}, ++ {"i915_error_state", i915_error_state, 0}, ++}; ++#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) ++ ++int i915_debugfs_init(struct drm_minor *minor) ++{ ++ return drm_debugfs_create_files(i915_debugfs_list, ++ I915_DEBUGFS_ENTRIES, ++ minor->debugfs_root, minor); ++} ++ ++void i915_debugfs_cleanup(struct drm_minor *minor) ++{ ++ drm_debugfs_remove_files(i915_debugfs_list, ++ I915_DEBUGFS_ENTRIES, minor); ++} ++ ++#endif /* CONFIG_DEBUG_FS */ ++ +diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c +index 50d1f78..9909505 100644 +--- a/drivers/gpu/drm/i915/i915_dma.c ++++ b/drivers/gpu/drm/i915/i915_dma.c +@@ -29,12 +29,11 @@ + #include "drmP.h" + #include "drm.h" + #include "drm_crtc_helper.h" ++#include "drm_fb_helper.h" + #include "intel_drv.h" + #include "i915_drm.h" + #include "i915_drv.h" + +-#define I915_DRV "i915_drv" +- + /* Really want an OS-independent resettable timer. Would like to have + * this loop run for (eg) 3 sec, but have the timer reset every time + * the head pointer changes, so that EBUSY only happens if the ring +@@ -80,6 +79,34 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller) + return -EBUSY; + } + ++/* As a ringbuffer is only allowed to wrap between instructions, fill ++ * the tail with NOOPs. ++ */ ++int i915_wrap_ring(struct drm_device *dev) ++{ ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ volatile unsigned int *virt; ++ int rem; ++ ++ rem = dev_priv->ring.Size - dev_priv->ring.tail; ++ if (dev_priv->ring.space < rem) { ++ int ret = i915_wait_ring(dev, rem, __func__); ++ if (ret) ++ return ret; ++ } ++ dev_priv->ring.space -= rem; ++ ++ virt = (unsigned int *) ++ (dev_priv->ring.virtual_start + dev_priv->ring.tail); ++ rem /= 4; ++ while (rem--) ++ *virt++ = MI_NOOP; ++ ++ dev_priv->ring.tail = 0; ++ ++ return 0; ++} ++ + /** + * Sets up the hardware status page for devices that need a physical address + * in the register. +@@ -101,7 +128,7 @@ static int i915_init_phys_hws(struct drm_device *dev) + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + + I915_WRITE(HWS_PGA, dev_priv->dma_status_page); +- DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n"); ++ DRM_DEBUG_DRIVER("Enabled hardware status page\n"); + return 0; + } + +@@ -187,8 +214,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) + master_priv->sarea_priv = (drm_i915_sarea_t *) + ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); + } else { +- DRM_DEBUG_DRIVER(I915_DRV, +- "sarea not found assuming DRI2 userspace\n"); ++ DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); + } + + if (init->ring_size != 0) { +@@ -200,7 +226,6 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) + } + + dev_priv->ring.Size = init->ring_size; +- dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + + dev_priv->ring.map.offset = init->ring_start; + dev_priv->ring.map.size = init->ring_size; +@@ -238,7 +263,7 @@ static int i915_dma_resume(struct drm_device * dev) + { + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; + +- DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__); ++ DRM_DEBUG_DRIVER("%s\n", __func__); + + if (dev_priv->ring.map.handle == NULL) { + DRM_ERROR("can not ioremap virtual address for" +@@ -251,14 +276,14 @@ static int i915_dma_resume(struct drm_device * dev) + DRM_ERROR("Can not find hardware status page\n"); + return -EINVAL; + } +- DRM_DEBUG_DRIVER(I915_DRV, "hw status page @ %p\n", ++ DRM_DEBUG_DRIVER("hw status page @ %p\n", + dev_priv->hw_status_page); + + if (dev_priv->status_gfx_addr != 0) + I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); + else + I915_WRITE(HWS_PGA, dev_priv->dma_status_page); +- DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n"); ++ DRM_DEBUG_DRIVER("Enabled hardware status page\n"); + + return 0; + } +@@ -552,7 +577,7 @@ static int i915_dispatch_flip(struct drm_device * dev) + if (!master_priv->sarea_priv) + return -EINVAL; + +- DRM_DEBUG_DRIVER(I915_DRV, "%s: page=%d pfCurrentPage=%d\n", ++ DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", + __func__, + dev_priv->current_page, + master_priv->sarea_priv->pf_current_page); +@@ -633,8 +658,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data, + return -EINVAL; + } + +- DRM_DEBUG_DRIVER(I915_DRV, +- "i915 batchbuffer, start %x used %d cliprects %d\n", ++ DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", + batch->start, batch->used, batch->num_cliprects); + + RING_LOCK_TEST_WITH_RETURN(dev, file_priv); +@@ -681,8 +705,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, + void *batch_data; + int ret; + +- DRM_DEBUG_DRIVER(I915_DRV, +- "i915 cmdbuffer, buf %p sz %d cliprects %d\n", ++ DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", + cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); + + RING_LOCK_TEST_WITH_RETURN(dev, file_priv); +@@ -735,7 +758,7 @@ static int i915_flip_bufs(struct drm_device *dev, void *data, + { + int ret; + +- DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__); ++ DRM_DEBUG_DRIVER("%s\n", __func__); + + RING_LOCK_TEST_WITH_RETURN(dev, file_priv); + +@@ -778,7 +801,7 @@ static int i915_getparam(struct drm_device *dev, void *data, + value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; + break; + default: +- DRM_DEBUG_DRIVER(I915_DRV, "Unknown parameter %d\n", ++ DRM_DEBUG_DRIVER("Unknown parameter %d\n", + param->param); + return -EINVAL; + } +@@ -819,7 +842,7 @@ static int i915_setparam(struct drm_device *dev, void *data, + dev_priv->fence_reg_start = param->value; + break; + default: +- DRM_DEBUG_DRIVER(I915_DRV, "unknown parameter %d\n", ++ DRM_DEBUG_DRIVER("unknown parameter %d\n", + param->param); + return -EINVAL; + } +@@ -846,7 +869,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data, + return 0; + } + +- DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); ++ DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); + + dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); + +@@ -868,13 +891,25 @@ static int i915_set_status_page(struct drm_device *dev, void *data, + + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); +- DRM_DEBUG_DRIVER(I915_DRV, "load hws HWS_PGA with gfx mem 0x%x\n", ++ DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", + dev_priv->status_gfx_addr); +- DRM_DEBUG_DRIVER(I915_DRV, "load hws at %p\n", ++ DRM_DEBUG_DRIVER("load hws at %p\n", + dev_priv->hw_status_page); + return 0; + } + ++static int i915_get_bridge_dev(struct drm_device *dev) ++{ ++ struct drm_i915_private *dev_priv = dev->dev_private; ++ ++ dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); ++ if (!dev_priv->bridge_dev) { ++ DRM_ERROR("bridge device not found\n"); ++ return -1; ++ } ++ return 0; ++} ++ + /** + * i915_probe_agp - get AGP bootup configuration + * @pdev: PCI device +@@ -888,20 +923,13 @@ static int i915_set_status_page(struct drm_device *dev, void *data, + static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, + uint32_t *preallocated_size) + { +- struct pci_dev *bridge_dev; ++ struct drm_i915_private *dev_priv = dev->dev_private; + u16 tmp = 0; + unsigned long overhead; + unsigned long stolen; + +- bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); +- if (!bridge_dev) { +- DRM_ERROR("bridge device not found\n"); +- return -1; +- } +- + /* Get the fb aperture size and "stolen" memory amount. */ +- pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); +- pci_dev_put(bridge_dev); ++ pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); + + *aperture_size = 1024 * 1024; + *preallocated_size = 1024 * 1024; +@@ -1153,11 +1181,16 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) + base = drm_get_resource_start(dev, mmio_bar); + size = drm_get_resource_len(dev, mmio_bar); + ++ if (i915_get_bridge_dev(dev)) { ++ ret = -EIO; ++ goto free_priv; ++ } ++ + dev_priv->regs = ioremap(base, size); + if (!dev_priv->regs) { + DRM_ERROR("failed to map registers\n"); + ret = -EIO; +- goto free_priv; ++ goto put_bridge; + } + + dev_priv->mm.gtt_mapping = +@@ -1269,6 +1302,8 @@ out_iomapfree: + io_mapping_free(dev_priv->mm.gtt_mapping); + out_rmmap: + iounmap(dev_priv->regs); ++put_bridge: ++ pci_dev_put(dev_priv->bridge_dev); + free_priv: + kfree(dev_priv); + return ret; +@@ -1312,6 +1347,7 @@ int i915_driver_unload(struct drm_device *dev) + i915_gem_lastclose(dev); + } + ++ pci_dev_put(dev_priv->bridge_dev); + kfree(dev->dev_private); + + return 0; +@@ -1321,7 +1357,7 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) + { + struct drm_i915_file_private *i915_file_priv; + +- DRM_DEBUG_DRIVER(I915_DRV, "\n"); ++ DRM_DEBUG_DRIVER("\n"); + i915_file_priv = (struct drm_i915_file_private *) + kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); + +@@ -1352,7 +1388,7 @@ void i915_driver_lastclose(struct drm_device * dev) + drm_i915_private_t *dev_priv = dev->dev_private; + + if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { +- intelfb_restore(); ++ drm_fb_helper_restore(); + return; + } + +diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c +index fc4b68a..dbe568c 100644 +--- a/drivers/gpu/drm/i915/i915_drv.c ++++ b/drivers/gpu/drm/i915/i915_drv.c +@@ -37,12 +37,15 @@ + #include <linux/console.h> + #include "drm_crtc_helper.h" + +-static unsigned int i915_modeset = -1; ++static int i915_modeset = -1; + module_param_named(modeset, i915_modeset, int, 0400); + + unsigned int i915_fbpercrtc = 0; + module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); + ++unsigned int i915_powersave = 1; ++module_param_named(powersave, i915_powersave, int, 0400); ++ + static struct drm_driver driver; + + static struct pci_device_id pciidlist[] = { +@@ -188,8 +191,8 @@ static struct drm_driver driver = { + .master_create = i915_master_create, + .master_destroy = i915_master_destroy, + #if defined(CONFIG_DEBUG_FS) +- .debugfs_init = i915_gem_debugfs_init, +- .debugfs_cleanup = i915_gem_debugfs_cleanup, ++ .debugfs_init = i915_debugfs_init, ++ .debugfs_cleanup = i915_debugfs_cleanup, + #endif + .gem_init_object = i915_gem_init_object, + .gem_free_object = i915_gem_free_object, +diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h +index 5b4f87e..77ed060 100644 +--- a/drivers/gpu/drm/i915/i915_drv.h ++++ b/drivers/gpu/drm/i915/i915_drv.h +@@ -85,7 +85,6 @@ struct drm_i915_gem_phys_object { + }; + + typedef struct _drm_i915_ring_buffer { +- int tail_mask; + unsigned long Size; + u8 *virtual_start; + int head; +@@ -156,6 +155,7 @@ typedef struct drm_i915_private { + + void __iomem *regs; + ++ struct pci_dev *bridge_dev; + drm_i915_ring_buffer_t ring; + + drm_dma_handle_t *status_page_dmah; +@@ -311,7 +311,7 @@ typedef struct drm_i915_private { + u32 saveIMR; + u32 saveCACHE_MODE_0; + u32 saveD_STATE; +- u32 saveCG_2D_DIS; ++ u32 saveDSPCLK_GATE_D; + u32 saveMI_ARB_STATE; + u32 saveSWF0[16]; + u32 saveSWF1[16]; +@@ -443,6 +443,14 @@ typedef struct drm_i915_private { + struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; + } mm; + struct sdvo_device_mapping sdvo_mappings[2]; ++ ++ /* Reclocking support */ ++ bool render_reclock_avail; ++ bool lvds_downclock_avail; ++ struct work_struct idle_work; ++ struct timer_list idle_timer; ++ bool busy; ++ u16 orig_clock; + } drm_i915_private_t; + + /** driver private structure attached to each drm_gem_object */ +@@ -575,6 +583,7 @@ enum intel_chip_family { + extern struct drm_ioctl_desc i915_ioctls[]; + extern int i915_max_ioctl; + extern unsigned int i915_fbpercrtc; ++extern unsigned int i915_powersave; + + extern int i915_master_create(struct drm_device *dev, struct drm_master *master); + extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); +@@ -730,8 +739,8 @@ void i915_gem_dump_object(struct drm_gem_object *obj, int len, + void i915_dump_lru(struct drm_device *dev, const char *where); + + /* i915_debugfs.c */ +-int i915_gem_debugfs_init(struct drm_minor *minor); +-void i915_gem_debugfs_cleanup(struct drm_minor *minor); ++int i915_debugfs_init(struct drm_minor *minor); ++void i915_debugfs_cleanup(struct drm_minor *minor); + + /* i915_suspend.c */ + extern int i915_save_state(struct drm_device *dev); +@@ -781,33 +790,32 @@ extern void intel_modeset_cleanup(struct drm_device *dev); + + #define I915_VERBOSE 0 + +-#define RING_LOCALS unsigned int outring, ringmask, outcount; \ +- volatile char *virt; +- +-#define BEGIN_LP_RING(n) do { \ +- if (I915_VERBOSE) \ +- DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ +- if (dev_priv->ring.space < (n)*4) \ +- i915_wait_ring(dev, (n)*4, __func__); \ +- outcount = 0; \ +- outring = dev_priv->ring.tail; \ +- ringmask = dev_priv->ring.tail_mask; \ +- virt = dev_priv->ring.virtual_start; \ ++#define RING_LOCALS volatile unsigned int *ring_virt__; ++ ++#define BEGIN_LP_RING(n) do { \ ++ int bytes__ = 4*(n); \ ++ if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ ++ /* a wrap must occur between instructions so pad beforehand */ \ ++ if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \ ++ i915_wrap_ring(dev); \ ++ if (unlikely (dev_priv->ring.space < bytes__)) \ ++ i915_wait_ring(dev, bytes__, __func__); \ ++ ring_virt__ = (unsigned int *) \ ++ (dev_priv->ring.virtual_start + dev_priv->ring.tail); \ ++ dev_priv->ring.tail += bytes__; \ ++ dev_priv->ring.tail &= dev_priv->ring.Size - 1; \ ++ dev_priv->ring.space -= bytes__; \ + } while (0) + +-#define OUT_RING(n) do { \ ++#define OUT_RING(n) do { \ + if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ +- *(volatile unsigned int *)(virt + outring) = (n); \ +- outcount++; \ +- outring += 4; \ +- outring &= ringmask; \ ++ *ring_virt__++ = (n); \ + } while (0) + + #define ADVANCE_LP_RING() do { \ +- if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ +- dev_priv->ring.tail = outring; \ +- dev_priv->ring.space -= outcount * 4; \ +- I915_WRITE(PRB0_TAIL, outring); \ ++ if (I915_VERBOSE) \ ++ DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \ ++ I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \ + } while(0) + + /** +@@ -830,6 +838,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev); + #define I915_GEM_HWS_INDEX 0x20 + #define I915_BREADCRUMB_INDEX 0x21 + ++extern int i915_wrap_ring(struct drm_device * dev); + extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); + + #define IS_I830(dev) ((dev)->pci_device == 0x3577) +@@ -903,6 +912,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); + /* dsparb controlled by hw only */ + #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) + ++#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) ++#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) ++ + #define PRIMARY_RINGBUFFER_SIZE (128*1024) + + #endif +diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c +index 80e5ba4..c673171 100644 +--- a/drivers/gpu/drm/i915/i915_gem.c ++++ b/drivers/gpu/drm/i915/i915_gem.c +@@ -29,6 +29,7 @@ + #include "drm.h" + #include "i915_drm.h" + #include "i915_drv.h" ++#include "intel_drv.h" + #include <linux/swap.h> + #include <linux/pci.h> + +@@ -111,7 +112,8 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, + { + struct drm_i915_gem_create *args = data; + struct drm_gem_object *obj; +- int handle, ret; ++ int ret; ++ u32 handle; + + args->size = roundup(args->size, PAGE_SIZE); + +@@ -981,6 +983,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_gem_set_domain *args = data; + struct drm_gem_object *obj; ++ struct drm_i915_gem_object *obj_priv; + uint32_t read_domains = args->read_domains; + uint32_t write_domain = args->write_domain; + int ret; +@@ -1004,15 +1007,17 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, + obj = drm_gem_object_lookup(dev, file_priv, args->handle); + if (obj == NULL) + return -EBADF; ++ obj_priv = obj->driver_private; + + mutex_lock(&dev->struct_mutex); ++ ++ intel_mark_busy(dev, obj); ++ + #if WATCH_BUF + DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", + obj, obj->size, read_domains, write_domain); + #endif + if (read_domains & I915_GEM_DOMAIN_GTT) { +- struct drm_i915_gem_object *obj_priv = obj->driver_private; +- + ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); + + /* Update the LRU on the fence for the CPU access that's +@@ -2776,6 +2781,8 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) + BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); + BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); + ++ intel_mark_busy(dev, obj); ++ + #if WATCH_BUF + DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", + __func__, obj, +@@ -4093,7 +4100,6 @@ i915_gem_init_ringbuffer(struct drm_device *dev) + + /* Set up the kernel mapping for the ring. */ + ring->Size = obj->size; +- ring->tail_mask = obj->size - 1; + + ring->map.offset = dev->agp->base + obj_priv->gtt_offset; + ring->map.size = obj->size; +diff --git a/drivers/gpu/drm/i915/i915_gem_debugfs.c b/drivers/gpu/drm/i915/i915_gem_debugfs.c +deleted file mode 100644 +index cb3b974..0000000 +--- a/drivers/gpu/drm/i915/i915_gem_debugfs.c ++++ /dev/null +@@ -1,396 +0,0 @@ +-/* +- * Copyright © 2008 Intel Corporation +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +- * IN THE SOFTWARE. +- * +- * Authors: +- * Eric Anholt <eric@anholt.net> +- * Keith Packard <keithp@keithp.com> +- * +- */ +- +-#include <linux/seq_file.h> +-#include "drmP.h" +-#include "drm.h" +-#include "i915_drm.h" +-#include "i915_drv.h" +- +-#define DRM_I915_RING_DEBUG 1 +- +- +-#if defined(CONFIG_DEBUG_FS) +- +-#define ACTIVE_LIST 1 +-#define FLUSHING_LIST 2 +-#define INACTIVE_LIST 3 +- +-static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv) +-{ +- if (obj_priv->user_pin_count > 0) +- return "P"; +- else if (obj_priv->pin_count > 0) +- return "p"; +- else +- return " "; +-} +- +-static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv) +-{ +- switch (obj_priv->tiling_mode) { +- default: +- case I915_TILING_NONE: return " "; +- case I915_TILING_X: return "X"; +- case I915_TILING_Y: return "Y"; +- } +-} +- +-static int i915_gem_object_list_info(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- uintptr_t list = (uintptr_t) node->info_ent->data; +- struct list_head *head; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- struct drm_i915_gem_object *obj_priv; +- spinlock_t *lock = NULL; +- +- switch (list) { +- case ACTIVE_LIST: +- seq_printf(m, "Active:\n"); +- lock = &dev_priv->mm.active_list_lock; +- head = &dev_priv->mm.active_list; +- break; +- case INACTIVE_LIST: +- seq_printf(m, "Inactive:\n"); +- head = &dev_priv->mm.inactive_list; +- break; +- case FLUSHING_LIST: +- seq_printf(m, "Flushing:\n"); +- head = &dev_priv->mm.flushing_list; +- break; +- default: +- DRM_INFO("Ooops, unexpected list\n"); +- return 0; +- } +- +- if (lock) +- spin_lock(lock); +- list_for_each_entry(obj_priv, head, list) +- { +- struct drm_gem_object *obj = obj_priv->obj; +- +- seq_printf(m, " %p: %s %08x %08x %d", +- obj, +- get_pin_flag(obj_priv), +- obj->read_domains, obj->write_domain, +- obj_priv->last_rendering_seqno); +- +- if (obj->name) +- seq_printf(m, " (name: %d)", obj->name); +- if (obj_priv->fence_reg != I915_FENCE_REG_NONE) +- seq_printf(m, " (fence: %d)", obj_priv->fence_reg); +- if (obj_priv->gtt_space != NULL) +- seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset); +- +- seq_printf(m, "\n"); +- } +- +- if (lock) +- spin_unlock(lock); +- return 0; +-} +- +-static int i915_gem_request_info(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- struct drm_i915_gem_request *gem_request; +- +- seq_printf(m, "Request:\n"); +- list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) { +- seq_printf(m, " %d @ %d\n", +- gem_request->seqno, +- (int) (jiffies - gem_request->emitted_jiffies)); +- } +- return 0; +-} +- +-static int i915_gem_seqno_info(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- +- if (dev_priv->hw_status_page != NULL) { +- seq_printf(m, "Current sequence: %d\n", +- i915_get_gem_seqno(dev)); +- } else { +- seq_printf(m, "Current sequence: hws uninitialized\n"); +- } +- seq_printf(m, "Waiter sequence: %d\n", +- dev_priv->mm.waiting_gem_seqno); +- seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno); +- return 0; +-} +- +- +-static int i915_interrupt_info(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- +- seq_printf(m, "Interrupt enable: %08x\n", +- I915_READ(IER)); +- seq_printf(m, "Interrupt identity: %08x\n", +- I915_READ(IIR)); +- seq_printf(m, "Interrupt mask: %08x\n", +- I915_READ(IMR)); +- seq_printf(m, "Pipe A stat: %08x\n", +- I915_READ(PIPEASTAT)); +- seq_printf(m, "Pipe B stat: %08x\n", +- I915_READ(PIPEBSTAT)); +- seq_printf(m, "Interrupts received: %d\n", +- atomic_read(&dev_priv->irq_received)); +- if (dev_priv->hw_status_page != NULL) { +- seq_printf(m, "Current sequence: %d\n", +- i915_get_gem_seqno(dev)); +- } else { +- seq_printf(m, "Current sequence: hws uninitialized\n"); +- } +- seq_printf(m, "Waiter sequence: %d\n", +- dev_priv->mm.waiting_gem_seqno); +- seq_printf(m, "IRQ sequence: %d\n", +- dev_priv->mm.irq_gem_seqno); +- return 0; +-} +- +-static int i915_gem_fence_regs_info(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- int i; +- +- seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); +- seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); +- for (i = 0; i < dev_priv->num_fence_regs; i++) { +- struct drm_gem_object *obj = dev_priv->fence_regs[i].obj; +- +- if (obj == NULL) { +- seq_printf(m, "Fenced object[%2d] = unused\n", i); +- } else { +- struct drm_i915_gem_object *obj_priv; +- +- obj_priv = obj->driver_private; +- seq_printf(m, "Fenced object[%2d] = %p: %s " +- "%08x %08zx %08x %s %08x %08x %d", +- i, obj, get_pin_flag(obj_priv), +- obj_priv->gtt_offset, +- obj->size, obj_priv->stride, +- get_tiling_flag(obj_priv), +- obj->read_domains, obj->write_domain, +- obj_priv->last_rendering_seqno); +- if (obj->name) +- seq_printf(m, " (name: %d)", obj->name); +- seq_printf(m, "\n"); +- } +- } +- +- return 0; +-} +- +-static int i915_hws_info(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- int i; +- volatile u32 *hws; +- +- hws = (volatile u32 *)dev_priv->hw_status_page; +- if (hws == NULL) +- return 0; +- +- for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { +- seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", +- i * 4, +- hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); +- } +- return 0; +-} +- +-static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count) +-{ +- int page, i; +- uint32_t *mem; +- +- for (page = 0; page < page_count; page++) { +- mem = kmap(pages[page]); +- for (i = 0; i < PAGE_SIZE; i += 4) +- seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); +- kunmap(pages[page]); +- } +-} +- +-static int i915_batchbuffer_info(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- struct drm_gem_object *obj; +- struct drm_i915_gem_object *obj_priv; +- int ret; +- +- spin_lock(&dev_priv->mm.active_list_lock); +- +- list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { +- obj = obj_priv->obj; +- if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) { +- ret = i915_gem_object_get_pages(obj); +- if (ret) { +- DRM_ERROR("Failed to get pages: %d\n", ret); +- spin_unlock(&dev_priv->mm.active_list_lock); +- return ret; +- } +- +- seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset); +- i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE); +- +- i915_gem_object_put_pages(obj); +- } +- } +- +- spin_unlock(&dev_priv->mm.active_list_lock); +- +- return 0; +-} +- +-static int i915_ringbuffer_data(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- u8 *virt; +- uint32_t *ptr, off; +- +- if (!dev_priv->ring.ring_obj) { +- seq_printf(m, "No ringbuffer setup\n"); +- return 0; +- } +- +- virt = dev_priv->ring.virtual_start; +- +- for (off = 0; off < dev_priv->ring.Size; off += 4) { +- ptr = (uint32_t *)(virt + off); +- seq_printf(m, "%08x : %08x\n", off, *ptr); +- } +- +- return 0; +-} +- +-static int i915_ringbuffer_info(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- unsigned int head, tail, mask; +- +- head = I915_READ(PRB0_HEAD) & HEAD_ADDR; +- tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; +- mask = dev_priv->ring.tail_mask; +- +- seq_printf(m, "RingHead : %08x\n", head); +- seq_printf(m, "RingTail : %08x\n", tail); +- seq_printf(m, "RingMask : %08x\n", mask); +- seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size); +- seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); +- +- return 0; +-} +- +-static int i915_error_state(struct seq_file *m, void *unused) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct drm_device *dev = node->minor->dev; +- drm_i915_private_t *dev_priv = dev->dev_private; +- struct drm_i915_error_state *error; +- unsigned long flags; +- +- spin_lock_irqsave(&dev_priv->error_lock, flags); +- if (!dev_priv->first_error) { +- seq_printf(m, "no error state collected\n"); +- goto out; +- } +- +- error = dev_priv->first_error; +- +- seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, +- error->time.tv_usec); +- seq_printf(m, "EIR: 0x%08x\n", error->eir); +- seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er); +- seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); +- seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); +- seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); +- seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); +- seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); +- if (IS_I965G(dev)) { +- seq_printf(m, " INSTPS: 0x%08x\n", error->instps); +- seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); +- } +- +-out: +- spin_unlock_irqrestore(&dev_priv->error_lock, flags); +- +- return 0; +-} +- +-static struct drm_info_list i915_gem_debugfs_list[] = { +- {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, +- {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, +- {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, +- {"i915_gem_request", i915_gem_request_info, 0}, +- {"i915_gem_seqno", i915_gem_seqno_info, 0}, +- {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, +- {"i915_gem_interrupt", i915_interrupt_info, 0}, +- {"i915_gem_hws", i915_hws_info, 0}, +- {"i915_ringbuffer_data", i915_ringbuffer_data, 0}, +- {"i915_ringbuffer_info", i915_ringbuffer_info, 0}, +- {"i915_batchbuffers", i915_batchbuffer_info, 0}, +- {"i915_error_state", i915_error_state, 0}, +-}; +-#define I915_GEM_DEBUGFS_ENTRIES ARRAY_SIZE(i915_gem_debugfs_list) +- +-int i915_gem_debugfs_init(struct drm_minor *minor) +-{ +- return drm_debugfs_create_files(i915_gem_debugfs_list, +- I915_GEM_DEBUGFS_ENTRIES, +- minor->debugfs_root, minor); +-} +- +-void i915_gem_debugfs_cleanup(struct drm_minor *minor) +-{ +- drm_debugfs_remove_files(i915_gem_debugfs_list, +- I915_GEM_DEBUGFS_ENTRIES, minor); +-} +- +-#endif /* CONFIG_DEBUG_FS */ +- +diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c +index a2d527b..200e398 100644 +--- a/drivers/gpu/drm/i915/i915_gem_tiling.c ++++ b/drivers/gpu/drm/i915/i915_gem_tiling.c +@@ -94,23 +94,15 @@ + static int + intel_alloc_mchbar_resource(struct drm_device *dev) + { +- struct pci_dev *bridge_dev; + drm_i915_private_t *dev_priv = dev->dev_private; + int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; + u32 temp_lo, temp_hi = 0; + u64 mchbar_addr; + int ret = 0; + +- bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); +- if (!bridge_dev) { +- DRM_DEBUG("no bridge dev?!\n"); +- ret = -ENODEV; +- goto out; +- } +- + if (IS_I965G(dev)) +- pci_read_config_dword(bridge_dev, reg + 4, &temp_hi); +- pci_read_config_dword(bridge_dev, reg, &temp_lo); ++ pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); ++ pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); + mchbar_addr = ((u64)temp_hi << 32) | temp_lo; + + /* If ACPI doesn't have it, assume we need to allocate it ourselves */ +@@ -118,30 +110,28 @@ intel_alloc_mchbar_resource(struct drm_device *dev) + if (mchbar_addr && + pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { + ret = 0; +- goto out_put; ++ goto out; + } + #endif + + /* Get some space for it */ +- ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res, ++ ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, + MCHBAR_SIZE, MCHBAR_SIZE, + PCIBIOS_MIN_MEM, + 0, pcibios_align_resource, +- bridge_dev); ++ dev_priv->bridge_dev); + if (ret) { + DRM_DEBUG("failed bus alloc: %d\n", ret); + dev_priv->mch_res.start = 0; +- goto out_put; ++ goto out; + } + + if (IS_I965G(dev)) +- pci_write_config_dword(bridge_dev, reg + 4, ++ pci_write_config_dword(dev_priv->bridge_dev, reg + 4, + upper_32_bits(dev_priv->mch_res.start)); + +- pci_write_config_dword(bridge_dev, reg, ++ pci_write_config_dword(dev_priv->bridge_dev, reg, + lower_32_bits(dev_priv->mch_res.start)); +-out_put: +- pci_dev_put(bridge_dev); + out: + return ret; + } +@@ -150,44 +140,36 @@ out: + static bool + intel_setup_mchbar(struct drm_device *dev) + { +- struct pci_dev *bridge_dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; + int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; + u32 temp; + bool need_disable = false, enabled; + +- bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); +- if (!bridge_dev) { +- DRM_DEBUG("no bridge dev?!\n"); +- goto out; +- } +- + if (IS_I915G(dev) || IS_I915GM(dev)) { +- pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); ++ pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); + enabled = !!(temp & DEVEN_MCHBAR_EN); + } else { +- pci_read_config_dword(bridge_dev, mchbar_reg, &temp); ++ pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); + enabled = temp & 1; + } + + /* If it's already enabled, don't have to do anything */ + if (enabled) +- goto out_put; ++ goto out; + + if (intel_alloc_mchbar_resource(dev)) +- goto out_put; ++ goto out; + + need_disable = true; + + /* Space is allocated or reserved, so enable it. */ + if (IS_I915G(dev) || IS_I915GM(dev)) { +- pci_write_config_dword(bridge_dev, DEVEN_REG, ++ pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, + temp | DEVEN_MCHBAR_EN); + } else { +- pci_read_config_dword(bridge_dev, mchbar_reg, &temp); +- pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1); ++ pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); ++ pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); + } +-out_put: +- pci_dev_put(bridge_dev); + out: + return need_disable; + } +@@ -196,25 +178,18 @@ static void + intel_teardown_mchbar(struct drm_device *dev, bool disable) + { + drm_i915_private_t *dev_priv = dev->dev_private; +- struct pci_dev *bridge_dev; + int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; + u32 temp; + +- bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); +- if (!bridge_dev) { +- DRM_DEBUG("no bridge dev?!\n"); +- return; +- } +- + if (disable) { + if (IS_I915G(dev) || IS_I915GM(dev)) { +- pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); ++ pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); + temp &= ~DEVEN_MCHBAR_EN; +- pci_write_config_dword(bridge_dev, DEVEN_REG, temp); ++ pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); + } else { +- pci_read_config_dword(bridge_dev, mchbar_reg, &temp); ++ pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); + temp &= ~1; +- pci_write_config_dword(bridge_dev, mchbar_reg, temp); ++ pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); + } + } + +@@ -234,7 +209,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) + uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; + bool need_disable; + +- if (!IS_I9XX(dev)) { ++ if (IS_IGDNG(dev)) { ++ /* On IGDNG whatever DRAM config, GPU always do ++ * same swizzling setup. ++ */ ++ swizzle_x = I915_BIT_6_SWIZZLE_9_10; ++ swizzle_y = I915_BIT_6_SWIZZLE_9; ++ } else if (!IS_I9XX(dev)) { + /* As far as we know, the 865 doesn't have these bit 6 + * swizzling issues. + */ +@@ -317,13 +298,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) + } + } + +- /* FIXME: check with memory config on IGDNG */ +- if (IS_IGDNG(dev)) { +- DRM_ERROR("disable tiling on IGDNG...\n"); +- swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; +- swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; +- } +- + dev_priv->mm.bit_6_swizzle_x = swizzle_x; + dev_priv->mm.bit_6_swizzle_y = swizzle_y; + } +diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c +index 7ebc84c..6c89f2f 100644 +--- a/drivers/gpu/drm/i915/i915_irq.c ++++ b/drivers/gpu/drm/i915/i915_irq.c +@@ -565,6 +565,27 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) + + I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); + I915_READ(PORT_HOTPLUG_STAT); ++ ++ /* EOS interrupts occurs */ ++ if (IS_IGD(dev) && ++ (hotplug_status & CRT_EOS_INT_STATUS)) { ++ u32 temp; ++ ++ DRM_DEBUG("EOS interrupt occurs\n"); ++ /* status is already cleared */ ++ temp = I915_READ(ADPA); ++ temp &= ~ADPA_DAC_ENABLE; ++ I915_WRITE(ADPA, temp); ++ ++ temp = I915_READ(PORT_HOTPLUG_EN); ++ temp &= ~CRT_EOS_INT_EN; ++ I915_WRITE(PORT_HOTPLUG_EN, temp); ++ ++ temp = I915_READ(PORT_HOTPLUG_STAT); ++ if (temp & CRT_EOS_INT_STATUS) ++ I915_WRITE(PORT_HOTPLUG_STAT, ++ CRT_EOS_INT_STATUS); ++ } + } + + I915_WRITE(IIR, iir); +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +index 2955083..e38cd21 100644 +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -55,7 +55,7 @@ + /* PCI config space */ + + #define HPLLCC 0xc0 /* 855 only */ +-#define GC_CLOCK_CONTROL_MASK (3 << 0) ++#define GC_CLOCK_CONTROL_MASK (0xf << 0) + #define GC_CLOCK_133_200 (0 << 0) + #define GC_CLOCK_100_200 (1 << 0) + #define GC_CLOCK_100_133 (2 << 0) +@@ -65,6 +65,25 @@ + #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) + #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) + #define GC_DISPLAY_CLOCK_MASK (7 << 4) ++#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) ++#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) ++#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) ++#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) ++#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) ++#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) ++#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) ++#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) ++#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) ++#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) ++#define I945_GC_RENDER_CLOCK_MASK (7 << 0) ++#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) ++#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) ++#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) ++#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) ++#define I915_GC_RENDER_CLOCK_MASK (7 << 0) ++#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) ++#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) ++#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) + #define LBB 0xf4 + + /* VGA stuff */ +@@ -553,9 +572,118 @@ + #define DPLLA_TEST_M_BYPASS (1 << 2) + #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) + #define D_STATE 0x6104 +-#define CG_2D_DIS 0x6200 +-#define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) +-#define CG_3D_DIS 0x6204 ++#define DSTATE_PLL_D3_OFF (1<<3) ++#define DSTATE_GFX_CLOCK_GATING (1<<1) ++#define DSTATE_DOT_CLOCK_GATING (1<<0) ++#define DSPCLK_GATE_D 0x6200 ++# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ ++# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ ++# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ ++# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ ++# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ ++# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ ++# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ ++# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ ++# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ ++# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ ++# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ ++# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ ++# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ ++# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ ++# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ ++# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ ++# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ ++# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ ++# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ ++# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) ++# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) ++# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) ++# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) ++# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ ++# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ ++# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ ++# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) ++# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) ++/** ++ * This bit must be set on the 830 to prevent hangs when turning off the ++ * overlay scaler. ++ */ ++# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) ++# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) ++# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) ++# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ ++# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ ++ ++#define RENCLK_GATE_D1 0x6204 ++# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ ++# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ ++# define PC_FE_CLOCK_GATE_DISABLE (1 << 11) ++# define PC_BE_CLOCK_GATE_DISABLE (1 << 10) ++# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) ++# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) ++# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) ++# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) ++# define MAG_CLOCK_GATE_DISABLE (1 << 5) ++/** This bit must be unset on 855,865 */ ++# define MECI_CLOCK_GATE_DISABLE (1 << 4) ++# define DCMP_CLOCK_GATE_DISABLE (1 << 3) ++# define MEC_CLOCK_GATE_DISABLE (1 << 2) ++# define MECO_CLOCK_GATE_DISABLE (1 << 1) ++/** This bit must be set on 855,865. */ ++# define SV_CLOCK_GATE_DISABLE (1 << 0) ++# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) ++# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) ++# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) ++# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) ++# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) ++# define I915_WM_CLOCK_GATE_DISABLE (1 << 11) ++# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) ++# define I915_PI_CLOCK_GATE_DISABLE (1 << 9) ++# define I915_DI_CLOCK_GATE_DISABLE (1 << 8) ++# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) ++# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) ++# define I915_SC_CLOCK_GATE_DISABLE (1 << 5) ++# define I915_FL_CLOCK_GATE_DISABLE (1 << 4) ++# define I915_DM_CLOCK_GATE_DISABLE (1 << 3) ++# define I915_PS_CLOCK_GATE_DISABLE (1 << 2) ++# define I915_CC_CLOCK_GATE_DISABLE (1 << 1) ++# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) ++ ++# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) ++/** This bit must always be set on 965G/965GM */ ++# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) ++# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) ++# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) ++# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) ++# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) ++# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) ++/** This bit must always be set on 965G */ ++# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) ++# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) ++# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) ++# define I965_IF_CLOCK_GATE_DISABLE (1 << 20) ++# define I965_TC_CLOCK_GATE_DISABLE (1 << 19) ++# define I965_SO_CLOCK_GATE_DISABLE (1 << 17) ++# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) ++# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) ++# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) ++# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) ++# define I965_EM_CLOCK_GATE_DISABLE (1 << 12) ++# define I965_UC_CLOCK_GATE_DISABLE (1 << 11) ++# define I965_SI_CLOCK_GATE_DISABLE (1 << 6) ++# define I965_MT_CLOCK_GATE_DISABLE (1 << 5) ++# define I965_PL_CLOCK_GATE_DISABLE (1 << 4) ++# define I965_DG_CLOCK_GATE_DISABLE (1 << 3) ++# define I965_QC_CLOCK_GATE_DISABLE (1 << 2) ++# define I965_FT_CLOCK_GATE_DISABLE (1 << 1) ++# define I965_DM_CLOCK_GATE_DISABLE (1 << 0) ++ ++#define RENCLK_GATE_D2 0x6208 ++#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) ++#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) ++#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) ++#define RAMCLK_GATE_D 0x6210 /* CRL only */ ++#define DEUC 0x6214 /* CRL only */ + + /* + * Palette regs +@@ -683,6 +811,7 @@ + #define SDVOB_HOTPLUG_INT_EN (1 << 26) + #define SDVOC_HOTPLUG_INT_EN (1 << 25) + #define TV_HOTPLUG_INT_EN (1 << 18) ++#define CRT_EOS_INT_EN (1 << 10) + #define CRT_HOTPLUG_INT_EN (1 << 9) + #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) + #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) +@@ -717,6 +846,7 @@ + #define DPC_HOTPLUG_INT_STATUS (1 << 28) + #define HDMID_HOTPLUG_INT_STATUS (1 << 27) + #define DPD_HOTPLUG_INT_STATUS (1 << 27) ++#define CRT_EOS_INT_STATUS (1 << 12) + #define CRT_HOTPLUG_INT_STATUS (1 << 11) + #define TV_HOTPLUG_INT_STATUS (1 << 10) + #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +@@ -1586,6 +1716,7 @@ + #define PIPECONF_PROGRESSIVE (0 << 21) + #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) + #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) ++#define PIPECONF_CXSR_DOWNCLOCK (1<<16) + #define PIPEASTAT 0x70024 + #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) + #define PIPE_CRC_ERROR_ENABLE (1UL<<29) +@@ -1733,6 +1864,7 @@ + #define DISPPLANE_NO_LINE_DOUBLE 0 + #define DISPPLANE_STEREO_POLARITY_FIRST 0 + #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) ++#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* IGDNG */ + #define DISPPLANE_TILED (1<<10) + #define DSPAADDR 0x70184 + #define DSPASTRIDE 0x70188 +@@ -1913,6 +2045,9 @@ + #define GTIIR 0x44018 + #define GTIER 0x4401c + ++#define DISP_ARB_CTL 0x45000 ++#define DISP_TILE_SURFACE_SWIZZLING (1<<13) ++ + /* PCH */ + + /* south display engine interrupt */ +diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c +index 1d04e19..20d4d19 100644 +--- a/drivers/gpu/drm/i915/i915_suspend.c ++++ b/drivers/gpu/drm/i915/i915_suspend.c +@@ -461,7 +461,7 @@ int i915_save_state(struct drm_device *dev) + + /* Clock gating state */ + dev_priv->saveD_STATE = I915_READ(D_STATE); +- dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); ++ dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); + + /* Cache mode state */ + dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); +@@ -588,7 +588,7 @@ int i915_restore_state(struct drm_device *dev) + + /* Clock gating state */ + I915_WRITE (D_STATE, dev_priv->saveD_STATE); +- I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); ++ I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); + + /* Cache mode state */ + I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); +diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c +index f806fcc..1e28c16 100644 +--- a/drivers/gpu/drm/i915/intel_bios.c ++++ b/drivers/gpu/drm/i915/intel_bios.c +@@ -355,8 +355,14 @@ parse_driver_features(struct drm_i915_private *dev_priv, + } + + driver = find_section(bdb, BDB_DRIVER_FEATURES); +- if (driver && driver->lvds_config == BDB_DRIVER_FEATURE_EDP) ++ if (!driver) ++ return; ++ ++ if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP) + dev_priv->edp_support = 1; ++ ++ if (driver->dual_frequency) ++ dev_priv->render_reclock_avail = true; + } + + /** +diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c +index 590f81c..88814fa 100644 +--- a/drivers/gpu/drm/i915/intel_crt.c ++++ b/drivers/gpu/drm/i915/intel_crt.c +@@ -64,6 +64,34 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode) + } + + I915_WRITE(reg, temp); ++ ++ if (IS_IGD(dev)) { ++ if (mode == DRM_MODE_DPMS_OFF) { ++ /* turn off DAC */ ++ temp = I915_READ(PORT_HOTPLUG_EN); ++ temp &= ~CRT_EOS_INT_EN; ++ I915_WRITE(PORT_HOTPLUG_EN, temp); ++ ++ temp = I915_READ(PORT_HOTPLUG_STAT); ++ if (temp & CRT_EOS_INT_STATUS) ++ I915_WRITE(PORT_HOTPLUG_STAT, ++ CRT_EOS_INT_STATUS); ++ } else { ++ /* turn on DAC. EOS interrupt must be enabled after DAC ++ * is enabled, so it sounds not good to enable it in ++ * i915_driver_irq_postinstall() ++ * wait 12.5ms after DAC is enabled ++ */ ++ msleep(13); ++ temp = I915_READ(PORT_HOTPLUG_STAT); ++ if (temp & CRT_EOS_INT_STATUS) ++ I915_WRITE(PORT_HOTPLUG_STAT, ++ CRT_EOS_INT_STATUS); ++ temp = I915_READ(PORT_HOTPLUG_EN); ++ temp |= CRT_EOS_INT_EN; ++ I915_WRITE(PORT_HOTPLUG_EN, temp); ++ } ++ } + } + + static int intel_crt_mode_valid(struct drm_connector *connector, +diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c +index 748ed50..155719f 100644 +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -38,6 +38,7 @@ + + bool intel_pipe_has_type (struct drm_crtc *crtc, int type); + static void intel_update_watermarks(struct drm_device *dev); ++static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule); + + typedef struct { + /* given values */ +@@ -67,6 +68,8 @@ struct intel_limit { + intel_p2_t p2; + bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, + int, int, intel_clock_t *); ++ bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *, ++ int, int, intel_clock_t *); + }; + + #define I8XX_DOT_MIN 25000 +@@ -261,6 +264,9 @@ static bool + intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *best_clock); + static bool ++intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, ++ int target, int refclk, intel_clock_t *best_clock); ++static bool + intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *best_clock); + static bool +@@ -286,6 +292,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = { + .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, + .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, + .find_pll = intel_find_best_PLL, ++ .find_reduced_pll = intel_find_best_reduced_PLL, + }; + + static const intel_limit_t intel_limits_i8xx_lvds = { +@@ -300,6 +307,7 @@ static const intel_limit_t intel_limits_i8xx_lvds = { + .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, + .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, + .find_pll = intel_find_best_PLL, ++ .find_reduced_pll = intel_find_best_reduced_PLL, + }; + + static const intel_limit_t intel_limits_i9xx_sdvo = { +@@ -314,6 +322,7 @@ static const intel_limit_t intel_limits_i9xx_sdvo = { + .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, + .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, + .find_pll = intel_find_best_PLL, ++ .find_reduced_pll = intel_find_best_reduced_PLL, + }; + + static const intel_limit_t intel_limits_i9xx_lvds = { +@@ -331,6 +340,7 @@ static const intel_limit_t intel_limits_i9xx_lvds = { + .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, + .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, + .find_pll = intel_find_best_PLL, ++ .find_reduced_pll = intel_find_best_reduced_PLL, + }; + + /* below parameter and function is for G4X Chipset Family*/ +@@ -348,6 +358,7 @@ static const intel_limit_t intel_limits_g4x_sdvo = { + .p2_fast = G4X_P2_SDVO_FAST + }, + .find_pll = intel_g4x_find_best_PLL, ++ .find_reduced_pll = intel_g4x_find_best_PLL, + }; + + static const intel_limit_t intel_limits_g4x_hdmi = { +@@ -364,6 +375,7 @@ static const intel_limit_t intel_limits_g4x_hdmi = { + .p2_fast = G4X_P2_HDMI_DAC_FAST + }, + .find_pll = intel_g4x_find_best_PLL, ++ .find_reduced_pll = intel_g4x_find_best_PLL, + }; + + static const intel_limit_t intel_limits_g4x_single_channel_lvds = { +@@ -388,6 +400,7 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = { + .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST + }, + .find_pll = intel_g4x_find_best_PLL, ++ .find_reduced_pll = intel_g4x_find_best_PLL, + }; + + static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { +@@ -412,6 +425,7 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { + .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST + }, + .find_pll = intel_g4x_find_best_PLL, ++ .find_reduced_pll = intel_g4x_find_best_PLL, + }; + + static const intel_limit_t intel_limits_g4x_display_port = { +@@ -449,6 +463,7 @@ static const intel_limit_t intel_limits_igd_sdvo = { + .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, + .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, + .find_pll = intel_find_best_PLL, ++ .find_reduced_pll = intel_find_best_reduced_PLL, + }; + + static const intel_limit_t intel_limits_igd_lvds = { +@@ -464,6 +479,7 @@ static const intel_limit_t intel_limits_igd_lvds = { + .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, + .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, + .find_pll = intel_find_best_PLL, ++ .find_reduced_pll = intel_find_best_reduced_PLL, + }; + + static const intel_limit_t intel_limits_igdng_sdvo = { +@@ -688,15 +704,16 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + + memset (best_clock, 0, sizeof (*best_clock)); + +- for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { +- for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { +- /* m1 is always 0 in IGD */ +- if (clock.m2 >= clock.m1 && !IS_IGD(dev)) +- break; +- for (clock.n = limit->n.min; clock.n <= limit->n.max; +- clock.n++) { +- for (clock.p1 = limit->p1.min; +- clock.p1 <= limit->p1.max; clock.p1++) { ++ for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { ++ for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; ++ clock.m1++) { ++ for (clock.m2 = limit->m2.min; ++ clock.m2 <= limit->m2.max; clock.m2++) { ++ /* m1 is always 0 in IGD */ ++ if (clock.m2 >= clock.m1 && !IS_IGD(dev)) ++ break; ++ for (clock.n = limit->n.min; ++ clock.n <= limit->n.max; clock.n++) { + int this_err; + + intel_clock(dev, refclk, &clock); +@@ -717,6 +734,46 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + return (err != target); + } + ++ ++static bool ++intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, ++ int target, int refclk, intel_clock_t *best_clock) ++ ++{ ++ struct drm_device *dev = crtc->dev; ++ intel_clock_t clock; ++ int err = target; ++ bool found = false; ++ ++ memcpy(&clock, best_clock, sizeof(intel_clock_t)); ++ ++ for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { ++ for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { ++ /* m1 is always 0 in IGD */ ++ if (clock.m2 >= clock.m1 && !IS_IGD(dev)) ++ break; ++ for (clock.n = limit->n.min; clock.n <= limit->n.max; ++ clock.n++) { ++ int this_err; ++ ++ intel_clock(dev, refclk, &clock); ++ ++ if (!intel_PLL_is_valid(crtc, &clock)) ++ continue; ++ ++ this_err = abs(clock.dot - target); ++ if (this_err < err) { ++ *best_clock = clock; ++ err = this_err; ++ found = true; ++ } ++ } ++ } ++ } ++ ++ return found; ++} ++ + static bool + intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *best_clock) +@@ -747,7 +804,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + max_n = limit->n.max; + /* based on hardware requriment prefer smaller n to precision */ + for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { +- /* based on hardware requirment prefere larger m1,m2, p1 */ ++ /* based on hardware requirment prefere larger m1,m2 */ + for (clock.m1 = limit->m1.max; + clock.m1 >= limit->m1.min; clock.m1--) { + for (clock.m2 = limit->m2.max; +@@ -832,15 +889,14 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + + memset(best_clock, 0, sizeof(*best_clock)); + max_n = limit->n.max; +- /* based on hardware requriment prefer smaller n to precision */ +- for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { +- /* based on hardware requirment prefere larger m1,m2, p1 */ +- for (clock.m1 = limit->m1.max; +- clock.m1 >= limit->m1.min; clock.m1--) { +- for (clock.m2 = limit->m2.max; +- clock.m2 >= limit->m2.min; clock.m2--) { +- for (clock.p1 = limit->p1.max; +- clock.p1 >= limit->p1.min; clock.p1--) { ++ for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { ++ /* based on hardware requriment prefer smaller n to precision */ ++ for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { ++ /* based on hardware requirment prefere larger m1,m2 */ ++ for (clock.m1 = limit->m1.max; ++ clock.m1 >= limit->m1.min; clock.m1--) { ++ for (clock.m2 = limit->m2.max; ++ clock.m2 >= limit->m2.min; clock.m2--) { + int this_err; + + intel_clock(dev, refclk, &clock); +@@ -1008,6 +1064,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, + dspcntr &= ~DISPPLANE_TILED; + } + ++ if (IS_IGDNG(dev)) ++ /* must disable */ ++ dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; ++ + I915_WRITE(dspcntr_reg, dspcntr); + + Start = obj_priv->gtt_offset; +@@ -1030,8 +1090,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, + + if (old_fb) { + intel_fb = to_intel_framebuffer(old_fb); ++ obj_priv = intel_fb->obj->driver_private; + i915_gem_object_unpin(intel_fb->obj); + } ++ intel_increase_pllclock(crtc, true); ++ + mutex_unlock(&dev->struct_mutex); + + if (!dev->primary->master) +@@ -1581,6 +1644,8 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) + else + i9xx_crtc_dpms(crtc, mode); + ++ intel_crtc->dpms_mode = mode; ++ + if (!dev->primary->master) + return; + +@@ -1603,8 +1668,6 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) + DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); + break; + } +- +- intel_crtc->dpms_mode = mode; + } + + static void intel_crtc_prepare (struct drm_crtc *crtc) +@@ -2054,6 +2117,18 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane) + return size; + } + ++static void g4x_update_wm(struct drm_device *dev) ++{ ++ struct drm_i915_private *dev_priv = dev->dev_private; ++ u32 fw_blc_self = I915_READ(FW_BLC_SELF); ++ ++ if (i915_powersave) ++ fw_blc_self |= FW_BLC_SELF_EN; ++ else ++ fw_blc_self &= ~FW_BLC_SELF_EN; ++ I915_WRITE(FW_BLC_SELF, fw_blc_self); ++} ++ + static void i965_update_wm(struct drm_device *dev) + { + struct drm_i915_private *dev_priv = dev->dev_private; +@@ -2105,7 +2180,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, + cwm = 2; + + /* Calc sr entries for one plane configs */ +- if (sr_hdisplay && (!planea_clock || !planeb_clock)) { ++ if (HAS_FW_BLC(dev) && sr_hdisplay && ++ (!planea_clock || !planeb_clock)) { + /* self-refresh has much higher latency */ + const static int sr_latency_ns = 6000; + +@@ -2120,8 +2196,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, + srwm = total_size - sr_entries; + if (srwm < 0) + srwm = 1; +- if (IS_I9XX(dev)) +- I915_WRITE(FW_BLC_SELF, (srwm & 0x3f)); ++ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); + } + + DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", +@@ -2195,9 +2270,6 @@ static void intel_update_watermarks(struct drm_device *dev) + unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; + int enabled = 0, pixel_size = 0; + +- if (DSPARB_HWCONTROL(dev)) +- return; +- + /* Get the clock config from both planes */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + intel_crtc = to_intel_crtc(crtc); +@@ -2230,7 +2302,9 @@ static void intel_update_watermarks(struct drm_device *dev) + else if (IS_IGD(dev)) + igd_disable_cxsr(dev); + +- if (IS_I965G(dev)) ++ if (IS_G4X(dev)) ++ g4x_update_wm(dev); ++ else if (IS_I965G(dev)) + i965_update_wm(dev); + else if (IS_I9XX(dev) || IS_MOBILE(dev)) + i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay, +@@ -2264,9 +2338,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, + int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; + int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; + int refclk, num_outputs = 0; +- intel_clock_t clock; +- u32 dpll = 0, fp = 0, dspcntr, pipeconf; +- bool ok, is_sdvo = false, is_dvo = false; ++ intel_clock_t clock, reduced_clock; ++ u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; ++ bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; + bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; + bool is_edp = false; + struct drm_mode_config *mode_config = &dev->mode_config; +@@ -2349,6 +2423,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, + return -EINVAL; + } + ++ if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) { ++ memcpy(&reduced_clock, &clock, sizeof(intel_clock_t)); ++ has_reduced_clock = limit->find_reduced_pll(limit, crtc, ++ (adjusted_mode->clock*3/4), ++ refclk, ++ &reduced_clock); ++ } ++ + /* SDVO TV has fixed PLL values depend on its clock range, + this mirrors vbios setting. */ + if (is_sdvo && is_tv) { +@@ -2394,10 +2476,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, + link_bw, &m_n); + } + +- if (IS_IGD(dev)) ++ if (IS_IGD(dev)) { + fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; +- else ++ if (has_reduced_clock) ++ fp2 = (1 << reduced_clock.n) << 16 | ++ reduced_clock.m1 << 8 | reduced_clock.m2; ++ } else { + fp = clock.n << 16 | clock.m1 << 8 | clock.m2; ++ if (has_reduced_clock) ++ fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | ++ reduced_clock.m2; ++ } + + if (!IS_IGDNG(dev)) + dpll = DPLL_VGA_MODE_DIS; +@@ -2426,6 +2515,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, + /* also FPA1 */ + if (IS_IGDNG(dev)) + dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; ++ if (IS_G4X(dev) && has_reduced_clock) ++ dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; + } + switch (clock.p2) { + case 5: +@@ -2573,6 +2664,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, + udelay(150); + } + ++ if (is_lvds && has_reduced_clock && i915_powersave) { ++ I915_WRITE(fp_reg + 4, fp2); ++ intel_crtc->lowfreq_avail = true; ++ if (HAS_PIPE_CXSR(dev)) { ++ DRM_DEBUG("enabling CxSR downclocking\n"); ++ pipeconf |= PIPECONF_CXSR_DOWNCLOCK; ++ } ++ } else { ++ I915_WRITE(fp_reg + 4, fp); ++ intel_crtc->lowfreq_avail = false; ++ if (HAS_PIPE_CXSR(dev)) { ++ DRM_DEBUG("disabling CxSR downclocking\n"); ++ pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; ++ } ++ } ++ + I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | + ((adjusted_mode->crtc_htotal - 1) << 16)); + I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | +@@ -2616,6 +2723,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, + + intel_wait_for_vblank(dev); + ++ if (IS_IGDNG(dev)) { ++ /* enable address swizzle for tiling buffer */ ++ temp = I915_READ(DISP_ARB_CTL); ++ I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); ++ } ++ + I915_WRITE(dspcntr_reg, dspcntr); + + /* Flush the plane changes */ +@@ -2769,10 +2882,16 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ++ struct intel_framebuffer *intel_fb; + int pipe = intel_crtc->pipe; + uint32_t temp = 0; + uint32_t adder; + ++ if (crtc->fb) { ++ intel_fb = to_intel_framebuffer(crtc->fb); ++ intel_mark_busy(dev, intel_fb->obj); ++ } ++ + if (x < 0) { + temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; + x = -x; +@@ -3070,12 +3189,319 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, + return mode; + } + ++#define GPU_IDLE_TIMEOUT 500 /* ms */ ++ ++/* When this timer fires, we've been idle for awhile */ ++static void intel_gpu_idle_timer(unsigned long arg) ++{ ++ struct drm_device *dev = (struct drm_device *)arg; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ ++ DRM_DEBUG("idle timer fired, downclocking\n"); ++ ++ dev_priv->busy = false; ++ ++ queue_work(dev_priv->wq, &dev_priv->idle_work); ++} ++ ++void intel_increase_renderclock(struct drm_device *dev, bool schedule) ++{ ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ ++ if (IS_IGDNG(dev)) ++ return; ++ ++ if (!dev_priv->render_reclock_avail) { ++ DRM_DEBUG("not reclocking render clock\n"); ++ return; ++ } ++ ++ /* Restore render clock frequency to original value */ ++ if (IS_G4X(dev) || IS_I9XX(dev)) ++ pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock); ++ else if (IS_I85X(dev)) ++ pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock); ++ DRM_DEBUG("increasing render clock frequency\n"); ++ ++ /* Schedule downclock */ ++ if (schedule) ++ mod_timer(&dev_priv->idle_timer, jiffies + ++ msecs_to_jiffies(GPU_IDLE_TIMEOUT)); ++} ++ ++void intel_decrease_renderclock(struct drm_device *dev) ++{ ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ ++ if (IS_IGDNG(dev)) ++ return; ++ ++ if (!dev_priv->render_reclock_avail) { ++ DRM_DEBUG("not reclocking render clock\n"); ++ return; ++ } ++ ++ if (IS_G4X(dev)) { ++ u16 gcfgc; ++ ++ /* Adjust render clock... */ ++ pci_read_config_word(dev->pdev, GCFGC, &gcfgc); ++ ++ /* Down to minimum... */ ++ gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK; ++ gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ; ++ ++ pci_write_config_word(dev->pdev, GCFGC, gcfgc); ++ } else if (IS_I965G(dev)) { ++ u16 gcfgc; ++ ++ /* Adjust render clock... */ ++ pci_read_config_word(dev->pdev, GCFGC, &gcfgc); ++ ++ /* Down to minimum... */ ++ gcfgc &= ~I965_GC_RENDER_CLOCK_MASK; ++ gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ; ++ ++ pci_write_config_word(dev->pdev, GCFGC, gcfgc); ++ } else if (IS_I945G(dev) || IS_I945GM(dev)) { ++ u16 gcfgc; ++ ++ /* Adjust render clock... */ ++ pci_read_config_word(dev->pdev, GCFGC, &gcfgc); ++ ++ /* Down to minimum... */ ++ gcfgc &= ~I945_GC_RENDER_CLOCK_MASK; ++ gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ; ++ ++ pci_write_config_word(dev->pdev, GCFGC, gcfgc); ++ } else if (IS_I915G(dev)) { ++ u16 gcfgc; ++ ++ /* Adjust render clock... */ ++ pci_read_config_word(dev->pdev, GCFGC, &gcfgc); ++ ++ /* Down to minimum... */ ++ gcfgc &= ~I915_GC_RENDER_CLOCK_MASK; ++ gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ; ++ ++ pci_write_config_word(dev->pdev, GCFGC, gcfgc); ++ } else if (IS_I85X(dev)) { ++ u16 hpllcc; ++ ++ /* Adjust render clock... */ ++ pci_read_config_word(dev->pdev, HPLLCC, &hpllcc); ++ ++ /* Up to maximum... */ ++ hpllcc &= ~GC_CLOCK_CONTROL_MASK; ++ hpllcc |= GC_CLOCK_133_200; ++ ++ pci_write_config_word(dev->pdev, HPLLCC, hpllcc); ++ } ++ DRM_DEBUG("decreasing render clock frequency\n"); ++} ++ ++/* Note that no increase function is needed for this - increase_renderclock() ++ * will also rewrite these bits ++ */ ++void intel_decrease_displayclock(struct drm_device *dev) ++{ ++ if (IS_IGDNG(dev)) ++ return; ++ ++ if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) || ++ IS_I915GM(dev)) { ++ u16 gcfgc; ++ ++ /* Adjust render clock... */ ++ pci_read_config_word(dev->pdev, GCFGC, &gcfgc); ++ ++ /* Down to minimum... */ ++ gcfgc &= ~0xf0; ++ gcfgc |= 0x80; ++ ++ pci_write_config_word(dev->pdev, GCFGC, gcfgc); ++ } ++} ++ ++#define CRTC_IDLE_TIMEOUT 1000 /* ms */ ++ ++static void intel_crtc_idle_timer(unsigned long arg) ++{ ++ struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; ++ struct drm_crtc *crtc = &intel_crtc->base; ++ drm_i915_private_t *dev_priv = crtc->dev->dev_private; ++ ++ DRM_DEBUG("idle timer fired, downclocking\n"); ++ ++ intel_crtc->busy = false; ++ ++ queue_work(dev_priv->wq, &dev_priv->idle_work); ++} ++ ++static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule) ++{ ++ struct drm_device *dev = crtc->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ++ int pipe = intel_crtc->pipe; ++ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; ++ int dpll = I915_READ(dpll_reg); ++ ++ if (IS_IGDNG(dev)) ++ return; ++ ++ if (!dev_priv->lvds_downclock_avail) ++ return; ++ ++ if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { ++ DRM_DEBUG("upclocking LVDS\n"); ++ ++ /* Unlock panel regs */ ++ I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); ++ ++ dpll &= ~DISPLAY_RATE_SELECT_FPA1; ++ I915_WRITE(dpll_reg, dpll); ++ dpll = I915_READ(dpll_reg); ++ intel_wait_for_vblank(dev); ++ dpll = I915_READ(dpll_reg); ++ if (dpll & DISPLAY_RATE_SELECT_FPA1) ++ DRM_DEBUG("failed to upclock LVDS!\n"); ++ ++ /* ...and lock them again */ ++ I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); ++ } ++ ++ /* Schedule downclock */ ++ if (schedule) ++ mod_timer(&intel_crtc->idle_timer, jiffies + ++ msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); ++} ++ ++static void intel_decrease_pllclock(struct drm_crtc *crtc) ++{ ++ struct drm_device *dev = crtc->dev; ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ++ int pipe = intel_crtc->pipe; ++ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; ++ int dpll = I915_READ(dpll_reg); ++ ++ if (IS_IGDNG(dev)) ++ return; ++ ++ if (!dev_priv->lvds_downclock_avail) ++ return; ++ ++ /* ++ * Since this is called by a timer, we should never get here in ++ * the manual case. ++ */ ++ if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { ++ DRM_DEBUG("downclocking LVDS\n"); ++ ++ /* Unlock panel regs */ ++ I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); ++ ++ dpll |= DISPLAY_RATE_SELECT_FPA1; ++ I915_WRITE(dpll_reg, dpll); ++ dpll = I915_READ(dpll_reg); ++ intel_wait_for_vblank(dev); ++ dpll = I915_READ(dpll_reg); ++ if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) ++ DRM_DEBUG("failed to downclock LVDS!\n"); ++ ++ /* ...and lock them again */ ++ I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); ++ } ++ ++} ++ ++/** ++ * intel_idle_update - adjust clocks for idleness ++ * @work: work struct ++ * ++ * Either the GPU or display (or both) went idle. Check the busy status ++ * here and adjust the CRTC and GPU clocks as necessary. ++ */ ++static void intel_idle_update(struct work_struct *work) ++{ ++ drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, ++ idle_work); ++ struct drm_device *dev = dev_priv->dev; ++ struct drm_crtc *crtc; ++ struct intel_crtc *intel_crtc; ++ ++ if (!i915_powersave) ++ return; ++ ++ mutex_lock(&dev->struct_mutex); ++ ++ /* GPU isn't processing, downclock it. */ ++ if (!dev_priv->busy) { ++ intel_decrease_renderclock(dev); ++ intel_decrease_displayclock(dev); ++ } ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ /* Skip inactive CRTCs */ ++ if (!crtc->fb) ++ continue; ++ ++ intel_crtc = to_intel_crtc(crtc); ++ if (!intel_crtc->busy) ++ intel_decrease_pllclock(crtc); ++ } ++ ++ mutex_unlock(&dev->struct_mutex); ++} ++ ++/** ++ * intel_mark_busy - mark the GPU and possibly the display busy ++ * @dev: drm device ++ * @obj: object we're operating on ++ * ++ * Callers can use this function to indicate that the GPU is busy processing ++ * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout ++ * buffer), we'll also mark the display as busy, so we know to increase its ++ * clock frequency. ++ */ ++void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) ++{ ++ drm_i915_private_t *dev_priv = dev->dev_private; ++ struct drm_crtc *crtc = NULL; ++ struct intel_framebuffer *intel_fb; ++ struct intel_crtc *intel_crtc; ++ ++ if (!drm_core_check_feature(dev, DRIVER_MODESET)) ++ return; ++ ++ dev_priv->busy = true; ++ intel_increase_renderclock(dev, true); ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ if (!crtc->fb) ++ continue; ++ ++ intel_crtc = to_intel_crtc(crtc); ++ intel_fb = to_intel_framebuffer(crtc->fb); ++ if (intel_fb->obj == obj) { ++ if (!intel_crtc->busy) { ++ /* Non-busy -> busy, upclock */ ++ intel_increase_pllclock(crtc, true); ++ intel_crtc->busy = true; ++ } else { ++ /* Busy -> busy, put off timer */ ++ mod_timer(&intel_crtc->idle_timer, jiffies + ++ msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); ++ } ++ } ++ } ++} ++ + static void intel_crtc_destroy(struct drm_crtc *crtc) + { + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + +- if (intel_crtc->mode_set.mode) +- drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode); + drm_crtc_cleanup(crtc); + kfree(intel_crtc); + } +@@ -3122,15 +3548,10 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) + intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; + drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); + +- intel_crtc->mode_set.crtc = &intel_crtc->base; +- intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); +- intel_crtc->mode_set.num_connectors = 0; +- +- if (i915_fbpercrtc) { +- ++ intel_crtc->busy = false; + +- +- } ++ setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, ++ (unsigned long)intel_crtc); + } + + int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, +@@ -3138,30 +3559,26 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, + { + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; +- struct drm_crtc *crtc = NULL; +- int pipe = -1; ++ struct drm_mode_object *drmmode_obj; ++ struct intel_crtc *crtc; + + if (!dev_priv) { + DRM_ERROR("called with no initialization\n"); + return -EINVAL; + } + +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct intel_crtc *intel_crtc = to_intel_crtc(crtc); +- if (crtc->base.id == pipe_from_crtc_id->crtc_id) { +- pipe = intel_crtc->pipe; +- break; +- } +- } ++ drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, ++ DRM_MODE_OBJECT_CRTC); + +- if (pipe == -1) { ++ if (!drmmode_obj) { + DRM_ERROR("no such CRTC id\n"); + return -EINVAL; + } + +- pipe_from_crtc_id->pipe = pipe; ++ crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); ++ pipe_from_crtc_id->pipe = crtc->pipe; + +- return 0; ++ return 0; + } + + struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) +@@ -3362,8 +3779,56 @@ static const struct drm_mode_config_funcs intel_mode_funcs = { + .fb_changed = intelfb_probe, + }; + ++void intel_init_clock_gating(struct drm_device *dev) ++{ ++ struct drm_i915_private *dev_priv = dev->dev_private; ++ ++ /* ++ * Disable clock gating reported to work incorrectly according to the ++ * specs, but enable as much else as we can. ++ */ ++ if (IS_G4X(dev)) { ++ uint32_t dspclk_gate; ++ I915_WRITE(RENCLK_GATE_D1, 0); ++ I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | ++ GS_UNIT_CLOCK_GATE_DISABLE | ++ CL_UNIT_CLOCK_GATE_DISABLE); ++ I915_WRITE(RAMCLK_GATE_D, 0); ++ dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | ++ OVRUNIT_CLOCK_GATE_DISABLE | ++ OVCUNIT_CLOCK_GATE_DISABLE; ++ if (IS_GM45(dev)) ++ dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; ++ I915_WRITE(DSPCLK_GATE_D, dspclk_gate); ++ } else if (IS_I965GM(dev)) { ++ I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); ++ I915_WRITE(RENCLK_GATE_D2, 0); ++ I915_WRITE(DSPCLK_GATE_D, 0); ++ I915_WRITE(RAMCLK_GATE_D, 0); ++ I915_WRITE16(DEUC, 0); ++ } else if (IS_I965G(dev)) { ++ I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | ++ I965_RCC_CLOCK_GATE_DISABLE | ++ I965_RCPB_CLOCK_GATE_DISABLE | ++ I965_ISC_CLOCK_GATE_DISABLE | ++ I965_FBC_CLOCK_GATE_DISABLE); ++ I915_WRITE(RENCLK_GATE_D2, 0); ++ } else if (IS_I9XX(dev)) { ++ u32 dstate = I915_READ(D_STATE); ++ ++ dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | ++ DSTATE_DOT_CLOCK_GATING; ++ I915_WRITE(D_STATE, dstate); ++ } else if (IS_I855(dev) || IS_I865G(dev)) { ++ I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); ++ } else if (IS_I830(dev)) { ++ I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); ++ } ++} ++ + void intel_modeset_init(struct drm_device *dev) + { ++ struct drm_i915_private *dev_priv = dev->dev_private; + int num_pipe; + int i; + +@@ -3398,15 +3863,47 @@ void intel_modeset_init(struct drm_device *dev) + DRM_DEBUG("%d display pipe%s available.\n", + num_pipe, num_pipe > 1 ? "s" : ""); + ++ if (IS_I85X(dev)) ++ pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock); ++ else if (IS_I9XX(dev) || IS_G4X(dev)) ++ pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock); ++ + for (i = 0; i < num_pipe; i++) { + intel_crtc_init(dev, i); + } + + intel_setup_outputs(dev); ++ ++ intel_init_clock_gating(dev); ++ ++ INIT_WORK(&dev_priv->idle_work, intel_idle_update); ++ setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, ++ (unsigned long)dev); + } + + void intel_modeset_cleanup(struct drm_device *dev) + { ++ struct drm_i915_private *dev_priv = dev->dev_private; ++ struct drm_crtc *crtc; ++ struct intel_crtc *intel_crtc; ++ ++ mutex_lock(&dev->struct_mutex); ++ ++ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { ++ /* Skip inactive CRTCs */ ++ if (!crtc->fb) ++ continue; ++ ++ intel_crtc = to_intel_crtc(crtc); ++ intel_increase_pllclock(crtc, false); ++ del_timer_sync(&intel_crtc->idle_timer); ++ } ++ ++ intel_increase_renderclock(dev, false); ++ del_timer_sync(&dev_priv->idle_timer); ++ ++ mutex_unlock(&dev->struct_mutex); ++ + drm_mode_config_cleanup(dev); + } + +diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h +index 26a6227..51eec1b 100644 +--- a/drivers/gpu/drm/i915/intel_drv.h ++++ b/drivers/gpu/drm/i915/intel_drv.h +@@ -117,9 +117,9 @@ struct intel_crtc { + uint32_t cursor_addr; + u8 lut_r[256], lut_g[256], lut_b[256]; + int dpms_mode; +- struct intel_framebuffer *fbdev_fb; +- /* a mode_set for fbdev users on this crtc */ +- struct drm_mode_set mode_set; ++ bool busy; /* is scanout buffer being updated frequently? */ ++ struct timer_list idle_timer; ++ bool lowfreq_avail; + }; + + #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) +@@ -138,6 +138,7 @@ extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); + extern bool intel_sdvo_init(struct drm_device *dev, int output_device); + extern void intel_dvo_init(struct drm_device *dev); + extern void intel_tv_init(struct drm_device *dev); ++extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj); + extern void intel_lvds_init(struct drm_device *dev); + extern void intel_dp_init(struct drm_device *dev, int dp_reg); + void +diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c +index 1d30802..e85d7e9 100644 +--- a/drivers/gpu/drm/i915/intel_fb.c ++++ b/drivers/gpu/drm/i915/intel_fb.c +@@ -39,339 +39,34 @@ + #include "drmP.h" + #include "drm.h" + #include "drm_crtc.h" ++#include "drm_fb_helper.h" + #include "intel_drv.h" + #include "i915_drm.h" + #include "i915_drv.h" + + struct intelfb_par { +- struct drm_device *dev; +- struct drm_display_mode *our_mode; ++ struct drm_fb_helper helper; + struct intel_framebuffer *intel_fb; +- int crtc_count; +- /* crtc currently bound to this */ +- uint32_t crtc_ids[2]; ++ struct drm_display_mode *our_mode; + }; + +-static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green, +- unsigned blue, unsigned transp, +- struct fb_info *info) +-{ +- struct intelfb_par *par = info->par; +- struct drm_device *dev = par->dev; +- struct drm_crtc *crtc; +- int i; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct intel_crtc *intel_crtc = to_intel_crtc(crtc); +- struct drm_mode_set *modeset = &intel_crtc->mode_set; +- struct drm_framebuffer *fb = modeset->fb; +- +- for (i = 0; i < par->crtc_count; i++) +- if (crtc->base.id == par->crtc_ids[i]) +- break; +- +- if (i == par->crtc_count) +- continue; +- +- +- if (regno > 255) +- return 1; +- +- if (fb->depth == 8) { +- intel_crtc_fb_gamma_set(crtc, red, green, blue, regno); +- return 0; +- } +- +- if (regno < 16) { +- switch (fb->depth) { +- case 15: +- fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | +- ((green & 0xf800) >> 6) | +- ((blue & 0xf800) >> 11); +- break; +- case 16: +- fb->pseudo_palette[regno] = (red & 0xf800) | +- ((green & 0xfc00) >> 5) | +- ((blue & 0xf800) >> 11); +- break; +- case 24: +- case 32: +- fb->pseudo_palette[regno] = ((red & 0xff00) << 8) | +- (green & 0xff00) | +- ((blue & 0xff00) >> 8); +- break; +- } +- } +- } +- return 0; +-} +- +-static int intelfb_check_var(struct fb_var_screeninfo *var, +- struct fb_info *info) +-{ +- struct intelfb_par *par = info->par; +- struct intel_framebuffer *intel_fb = par->intel_fb; +- struct drm_framebuffer *fb = &intel_fb->base; +- int depth; +- +- if (var->pixclock == -1 || !var->pixclock) +- return -EINVAL; +- +- /* Need to resize the fb object !!! */ +- if (var->xres > fb->width || var->yres > fb->height) { +- DRM_ERROR("Requested width/height is greater than current fb object %dx%d > %dx%d\n",var->xres,var->yres,fb->width,fb->height); +- DRM_ERROR("Need resizing code.\n"); +- return -EINVAL; +- } +- +- switch (var->bits_per_pixel) { +- case 16: +- depth = (var->green.length == 6) ? 16 : 15; +- break; +- case 32: +- depth = (var->transp.length > 0) ? 32 : 24; +- break; +- default: +- depth = var->bits_per_pixel; +- break; +- } +- +- switch (depth) { +- case 8: +- var->red.offset = 0; +- var->green.offset = 0; +- var->blue.offset = 0; +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; +- var->transp.length = 0; +- var->transp.offset = 0; +- break; +- case 15: +- var->red.offset = 10; +- var->green.offset = 5; +- var->blue.offset = 0; +- var->red.length = 5; +- var->green.length = 5; +- var->blue.length = 5; +- var->transp.length = 1; +- var->transp.offset = 15; +- break; +- case 16: +- var->red.offset = 11; +- var->green.offset = 5; +- var->blue.offset = 0; +- var->red.length = 5; +- var->green.length = 6; +- var->blue.length = 5; +- var->transp.length = 0; +- var->transp.offset = 0; +- break; +- case 24: +- var->red.offset = 16; +- var->green.offset = 8; +- var->blue.offset = 0; +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; +- var->transp.length = 0; +- var->transp.offset = 0; +- break; +- case 32: +- var->red.offset = 16; +- var->green.offset = 8; +- var->blue.offset = 0; +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; +- var->transp.length = 8; +- var->transp.offset = 24; +- break; +- default: +- return -EINVAL; +- } +- +- return 0; +-} +- +-/* this will let fbcon do the mode init */ +-/* FIXME: take mode config lock? */ +-static int intelfb_set_par(struct fb_info *info) +-{ +- struct intelfb_par *par = info->par; +- struct drm_device *dev = par->dev; +- struct fb_var_screeninfo *var = &info->var; +- int i; +- +- DRM_DEBUG("%d %d\n", var->xres, var->pixclock); +- +- if (var->pixclock != -1) { +- +- DRM_ERROR("PIXEL CLOCK SET\n"); +- return -EINVAL; +- } else { +- struct drm_crtc *crtc; +- int ret; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct intel_crtc *intel_crtc = to_intel_crtc(crtc); +- +- for (i = 0; i < par->crtc_count; i++) +- if (crtc->base.id == par->crtc_ids[i]) +- break; +- +- if (i == par->crtc_count) +- continue; +- +- if (crtc->fb == intel_crtc->mode_set.fb) { +- mutex_lock(&dev->mode_config.mutex); +- ret = crtc->funcs->set_config(&intel_crtc->mode_set); +- mutex_unlock(&dev->mode_config.mutex); +- if (ret) +- return ret; +- } +- } +- return 0; +- } +-} +- +-static int intelfb_pan_display(struct fb_var_screeninfo *var, +- struct fb_info *info) +-{ +- struct intelfb_par *par = info->par; +- struct drm_device *dev = par->dev; +- struct drm_mode_set *modeset; +- struct drm_crtc *crtc; +- struct intel_crtc *intel_crtc; +- int ret = 0; +- int i; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- for (i = 0; i < par->crtc_count; i++) +- if (crtc->base.id == par->crtc_ids[i]) +- break; +- +- if (i == par->crtc_count) +- continue; +- +- intel_crtc = to_intel_crtc(crtc); +- modeset = &intel_crtc->mode_set; +- +- modeset->x = var->xoffset; +- modeset->y = var->yoffset; +- +- if (modeset->num_connectors) { +- mutex_lock(&dev->mode_config.mutex); +- ret = crtc->funcs->set_config(modeset); +- mutex_unlock(&dev->mode_config.mutex); +- if (!ret) { +- info->var.xoffset = var->xoffset; +- info->var.yoffset = var->yoffset; +- } +- } +- } +- +- return ret; +-} +- +-static void intelfb_on(struct fb_info *info) +-{ +- struct intelfb_par *par = info->par; +- struct drm_device *dev = par->dev; +- struct drm_crtc *crtc; +- struct drm_encoder *encoder; +- int i; +- +- /* +- * For each CRTC in this fb, find all associated encoders +- * and turn them off, then turn off the CRTC. +- */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; +- +- for (i = 0; i < par->crtc_count; i++) +- if (crtc->base.id == par->crtc_ids[i]) +- break; +- +- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); +- +- /* Found a CRTC on this fb, now find encoders */ +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- if (encoder->crtc == crtc) { +- struct drm_encoder_helper_funcs *encoder_funcs; +- encoder_funcs = encoder->helper_private; +- encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); +- } +- } +- } +-} +- +-static void intelfb_off(struct fb_info *info, int dpms_mode) +-{ +- struct intelfb_par *par = info->par; +- struct drm_device *dev = par->dev; +- struct drm_crtc *crtc; +- struct drm_encoder *encoder; +- int i; +- +- /* +- * For each CRTC in this fb, find all associated encoders +- * and turn them off, then turn off the CRTC. +- */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; +- +- for (i = 0; i < par->crtc_count; i++) +- if (crtc->base.id == par->crtc_ids[i]) +- break; +- +- /* Found a CRTC on this fb, now find encoders */ +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- if (encoder->crtc == crtc) { +- struct drm_encoder_helper_funcs *encoder_funcs; +- encoder_funcs = encoder->helper_private; +- encoder_funcs->dpms(encoder, dpms_mode); +- } +- } +- if (dpms_mode == DRM_MODE_DPMS_OFF) +- crtc_funcs->dpms(crtc, dpms_mode); +- } +-} +- +-static int intelfb_blank(int blank, struct fb_info *info) +-{ +- switch (blank) { +- case FB_BLANK_UNBLANK: +- intelfb_on(info); +- break; +- case FB_BLANK_NORMAL: +- intelfb_off(info, DRM_MODE_DPMS_STANDBY); +- break; +- case FB_BLANK_HSYNC_SUSPEND: +- intelfb_off(info, DRM_MODE_DPMS_STANDBY); +- break; +- case FB_BLANK_VSYNC_SUSPEND: +- intelfb_off(info, DRM_MODE_DPMS_SUSPEND); +- break; +- case FB_BLANK_POWERDOWN: +- intelfb_off(info, DRM_MODE_DPMS_OFF); +- break; +- } +- return 0; +-} +- + static struct fb_ops intelfb_ops = { + .owner = THIS_MODULE, +- .fb_check_var = intelfb_check_var, +- .fb_set_par = intelfb_set_par, +- .fb_setcolreg = intelfb_setcolreg, ++ .fb_check_var = drm_fb_helper_check_var, ++ .fb_set_par = drm_fb_helper_set_par, ++ .fb_setcolreg = drm_fb_helper_setcolreg, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +- .fb_pan_display = intelfb_pan_display, +- .fb_blank = intelfb_blank, ++ .fb_pan_display = drm_fb_helper_pan_display, ++ .fb_blank = drm_fb_helper_blank, + }; + ++static struct drm_fb_helper_funcs intel_fb_helper_funcs = { ++ .gamma_set = intel_crtc_fb_gamma_set, ++}; ++ ++ + /** + * Curretly it is assumed that the old framebuffer is reused. + * +@@ -412,25 +107,11 @@ int intelfb_resize(struct drm_device *dev, struct drm_crtc *crtc) + } + EXPORT_SYMBOL(intelfb_resize); + +-static struct drm_mode_set kernelfb_mode; +- +-static int intelfb_panic(struct notifier_block *n, unsigned long ununsed, +- void *panic_str) +-{ +- DRM_ERROR("panic occurred, switching back to text console\n"); +- +- intelfb_restore(); +- return 0; +-} +- +-static struct notifier_block paniced = { +- .notifier_call = intelfb_panic, +-}; +- + static int intelfb_create(struct drm_device *dev, uint32_t fb_width, + uint32_t fb_height, uint32_t surface_width, + uint32_t surface_height, +- struct intel_framebuffer **intel_fb_p) ++ uint32_t surface_depth, uint32_t surface_bpp, ++ struct drm_framebuffer **fb_p) + { + struct fb_info *info; + struct intelfb_par *par; +@@ -445,9 +126,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, + mode_cmd.width = surface_width; + mode_cmd.height = surface_height; + +- mode_cmd.bpp = 32; ++ mode_cmd.bpp = surface_bpp; + mode_cmd.pitch = ALIGN(mode_cmd.width * ((mode_cmd.bpp + 1) / 8), 64); +- mode_cmd.depth = 24; ++ mode_cmd.depth = surface_depth; + + size = mode_cmd.pitch * mode_cmd.height; + size = ALIGN(size, PAGE_SIZE); +@@ -479,7 +160,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, + list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list); + + intel_fb = to_intel_framebuffer(fb); +- *intel_fb_p = intel_fb; ++ *fb_p = fb; + + info = framebuffer_alloc(sizeof(struct intelfb_par), device); + if (!info) { +@@ -489,21 +170,19 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, + + par = info->par; + ++ par->helper.funcs = &intel_fb_helper_funcs; ++ par->helper.dev = dev; ++ ret = drm_fb_helper_init_crtc_count(&par->helper, 2, ++ INTELFB_CONN_LIMIT); ++ if (ret) ++ goto out_unref; ++ + strcpy(info->fix.id, "inteldrmfb"); +- info->fix.type = FB_TYPE_PACKED_PIXELS; +- info->fix.visual = FB_VISUAL_TRUECOLOR; +- info->fix.type_aux = 0; +- info->fix.xpanstep = 1; /* doing it in hw */ +- info->fix.ypanstep = 1; /* doing it in hw */ +- info->fix.ywrapstep = 0; +- info->fix.accel = FB_ACCEL_I830; +- info->fix.type_aux = 0; + + info->flags = FBINFO_DEFAULT; + + info->fbops = &intelfb_ops; + +- info->fix.line_length = fb->pitch; + + /* setup aperture base/size for vesafb takeover */ + info->aperture_base = dev->mode_config.fb_base; +@@ -527,18 +206,8 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, + + // memset(info->screen_base, 0, size); + +- info->pseudo_palette = fb->pseudo_palette; +- info->var.xres_virtual = fb->width; +- info->var.yres_virtual = fb->height; +- info->var.bits_per_pixel = fb->bits_per_pixel; +- info->var.xoffset = 0; +- info->var.yoffset = 0; +- info->var.activate = FB_ACTIVATE_NOW; +- info->var.height = -1; +- info->var.width = -1; +- +- info->var.xres = fb_width; +- info->var.yres = fb_height; ++ drm_fb_helper_fill_fix(info, fb->pitch); ++ drm_fb_helper_fill_var(info, fb, fb_width, fb_height); + + /* FIXME: we really shouldn't expose mmio space at all */ + info->fix.mmio_start = pci_resource_start(dev->pdev, mmio_bar); +@@ -550,64 +219,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, + info->pixmap.flags = FB_PIXMAP_SYSTEM; + info->pixmap.scan_align = 1; + +- switch(fb->depth) { +- case 8: +- info->var.red.offset = 0; +- info->var.green.offset = 0; +- info->var.blue.offset = 0; +- info->var.red.length = 8; /* 8bit DAC */ +- info->var.green.length = 8; +- info->var.blue.length = 8; +- info->var.transp.offset = 0; +- info->var.transp.length = 0; +- break; +- case 15: +- info->var.red.offset = 10; +- info->var.green.offset = 5; +- info->var.blue.offset = 0; +- info->var.red.length = 5; +- info->var.green.length = 5; +- info->var.blue.length = 5; +- info->var.transp.offset = 15; +- info->var.transp.length = 1; +- break; +- case 16: +- info->var.red.offset = 11; +- info->var.green.offset = 5; +- info->var.blue.offset = 0; +- info->var.red.length = 5; +- info->var.green.length = 6; +- info->var.blue.length = 5; +- info->var.transp.offset = 0; +- break; +- case 24: +- info->var.red.offset = 16; +- info->var.green.offset = 8; +- info->var.blue.offset = 0; +- info->var.red.length = 8; +- info->var.green.length = 8; +- info->var.blue.length = 8; +- info->var.transp.offset = 0; +- info->var.transp.length = 0; +- break; +- case 32: +- info->var.red.offset = 16; +- info->var.green.offset = 8; +- info->var.blue.offset = 0; +- info->var.red.length = 8; +- info->var.green.length = 8; +- info->var.blue.length = 8; +- info->var.transp.offset = 24; +- info->var.transp.length = 8; +- break; +- default: +- break; +- } +- + fb->fbdev = info; + + par->intel_fb = intel_fb; +- par->dev = dev; + + /* To allow resizeing without swapping buffers */ + DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width, +@@ -625,307 +239,12 @@ out: + return ret; + } + +-static int intelfb_multi_fb_probe_crtc(struct drm_device *dev, struct drm_crtc *crtc) +-{ +- struct intel_crtc *intel_crtc = to_intel_crtc(crtc); +- struct intel_framebuffer *intel_fb; +- struct drm_framebuffer *fb; +- struct drm_connector *connector; +- struct fb_info *info; +- struct intelfb_par *par; +- struct drm_mode_set *modeset; +- unsigned int width, height; +- int new_fb = 0; +- int ret, i, conn_count; +- +- if (!drm_helper_crtc_in_use(crtc)) +- return 0; +- +- if (!crtc->desired_mode) +- return 0; +- +- width = crtc->desired_mode->hdisplay; +- height = crtc->desired_mode->vdisplay; +- +- /* is there an fb bound to this crtc already */ +- if (!intel_crtc->mode_set.fb) { +- ret = intelfb_create(dev, width, height, width, height, &intel_fb); +- if (ret) +- return -EINVAL; +- new_fb = 1; +- } else { +- fb = intel_crtc->mode_set.fb; +- intel_fb = to_intel_framebuffer(fb); +- if ((intel_fb->base.width < width) || (intel_fb->base.height < height)) +- return -EINVAL; +- } +- +- info = intel_fb->base.fbdev; +- par = info->par; +- +- modeset = &intel_crtc->mode_set; +- modeset->fb = &intel_fb->base; +- conn_count = 0; +- list_for_each_entry(connector, &dev->mode_config.connector_list, head) { +- if (connector->encoder) +- if (connector->encoder->crtc == modeset->crtc) { +- modeset->connectors[conn_count] = connector; +- conn_count++; +- if (conn_count > INTELFB_CONN_LIMIT) +- BUG(); +- } +- } +- +- for (i = conn_count; i < INTELFB_CONN_LIMIT; i++) +- modeset->connectors[i] = NULL; +- +- par->crtc_ids[0] = crtc->base.id; +- +- modeset->num_connectors = conn_count; +- if (modeset->crtc->desired_mode) { +- if (modeset->mode) +- drm_mode_destroy(dev, modeset->mode); +- modeset->mode = drm_mode_duplicate(dev, +- modeset->crtc->desired_mode); +- } +- +- par->crtc_count = 1; +- +- if (new_fb) { +- info->var.pixclock = -1; +- if (register_framebuffer(info) < 0) +- return -EINVAL; +- } else +- intelfb_set_par(info); +- +- DRM_INFO("fb%d: %s frame buffer device\n", info->node, +- info->fix.id); +- +- /* Switch back to kernel console on panic */ +- kernelfb_mode = *modeset; +- atomic_notifier_chain_register(&panic_notifier_list, &paniced); +- DRM_DEBUG("registered panic notifier\n"); +- +- return 0; +-} +- +-static int intelfb_multi_fb_probe(struct drm_device *dev) +-{ +- +- struct drm_crtc *crtc; +- int ret = 0; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- ret = intelfb_multi_fb_probe_crtc(dev, crtc); +- if (ret) +- return ret; +- } +- return ret; +-} +- +-static int intelfb_single_fb_probe(struct drm_device *dev) +-{ +- struct drm_crtc *crtc; +- struct drm_connector *connector; +- unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; +- unsigned int surface_width = 0, surface_height = 0; +- int new_fb = 0; +- int crtc_count = 0; +- int ret, i, conn_count = 0; +- struct intel_framebuffer *intel_fb; +- struct fb_info *info; +- struct intelfb_par *par; +- struct drm_mode_set *modeset = NULL; +- +- DRM_DEBUG("\n"); +- +- /* Get a count of crtcs now in use and new min/maxes width/heights */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- if (!drm_helper_crtc_in_use(crtc)) +- continue; +- +- crtc_count++; +- if (!crtc->desired_mode) +- continue; +- +- /* Smallest mode determines console size... */ +- if (crtc->desired_mode->hdisplay < fb_width) +- fb_width = crtc->desired_mode->hdisplay; +- +- if (crtc->desired_mode->vdisplay < fb_height) +- fb_height = crtc->desired_mode->vdisplay; +- +- /* ... but largest for memory allocation dimensions */ +- if (crtc->desired_mode->hdisplay > surface_width) +- surface_width = crtc->desired_mode->hdisplay; +- +- if (crtc->desired_mode->vdisplay > surface_height) +- surface_height = crtc->desired_mode->vdisplay; +- } +- +- if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { +- /* hmm everyone went away - assume VGA cable just fell out +- and will come back later. */ +- DRM_DEBUG("no CRTCs available?\n"); +- return 0; +- } +- +-//fail +- /* Find the fb for our new config */ +- if (list_empty(&dev->mode_config.fb_kernel_list)) { +- DRM_DEBUG("creating new fb (console size %dx%d, " +- "buffer size %dx%d)\n", fb_width, fb_height, +- surface_width, surface_height); +- ret = intelfb_create(dev, fb_width, fb_height, surface_width, +- surface_height, &intel_fb); +- if (ret) +- return -EINVAL; +- new_fb = 1; +- } else { +- struct drm_framebuffer *fb; +- +- fb = list_first_entry(&dev->mode_config.fb_kernel_list, +- struct drm_framebuffer, filp_head); +- intel_fb = to_intel_framebuffer(fb); +- +- /* if someone hotplugs something bigger than we have already +- * allocated, we are pwned. As really we can't resize an +- * fbdev that is in the wild currently due to fbdev not really +- * being designed for the lower layers moving stuff around +- * under it. +- * - so in the grand style of things - punt. +- */ +- if ((fb->width < surface_width) || +- (fb->height < surface_height)) { +- DRM_ERROR("fb not large enough for console\n"); +- return -EINVAL; +- } +- } +-// fail +- +- info = intel_fb->base.fbdev; +- par = info->par; +- +- crtc_count = 0; +- /* +- * For each CRTC, set up the connector list for the CRTC's mode +- * set configuration. +- */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct intel_crtc *intel_crtc = to_intel_crtc(crtc); +- +- modeset = &intel_crtc->mode_set; +- modeset->fb = &intel_fb->base; +- conn_count = 0; +- list_for_each_entry(connector, &dev->mode_config.connector_list, +- head) { +- if (!connector->encoder) +- continue; +- +- if(connector->encoder->crtc == modeset->crtc) { +- modeset->connectors[conn_count++] = connector; +- if (conn_count > INTELFB_CONN_LIMIT) +- BUG(); +- } +- } +- +- /* Zero out remaining connector pointers */ +- for (i = conn_count; i < INTELFB_CONN_LIMIT; i++) +- modeset->connectors[i] = NULL; +- +- par->crtc_ids[crtc_count++] = crtc->base.id; +- +- modeset->num_connectors = conn_count; +- if (modeset->crtc->desired_mode) { +- if (modeset->mode) +- drm_mode_destroy(dev, modeset->mode); +- modeset->mode = drm_mode_duplicate(dev, +- modeset->crtc->desired_mode); +- } +- } +- par->crtc_count = crtc_count; +- +- if (new_fb) { +- info->var.pixclock = -1; +- if (register_framebuffer(info) < 0) +- return -EINVAL; +- } else +- intelfb_set_par(info); +- +- DRM_INFO("fb%d: %s frame buffer device\n", info->node, +- info->fix.id); +- +- /* Switch back to kernel console on panic */ +- kernelfb_mode = *modeset; +- atomic_notifier_chain_register(&panic_notifier_list, &paniced); +- DRM_DEBUG("registered panic notifier\n"); +- +- return 0; +-} +- +-/** +- * intelfb_restore - restore the framebuffer console (kernel) config +- * +- * Restore's the kernel's fbcon mode, used for lastclose & panic paths. +- */ +-void intelfb_restore(void) +-{ +- int ret; +- if ((ret = drm_crtc_helper_set_config(&kernelfb_mode)) != 0) { +- DRM_ERROR("Failed to restore crtc configuration: %d\n", +- ret); +- } +-} +- +-static void intelfb_restore_work_fn(struct work_struct *ignored) +-{ +- intelfb_restore(); +-} +-static DECLARE_WORK(intelfb_restore_work, intelfb_restore_work_fn); +- +-static void intelfb_sysrq(int dummy1, struct tty_struct *dummy3) +-{ +- schedule_work(&intelfb_restore_work); +-} +- +-static struct sysrq_key_op sysrq_intelfb_restore_op = { +- .handler = intelfb_sysrq, +- .help_msg = "force-fb(V)", +- .action_msg = "Restore framebuffer console", +-}; +- + int intelfb_probe(struct drm_device *dev) + { + int ret; + + DRM_DEBUG("\n"); +- +- /* something has changed in the lower levels of hell - deal with it +- here */ +- +- /* two modes : a) 1 fb to rule all crtcs. +- b) one fb per crtc. +- two actions 1) new connected device +- 2) device removed. +- case a/1 : if the fb surface isn't big enough - resize the surface fb. +- if the fb size isn't big enough - resize fb into surface. +- if everything big enough configure the new crtc/etc. +- case a/2 : undo the configuration +- possibly resize down the fb to fit the new configuration. +- case b/1 : see if it is on a new crtc - setup a new fb and add it. +- case b/2 : teardown the new fb. +- */ +- +- /* mode a first */ +- /* search for an fb */ +- if (i915_fbpercrtc == 1) { +- ret = intelfb_multi_fb_probe(dev); +- } else { +- ret = intelfb_single_fb_probe(dev); +- } +- +- register_sysrq_key('v', &sysrq_intelfb_restore_op); +- ++ ret = drm_fb_helper_single_fb_probe(dev, intelfb_create); + return ret; + } + EXPORT_SYMBOL(intelfb_probe); +@@ -940,13 +259,14 @@ int intelfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) + info = fb->fbdev; + + if (info) { ++ struct intelfb_par *par = info->par; + unregister_framebuffer(info); + iounmap(info->screen_base); ++ if (info->par) ++ drm_fb_helper_free(&par->helper); + framebuffer_release(info); + } + +- atomic_notifier_chain_unregister(&panic_notifier_list, &paniced); +- memset(&kernelfb_mode, 0, sizeof(struct drm_mode_set)); + return 0; + } + EXPORT_SYMBOL(intelfb_remove); +diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c +index 62b8bea..c7eab72 100644 +--- a/drivers/gpu/drm/i915/intel_i2c.c ++++ b/drivers/gpu/drm/i915/intel_i2c.c +@@ -42,11 +42,11 @@ void intel_i2c_quirk_set(struct drm_device *dev, bool enable) + if (!IS_IGD(dev)) + return; + if (enable) +- I915_WRITE(CG_2D_DIS, +- I915_READ(CG_2D_DIS) | DPCUNIT_CLOCK_GATE_DISABLE); ++ I915_WRITE(DSPCLK_GATE_D, ++ I915_READ(DSPCLK_GATE_D) | DPCUNIT_CLOCK_GATE_DISABLE); + else +- I915_WRITE(CG_2D_DIS, +- I915_READ(CG_2D_DIS) & (~DPCUNIT_CLOCK_GATE_DISABLE)); ++ I915_WRITE(DSPCLK_GATE_D, ++ I915_READ(DSPCLK_GATE_D) & (~DPCUNIT_CLOCK_GATE_DISABLE)); + } + + /* +diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c +index 8df02ef..dafc0da 100644 +--- a/drivers/gpu/drm/i915/intel_lvds.c ++++ b/drivers/gpu/drm/i915/intel_lvds.c +@@ -38,16 +38,6 @@ + #include "i915_drv.h" + #include <linux/acpi.h> + +-#define I915_LVDS "i915_lvds" +- +-/* +- * the following four scaling options are defined. +- * #define DRM_MODE_SCALE_NON_GPU 0 +- * #define DRM_MODE_SCALE_FULLSCREEN 1 +- * #define DRM_MODE_SCALE_NO_SCALE 2 +- * #define DRM_MODE_SCALE_ASPECT 3 +- */ +- + /* Private structure for the integrated LVDS support */ + struct intel_lvds_priv { + int fitting_mode; +@@ -336,7 +326,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, + I915_WRITE(BCLRPAT_B, 0); + + switch (lvds_priv->fitting_mode) { +- case DRM_MODE_SCALE_NO_SCALE: ++ case DRM_MODE_SCALE_CENTER: + /* + * For centered modes, we have to calculate border widths & + * heights and modify the values programmed into the CRTC. +@@ -672,9 +662,8 @@ static int intel_lvds_set_property(struct drm_connector *connector, + connector->encoder) { + struct drm_crtc *crtc = connector->encoder->crtc; + struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; +- if (value == DRM_MODE_SCALE_NON_GPU) { +- DRM_DEBUG_KMS(I915_LVDS, +- "non_GPU property is unsupported\n"); ++ if (value == DRM_MODE_SCALE_NONE) { ++ DRM_DEBUG_KMS("no scaling not supported\n"); + return 0; + } + if (lvds_priv->fitting_mode == value) { +@@ -731,8 +720,7 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = { + + static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) + { +- DRM_DEBUG_KMS(I915_LVDS, +- "Skipping LVDS initialization for %s\n", id->ident); ++ DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); + return 1; + } + +@@ -1027,7 +1015,7 @@ out: + return; + + failed: +- DRM_DEBUG_KMS(I915_LVDS, "No LVDS modes found, disabling.\n"); ++ DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); + if (intel_output->ddc_bus) + intel_i2c_destroy(intel_output->ddc_bus); + drm_connector_cleanup(connector); +diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c +index d3b74ba..0bf28ef 100644 +--- a/drivers/gpu/drm/i915/intel_sdvo.c ++++ b/drivers/gpu/drm/i915/intel_sdvo.c +@@ -37,7 +37,19 @@ + #include "intel_sdvo_regs.h" + + #undef SDVO_DEBUG +-#define I915_SDVO "i915_sdvo" ++ ++static char *tv_format_names[] = { ++ "NTSC_M" , "NTSC_J" , "NTSC_443", ++ "PAL_B" , "PAL_D" , "PAL_G" , ++ "PAL_H" , "PAL_I" , "PAL_M" , ++ "PAL_N" , "PAL_NC" , "PAL_60" , ++ "SECAM_B" , "SECAM_D" , "SECAM_G" , ++ "SECAM_K" , "SECAM_K1", "SECAM_L" , ++ "SECAM_60" ++}; ++ ++#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) ++ + struct intel_sdvo_priv { + u8 slave_addr; + +@@ -71,6 +83,15 @@ struct intel_sdvo_priv { + */ + bool is_tv; + ++ /* This is for current tv format name */ ++ char *tv_format_name; ++ ++ /* This contains all current supported TV format */ ++ char *tv_format_supported[TV_FORMAT_NUM]; ++ int format_supported_num; ++ struct drm_property *tv_format_property; ++ struct drm_property *tv_format_name_property[TV_FORMAT_NUM]; ++ + /** + * This is set if we treat the device as HDMI, instead of DVI. + */ +@@ -97,14 +118,6 @@ struct intel_sdvo_priv { + */ + struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; + +- /** +- * Current selected TV format. +- * +- * This is stored in the same structure that's passed to the device, for +- * convenience. +- */ +- struct intel_sdvo_tv_format tv_format; +- + /* + * supported encoding mode, used to determine whether HDMI is + * supported +@@ -114,6 +127,9 @@ struct intel_sdvo_priv { + /* DDC bus used by this SDVO output */ + uint8_t ddc_bus; + ++ /* Mac mini hack -- use the same DDC as the analog connector */ ++ struct i2c_adapter *analog_ddc_bus; ++ + int save_sdvo_mult; + u16 save_active_outputs; + struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; +@@ -188,7 +204,7 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr, + return true; + } + +- DRM_DEBUG("i2c transfer returned %d\n", ret); ++ DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); + return false; + } + +@@ -298,7 +314,7 @@ static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd, + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + int i; + +- DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ", ++ DRM_DEBUG_KMS("%s: W: %02X ", + SDVO_NAME(sdvo_priv), cmd); + for (i = 0; i < args_len; i++) + DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); +@@ -351,7 +367,7 @@ static void intel_sdvo_debug_response(struct intel_output *intel_output, + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + int i; + +- DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv)); ++ DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv)); + for (i = 0; i < response_len; i++) + DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); + for (; i < 8; i++) +@@ -668,10 +684,10 @@ static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output) + status = intel_sdvo_read_response(intel_output, &response, 1); + + if (status != SDVO_CMD_STATUS_SUCCESS) { +- DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n"); ++ DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n"); + return SDVO_CLOCK_RATE_MULT_1X; + } else { +- DRM_DEBUG("Current clock rate multiplier: %d\n", response); ++ DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response); + } + + return response; +@@ -945,23 +961,28 @@ static void intel_sdvo_set_avi_infoframe(struct intel_output *output, + + static void intel_sdvo_set_tv_format(struct intel_output *output) + { ++ ++ struct intel_sdvo_tv_format format; + struct intel_sdvo_priv *sdvo_priv = output->dev_priv; +- struct intel_sdvo_tv_format *format, unset; +- u8 status; ++ uint32_t format_map, i; ++ uint8_t status; + +- format = &sdvo_priv->tv_format; +- memset(&unset, 0, sizeof(unset)); +- if (memcmp(format, &unset, sizeof(*format))) { +- DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n", +- SDVO_NAME(sdvo_priv)); +- format->ntsc_m = 1; +- intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format, +- sizeof(*format)); +- status = intel_sdvo_read_response(output, NULL, 0); +- if (status != SDVO_CMD_STATUS_SUCCESS) +- DRM_DEBUG("%s: Failed to set TV format\n", +- SDVO_NAME(sdvo_priv)); +- } ++ for (i = 0; i < TV_FORMAT_NUM; i++) ++ if (tv_format_names[i] == sdvo_priv->tv_format_name) ++ break; ++ ++ format_map = 1 << i; ++ memset(&format, 0, sizeof(format)); ++ memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? ++ sizeof(format) : sizeof(format_map)); ++ ++ intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map, ++ sizeof(format)); ++ ++ status = intel_sdvo_read_response(output, NULL, 0); ++ if (status != SDVO_CMD_STATUS_SUCCESS) ++ DRM_DEBUG("%s: Failed to set TV format\n", ++ SDVO_NAME(sdvo_priv)); + } + + static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, +@@ -1230,8 +1251,8 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) + * a given it the status is a success, we succeeded. + */ + if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { +- DRM_DEBUG("First %s output reported failure to sync\n", +- SDVO_NAME(sdvo_priv)); ++ DRM_DEBUG_KMS("First %s output reported failure to " ++ "sync\n", SDVO_NAME(sdvo_priv)); + } + + if (0) +@@ -1326,8 +1347,8 @@ static void intel_sdvo_restore(struct drm_connector *connector) + intel_wait_for_vblank(dev); + status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2); + if (status == SDVO_CMD_STATUS_SUCCESS && !input1) +- DRM_DEBUG("First %s output reported failure to sync\n", +- SDVO_NAME(sdvo_priv)); ++ DRM_DEBUG_KMS("First %s output reported failure to " ++ "sync\n", SDVO_NAME(sdvo_priv)); + } + + intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs); +@@ -1405,7 +1426,7 @@ int intel_sdvo_supports_hotplug(struct drm_connector *connector) + u8 response[2]; + u8 status; + struct intel_output *intel_output; +- DRM_DEBUG("\n"); ++ DRM_DEBUG_KMS("\n"); + + if (!connector) + return 0; +@@ -1478,6 +1499,36 @@ intel_sdvo_multifunc_encoder(struct intel_output *intel_output) + return (caps > 1); + } + ++static struct drm_connector * ++intel_find_analog_connector(struct drm_device *dev) ++{ ++ struct drm_connector *connector; ++ struct intel_output *intel_output; ++ ++ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { ++ intel_output = to_intel_output(connector); ++ if (intel_output->type == INTEL_OUTPUT_ANALOG) ++ return connector; ++ } ++ return NULL; ++} ++ ++static int ++intel_analog_is_connected(struct drm_device *dev) ++{ ++ struct drm_connector *analog_connector; ++ analog_connector = intel_find_analog_connector(dev); ++ ++ if (!analog_connector) ++ return false; ++ ++ if (analog_connector->funcs->detect(analog_connector) == ++ connector_status_disconnected) ++ return false; ++ ++ return true; ++} ++ + enum drm_connector_status + intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) + { +@@ -1488,6 +1539,15 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) + + edid = drm_get_edid(&intel_output->base, + intel_output->ddc_bus); ++ ++ /* when there is no edid and no monitor is connected with VGA ++ * port, try to use the CRT ddc to read the EDID for DVI-connector ++ */ ++ if (edid == NULL && ++ sdvo_priv->analog_ddc_bus && ++ !intel_analog_is_connected(intel_output->base.dev)) ++ edid = drm_get_edid(&intel_output->base, ++ sdvo_priv->analog_ddc_bus); + if (edid != NULL) { + /* Don't report the output as connected if it's a DVI-I + * connector with a non-digital EDID coming out. +@@ -1516,10 +1576,11 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect + struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + +- intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); ++ intel_sdvo_write_cmd(intel_output, ++ SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); + status = intel_sdvo_read_response(intel_output, &response, 2); + +- DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8); ++ DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); + + if (status != SDVO_CMD_STATUS_SUCCESS) + return connector_status_unknown; +@@ -1540,50 +1601,32 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect + static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) + { + struct intel_output *intel_output = to_intel_output(connector); ++ struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; ++ int num_modes; + + /* set the bus switch and get the modes */ +- intel_ddc_get_modes(intel_output); ++ num_modes = intel_ddc_get_modes(intel_output); + +-#if 0 +- struct drm_device *dev = encoder->dev; +- struct drm_i915_private *dev_priv = dev->dev_private; +- /* Mac mini hack. On this device, I get DDC through the analog, which +- * load-detects as disconnected. I fail to DDC through the SDVO DDC, +- * but it does load-detect as connected. So, just steal the DDC bits +- * from analog when we fail at finding it the right way. ++ /* ++ * Mac mini hack. On this device, the DVI-I connector shares one DDC ++ * link between analog and digital outputs. So, if the regular SDVO ++ * DDC fails, check to see if the analog output is disconnected, in ++ * which case we'll look there for the digital DDC data. + */ +- crt = xf86_config->output[0]; +- intel_output = crt->driver_private; +- if (intel_output->type == I830_OUTPUT_ANALOG && +- crt->funcs->detect(crt) == XF86OutputStatusDisconnected) { +- I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A"); +- edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus); +- xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true); +- } +- if (edid_mon) { +- xf86OutputSetEDID(output, edid_mon); +- modes = xf86OutputGetEDIDModes(output); +- } +-#endif +-} ++ if (num_modes == 0 && ++ sdvo_priv->analog_ddc_bus && ++ !intel_analog_is_connected(intel_output->base.dev)) { ++ struct i2c_adapter *digital_ddc_bus; + +-/** +- * This function checks the current TV format, and chooses a default if +- * it hasn't been set. +- */ +-static void +-intel_sdvo_check_tv_format(struct intel_output *output) +-{ +- struct intel_sdvo_priv *dev_priv = output->dev_priv; +- struct intel_sdvo_tv_format format; +- uint8_t status; ++ /* Switch to the analog ddc bus and try that ++ */ ++ digital_ddc_bus = intel_output->ddc_bus; ++ intel_output->ddc_bus = sdvo_priv->analog_ddc_bus; + +- intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0); +- status = intel_sdvo_read_response(output, &format, sizeof(format)); +- if (status != SDVO_CMD_STATUS_SUCCESS) +- return; ++ (void) intel_ddc_get_modes(intel_output); + +- memcpy(&dev_priv->tv_format, &format, sizeof(format)); ++ intel_output->ddc_bus = digital_ddc_bus; ++ } + } + + /* +@@ -1656,17 +1699,26 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector) + struct intel_output *output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = output->dev_priv; + struct intel_sdvo_sdtv_resolution_request tv_res; +- uint32_t reply = 0; ++ uint32_t reply = 0, format_map = 0; ++ int i; + uint8_t status; +- int i = 0; + +- intel_sdvo_check_tv_format(output); + + /* Read the list of supported input resolutions for the selected TV + * format. + */ +- memset(&tv_res, 0, sizeof(tv_res)); +- memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res)); ++ for (i = 0; i < TV_FORMAT_NUM; i++) ++ if (tv_format_names[i] == sdvo_priv->tv_format_name) ++ break; ++ ++ format_map = (1 << i); ++ memcpy(&tv_res, &format_map, ++ sizeof(struct intel_sdvo_sdtv_resolution_request) > ++ sizeof(format_map) ? sizeof(format_map) : ++ sizeof(struct intel_sdvo_sdtv_resolution_request)); ++ ++ intel_sdvo_set_target_output(output, sdvo_priv->controlled_output); ++ + intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, + &tv_res, sizeof(tv_res)); + status = intel_sdvo_read_response(output, &reply, 3); +@@ -1681,6 +1733,7 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector) + if (nmode) + drm_mode_probed_add(connector, nmode); + } ++ + } + + static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) +@@ -1748,17 +1801,62 @@ static void intel_sdvo_destroy(struct drm_connector *connector) + intel_i2c_destroy(intel_output->i2c_bus); + if (intel_output->ddc_bus) + intel_i2c_destroy(intel_output->ddc_bus); ++ if (sdvo_priv->analog_ddc_bus) ++ intel_i2c_destroy(sdvo_priv->analog_ddc_bus); + + if (sdvo_priv->sdvo_lvds_fixed_mode != NULL) + drm_mode_destroy(connector->dev, + sdvo_priv->sdvo_lvds_fixed_mode); + ++ if (sdvo_priv->tv_format_property) ++ drm_property_destroy(connector->dev, ++ sdvo_priv->tv_format_property); ++ + drm_sysfs_connector_remove(connector); + drm_connector_cleanup(connector); + + kfree(intel_output); + } + ++static int ++intel_sdvo_set_property(struct drm_connector *connector, ++ struct drm_property *property, ++ uint64_t val) ++{ ++ struct intel_output *intel_output = to_intel_output(connector); ++ struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; ++ struct drm_encoder *encoder = &intel_output->enc; ++ struct drm_crtc *crtc = encoder->crtc; ++ int ret = 0; ++ bool changed = false; ++ ++ ret = drm_connector_property_set_value(connector, property, val); ++ if (ret < 0) ++ goto out; ++ ++ if (property == sdvo_priv->tv_format_property) { ++ if (val >= TV_FORMAT_NUM) { ++ ret = -EINVAL; ++ goto out; ++ } ++ if (sdvo_priv->tv_format_name == ++ sdvo_priv->tv_format_supported[val]) ++ goto out; ++ ++ sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val]; ++ changed = true; ++ } else { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (changed && crtc) ++ drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, ++ crtc->y, crtc->fb); ++out: ++ return ret; ++} ++ + static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { + .dpms = intel_sdvo_dpms, + .mode_fixup = intel_sdvo_mode_fixup, +@@ -1773,6 +1871,7 @@ static const struct drm_connector_funcs intel_sdvo_connector_funcs = { + .restore = intel_sdvo_restore, + .detect = intel_sdvo_detect, + .fill_modes = drm_helper_probe_single_connector_modes, ++ .set_property = intel_sdvo_set_property, + .destroy = intel_sdvo_destroy, + }; + +@@ -2013,10 +2112,9 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) + + sdvo_priv->controlled_output = 0; + memcpy(bytes, &sdvo_priv->caps.output_flags, 2); +- DRM_DEBUG_KMS(I915_SDVO, +- "%s: Unknown SDVO output type (0x%02x%02x)\n", +- SDVO_NAME(sdvo_priv), +- bytes[0], bytes[1]); ++ DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", ++ SDVO_NAME(sdvo_priv), ++ bytes[0], bytes[1]); + ret = false; + } + intel_output->crtc_mask = (1 << 0) | (1 << 1); +@@ -2029,6 +2127,55 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) + + } + ++static void intel_sdvo_tv_create_property(struct drm_connector *connector) ++{ ++ struct intel_output *intel_output = to_intel_output(connector); ++ struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; ++ struct intel_sdvo_tv_format format; ++ uint32_t format_map, i; ++ uint8_t status; ++ ++ intel_sdvo_set_target_output(intel_output, ++ sdvo_priv->controlled_output); ++ ++ intel_sdvo_write_cmd(intel_output, ++ SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); ++ status = intel_sdvo_read_response(intel_output, ++ &format, sizeof(format)); ++ if (status != SDVO_CMD_STATUS_SUCCESS) ++ return; ++ ++ memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ? ++ sizeof(format_map) : sizeof(format)); ++ ++ if (format_map == 0) ++ return; ++ ++ sdvo_priv->format_supported_num = 0; ++ for (i = 0 ; i < TV_FORMAT_NUM; i++) ++ if (format_map & (1 << i)) { ++ sdvo_priv->tv_format_supported ++ [sdvo_priv->format_supported_num++] = ++ tv_format_names[i]; ++ } ++ ++ ++ sdvo_priv->tv_format_property = ++ drm_property_create( ++ connector->dev, DRM_MODE_PROP_ENUM, ++ "mode", sdvo_priv->format_supported_num); ++ ++ for (i = 0; i < sdvo_priv->format_supported_num; i++) ++ drm_property_add_enum( ++ sdvo_priv->tv_format_property, i, ++ i, sdvo_priv->tv_format_supported[i]); ++ ++ sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0]; ++ drm_connector_attach_property( ++ connector, sdvo_priv->tv_format_property, 0); ++ ++} ++ + bool intel_sdvo_init(struct drm_device *dev, int output_device) + { + struct drm_connector *connector; +@@ -2066,18 +2213,22 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) + /* Read the regs to test if we can talk to the device */ + for (i = 0; i < 0x40; i++) { + if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { +- DRM_DEBUG_KMS(I915_SDVO, +- "No SDVO device found on SDVO%c\n", ++ DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", + output_device == SDVOB ? 'B' : 'C'); + goto err_i2c; + } + } + + /* setup the DDC bus. */ +- if (output_device == SDVOB) ++ if (output_device == SDVOB) { + intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); +- else ++ sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, ++ "SDVOB/VGA DDC BUS"); ++ } else { + intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); ++ sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, ++ "SDVOC/VGA DDC BUS"); ++ } + + if (intel_output->ddc_bus == NULL) + goto err_i2c; +@@ -2090,7 +2241,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) + + if (intel_sdvo_output_setup(intel_output, + sdvo_priv->caps.output_flags) != true) { +- DRM_DEBUG("SDVO output failed to setup on SDVO%c\n", ++ DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", + output_device == SDVOB ? 'B' : 'C'); + goto err_i2c; + } +@@ -2111,6 +2262,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) + drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs); + + drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); ++ if (sdvo_priv->is_tv) ++ intel_sdvo_tv_create_property(connector); + drm_sysfs_connector_add(connector); + + intel_sdvo_select_ddc_bus(sdvo_priv); +@@ -2123,7 +2276,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) + &sdvo_priv->pixel_clock_max); + + +- DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, " ++ DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " + "clock range %dMHz - %dMHz, " + "input 1: %c, input 2: %c, " + "output 1: %c, output 2: %c\n", +@@ -2143,6 +2296,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) + return true; + + err_i2c: ++ if (sdvo_priv->analog_ddc_bus != NULL) ++ intel_i2c_destroy(sdvo_priv->analog_ddc_bus); + if (intel_output->ddc_bus != NULL) + intel_i2c_destroy(intel_output->ddc_bus); + if (intel_output->i2c_bus != NULL) +diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c +index 5b1c9e9..c64eab4 100644 +--- a/drivers/gpu/drm/i915/intel_tv.c ++++ b/drivers/gpu/drm/i915/intel_tv.c +@@ -1437,6 +1437,35 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output) + return type; + } + ++/* ++ * Here we set accurate tv format according to connector type ++ * i.e Component TV should not be assigned by NTSC or PAL ++ */ ++static void intel_tv_find_better_format(struct drm_connector *connector) ++{ ++ struct intel_output *intel_output = to_intel_output(connector); ++ struct intel_tv_priv *tv_priv = intel_output->dev_priv; ++ const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output); ++ int i; ++ ++ if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == ++ tv_mode->component_only) ++ return; ++ ++ ++ for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) { ++ tv_mode = tv_modes + i; ++ ++ if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == ++ tv_mode->component_only) ++ break; ++ } ++ ++ tv_priv->tv_format = tv_mode->name; ++ drm_connector_property_set_value(connector, ++ connector->dev->mode_config.tv_mode_property, i); ++} ++ + /** + * Detect the TV connection. + * +@@ -1473,6 +1502,7 @@ intel_tv_detect(struct drm_connector *connector) + if (type < 0) + return connector_status_disconnected; + ++ intel_tv_find_better_format(connector); + return connector_status_connected; + } + +diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c +index 6c67a02..3c917fb 100644 +--- a/drivers/gpu/drm/mga/mga_dma.c ++++ b/drivers/gpu/drm/mga/mga_dma.c +@@ -444,7 +444,7 @@ static int mga_do_agp_dma_bootstrap(struct drm_device * dev, + { + drm_mga_private_t *const dev_priv = + (drm_mga_private_t *) dev->dev_private; +- unsigned int warp_size = mga_warp_microcode_size(dev_priv); ++ unsigned int warp_size = MGA_WARP_UCODE_SIZE; + int err; + unsigned offset; + const unsigned secondary_size = dma_bs->secondary_bin_count +@@ -619,7 +619,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev, + { + drm_mga_private_t *const dev_priv = + (drm_mga_private_t *) dev->dev_private; +- unsigned int warp_size = mga_warp_microcode_size(dev_priv); ++ unsigned int warp_size = MGA_WARP_UCODE_SIZE; + unsigned int primary_size; + unsigned int bin_count; + int err; +diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h +index 3d264f2..be6c6b9 100644 +--- a/drivers/gpu/drm/mga/mga_drv.h ++++ b/drivers/gpu/drm/mga/mga_drv.h +@@ -177,7 +177,6 @@ extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); + extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); + + /* mga_warp.c */ +-extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); + extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); + extern int mga_warp_init(drm_mga_private_t * dev_priv); + +diff --git a/drivers/gpu/drm/mga/mga_ucode.h b/drivers/gpu/drm/mga/mga_ucode.h +deleted file mode 100644 +index b611e27..0000000 +--- a/drivers/gpu/drm/mga/mga_ucode.h ++++ /dev/null +@@ -1,11645 +0,0 @@ +-/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*- +- * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com +- * +- * Copyright 1999 Matrox Graphics Inc. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, +- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +- * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- * Kernel-based WARP engine management: +- * Gareth Hughes <gareth@valinux.com> +- */ +- +-/* +- * WARP pipes are named according to the functions they perform, where: +- * +- * - T stands for computation of texture stage 0 +- * - T2 stands for computation of both texture stage 0 and texture stage 1 +- * - G stands for computation of triangle intensity (Gouraud interpolation) +- * - Z stands for computation of Z buffer interpolation +- * - S stands for computation of specular highlight +- * - A stands for computation of the alpha channel +- * - F stands for computation of vertex fog interpolation +- */ +- +-static unsigned char warp_g200_tgz[] = { +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x98, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x81, 0x04, +- 0x89, 0x04, +- 0x01, 0x04, +- 0x09, 0x04, +- +- 0xC9, 0x41, 0xC0, 0xEC, +- 0x11, 0x04, +- 0x00, 0xE0, +- +- 0x41, 0xCC, 0x41, 0xCD, +- 0x49, 0xCC, 0x49, 0xCD, +- +- 0xD1, 0x41, 0xC0, 0xEC, +- 0x51, 0xCC, 0x51, 0xCD, +- +- 0x80, 0x04, +- 0x10, 0x04, +- 0x08, 0x04, +- 0x00, 0xE0, +- +- 0x00, 0xCC, 0xC0, 0xCD, +- 0xD1, 0x49, 0xC0, 0xEC, +- +- 0x8A, 0x1F, 0x20, 0xE9, +- 0x8B, 0x3F, 0x20, 0xE9, +- +- 0x41, 0x3C, 0x41, 0xAD, +- 0x49, 0x3C, 0x49, 0xAD, +- +- 0x10, 0xCC, 0x10, 0xCD, +- 0x08, 0xCC, 0x08, 0xCD, +- +- 0xB9, 0x41, 0x49, 0xBB, +- 0x1F, 0xF0, 0x41, 0xCD, +- +- 0x51, 0x3C, 0x51, 0xAD, +- 0x00, 0x98, 0x80, 0xE9, +- +- 0x72, 0x80, 0x07, 0xEA, +- 0x24, 0x1F, 0x20, 0xE9, +- +- 0x15, 0x41, 0x49, 0xBD, +- 0x1D, 0x41, 0x51, 0xBD, +- +- 0x2E, 0x41, 0x2A, 0xB8, +- 0x34, 0x53, 0xA0, 0xE8, +- +- 0x15, 0x30, +- 0x1D, 0x30, +- 0x58, 0xE3, +- 0x00, 0xE0, +- +- 0xB5, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x24, 0x43, 0xA0, 0xE8, +- 0x2C, 0x4B, 0xA0, 0xE8, +- +- 0x15, 0x72, +- 0x09, 0xE3, +- 0x00, 0xE0, +- 0x1D, 0x72, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0x97, 0x57, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x6C, 0x64, 0xC8, 0xEC, +- 0x98, 0xE1, +- 0xB5, 0x05, +- +- 0xBD, 0x05, +- 0x2E, 0x30, +- 0x32, 0xC0, 0xA0, 0xE8, +- +- 0x33, 0xC0, 0xA0, 0xE8, +- 0x74, 0x64, 0xC8, 0xEC, +- +- 0x40, 0x3C, 0x40, 0xAD, +- 0x32, 0x6A, +- 0x2A, 0x30, +- +- 0x20, 0x73, +- 0x33, 0x6A, +- 0x00, 0xE0, +- 0x28, 0x73, +- +- 0x1C, 0x72, +- 0x83, 0xE2, +- 0x60, 0x80, 0x15, 0xEA, +- +- 0xB8, 0x3D, 0x28, 0xDF, +- 0x30, 0x35, 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0xDF, +- +- 0x28, 0x15, 0x28, 0xDF, +- 0x20, 0x1D, 0x20, 0xDF, +- +- 0x57, 0x34, 0x57, 0xDF, +- 0x00, 0xE0, +- 0x1D, 0x05, +- +- 0x04, 0x80, 0x10, 0xEA, +- 0x89, 0xE2, +- 0x2B, 0x30, +- +- 0x3F, 0xC1, 0x1D, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xA0, 0x68, +- 0xBF, 0x25, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x20, 0xC0, 0x20, 0xAF, +- 0x28, 0x05, +- 0x97, 0x74, +- +- 0x00, 0xE0, +- 0x2A, 0x10, +- 0x16, 0xC0, 0x20, 0xE9, +- +- 0x04, 0x80, 0x10, 0xEA, +- 0x8C, 0xE2, +- 0x95, 0x05, +- +- 0x28, 0xC1, 0x28, 0xAD, +- 0x1F, 0xC1, 0x15, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xA8, 0x67, +- 0x9F, 0x6B, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x28, 0xC0, 0x28, 0xAD, +- 0x1D, 0x25, +- 0x20, 0x05, +- +- 0x28, 0x32, 0x80, 0xAD, +- 0x40, 0x2A, 0x40, 0xBD, +- +- 0x1C, 0x80, 0x20, 0xE9, +- 0x20, 0x33, 0x20, 0xAD, +- +- 0x20, 0x73, +- 0x00, 0xE0, +- 0xB6, 0x49, 0x51, 0xBB, +- +- 0x26, 0x2F, 0xB0, 0xE8, +- 0x19, 0x20, 0x20, 0xE9, +- +- 0x35, 0x20, 0x35, 0xDF, +- 0x3D, 0x20, 0x3D, 0xDF, +- +- 0x15, 0x20, 0x15, 0xDF, +- 0x1D, 0x20, 0x1D, 0xDF, +- +- 0x26, 0xD0, 0x26, 0xCD, +- 0x29, 0x49, 0x2A, 0xB8, +- +- 0x26, 0x40, 0x80, 0xBD, +- 0x3B, 0x48, 0x50, 0xBD, +- +- 0x3E, 0x54, 0x57, 0x9F, +- 0x00, 0xE0, +- 0x82, 0xE1, +- +- 0x1E, 0xAF, 0x59, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x26, 0x30, +- 0x29, 0x30, +- 0x48, 0x3C, 0x48, 0xAD, +- +- 0x2B, 0x72, +- 0xC2, 0xE1, +- 0x2C, 0xC0, 0x44, 0xC2, +- +- 0x05, 0x24, 0x34, 0xBF, +- 0x0D, 0x24, 0x2C, 0xBF, +- +- 0x2D, 0x46, 0x4E, 0xBF, +- 0x25, 0x46, 0x56, 0xBF, +- +- 0x20, 0x1D, 0x6F, 0x8F, +- 0x32, 0x3E, 0x5F, 0xE9, +- +- 0x3E, 0x50, 0x56, 0x9F, +- 0x00, 0xE0, +- 0x3B, 0x30, +- +- 0x1E, 0x8F, 0x51, 0x9F, +- 0x33, 0x1E, 0x5F, 0xE9, +- +- 0x05, 0x44, 0x54, 0xB2, +- 0x0D, 0x44, 0x4C, 0xB2, +- +- 0x19, 0xC0, 0xB0, 0xE8, +- 0x34, 0xC0, 0x44, 0xC4, +- +- 0x33, 0x73, +- 0x00, 0xE0, +- 0x3E, 0x62, 0x57, 0x9F, +- +- 0x1E, 0xAF, 0x59, 0x9F, +- 0x00, 0xE0, +- 0x0D, 0x20, +- +- 0x84, 0x3E, 0x58, 0xE9, +- 0x28, 0x1D, 0x6F, 0x8F, +- +- 0x05, 0x20, +- 0x00, 0xE0, +- 0x85, 0x1E, 0x58, 0xE9, +- +- 0x9B, 0x3B, 0x33, 0xDF, +- 0x20, 0x20, 0x42, 0xAF, +- +- 0x30, 0x42, 0x56, 0x9F, +- 0x80, 0x3E, 0x57, 0xE9, +- +- 0x3F, 0x8F, 0x51, 0x9F, +- 0x30, 0x80, 0x5F, 0xE9, +- +- 0x28, 0x28, 0x24, 0xAF, +- 0x81, 0x1E, 0x57, 0xE9, +- +- 0x05, 0x47, 0x57, 0xBF, +- 0x0D, 0x47, 0x4F, 0xBF, +- +- 0x88, 0x80, 0x58, 0xE9, +- 0x1B, 0x29, 0x1B, 0xDF, +- +- 0x30, 0x1D, 0x6F, 0x8F, +- 0x3A, 0x30, 0x4F, 0xE9, +- +- 0x1C, 0x30, 0x26, 0xDF, +- 0x09, 0xE3, +- 0x3B, 0x05, +- +- 0x3E, 0x50, 0x56, 0x9F, +- 0x3B, 0x3F, 0x4F, 0xE9, +- +- 0x1E, 0x8F, 0x51, 0x9F, +- 0x00, 0xE0, +- 0xAC, 0x20, +- +- 0x2D, 0x44, 0x4C, 0xB4, +- 0x2C, 0x1C, 0xC0, 0xAF, +- +- 0x25, 0x44, 0x54, 0xB4, +- 0x00, 0xE0, +- 0xC8, 0x30, +- +- 0x30, 0x46, 0x30, 0xAF, +- 0x1B, 0x1B, 0x48, 0xAF, +- +- 0x00, 0xE0, +- 0x25, 0x20, +- 0x38, 0x2C, 0x4F, 0xE9, +- +- 0x86, 0x80, 0x57, 0xE9, +- 0x38, 0x1D, 0x6F, 0x8F, +- +- 0x28, 0x74, +- 0x00, 0xE0, +- 0x0D, 0x44, 0x4C, 0xB0, +- +- 0x05, 0x44, 0x54, 0xB0, +- 0x2D, 0x20, +- 0x9B, 0x10, +- +- 0x82, 0x3E, 0x57, 0xE9, +- 0x32, 0xF0, 0x1B, 0xCD, +- +- 0x1E, 0xBD, 0x59, 0x9F, +- 0x83, 0x1E, 0x57, 0xE9, +- +- 0x38, 0x47, 0x38, 0xAF, +- 0x34, 0x20, +- 0x2A, 0x30, +- +- 0x00, 0xE0, +- 0x0D, 0x20, +- 0x32, 0x20, +- 0x05, 0x20, +- +- 0x87, 0x80, 0x57, 0xE9, +- 0x1F, 0x54, 0x57, 0x9F, +- +- 0x17, 0x42, 0x56, 0x9F, +- 0x00, 0xE0, +- 0x3B, 0x6A, +- +- 0x3F, 0x8F, 0x51, 0x9F, +- 0x37, 0x1E, 0x4F, 0xE9, +- +- 0x37, 0x32, 0x2A, 0xAF, +- 0x00, 0xE0, +- 0x32, 0x00, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x27, 0xC0, 0x44, 0xC0, +- +- 0x36, 0x1F, 0x4F, 0xE9, +- 0x1F, 0x1F, 0x26, 0xDF, +- +- 0x37, 0x1B, 0x37, 0xBF, +- 0x17, 0x26, 0x17, 0xDF, +- +- 0x3E, 0x17, 0x4F, 0xE9, +- 0x3F, 0x3F, 0x4F, 0xE9, +- +- 0x34, 0x1F, 0x34, 0xAF, +- 0x2B, 0x05, +- 0xA7, 0x20, +- +- 0x33, 0x2B, 0x37, 0xDF, +- 0x27, 0x17, 0xC0, 0xAF, +- +- 0x34, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x03, 0x80, 0x0A, 0xEA, +- 0x17, 0xC1, 0x2B, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xB3, 0x68, +- 0x97, 0x25, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x33, 0xC0, 0x33, 0xAF, +- 0x3C, 0x27, 0x4F, 0xE9, +- +- 0x57, 0x39, 0x20, 0xE9, +- 0x28, 0x19, 0x60, 0xEC, +- +- 0x2B, 0x32, 0x20, 0xE9, +- 0x1D, 0x3B, 0x20, 0xE9, +- +- 0xB3, 0x05, +- 0x00, 0xE0, +- 0x16, 0x28, 0x20, 0xE9, +- +- 0x23, 0x3B, 0x33, 0xAD, +- 0x1E, 0x2B, 0x20, 0xE9, +- +- 0x1C, 0x80, 0x20, 0xE9, +- 0x57, 0x36, 0x20, 0xE9, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x90, 0xE2, +- 0x00, 0xE0, +- +- 0x85, 0xFF, 0x20, 0xEA, +- 0x19, 0xC8, 0xC1, 0xCD, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x9F, 0x41, 0x49, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x25, 0x41, 0x49, 0xBD, +- 0x2D, 0x41, 0x51, 0xBD, +- +- 0x0D, 0x80, 0x07, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x35, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x25, 0x30, +- 0x2D, 0x30, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0xA7, 0x5B, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x84, 0xFF, 0x0A, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC9, 0x41, 0xC8, 0xEC, +- 0x42, 0xE1, +- 0x00, 0xE0, +- +- 0x82, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC8, 0x40, 0xC0, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x7F, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +-}; +- +-static unsigned char warp_g200_tgza[] = { +- +- 0x00, 0x98, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x81, 0x04, +- 0x89, 0x04, +- 0x01, 0x04, +- 0x09, 0x04, +- +- 0xC9, 0x41, 0xC0, 0xEC, +- 0x11, 0x04, +- 0x00, 0xE0, +- +- 0x41, 0xCC, 0x41, 0xCD, +- 0x49, 0xCC, 0x49, 0xCD, +- +- 0xD1, 0x41, 0xC0, 0xEC, +- 0x51, 0xCC, 0x51, 0xCD, +- +- 0x80, 0x04, +- 0x10, 0x04, +- 0x08, 0x04, +- 0x00, 0xE0, +- +- 0x00, 0xCC, 0xC0, 0xCD, +- 0xD1, 0x49, 0xC0, 0xEC, +- +- 0x8A, 0x1F, 0x20, 0xE9, +- 0x8B, 0x3F, 0x20, 0xE9, +- +- 0x41, 0x3C, 0x41, 0xAD, +- 0x49, 0x3C, 0x49, 0xAD, +- +- 0x10, 0xCC, 0x10, 0xCD, +- 0x08, 0xCC, 0x08, 0xCD, +- +- 0xB9, 0x41, 0x49, 0xBB, +- 0x1F, 0xF0, 0x41, 0xCD, +- +- 0x51, 0x3C, 0x51, 0xAD, +- 0x00, 0x98, 0x80, 0xE9, +- +- 0x7D, 0x80, 0x07, 0xEA, +- 0x24, 0x1F, 0x20, 0xE9, +- +- 0x15, 0x41, 0x49, 0xBD, +- 0x1D, 0x41, 0x51, 0xBD, +- +- 0x2E, 0x41, 0x2A, 0xB8, +- 0x34, 0x53, 0xA0, 0xE8, +- +- 0x15, 0x30, +- 0x1D, 0x30, +- 0x58, 0xE3, +- 0x00, 0xE0, +- +- 0xB5, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x24, 0x43, 0xA0, 0xE8, +- 0x2C, 0x4B, 0xA0, 0xE8, +- +- 0x15, 0x72, +- 0x09, 0xE3, +- 0x00, 0xE0, +- 0x1D, 0x72, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0x97, 0x57, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x6C, 0x64, 0xC8, 0xEC, +- 0x98, 0xE1, +- 0xB5, 0x05, +- +- 0xBD, 0x05, +- 0x2E, 0x30, +- 0x32, 0xC0, 0xA0, 0xE8, +- +- 0x33, 0xC0, 0xA0, 0xE8, +- 0x74, 0x64, 0xC8, 0xEC, +- +- 0x40, 0x3C, 0x40, 0xAD, +- 0x32, 0x6A, +- 0x2A, 0x30, +- +- 0x20, 0x73, +- 0x33, 0x6A, +- 0x00, 0xE0, +- 0x28, 0x73, +- +- 0x1C, 0x72, +- 0x83, 0xE2, +- 0x6B, 0x80, 0x15, 0xEA, +- +- 0xB8, 0x3D, 0x28, 0xDF, +- 0x30, 0x35, 0x20, 0xDF, +- +- 0x40, 0x30, +- 0x00, 0xE0, +- 0xCC, 0xE2, +- 0x64, 0x72, +- +- 0x25, 0x42, 0x52, 0xBF, +- 0x2D, 0x42, 0x4A, 0xBF, +- +- 0x30, 0x2E, 0x30, 0xDF, +- 0x38, 0x2E, 0x38, 0xDF, +- +- 0x18, 0x1D, 0x45, 0xE9, +- 0x1E, 0x15, 0x45, 0xE9, +- +- 0x2B, 0x49, 0x51, 0xBD, +- 0x00, 0xE0, +- 0x1F, 0x73, +- +- 0x38, 0x38, 0x40, 0xAF, +- 0x30, 0x30, 0x40, 0xAF, +- +- 0x24, 0x1F, 0x24, 0xDF, +- 0x1D, 0x32, 0x20, 0xE9, +- +- 0x2C, 0x1F, 0x2C, 0xDF, +- 0x1A, 0x33, 0x20, 0xE9, +- +- 0xB0, 0x10, +- 0x08, 0xE3, +- 0x40, 0x10, +- 0xB8, 0x10, +- +- 0x26, 0xF0, 0x30, 0xCD, +- 0x2F, 0xF0, 0x38, 0xCD, +- +- 0x2B, 0x80, 0x20, 0xE9, +- 0x2A, 0x80, 0x20, 0xE9, +- +- 0xA6, 0x20, +- 0x88, 0xE2, +- 0x00, 0xE0, +- 0xAF, 0x20, +- +- 0x28, 0x2A, 0x26, 0xAF, +- 0x20, 0x2A, 0xC0, 0xAF, +- +- 0x34, 0x1F, 0x34, 0xDF, +- 0x46, 0x24, 0x46, 0xDF, +- +- 0x28, 0x30, 0x80, 0xBF, +- 0x20, 0x38, 0x80, 0xBF, +- +- 0x47, 0x24, 0x47, 0xDF, +- 0x4E, 0x2C, 0x4E, 0xDF, +- +- 0x4F, 0x2C, 0x4F, 0xDF, +- 0x56, 0x34, 0x56, 0xDF, +- +- 0x28, 0x15, 0x28, 0xDF, +- 0x20, 0x1D, 0x20, 0xDF, +- +- 0x57, 0x34, 0x57, 0xDF, +- 0x00, 0xE0, +- 0x1D, 0x05, +- +- 0x04, 0x80, 0x10, 0xEA, +- 0x89, 0xE2, +- 0x2B, 0x30, +- +- 0x3F, 0xC1, 0x1D, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xA0, 0x68, +- 0xBF, 0x25, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x20, 0xC0, 0x20, 0xAF, +- 0x28, 0x05, +- 0x97, 0x74, +- +- 0x00, 0xE0, +- 0x2A, 0x10, +- 0x16, 0xC0, 0x20, 0xE9, +- +- 0x04, 0x80, 0x10, 0xEA, +- 0x8C, 0xE2, +- 0x95, 0x05, +- +- 0x28, 0xC1, 0x28, 0xAD, +- 0x1F, 0xC1, 0x15, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xA8, 0x67, +- 0x9F, 0x6B, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x28, 0xC0, 0x28, 0xAD, +- 0x1D, 0x25, +- 0x20, 0x05, +- +- 0x28, 0x32, 0x80, 0xAD, +- 0x40, 0x2A, 0x40, 0xBD, +- +- 0x1C, 0x80, 0x20, 0xE9, +- 0x20, 0x33, 0x20, 0xAD, +- +- 0x20, 0x73, +- 0x00, 0xE0, +- 0xB6, 0x49, 0x51, 0xBB, +- +- 0x26, 0x2F, 0xB0, 0xE8, +- 0x19, 0x20, 0x20, 0xE9, +- +- 0x35, 0x20, 0x35, 0xDF, +- 0x3D, 0x20, 0x3D, 0xDF, +- +- 0x15, 0x20, 0x15, 0xDF, +- 0x1D, 0x20, 0x1D, 0xDF, +- +- 0x26, 0xD0, 0x26, 0xCD, +- 0x29, 0x49, 0x2A, 0xB8, +- +- 0x26, 0x40, 0x80, 0xBD, +- 0x3B, 0x48, 0x50, 0xBD, +- +- 0x3E, 0x54, 0x57, 0x9F, +- 0x00, 0xE0, +- 0x82, 0xE1, +- +- 0x1E, 0xAF, 0x59, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x26, 0x30, +- 0x29, 0x30, +- 0x48, 0x3C, 0x48, 0xAD, +- +- 0x2B, 0x72, +- 0xC2, 0xE1, +- 0x2C, 0xC0, 0x44, 0xC2, +- +- 0x05, 0x24, 0x34, 0xBF, +- 0x0D, 0x24, 0x2C, 0xBF, +- +- 0x2D, 0x46, 0x4E, 0xBF, +- 0x25, 0x46, 0x56, 0xBF, +- +- 0x20, 0x1D, 0x6F, 0x8F, +- 0x32, 0x3E, 0x5F, 0xE9, +- +- 0x3E, 0x50, 0x56, 0x9F, +- 0x00, 0xE0, +- 0x3B, 0x30, +- +- 0x1E, 0x8F, 0x51, 0x9F, +- 0x33, 0x1E, 0x5F, 0xE9, +- +- 0x05, 0x44, 0x54, 0xB2, +- 0x0D, 0x44, 0x4C, 0xB2, +- +- 0x19, 0xC0, 0xB0, 0xE8, +- 0x34, 0xC0, 0x44, 0xC4, +- +- 0x33, 0x73, +- 0x00, 0xE0, +- 0x3E, 0x62, 0x57, 0x9F, +- +- 0x1E, 0xAF, 0x59, 0x9F, +- 0x00, 0xE0, +- 0x0D, 0x20, +- +- 0x84, 0x3E, 0x58, 0xE9, +- 0x28, 0x1D, 0x6F, 0x8F, +- +- 0x05, 0x20, +- 0x00, 0xE0, +- 0x85, 0x1E, 0x58, 0xE9, +- +- 0x9B, 0x3B, 0x33, 0xDF, +- 0x20, 0x20, 0x42, 0xAF, +- +- 0x30, 0x42, 0x56, 0x9F, +- 0x80, 0x3E, 0x57, 0xE9, +- +- 0x3F, 0x8F, 0x51, 0x9F, +- 0x30, 0x80, 0x5F, 0xE9, +- +- 0x28, 0x28, 0x24, 0xAF, +- 0x81, 0x1E, 0x57, 0xE9, +- +- 0x05, 0x47, 0x57, 0xBF, +- 0x0D, 0x47, 0x4F, 0xBF, +- +- 0x88, 0x80, 0x58, 0xE9, +- 0x1B, 0x29, 0x1B, 0xDF, +- +- 0x30, 0x1D, 0x6F, 0x8F, +- 0x3A, 0x30, 0x4F, 0xE9, +- +- 0x1C, 0x30, 0x26, 0xDF, +- 0x09, 0xE3, +- 0x3B, 0x05, +- +- 0x3E, 0x50, 0x56, 0x9F, +- 0x3B, 0x3F, 0x4F, 0xE9, +- +- 0x1E, 0x8F, 0x51, 0x9F, +- 0x00, 0xE0, +- 0xAC, 0x20, +- +- 0x2D, 0x44, 0x4C, 0xB4, +- 0x2C, 0x1C, 0xC0, 0xAF, +- +- 0x25, 0x44, 0x54, 0xB4, +- 0x00, 0xE0, +- 0xC8, 0x30, +- +- 0x30, 0x46, 0x30, 0xAF, +- 0x1B, 0x1B, 0x48, 0xAF, +- +- 0x00, 0xE0, +- 0x25, 0x20, +- 0x38, 0x2C, 0x4F, 0xE9, +- +- 0x86, 0x80, 0x57, 0xE9, +- 0x38, 0x1D, 0x6F, 0x8F, +- +- 0x28, 0x74, +- 0x00, 0xE0, +- 0x0D, 0x44, 0x4C, 0xB0, +- +- 0x05, 0x44, 0x54, 0xB0, +- 0x2D, 0x20, +- 0x9B, 0x10, +- +- 0x82, 0x3E, 0x57, 0xE9, +- 0x32, 0xF0, 0x1B, 0xCD, +- +- 0x1E, 0xBD, 0x59, 0x9F, +- 0x83, 0x1E, 0x57, 0xE9, +- +- 0x38, 0x47, 0x38, 0xAF, +- 0x34, 0x20, +- 0x2A, 0x30, +- +- 0x00, 0xE0, +- 0x0D, 0x20, +- 0x32, 0x20, +- 0x05, 0x20, +- +- 0x87, 0x80, 0x57, 0xE9, +- 0x1F, 0x54, 0x57, 0x9F, +- +- 0x17, 0x42, 0x56, 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0x28, 0x19, 0x60, 0xEC, +- +- 0xB3, 0x05, +- 0x00, 0xE0, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x23, 0x3B, 0x33, 0xAD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x1F, 0x26, 0x1F, 0xDF, +- 0x9D, 0x1F, 0x4F, 0xE9, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x9E, 0x3F, 0x4F, 0xE9, +- +- 0x07, 0x07, 0x1F, 0xAF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x9C, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x57, 0x39, 0x20, 0xE9, +- +- 0x16, 0x28, 0x20, 0xE9, +- 0x1D, 0x3B, 0x20, 0xE9, +- +- 0x1E, 0x2B, 0x20, 0xE9, +- 0x2B, 0x32, 0x20, 0xE9, +- +- 0x1C, 0x23, 0x20, 0xE9, +- 0x57, 0x36, 0x20, 0xE9, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x90, 0xE2, +- 0x00, 0xE0, +- +- 0x7A, 0xFF, 0x20, 0xEA, +- 0x19, 0xC8, 0xC1, 0xCD, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x9F, 0x41, 0x49, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x25, 0x41, 0x49, 0xBD, +- 0x2D, 0x41, 0x51, 0xBD, +- +- 0x0D, 0x80, 0x07, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x35, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x25, 0x30, +- 0x2D, 0x30, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0xA7, 0x5B, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x79, 0xFF, 0x0A, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC9, 0x41, 0xC8, 0xEC, +- 0x42, 0xE1, +- 0x00, 0xE0, +- +- 0x77, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC8, 0x40, 0xC0, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x74, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +-}; +- +-static unsigned char warp_g200_tgzaf[] = { +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x98, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x81, 0x04, +- 0x89, 0x04, +- 0x01, 0x04, +- 0x09, 0x04, +- +- 0xC9, 0x41, 0xC0, 0xEC, +- 0x11, 0x04, +- 0x00, 0xE0, +- +- 0x41, 0xCC, 0x41, 0xCD, +- 0x49, 0xCC, 0x49, 0xCD, +- +- 0xD1, 0x41, 0xC0, 0xEC, +- 0x51, 0xCC, 0x51, 0xCD, +- +- 0x80, 0x04, +- 0x10, 0x04, +- 0x08, 0x04, +- 0x00, 0xE0, +- +- 0x00, 0xCC, 0xC0, 0xCD, +- 0xD1, 0x49, 0xC0, 0xEC, +- +- 0x8A, 0x1F, 0x20, 0xE9, +- 0x8B, 0x3F, 0x20, 0xE9, +- +- 0x41, 0x3C, 0x41, 0xAD, +- 0x49, 0x3C, 0x49, 0xAD, +- +- 0x10, 0xCC, 0x10, 0xCD, +- 0x08, 0xCC, 0x08, 0xCD, +- +- 0xB9, 0x41, 0x49, 0xBB, +- 0x1F, 0xF0, 0x41, 0xCD, +- +- 0x51, 0x3C, 0x51, 0xAD, +- 0x00, 0x98, 0x80, 0xE9, +- +- 0x83, 0x80, 0x07, 0xEA, +- 0x24, 0x1F, 0x20, 0xE9, +- +- 0x21, 0x45, 0x80, 0xE8, +- 0x1A, 0x4D, 0x80, 0xE8, +- +- 0x31, 0x55, 0x80, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0x41, 0x49, 0xBD, +- 0x1D, 0x41, 0x51, 0xBD, +- +- 0x2E, 0x41, 0x2A, 0xB8, +- 0x34, 0x53, 0xA0, 0xE8, +- +- 0x15, 0x30, +- 0x1D, 0x30, +- 0x58, 0xE3, +- 0x00, 0xE0, +- +- 0xB5, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x24, 0x43, 0xA0, 0xE8, +- 0x2C, 0x4B, 0xA0, 0xE8, +- +- 0x15, 0x72, +- 0x09, 0xE3, +- 0x00, 0xE0, +- 0x1D, 0x72, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0x97, 0x57, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x6C, 0x64, 0xC8, 0xEC, +- 0x98, 0xE1, +- 0xB5, 0x05, +- +- 0xBD, 0x05, +- 0x2E, 0x30, +- 0x32, 0xC0, 0xA0, 0xE8, +- +- 0x33, 0xC0, 0xA0, 0xE8, +- 0x74, 0x64, 0xC8, 0xEC, +- +- 0x40, 0x3C, 0x40, 0xAD, +- 0x32, 0x6A, +- 0x2A, 0x30, +- +- 0x20, 0x73, +- 0x33, 0x6A, +- 0x00, 0xE0, +- 0x28, 0x73, +- +- 0x1C, 0x72, +- 0x83, 0xE2, +- 0x6F, 0x80, 0x15, 0xEA, +- +- 0xB8, 0x3D, 0x28, 0xDF, +- 0x30, 0x35, 0x20, 0xDF, +- +- 0x40, 0x30, +- 0x00, 0xE0, +- 0xCC, 0xE2, +- 0x64, 0x72, +- +- 0x25, 0x42, 0x52, 0xBF, +- 0x2D, 0x42, 0x4A, 0xBF, +- +- 0x30, 0x2E, 0x30, 0xDF, +- 0x38, 0x2E, 0x38, 0xDF, +- +- 0x18, 0x1D, 0x45, 0xE9, +- 0x1E, 0x15, 0x45, 0xE9, +- +- 0x2B, 0x49, 0x51, 0xBD, +- 0x00, 0xE0, +- 0x1F, 0x73, +- +- 0x38, 0x38, 0x40, 0xAF, +- 0x30, 0x30, 0x40, 0xAF, +- +- 0x24, 0x1F, 0x24, 0xDF, +- 0x1D, 0x32, 0x20, 0xE9, +- +- 0x2C, 0x1F, 0x2C, 0xDF, +- 0x1A, 0x33, 0x20, 0xE9, +- +- 0xB0, 0x10, +- 0x08, 0xE3, +- 0x40, 0x10, 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0x95, 0x05, +- +- 0x28, 0xC1, 0x28, 0xAD, +- 0x1F, 0xC1, 0x15, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xA8, 0x67, +- 0x9F, 0x6B, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x28, 0xC0, 0x28, 0xAD, +- 0x1D, 0x25, +- 0x20, 0x05, +- +- 0x28, 0x32, 0x80, 0xAD, +- 0x40, 0x2A, 0x40, 0xBD, +- +- 0x1C, 0x80, 0x20, 0xE9, +- 0x20, 0x33, 0x20, 0xAD, +- +- 0x20, 0x73, +- 0x00, 0xE0, +- 0xB6, 0x49, 0x51, 0xBB, +- +- 0x26, 0x2F, 0xB0, 0xE8, +- 0x19, 0x20, 0x20, 0xE9, +- +- 0x35, 0x20, 0x35, 0xDF, +- 0x3D, 0x20, 0x3D, 0xDF, +- +- 0x15, 0x20, 0x15, 0xDF, +- 0x1D, 0x20, 0x1D, 0xDF, +- +- 0x26, 0xD0, 0x26, 0xCD, +- 0x29, 0x49, 0x2A, 0xB8, +- +- 0x26, 0x40, 0x80, 0xBD, +- 0x3B, 0x48, 0x50, 0xBD, +- +- 0x3E, 0x54, 0x57, 0x9F, +- 0x00, 0xE0, +- 0x82, 0xE1, +- +- 0x1E, 0xAF, 0x59, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x26, 0x30, +- 0x29, 0x30, +- 0x48, 0x3C, 0x48, 0xAD, +- +- 0x2B, 0x72, +- 0xC2, 0xE1, +- 0x2C, 0xC0, 0x44, 0xC2, +- +- 0x05, 0x24, 0x34, 0xBF, +- 0x0D, 0x24, 0x2C, 0xBF, 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0x26, 0xDF, +- 0x09, 0xE3, +- 0x3B, 0x05, +- +- 0x3E, 0x50, 0x56, 0x9F, +- 0x3B, 0x3F, 0x4F, 0xE9, +- +- 0x1E, 0x8F, 0x51, 0x9F, +- 0x00, 0xE0, +- 0xAC, 0x20, +- +- 0x2D, 0x44, 0x4C, 0xB4, +- 0x2C, 0x1C, 0xC0, 0xAF, +- +- 0x25, 0x44, 0x54, 0xB4, +- 0x00, 0xE0, +- 0xC8, 0x30, +- +- 0x30, 0x46, 0x30, 0xAF, +- 0x1B, 0x1B, 0x48, 0xAF, +- +- 0x00, 0xE0, +- 0x25, 0x20, +- 0x38, 0x2C, 0x4F, 0xE9, +- +- 0x86, 0x80, 0x57, 0xE9, +- 0x38, 0x1D, 0x6F, 0x8F, +- +- 0x28, 0x74, +- 0x00, 0xE0, +- 0x0D, 0x44, 0x4C, 0xB0, +- +- 0x05, 0x44, 0x54, 0xB0, +- 0x2D, 0x20, +- 0x9B, 0x10, +- +- 0x82, 0x3E, 0x57, 0xE9, +- 0x32, 0xF0, 0x1B, 0xCD, +- +- 0x1E, 0xBD, 0x59, 0x9F, +- 0x83, 0x1E, 0x57, 0xE9, +- +- 0x38, 0x47, 0x38, 0xAF, +- 0x34, 0x20, +- 0x2A, 0x30, +- +- 0x00, 0xE0, +- 0x0D, 0x20, +- 0x32, 0x20, +- 0x05, 0x20, +- +- 0x87, 0x80, 0x57, 0xE9, +- 0x1F, 0x54, 0x57, 0x9F, +- +- 0x17, 0x42, 0x56, 0x9F, +- 0x00, 0xE0, +- 0x3B, 0x6A, +- +- 0x3F, 0x8F, 0x51, 0x9F, +- 0x37, 0x1E, 0x4F, 0xE9, +- +- 0x37, 0x32, 0x2A, 0xAF, +- 0x00, 0xE0, +- 0x32, 0x00, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x27, 0xC0, 0x44, 0xC0, +- +- 0x36, 0x1F, 0x4F, 0xE9, +- 0x1F, 0x1F, 0x26, 0xDF, +- +- 0x37, 0x1B, 0x37, 0xBF, +- 0x17, 0x26, 0x17, 0xDF, +- +- 0x3E, 0x17, 0x4F, 0xE9, +- 0x3F, 0x3F, 0x4F, 0xE9, +- +- 0x34, 0x1F, 0x34, 0xAF, +- 0x2B, 0x05, +- 0xA7, 0x20, +- +- 0x33, 0x2B, 0x37, 0xDF, +- 0x27, 0x17, 0xC0, 0xAF, +- +- 0x34, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x0D, 0x21, 0x1A, 0xB6, +- 0x05, 0x21, 0x31, 0xB6, +- +- 0x2D, 0x44, 0x4C, 0xB6, +- 0x25, 0x44, 0x54, 0xB6, +- +- 0x03, 0x80, 0x2A, 0xEA, +- 0x17, 0xC1, 0x2B, 0xBD, +- +- 0x0D, 0x20, +- 0x05, 0x20, +- 0x2F, 0xC0, 0x21, 0xC6, +- +- 0xB3, 0x68, +- 0x97, 0x25, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x33, 0xC0, 0x33, 0xAF, +- 0x3C, 0x27, 0x4F, 0xE9, +- +- 0x00, 0xE0, +- 0x25, 0x20, +- 0x07, 0xC0, 0x44, 0xC6, +- +- 0x17, 0x50, 0x56, 0x9F, +- 0x00, 0xE0, +- 0x2D, 0x20, +- +- 0x37, 0x0F, 0x5C, 0x9F, +- 0x00, 0xE0, +- 0x2F, 0x20, +- +- 0x1F, 0x62, 0x57, 0x9F, +- 0x00, 0xE0, +- 0x07, 0x20, +- +- 0x3F, 0x3D, 0x5D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x28, 0x19, 0x60, 0xEC, +- +- 0xB3, 0x05, +- 0x00, 0xE0, +- 0x17, 0x26, 0x17, 0xDF, +- +- 0x23, 0x3B, 0x33, 0xAD, +- 0x35, 0x17, 0x4F, 0xE9, +- +- 0x1F, 0x26, 0x1F, 0xDF, +- 0x9D, 0x1F, 0x4F, 0xE9, +- +- 0x9E, 0x3F, 0x4F, 0xE9, +- 0x39, 0x37, 0x4F, 0xE9, +- +- 0x2F, 0x2F, 0x17, 0xAF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x07, 0x07, 0x1F, 0xAF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x31, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x9C, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x57, 0x39, 0x20, 0xE9, +- +- 0x16, 0x28, 0x20, 0xE9, +- 0x1D, 0x3B, 0x20, 0xE9, +- +- 0x1E, 0x2B, 0x20, 0xE9, +- 0x2B, 0x32, 0x20, 0xE9, +- +- 0x1C, 0x23, 0x20, 0xE9, +- 0x57, 0x36, 0x20, 0xE9, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x90, 0xE2, +- 0x00, 0xE0, +- +- 0x74, 0xFF, 0x20, 0xEA, +- 0x19, 0xC8, 0xC1, 0xCD, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x9F, 0x41, 0x49, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x25, 0x41, 0x49, 0xBD, +- 0x2D, 0x41, 0x51, 0xBD, +- +- 0x0D, 0x80, 0x07, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x35, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x25, 0x30, +- 0x2D, 0x30, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0xA7, 0x5B, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x73, 0xFF, 0x0A, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC9, 0x41, 0xC8, 0xEC, +- 0x42, 0xE1, +- 0x00, 0xE0, +- +- 0x71, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC8, 0x40, 0xC0, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x6E, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +-}; +- +-static unsigned char warp_g200_tgzf[] = { +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x98, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x81, 0x04, +- 0x89, 0x04, +- 0x01, 0x04, +- 0x09, 0x04, +- +- 0xC9, 0x41, 0xC0, 0xEC, +- 0x11, 0x04, +- 0x00, 0xE0, +- +- 0x41, 0xCC, 0x41, 0xCD, +- 0x49, 0xCC, 0x49, 0xCD, +- +- 0xD1, 0x41, 0xC0, 0xEC, +- 0x51, 0xCC, 0x51, 0xCD, +- +- 0x80, 0x04, +- 0x10, 0x04, +- 0x08, 0x04, +- 0x00, 0xE0, +- +- 0x00, 0xCC, 0xC0, 0xCD, +- 0xD1, 0x49, 0xC0, 0xEC, +- +- 0x8A, 0x1F, 0x20, 0xE9, +- 0x8B, 0x3F, 0x20, 0xE9, +- +- 0x41, 0x3C, 0x41, 0xAD, +- 0x49, 0x3C, 0x49, 0xAD, +- +- 0x10, 0xCC, 0x10, 0xCD, +- 0x08, 0xCC, 0x08, 0xCD, +- +- 0xB9, 0x41, 0x49, 0xBB, +- 0x1F, 0xF0, 0x41, 0xCD, +- +- 0x51, 0x3C, 0x51, 0xAD, +- 0x00, 0x98, 0x80, 0xE9, +- +- 0x7F, 0x80, 0x07, 0xEA, +- 0x24, 0x1F, 0x20, 0xE9, +- +- 0x21, 0x45, 0x80, 0xE8, +- 0x1A, 0x4D, 0x80, 0xE8, +- +- 0x31, 0x55, 0x80, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0x41, 0x49, 0xBD, +- 0x1D, 0x41, 0x51, 0xBD, +- +- 0x2E, 0x41, 0x2A, 0xB8, +- 0x34, 0x53, 0xA0, 0xE8, +- +- 0x15, 0x30, +- 0x1D, 0x30, +- 0x58, 0xE3, +- 0x00, 0xE0, +- +- 0xB5, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x24, 0x43, 0xA0, 0xE8, +- 0x2C, 0x4B, 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0x1D, 0x32, 0x20, 0xE9, +- +- 0x2C, 0x1F, 0x2C, 0xDF, +- 0x1A, 0x33, 0x20, 0xE9, +- +- 0xB0, 0x10, +- 0x08, 0xE3, +- 0x40, 0x10, +- 0xB8, 0x10, +- +- 0x26, 0xF0, 0x30, 0xCD, +- 0x2F, 0xF0, 0x38, 0xCD, +- +- 0x2B, 0x80, 0x20, 0xE9, +- 0x2A, 0x80, 0x20, 0xE9, +- +- 0xA6, 0x20, +- 0x88, 0xE2, +- 0x00, 0xE0, +- 0xAF, 0x20, +- +- 0x28, 0x2A, 0x26, 0xAF, +- 0x20, 0x2A, 0xC0, 0xAF, +- +- 0x34, 0x1F, 0x34, 0xDF, +- 0x46, 0x24, 0x46, 0xDF, +- +- 0x28, 0x30, 0x80, 0xBF, +- 0x20, 0x38, 0x80, 0xBF, +- +- 0x47, 0x24, 0x47, 0xDF, +- 0x4E, 0x2C, 0x4E, 0xDF, +- +- 0x4F, 0x2C, 0x4F, 0xDF, +- 0x56, 0x34, 0x56, 0xDF, +- +- 0x28, 0x15, 0x28, 0xDF, +- 0x20, 0x1D, 0x20, 0xDF, +- +- 0x57, 0x34, 0x57, 0xDF, +- 0x00, 0xE0, +- 0x1D, 0x05, +- +- 0x04, 0x80, 0x10, 0xEA, +- 0x89, 0xE2, +- 0x2B, 0x30, +- +- 0x3F, 0xC1, 0x1D, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xA0, 0x68, +- 0xBF, 0x25, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x20, 0xC0, 0x20, 0xAF, +- 0x28, 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0x00, 0xE8, +- 0x28, 0x19, 0x60, 0xEC, +- +- 0xB3, 0x05, +- 0x00, 0xE0, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x23, 0x3B, 0x33, 0xAD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x17, 0x26, 0x17, 0xDF, +- 0x35, 0x17, 0x4F, 0xE9, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x39, 0x37, 0x4F, 0xE9, +- +- 0x2F, 0x2F, 0x17, 0xAF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x31, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x57, 0x39, 0x20, 0xE9, +- +- 0x16, 0x28, 0x20, 0xE9, +- 0x1D, 0x3B, 0x20, 0xE9, +- +- 0x1E, 0x2B, 0x20, 0xE9, +- 0x2B, 0x32, 0x20, 0xE9, +- +- 0x1C, 0x23, 0x20, 0xE9, +- 0x57, 0x36, 0x20, 0xE9, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x90, 0xE2, +- 0x00, 0xE0, +- +- 0x78, 0xFF, 0x20, 0xEA, +- 0x19, 0xC8, 0xC1, 0xCD, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x9F, 0x41, 0x49, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x25, 0x41, 0x49, 0xBD, +- 0x2D, 0x41, 0x51, 0xBD, +- +- 0x0D, 0x80, 0x07, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x35, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x25, 0x30, +- 0x2D, 0x30, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0xA7, 0x5B, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x77, 0xFF, 0x0A, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC9, 0x41, 0xC8, 0xEC, +- 0x42, 0xE1, +- 0x00, 0xE0, +- +- 0x75, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC8, 0x40, 0xC0, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x72, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +-}; +- +-static unsigned char warp_g200_tgzs[] = { +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x98, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x81, 0x04, +- 0x89, 0x04, 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0xE9, +- 0xA2, 0x3F, 0x4F, 0xE9, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x06, 0x06, 0x1F, 0xAF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xA0, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x57, 0x39, 0x20, 0xE9, +- +- 0x16, 0x28, 0x20, 0xE9, +- 0x1D, 0x3B, 0x20, 0xE9, +- +- 0x1E, 0x2B, 0x20, 0xE9, +- 0x2B, 0x32, 0x20, 0xE9, +- +- 0x1C, 0x23, 0x20, 0xE9, +- 0x57, 0x36, 0x20, 0xE9, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x90, 0xE2, +- 0x00, 0xE0, +- +- 0x6C, 0xFF, 0x20, 0xEA, +- 0x19, 0xC8, 0xC1, 0xCD, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x9F, 0x41, 0x49, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x25, 0x41, 0x49, 0xBD, +- 0x2D, 0x41, 0x51, 0xBD, +- +- 0x0D, 0x80, 0x07, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x35, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x25, 0x30, +- 0x2D, 0x30, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0xA7, 0x5B, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x6B, 0xFF, 0x0A, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC9, 0x41, 0xC8, 0xEC, +- 0x42, 0xE1, +- 0x00, 0xE0, +- +- 0x69, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC8, 0x40, 0xC0, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x66, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +-}; +- +-static unsigned char warp_g200_tgzsa[] = { +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 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0x30, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0xA7, 0x5B, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x67, 0xFF, 0x0A, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC9, 0x41, 0xC8, 0xEC, +- 0x42, 0xE1, +- 0x00, 0xE0, +- +- 0x65, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC8, 0x40, 0xC0, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x62, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +-}; +- +-static unsigned char warp_g200_tgzsaf[] = { +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 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0xE8, +- 0x57, 0x39, 0x20, 0xE9, +- +- 0x16, 0x28, 0x20, 0xE9, +- 0x1D, 0x3B, 0x20, 0xE9, +- +- 0x1E, 0x2B, 0x20, 0xE9, +- 0x2B, 0x32, 0x20, 0xE9, +- +- 0x1C, 0x23, 0x20, 0xE9, +- 0x57, 0x36, 0x20, 0xE9, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x90, 0xE2, +- 0x00, 0xE0, +- +- 0x63, 0xFF, 0x20, 0xEA, +- 0x19, 0xC8, 0xC1, 0xCD, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x9F, 0x41, 0x49, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x25, 0x41, 0x49, 0xBD, +- 0x2D, 0x41, 0x51, 0xBD, +- +- 0x0D, 0x80, 0x07, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x35, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x25, 0x30, +- 0x2D, 0x30, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0xA7, 0x5B, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x62, 0xFF, 0x0A, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC9, 0x41, 0xC8, 0xEC, +- 0x42, 0xE1, +- 0x00, 0xE0, +- +- 0x60, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC8, 0x40, 0xC0, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x5D, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +-}; +- +-static unsigned char warp_g200_tgzsf[] = { +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 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0xBB, +- 0x1F, 0xF0, 0x41, 0xCD, +- +- 0x51, 0x3C, 0x51, 0xAD, +- 0x00, 0x98, 0x80, 0xE9, +- +- 0x8F, 0x80, 0x07, 0xEA, +- 0x24, 0x1F, 0x20, 0xE9, +- +- 0x21, 0x45, 0x80, 0xE8, +- 0x1A, 0x4D, 0x80, 0xE8, +- +- 0x31, 0x55, 0x80, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0x41, 0x49, 0xBD, +- 0x1D, 0x41, 0x51, 0xBD, +- +- 0x2E, 0x41, 0x2A, 0xB8, +- 0x34, 0x53, 0xA0, 0xE8, +- +- 0x15, 0x30, +- 0x1D, 0x30, +- 0x58, 0xE3, +- 0x00, 0xE0, +- +- 0xB5, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x24, 0x43, 0xA0, 0xE8, +- 0x2C, 0x4B, 0xA0, 0xE8, +- +- 0x15, 0x72, +- 0x09, 0xE3, +- 0x00, 0xE0, +- 0x1D, 0x72, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0x97, 0x57, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x6C, 0x64, 0xC8, 0xEC, +- 0x98, 0xE1, +- 0xB5, 0x05, +- +- 0xBD, 0x05, +- 0x2E, 0x30, +- 0x32, 0xC0, 0xA0, 0xE8, +- +- 0x33, 0xC0, 0xA0, 0xE8, +- 0x74, 0x64, 0xC8, 0xEC, +- +- 0x40, 0x3C, 0x40, 0xAD, +- 0x32, 0x6A, +- 0x2A, 0x30, +- +- 0x20, 0x73, +- 0x33, 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0x44, 0xC4, +- +- 0x33, 0x73, +- 0x00, 0xE0, +- 0x3E, 0x62, 0x57, 0x9F, +- +- 0x1E, 0xAF, 0x59, 0x9F, +- 0x00, 0xE0, +- 0x0D, 0x20, +- +- 0x84, 0x3E, 0x58, 0xE9, +- 0x28, 0x1D, 0x6F, 0x8F, +- +- 0x05, 0x20, +- 0x00, 0xE0, +- 0x85, 0x1E, 0x58, 0xE9, +- +- 0x9B, 0x3B, 0x33, 0xDF, +- 0x20, 0x20, 0x42, 0xAF, +- +- 0x30, 0x42, 0x56, 0x9F, +- 0x80, 0x3E, 0x57, 0xE9, +- +- 0x3F, 0x8F, 0x51, 0x9F, +- 0x30, 0x80, 0x5F, 0xE9, +- +- 0x28, 0x28, 0x24, 0xAF, +- 0x81, 0x1E, 0x57, 0xE9, +- +- 0x05, 0x47, 0x57, 0xBF, +- 0x0D, 0x47, 0x4F, 0xBF, +- +- 0x88, 0x80, 0x58, 0xE9, +- 0x1B, 0x29, 0x1B, 0xDF, +- +- 0x30, 0x1D, 0x6F, 0x8F, +- 0x3A, 0x30, 0x4F, 0xE9, +- +- 0x1C, 0x30, 0x26, 0xDF, +- 0x09, 0xE3, +- 0x3B, 0x05, +- +- 0x3E, 0x50, 0x56, 0x9F, +- 0x3B, 0x3F, 0x4F, 0xE9, +- +- 0x1E, 0x8F, 0x51, 0x9F, +- 0x00, 0xE0, +- 0xAC, 0x20, +- +- 0x2D, 0x44, 0x4C, 0xB4, +- 0x2C, 0x1C, 0xC0, 0xAF, +- +- 0x25, 0x44, 0x54, 0xB4, +- 0x00, 0xE0, +- 0xC8, 0x30, +- +- 0x30, 0x46, 0x30, 0xAF, +- 0x1B, 0x1B, 0x48, 0xAF, +- +- 0x00, 0xE0, +- 0x25, 0x20, +- 0x38, 0x2C, 0x4F, 0xE9, +- +- 0x86, 0x80, 0x57, 0xE9, +- 0x38, 0x1D, 0x6F, 0x8F, +- +- 0x28, 0x74, +- 0x00, 0xE0, +- 0x0D, 0x44, 0x4C, 0xB0, +- +- 0x05, 0x44, 0x54, 0xB0, +- 0x2D, 0x20, +- 0x9B, 0x10, +- +- 0x82, 0x3E, 0x57, 0xE9, +- 0x32, 0xF0, 0x1B, 0xCD, +- +- 0x1E, 0xBD, 0x59, 0x9F, +- 0x83, 0x1E, 0x57, 0xE9, +- +- 0x38, 0x47, 0x38, 0xAF, +- 0x34, 0x20, +- 0x2A, 0x30, +- +- 0x00, 0xE0, +- 0x0D, 0x20, +- 0x32, 0x20, +- 0x05, 0x20, +- +- 0x87, 0x80, 0x57, 0xE9, +- 0x1F, 0x54, 0x57, 0x9F, +- +- 0x17, 0x42, 0x56, 0x9F, +- 0x00, 0xE0, +- 0x3B, 0x6A, +- +- 0x3F, 0x8F, 0x51, 0x9F, +- 0x37, 0x1E, 0x4F, 0xE9, +- +- 0x37, 0x32, 0x2A, 0xAF, +- 0x00, 0xE0, +- 0x32, 0x00, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x27, 0xC0, 0x44, 0xC0, +- +- 0x36, 0x1F, 0x4F, 0xE9, +- 0x1F, 0x1F, 0x26, 0xDF, +- +- 0x37, 0x1B, 0x37, 0xBF, +- 0x17, 0x26, 0x17, 0xDF, +- +- 0x3E, 0x17, 0x4F, 0xE9, +- 0x3F, 0x3F, 0x4F, 0xE9, +- +- 0x34, 0x1F, 0x34, 0xAF, +- 0x2B, 0x05, +- 0xA7, 0x20, +- +- 0x33, 0x2B, 0x37, 0xDF, +- 0x27, 0x17, 0xC0, 0xAF, +- +- 0x34, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x2D, 0x21, 0x1A, 0xB0, +- 0x25, 0x21, 0x31, 0xB0, +- +- 0x0D, 0x21, 0x1A, 0xB2, +- 0x05, 0x21, 0x31, 0xB2, +- +- 0x03, 0x80, 0x2A, 0xEA, +- 0x17, 0xC1, 0x2B, 0xBD, +- +- 0x2D, 0x20, +- 0x25, 0x20, +- 0x05, 0x20, +- 0x0D, 0x20, +- +- 0xB3, 0x68, +- 0x97, 0x25, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x33, 0xC0, 0x33, 0xAF, +- 0x2F, 0xC0, 0x21, 0xC0, +- +- 0x16, 0x42, 0x56, 0x9F, +- 0x3C, 0x27, 0x4F, 0xE9, +- +- 0x1E, 0x62, 0x57, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x25, 0x21, 0x31, 0xB4, +- 0x2D, 0x21, 0x1A, 0xB4, +- +- 0x3F, 0x2F, 0x5D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x33, 0x05, +- 0x00, 0xE0, +- 0x28, 0x19, 0x60, 0xEC, +- +- 0x0D, 0x21, 0x1A, 0xB6, +- 0x05, 0x21, 0x31, 0xB6, +- +- 0x37, 0x0F, 0x5C, 0x9F, +- 0x00, 0xE0, +- 0x2F, 0x20, +- +- 0x23, 0x3B, 0x33, 0xAD, +- 0x1E, 0x26, 0x1E, 0xDF, +- +- 0xA7, 0x1E, 0x4F, 0xE9, +- 0x17, 0x26, 0x16, 0xDF, +- +- 0x2D, 0x20, +- 0x00, 0xE0, +- 0xA8, 0x3F, 0x4F, 0xE9, +- +- 0x2F, 0x2F, 0x1E, 0xAF, +- 0x25, 0x20, +- 0x00, 0xE0, +- +- 0xA4, 0x16, 0x4F, 0xE9, +- 0x0F, 0xC0, 0x21, 0xC2, +- +- 0xA6, 0x80, 0x4F, 0xE9, +- 0x1F, 0x62, 0x57, 0x9F, +- +- 0x0D, 0x20, +- 0x05, 0x20, +- 0x2F, 0xC0, 0x21, 0xC6, +- +- 0x3F, 0x2F, 0x5D, 0x9F, +- 0x00, 0xE0, +- 0x0F, 0x20, +- +- 0x17, 0x50, 0x56, 0x9F, +- 0xA5, 0x37, 0x4F, 0xE9, +- +- 0x06, 0xC0, 0x21, 0xC4, +- 0x0F, 0x17, 0x0F, 0xAF, +- +- 0x37, 0x0F, 0x5C, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x2F, 0x20, +- 0x00, 0xE0, +- 0xA3, 0x80, 0x4F, 0xE9, +- +- 0x06, 0x20, +- 0x00, 0xE0, +- 0x1F, 0x26, 0x1F, 0xDF, +- +- 0x17, 0x26, 0x17, 0xDF, +- 0x35, 0x17, 0x4F, 0xE9, +- +- 0xA1, 0x1F, 0x4F, 0xE9, +- 0xA2, 0x3F, 0x4F, 0xE9, +- +- 0x06, 0x06, 0x1F, 0xAF, +- 0x39, 0x37, 0x4F, 0xE9, +- +- 0x2F, 0x2F, 0x17, 0xAF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xA0, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x31, 0x80, 0x4F, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x57, 0x39, 0x20, 0xE9, +- +- 0x16, 0x28, 0x20, 0xE9, +- 0x1D, 0x3B, 0x20, 0xE9, +- +- 0x1E, 0x2B, 0x20, 0xE9, +- 0x2B, 0x32, 0x20, 0xE9, +- +- 0x1C, 0x23, 0x20, 0xE9, +- 0x57, 0x36, 0x20, 0xE9, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x40, 0x40, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x90, 0xE2, +- 0x00, 0xE0, +- +- 0x68, 0xFF, 0x20, 0xEA, +- 0x19, 0xC8, 0xC1, 0xCD, +- +- 0x1F, 0xD7, 0x18, 0xBD, +- 0x3F, 0xD7, 0x22, 0xBD, +- +- 0x9F, 0x41, 0x49, 0xBD, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x25, 0x41, 0x49, 0xBD, +- 0x2D, 0x41, 0x51, 0xBD, +- +- 0x0D, 0x80, 0x07, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x35, 0x40, 0x48, 0xBD, +- 0x3D, 0x40, 0x50, 0xBD, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x25, 0x30, +- 0x2D, 0x30, +- +- 0x35, 0x30, +- 0xB5, 0x30, +- 0xBD, 0x30, +- 0x3D, 0x30, +- +- 0x9C, 0xA7, 0x5B, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x67, 0xFF, 0x0A, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC9, 0x41, 0xC8, 0xEC, +- 0x42, 0xE1, +- 0x00, 0xE0, +- +- 0x65, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xC8, 0x40, 0xC0, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x62, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +-}; +- +-static unsigned char warp_g400_t2gz[] = { +- +- 0x00, 0x8A, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x0A, 0x40, 0x50, 0xBF, +- 0x2A, 0x40, 0x60, 0xBF, +- +- 0x32, 0x41, 0x51, 0xBF, +- 0x3A, 0x41, 0x61, 0xBF, +- +- 0xC3, 0x6B, +- 0xD3, 0x6B, +- 0x00, 0x8A, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x23, 0x9F, +- 0x00, 0xE0, +- 0x51, 0x04, +- +- 0x90, 0xE2, +- 0x61, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x51, 0x41, 0xE0, 0xEC, +- 0x39, 0x67, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x63, 0xA0, 0xE8, +- +- 0x61, 0x41, 0xE0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x78, 0x80, 0x15, 0xEA, +- 0x10, 0x04, +- 0x20, 0x04, +- +- 0x61, 0x51, 0xE0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x52, 0xBF, +- 0x0F, 0x52, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x62, 0xBF, +- 0x1E, 0x51, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x0E, 0x61, 0x60, 0xEA, +- +- 0x32, 0x40, 0x50, 0xBD, +- 0x22, 0x40, 0x60, 0xBD, +- +- 0x12, 0x41, 0x51, 0xBD, +- 0x3A, 0x41, 0x61, 0xBD, +- +- 0xBF, 0x2F, 0x0E, 0xBD, +- 0x97, 0xE2, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x35, 0x48, 0xB1, 0xE8, +- 0x3D, 0x59, 0xB1, 0xE8, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x56, 0x31, 0x56, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x66, 0x31, 0x66, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x57, 0x39, 0x57, 0xBF, +- 0x67, 0x39, 0x67, 0xBF, +- +- 0x69, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x35, 0x00, +- 0x3D, 0x00, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0x8D, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x75, 0xF8, 0xEC, +- 0x35, 0x20, +- 0x3D, 0x20, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x53, 0x53, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x0E, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x48, 0x35, 0x48, 0xBF, +- 0x58, 0x35, 0x58, 0xBF, +- +- 0x68, 0x35, 0x68, 0xBF, +- 0x49, 0x3D, 0x49, 0xBF, +- +- 0x59, 0x3D, 0x59, 0xBF, +- 0x69, 0x3D, 0x69, 0xBF, +- +- 0x63, 0x63, 0x2D, 0xDF, +- 0x4D, 0x7D, 0xF8, 0xEC, +- +- 0x59, 0xE3, +- 0x00, 0xE0, +- 0xB8, 0x38, 0x33, 0xBF, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x18, 0x3A, 0x41, 0xE9, +- +- 0x3F, 0x53, 0xA0, 0xE8, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x63, 0xA0, 0xE8, +- +- 0x50, 0x70, 0xF8, 0xEC, +- 0x2B, 0x50, 0x3C, 0xE9, +- +- 0x1F, 0x0F, 0xBC, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x59, 0x78, 0xF8, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x1E, 0x12, 0x41, 0xE9, +- 0x1A, 0x22, 0x41, 0xE9, +- +- 0x46, 0x37, 0x46, 0xDF, +- 0x56, 0x3F, 0x56, 0xDF, +- +- 0x2B, 0x40, 0x3D, 0xE9, +- 0x66, 0x3D, 0x66, 0xDF, +- +- 0x1D, 0x32, 0x41, 0xE9, +- 0x67, 0x3D, 0x67, 0xDF, +- +- 0x47, 0x37, 0x47, 0xDF, +- 0x57, 0x3F, 0x57, 0xDF, +- +- 0x2A, 0x40, 0x20, 0xE9, +- 0x59, 0x3F, 0x59, 0xDF, +- +- 0x16, 0x30, 0x20, 0xE9, +- 0x69, 0x3D, 0x69, 0xDF, +- +- 0x48, 0x37, 0x48, 0xDF, +- 0x58, 0x3F, 0x58, 0xDF, +- +- 0x12, 0x12, 0x2D, 0xDF, +- 0x22, 0x22, 0x2D, 0xDF, +- +- 0x32, 0x32, 0x2D, 0xDF, +- 0x3A, 0x3A, 0x2D, 0xDF, +- +- 0x68, 0x3D, 0x68, 0xDF, +- 0x49, 0x37, 0x49, 0xDF, +- +- 0x3D, 0xCF, 0x74, 0xC0, +- 0x37, 0xCF, 0x74, 0xC4, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x34, 0x80, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3C, 0x3D, 0x20, 0xE9, +- +- 0x0A, 0x44, 0x54, 0xB0, +- 0x02, 0x44, 0x64, 0xB0, +- +- 0x2A, 0x44, 0x54, 0xB2, +- 0x1A, 0x44, 0x64, 0xB2, +- +- 0x25, 0x80, 0x3A, 0xEA, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x3D, 0xCF, 0x74, 0xC2, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x32, 0x31, 0x5F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x33, 0x39, 0x5F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x2A, 0x44, 0x54, 0xB4, +- 0x1A, 0x44, 0x64, 0xB4, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x38, 0x3D, 0x20, 0xE9, +- +- 0x88, 0x73, 0x5E, 0xE9, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x2A, 0x46, 0x56, 0xBF, +- 0x1A, 0x46, 0x66, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3E, 0x30, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3F, 0x38, 0x4F, 0xE9, +- +- 0x0A, 0x47, 0x57, 0xBF, +- 0x02, 0x47, 0x67, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3A, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3B, 0x39, 0x4F, 0xE9, +- +- 0x2A, 0x43, 0x53, 0xBF, +- 0x1A, 0x43, 0x63, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x36, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x37, 0x39, 0x4F, 0xE9, +- +- 0x0A, 0x48, 0x58, 0xBF, +- 0x02, 0x48, 0x68, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x2A, 0x49, 0x59, 0xBF, +- 0x1A, 0x49, 0x69, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x82, 0x30, 0x57, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x83, 0x38, 0x57, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x84, 0x31, 0x5E, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x85, 0x39, 0x5E, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x87, 0x77, 0x57, 0xE9, +- 0x8B, 0x3E, 0xBF, 0xEA, +- +- 0x80, 0x30, 0x57, 0xE9, +- 0x81, 0x38, 0x57, 0xE9, +- +- 0x82, 0x31, 0x57, 0xE9, +- 0x86, 0x78, 0x57, 0xE9, +- +- 0x83, 0x39, 0x57, 0xE9, +- 0x87, 0x79, 0x57, 0xE9, +- +- 0x30, 0x1F, 0x5F, 0xE9, +- 0x8A, 0x34, 0x20, 0xE9, +- +- 0x8B, 0x3C, 0x20, 0xE9, +- 0x37, 0x50, 0x60, 0xBD, +- +- 0x57, 0x0D, 0x20, 0xE9, +- 0x35, 0x51, 0x61, 0xBD, +- +- 0x2B, 0x50, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x0E, 0x77, +- +- 0x24, 0x51, 0x20, 0xE9, +- 0x9F, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x0E, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x0B, 0x46, 0xA0, 0xE8, +- 0x1B, 0x56, 0xA0, 0xE8, +- +- 0x2B, 0x66, 0xA0, 0xE8, +- 0x0C, 0x47, 0xA0, 0xE8, +- +- 0x1C, 0x57, 0xA0, 0xE8, +- 0x2C, 0x67, 0xA0, 0xE8, +- +- 0x0B, 0x00, +- 0x1B, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x0C, 0x00, +- 0x1C, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x0B, 0x65, +- 0x1B, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x0C, 0x65, +- 0x1C, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x0B, 0x1B, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x57, 0x80, 0x57, 0xCF, +- +- 0x66, 0x33, 0x66, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x67, 0x3B, 0x67, 0xCF, +- +- 0x0B, 0x48, 0xA0, 0xE8, +- 0x1B, 0x58, 0xA0, 0xE8, +- +- 0x2B, 0x68, 0xA0, 0xE8, +- 0x0C, 0x49, 0xA0, 0xE8, +- +- 0x1C, 0x59, 0xA0, 0xE8, +- 0x2C, 0x69, 0xA0, 0xE8, +- +- 0x0B, 0x00, +- 0x1B, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x0C, 0x00, +- 0x1C, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x0B, 0x65, +- 0x1B, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x0C, 0x65, +- 0x1C, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x0B, 0x1B, 0x60, 0xEC, +- 0x34, 0xD7, 0x34, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3C, 0xD7, 0x3C, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x34, 0x80, 0x34, 0xBD, +- 0x3C, 0x80, 0x3C, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x48, 0x80, 0x48, 0xCF, +- 0x59, 0x80, 0x59, 0xCF, +- +- 0x68, 0x33, 0x68, 0xCF, +- 0x49, 0x3B, 0x49, 0xCF, +- +- 0xBE, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x58, 0x33, 0x58, 0xCF, +- 0x69, 0x3B, 0x69, 0xCF, +- +- 0x7D, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_t2gza[] = { +- +- 0x00, 0x8A, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x0A, 0x40, 0x50, 0xBF, +- 0x2A, 0x40, 0x60, 0xBF, +- +- 0x32, 0x41, 0x51, 0xBF, +- 0x3A, 0x41, 0x61, 0xBF, +- +- 0xC3, 0x6B, +- 0xD3, 0x6B, +- 0x00, 0x8A, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x23, 0x9F, +- 0x00, 0xE0, +- 0x51, 0x04, +- +- 0x90, 0xE2, +- 0x61, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x51, 0x41, 0xE0, 0xEC, +- 0x39, 0x67, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x63, 0xA0, 0xE8, +- +- 0x61, 0x41, 0xE0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x7C, 0x80, 0x15, 0xEA, +- 0x10, 0x04, +- 0x20, 0x04, +- +- 0x61, 0x51, 0xE0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x52, 0xBF, +- 0x0F, 0x52, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x62, 0xBF, +- 0x1E, 0x51, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x0E, 0x61, 0x60, 0xEA, +- +- 0x32, 0x40, 0x50, 0xBD, +- 0x22, 0x40, 0x60, 0xBD, +- +- 0x12, 0x41, 0x51, 0xBD, +- 0x3A, 0x41, 0x61, 0xBD, +- +- 0xBF, 0x2F, 0x0E, 0xBD, +- 0x97, 0xE2, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x35, 0x48, 0xB1, 0xE8, +- 0x3D, 0x59, 0xB1, 0xE8, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x56, 0x31, 0x56, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x66, 0x31, 0x66, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x57, 0x39, 0x57, 0xBF, +- 0x67, 0x39, 0x67, 0xBF, +- +- 0x6D, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x35, 0x00, +- 0x3D, 0x00, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0x8D, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x75, 0xF8, 0xEC, +- 0x35, 0x20, +- 0x3D, 0x20, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x53, 0x53, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x0E, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x48, 0x35, 0x48, 0xBF, +- 0x58, 0x35, 0x58, 0xBF, +- +- 0x68, 0x35, 0x68, 0xBF, +- 0x49, 0x3D, 0x49, 0xBF, +- +- 0x59, 0x3D, 0x59, 0xBF, +- 0x69, 0x3D, 0x69, 0xBF, +- +- 0x63, 0x63, 0x2D, 0xDF, +- 0x4D, 0x7D, 0xF8, 0xEC, +- +- 0x59, 0xE3, +- 0x00, 0xE0, +- 0xB8, 0x38, 0x33, 0xBF, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x18, 0x3A, 0x41, 0xE9, +- +- 0x3F, 0x53, 0xA0, 0xE8, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x63, 0xA0, 0xE8, +- +- 0x50, 0x70, 0xF8, 0xEC, +- 0x2B, 0x50, 0x3C, 0xE9, +- +- 0x1F, 0x0F, 0xBC, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x59, 0x78, 0xF8, 0xEC, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x1E, 0x12, 0x41, 0xE9, +- 0x1A, 0x22, 0x41, 0xE9, +- +- 0x46, 0x37, 0x46, 0xDF, +- 0x56, 0x3F, 0x56, 0xDF, +- +- 0x2B, 0x40, 0x3D, 0xE9, +- 0x66, 0x3D, 0x66, 0xDF, +- +- 0x1D, 0x32, 0x41, 0xE9, +- 0x67, 0x3D, 0x67, 0xDF, +- +- 0x47, 0x37, 0x47, 0xDF, +- 0x57, 0x3F, 0x57, 0xDF, +- +- 0x2A, 0x40, 0x20, 0xE9, +- 0x59, 0x3F, 0x59, 0xDF, +- +- 0x16, 0x30, 0x20, 0xE9, +- 0x69, 0x3D, 0x69, 0xDF, +- +- 0x48, 0x37, 0x48, 0xDF, +- 0x58, 0x3F, 0x58, 0xDF, +- +- 0x12, 0x12, 0x2D, 0xDF, +- 0x22, 0x22, 0x2D, 0xDF, +- +- 0x32, 0x32, 0x2D, 0xDF, +- 0x3A, 0x3A, 0x2D, 0xDF, +- +- 0x68, 0x3D, 0x68, 0xDF, +- 0x49, 0x37, 0x49, 0xDF, +- +- 0x3D, 0xCF, 0x74, 0xC0, +- 0x37, 0xCF, 0x74, 0xC4, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x34, 0x80, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3C, 0x3D, 0x20, 0xE9, +- +- 0x0A, 0x44, 0x54, 0xB0, +- 0x02, 0x44, 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0x31, 0x53, 0x2F, 0x9F, +- 0x36, 0x30, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x37, 0x38, 0x4F, 0xE9, +- +- 0x2A, 0x43, 0x53, 0xBF, +- 0x1A, 0x43, 0x63, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x9D, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x9E, 0x39, 0x4F, 0xE9, +- +- 0x0A, 0x48, 0x58, 0xBF, +- 0x02, 0x48, 0x68, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x2A, 0x49, 0x59, 0xBF, +- 0x1A, 0x49, 0x69, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x82, 0x30, 0x57, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x83, 0x38, 0x57, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x84, 0x31, 0x5E, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x85, 0x39, 0x5E, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x87, 0x77, 0x57, 0xE9, +- 0x8B, 0x3E, 0xBF, 0xEA, +- +- 0x80, 0x30, 0x57, 0xE9, +- 0x81, 0x38, 0x57, 0xE9, +- +- 0x82, 0x31, 0x57, 0xE9, +- 0x86, 0x78, 0x57, 0xE9, +- +- 0x83, 0x39, 0x57, 0xE9, +- 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0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x57, 0x80, 0x57, 0xCF, +- +- 0x66, 0x33, 0x66, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x67, 0x3B, 0x67, 0xCF, +- +- 0x0B, 0x48, 0xA0, 0xE8, +- 0x1B, 0x58, 0xA0, 0xE8, +- +- 0x2B, 0x68, 0xA0, 0xE8, +- 0x0C, 0x49, 0xA0, 0xE8, +- +- 0x1C, 0x59, 0xA0, 0xE8, +- 0x2C, 0x69, 0xA0, 0xE8, +- +- 0x0B, 0x00, +- 0x1B, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x0C, 0x00, +- 0x1C, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x0B, 0x65, +- 0x1B, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x0C, 0x65, +- 0x1C, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x0B, 0x1B, 0x60, 0xEC, +- 0x34, 0xD7, 0x34, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3C, 0xD7, 0x3C, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x34, 0x80, 0x34, 0xBD, +- 0x3C, 0x80, 0x3C, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x48, 0x80, 0x48, 0xCF, +- 0x59, 0x80, 0x59, 0xCF, +- +- 0x68, 0x33, 0x68, 0xCF, +- 0x49, 0x3B, 0x49, 0xCF, +- +- 0xBA, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x58, 0x33, 0x58, 0xCF, +- 0x69, 0x3B, 0x69, 0xCF, +- +- 0x79, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_t2gzaf[] = { +- +- 0x00, 0x8A, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x0A, 0x40, 0x50, 0xBF, +- 0x2A, 0x40, 0x60, 0xBF, +- +- 0x32, 0x41, 0x51, 0xBF, +- 0x3A, 0x41, 0x61, 0xBF, +- +- 0xC3, 0x6B, +- 0xD3, 0x6B, +- 0x00, 0x8A, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x23, 0x9F, +- 0x00, 0xE0, +- 0x51, 0x04, +- +- 0x90, 0xE2, +- 0x61, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x51, 0x41, 0xE0, 0xEC, +- 0x39, 0x67, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x63, 0xA0, 0xE8, +- +- 0x61, 0x41, 0xE0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x81, 0x80, 0x15, 0xEA, +- 0x10, 0x04, +- 0x20, 0x04, +- +- 0x61, 0x51, 0xE0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x52, 0xBF, +- 0x0F, 0x52, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x62, 0xBF, +- 0x1E, 0x51, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x0E, 0x61, 0x60, 0xEA, +- +- 0x32, 0x40, 0x50, 0xBD, +- 0x22, 0x40, 0x60, 0xBD, +- +- 0x12, 0x41, 0x51, 0xBD, +- 0x3A, 0x41, 0x61, 0xBD, +- +- 0xBF, 0x2F, 0x0E, 0xBD, +- 0x97, 0xE2, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x35, 0x48, 0xB1, 0xE8, +- 0x3D, 0x59, 0xB1, 0xE8, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x56, 0x31, 0x56, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x66, 0x31, 0x66, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x57, 0x39, 0x57, 0xBF, +- 0x67, 0x39, 0x67, 0xBF, +- +- 0x72, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x35, 0x00, +- 0x3D, 0x00, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0x8D, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x75, 0xF8, 0xEC, +- 0x35, 0x20, +- 0x3D, 0x20, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x53, 0x53, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x0E, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x48, 0x35, 0x48, 0xBF, +- 0x58, 0x35, 0x58, 0xBF, +- +- 0x68, 0x35, 0x68, 0xBF, +- 0x49, 0x3D, 0x49, 0xBF, +- +- 0x59, 0x3D, 0x59, 0xBF, +- 0x69, 0x3D, 0x69, 0xBF, +- +- 0x63, 0x63, 0x2D, 0xDF, +- 0x4D, 0x7D, 0xF8, 0xEC, +- +- 0x59, 0xE3, +- 0x00, 0xE0, +- 0xB8, 0x38, 0x33, 0xBF, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x18, 0x3A, 0x41, 0xE9, +- +- 0x3F, 0x53, 0xA0, 0xE8, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x63, 0xA0, 0xE8, +- +- 0x50, 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0xE0, +- +- 0x0C, 0x00, +- 0x1C, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x0B, 0x65, +- 0x1B, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x0C, 0x65, +- 0x1C, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x0B, 0x1B, 0x60, 0xEC, +- 0x34, 0xD7, 0x34, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3C, 0xD7, 0x3C, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x34, 0x80, 0x34, 0xBD, +- 0x3C, 0x80, 0x3C, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x48, 0x80, 0x48, 0xCF, +- 0x59, 0x80, 0x59, 0xCF, +- +- 0x68, 0x33, 0x68, 0xCF, +- 0x49, 0x3B, 0x49, 0xCF, +- +- 0xB5, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x58, 0x33, 0x58, 0xCF, +- 0x69, 0x3B, 0x69, 0xCF, +- +- 0x74, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_t2gzf[] = { +- +- 0x00, 0x8A, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 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0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_t2gzs[] = { +- +- 0x00, 0x8A, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x0A, 0x40, 0x50, 0xBF, +- 0x2A, 0x40, 0x60, 0xBF, +- +- 0x32, 0x41, 0x51, 0xBF, +- 0x3A, 0x41, 0x61, 0xBF, +- +- 0xC3, 0x6B, +- 0xD3, 0x6B, +- 0x00, 0x8A, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x23, 0x9F, +- 0x00, 0xE0, +- 0x51, 0x04, +- +- 0x90, 0xE2, +- 0x61, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x51, 0x41, 0xE0, 0xEC, +- 0x39, 0x67, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x63, 0xA0, 0xE8, +- +- 0x61, 0x41, 0xE0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x85, 0x80, 0x15, 0xEA, +- 0x10, 0x04, +- 0x20, 0x04, +- +- 0x61, 0x51, 0xE0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 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0x1B, 0x60, 0xEC, +- 0x34, 0xD7, 0x34, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3C, 0xD7, 0x3C, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x34, 0x80, 0x34, 0xBD, +- 0x3C, 0x80, 0x3C, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x48, 0x80, 0x48, 0xCF, +- 0x59, 0x80, 0x59, 0xCF, +- +- 0x68, 0x33, 0x68, 0xCF, +- 0x49, 0x3B, 0x49, 0xCF, +- +- 0xB2, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x58, 0x33, 0x58, 0xCF, +- 0x69, 0x3B, 0x69, 0xCF, +- +- 0x70, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_t2gzsa[] = { +- +- 0x00, 0x8A, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x0A, 0x40, 0x50, 0xBF, +- 0x2A, 0x40, 0x60, 0xBF, +- +- 0x32, 0x41, 0x51, 0xBF, +- 0x3A, 0x41, 0x61, 0xBF, +- +- 0xC3, 0x6B, +- 0xD3, 0x6B, +- 0x00, 0x8A, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x23, 0x9F, +- 0x00, 0xE0, +- 0x51, 0x04, +- +- 0x90, 0xE2, +- 0x61, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x51, 0x41, 0xE0, 0xEC, +- 0x39, 0x67, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x63, 0xA0, 0xE8, +- +- 0x61, 0x41, 0xE0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x8A, 0x80, 0x15, 0xEA, +- 0x10, 0x04, +- 0x20, 0x04, +- +- 0x61, 0x51, 0xE0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x52, 0xBF, +- 0x0F, 0x52, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x62, 0xBF, +- 0x1E, 0x51, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x0E, 0x61, 0x60, 0xEA, +- +- 0x32, 0x40, 0x50, 0xBD, +- 0x22, 0x40, 0x60, 0xBD, +- +- 0x12, 0x41, 0x51, 0xBD, +- 0x3A, 0x41, 0x61, 0xBD, +- +- 0xBF, 0x2F, 0x0E, 0xBD, +- 0x97, 0xE2, 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0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3C, 0xD7, 0x3C, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x34, 0x80, 0x34, 0xBD, +- 0x3C, 0x80, 0x3C, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x48, 0x80, 0x48, 0xCF, +- 0x59, 0x80, 0x59, 0xCF, +- +- 0x68, 0x33, 0x68, 0xCF, +- 0x49, 0x3B, 0x49, 0xCF, +- +- 0xAD, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x58, 0x33, 0x58, 0xCF, +- 0x69, 0x3B, 0x69, 0xCF, +- +- 0x6B, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_t2gzsaf[] = { +- +- 0x00, 0x8A, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x0A, 0x40, 0x50, 0xBF, +- 0x2A, 0x40, 0x60, 0xBF, +- +- 0x32, 0x41, 0x51, 0xBF, +- 0x3A, 0x41, 0x61, 0xBF, +- +- 0xC3, 0x6B, +- 0xD3, 0x6B, +- 0x00, 0x8A, 0x98, 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0xE0, +- +- 0x0C, 0x65, +- 0x1C, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x0B, 0x1B, 0x60, 0xEC, +- 0x34, 0xD7, 0x34, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3C, 0xD7, 0x3C, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x34, 0x80, 0x34, 0xBD, +- 0x3C, 0x80, 0x3C, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x48, 0x80, 0x48, 0xCF, +- 0x59, 0x80, 0x59, 0xCF, +- +- 0x68, 0x33, 0x68, 0xCF, +- 0x49, 0x3B, 0x49, 0xCF, +- +- 0xA9, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x58, 0x33, 0x58, 0xCF, +- 0x69, 0x3B, 0x69, 0xCF, +- +- 0x67, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_t2gzsf[] = { +- +- 0x00, 0x8A, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x0A, 0x40, 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0x87, 0x77, 0x57, 0xE9, +- 0x8B, 0x3E, 0xBF, 0xEA, +- +- 0x80, 0x30, 0x57, 0xE9, +- 0x81, 0x38, 0x57, 0xE9, +- +- 0x82, 0x31, 0x57, 0xE9, +- 0x86, 0x78, 0x57, 0xE9, +- +- 0x83, 0x39, 0x57, 0xE9, +- 0x87, 0x79, 0x57, 0xE9, +- +- 0x30, 0x1F, 0x5F, 0xE9, +- 0x8A, 0x34, 0x20, 0xE9, +- +- 0x8B, 0x3C, 0x20, 0xE9, +- 0x37, 0x50, 0x60, 0xBD, +- +- 0x57, 0x0D, 0x20, 0xE9, +- 0x35, 0x51, 0x61, 0xBD, +- +- 0x2B, 0x50, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x0E, 0x77, +- +- 0x24, 0x51, 0x20, 0xE9, +- 0x8D, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x0E, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x0B, 0x46, 0xA0, 0xE8, +- 0x1B, 0x56, 0xA0, 0xE8, +- +- 0x2B, 0x66, 0xA0, 0xE8, +- 0x0C, 0x47, 0xA0, 0xE8, +- +- 0x1C, 0x57, 0xA0, 0xE8, +- 0x2C, 0x67, 0xA0, 0xE8, +- +- 0x0B, 0x00, +- 0x1B, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x0C, 0x00, +- 0x1C, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x0B, 0x65, +- 0x1B, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x0C, 0x65, +- 0x1C, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x0B, 0x1B, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x57, 0x80, 0x57, 0xCF, +- +- 0x66, 0x33, 0x66, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x67, 0x3B, 0x67, 0xCF, +- +- 0x0B, 0x48, 0xA0, 0xE8, +- 0x1B, 0x58, 0xA0, 0xE8, +- +- 0x2B, 0x68, 0xA0, 0xE8, +- 0x0C, 0x49, 0xA0, 0xE8, +- +- 0x1C, 0x59, 0xA0, 0xE8, +- 0x2C, 0x69, 0xA0, 0xE8, +- +- 0x0B, 0x00, +- 0x1B, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x0C, 0x00, +- 0x1C, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x0B, 0x65, +- 0x1B, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x0C, 0x65, +- 0x1C, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x0B, 0x1B, 0x60, 0xEC, +- 0x34, 0xD7, 0x34, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x0C, 0x1C, 0x60, 0xEC, +- +- 0x3C, 0xD7, 0x3C, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x0B, 0x2B, 0xDE, 0xE8, +- 0x1B, 0x80, 0xDE, 0xE8, +- +- 0x34, 0x80, 0x34, 0xBD, +- 0x3C, 0x80, 0x3C, 0xBD, +- +- 0x33, 0xD7, 0x0B, 0xBD, +- 0x3B, 0xD7, 0x1B, 0xBD, +- +- 0x48, 0x80, 0x48, 0xCF, +- 0x59, 0x80, 0x59, 0xCF, +- +- 0x68, 0x33, 0x68, 0xCF, +- 0x49, 0x3B, 0x49, 0xCF, +- +- 0xAD, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x58, 0x33, 0x58, 0xCF, +- 0x69, 0x3B, 0x69, 0xCF, +- +- 0x6B, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_tgz[] = { +- +- 0x00, 0x88, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x22, 0x40, 0x48, 0xBF, +- 0x2A, 0x40, 0x50, 0xBF, +- +- 0x32, 0x41, 0x49, 0xBF, +- 0x3A, 0x41, 0x51, 0xBF, +- +- 0xC3, 0x6B, +- 0xCB, 0x6B, +- 0x00, 0x88, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x4B, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x29, 0x9F, +- 0x00, 0xE0, +- 0x49, 0x04, +- +- 0x90, 0xE2, +- 0x51, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x49, 0x41, 0xC0, 0xEC, +- 0x39, 0x57, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0x51, 0x41, 0xC0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x58, 0x80, 0x15, 0xEA, +- 0x08, 0x04, +- 0x10, 0x04, +- +- 0x51, 0x49, 0xC0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x4A, 0xBF, +- 0x27, 0x4A, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x52, 0xBF, +- 0x1E, 0x49, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x26, 0x51, 0x60, 0xEA, +- +- 0x32, 0x40, 0x48, 0xBD, +- 0x22, 0x40, 0x50, 0xBD, +- +- 0x12, 0x41, 0x49, 0xBD, +- 0x3A, 0x41, 0x51, 0xBD, +- +- 0xBF, 0x2F, 0x26, 0xBD, +- 0x00, 0xE0, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x4E, 0x31, 0x4E, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x56, 0x31, 0x56, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x4F, 0x39, 0x4F, 0xBF, +- 0x57, 0x39, 0x57, 0xBF, +- +- 0x4A, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x42, 0x73, 0xF8, 0xEC, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0xA5, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x4B, 0x4B, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x26, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x53, 0x53, 0x2D, 0xDF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xB8, 0x38, 0x33, 0xBF, +- 0x00, 0xE0, +- 0x59, 0xE3, +- +- 0x1E, 0x12, 0x41, 0xE9, +- 0x1A, 0x22, 0x41, 0xE9, +- +- 0x2B, 0x40, 0x3D, 0xE9, +- 0x3F, 0x4B, 0xA0, 0xE8, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x53, 0xA0, 0xE8, +- +- 0x48, 0x70, 0xF8, 0xEC, +- 0x2B, 0x48, 0x3C, 0xE9, +- +- 0x1F, 0x27, 0xBC, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x18, 0x3A, 0x41, 0xE9, +- 0x1D, 0x32, 0x41, 0xE9, +- +- 0x2A, 0x40, 0x20, 0xE9, +- 0x56, 0x3D, 0x56, 0xDF, +- +- 0x46, 0x37, 0x46, 0xDF, +- 0x4E, 0x3F, 0x4E, 0xDF, +- +- 0x16, 0x30, 0x20, 0xE9, +- 0x4F, 0x3F, 0x4F, 0xDF, +- +- 0x32, 0x32, 0x2D, 0xDF, +- 0x22, 0x22, 0x2D, 0xDF, +- +- 0x12, 0x12, 0x2D, 0xDF, +- 0x3A, 0x3A, 0x2D, 0xDF, +- +- 0x47, 0x37, 0x47, 0xDF, +- 0x57, 0x3D, 0x57, 0xDF, +- +- 0x3D, 0xCF, 0x74, 0xC0, +- 0x37, 0xCF, 0x74, 0xC4, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x34, 0x80, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3C, 0x3D, 0x20, 0xE9, +- +- 0x0A, 0x44, 0x4C, 0xB0, +- 0x02, 0x44, 0x54, 0xB0, +- +- 0x2A, 0x44, 0x4C, 0xB2, +- 0x1A, 0x44, 0x54, 0xB2, +- +- 0x1D, 0x80, 0x3A, 0xEA, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x3D, 0xCF, 0x74, 0xC2, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x32, 0x31, 0x5F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x33, 0x39, 0x5F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x2A, 0x44, 0x4C, 0xB4, +- 0x1A, 0x44, 0x54, 0xB4, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x38, 0x3D, 0x20, 0xE9, +- +- 0x88, 0x73, 0x5E, 0xE9, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x2A, 0x46, 0x4E, 0xBF, +- 0x1A, 0x46, 0x56, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3E, 0x30, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3F, 0x38, 0x4F, 0xE9, +- +- 0x0A, 0x47, 0x4F, 0xBF, +- 0x02, 0x47, 0x57, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3A, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3B, 0x39, 0x4F, 0xE9, +- +- 0x2A, 0x43, 0x4B, 0xBF, +- 0x1A, 0x43, 0x53, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x36, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x37, 0x39, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x37, 0x48, 0x50, 0xBD, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8B, 0x3E, 0x20, 0xE9, +- +- 0x82, 0x30, 0x57, 0xE9, +- 0x87, 0x77, 0x57, 0xE9, +- +- 0x83, 0x38, 0x57, 0xE9, +- 0x35, 0x49, 0x51, 0xBD, +- +- 0x84, 0x31, 0x5E, 0xE9, +- 0x30, 0x1F, 0x5F, 0xE9, +- +- 0x85, 0x39, 0x5E, 0xE9, +- 0x57, 0x25, 0x20, 0xE9, +- +- 0x2B, 0x48, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x26, 0x77, +- +- 0x24, 0x49, 0x20, 0xE9, +- 0xAF, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x26, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x1C, 0x46, 0xA0, 0xE8, +- 0x23, 0x4E, 0xA0, 0xE8, +- +- 0x2B, 0x56, 0xA0, 0xE8, +- 0x1D, 0x47, 0xA0, 0xE8, +- +- 0x24, 0x4F, 0xA0, 0xE8, +- 0x2C, 0x57, 0xA0, 0xE8, +- +- 0x1C, 0x00, +- 0x23, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x1D, 0x00, +- 0x24, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x1C, 0x65, +- 0x23, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x1D, 0x65, +- 0x24, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x1C, 0x23, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x1D, 0x24, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x1C, 0x2B, 0xDE, 0xE8, +- 0x23, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x1C, 0xBD, +- 0x3B, 0xD7, 0x23, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x4F, 0x80, 0x4F, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0xD6, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x4E, 0x33, 0x4E, 0xCF, +- 0x57, 0x3B, 0x57, 0xCF, +- +- 0x9D, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_tgza[] = { +- +- 0x00, 0x88, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x22, 0x40, 0x48, 0xBF, +- 0x2A, 0x40, 0x50, 0xBF, +- +- 0x32, 0x41, 0x49, 0xBF, +- 0x3A, 0x41, 0x51, 0xBF, +- +- 0xC3, 0x6B, +- 0xCB, 0x6B, +- 0x00, 0x88, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x4B, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x29, 0x9F, +- 0x00, 0xE0, +- 0x49, 0x04, +- +- 0x90, 0xE2, +- 0x51, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x49, 0x41, 0xC0, 0xEC, +- 0x39, 0x57, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0x51, 0x41, 0xC0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x5C, 0x80, 0x15, 0xEA, +- 0x08, 0x04, +- 0x10, 0x04, +- +- 0x51, 0x49, 0xC0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x4A, 0xBF, +- 0x27, 0x4A, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x52, 0xBF, +- 0x1E, 0x49, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x26, 0x51, 0x60, 0xEA, +- +- 0x32, 0x40, 0x48, 0xBD, +- 0x22, 0x40, 0x50, 0xBD, +- +- 0x12, 0x41, 0x49, 0xBD, +- 0x3A, 0x41, 0x51, 0xBD, +- +- 0xBF, 0x2F, 0x26, 0xBD, +- 0x00, 0xE0, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x4E, 0x31, 0x4E, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x56, 0x31, 0x56, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x4F, 0x39, 0x4F, 0xBF, +- 0x57, 0x39, 0x57, 0xBF, +- +- 0x4E, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x42, 0x73, 0xF8, 0xEC, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0xA5, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x4B, 0x4B, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x26, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x53, 0x53, 0x2D, 0xDF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xB8, 0x38, 0x33, 0xBF, +- 0x00, 0xE0, +- 0x59, 0xE3, +- +- 0x1E, 0x12, 0x41, 0xE9, +- 0x1A, 0x22, 0x41, 0xE9, +- +- 0x2B, 0x40, 0x3D, 0xE9, +- 0x3F, 0x4B, 0xA0, 0xE8, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x53, 0xA0, 0xE8, +- +- 0x48, 0x70, 0xF8, 0xEC, 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0x4B, 0xBF, +- 0x1A, 0x43, 0x53, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x9D, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x9E, 0x39, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x37, 0x48, 0x50, 0xBD, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8B, 0x3E, 0x20, 0xE9, +- +- 0x82, 0x30, 0x57, 0xE9, +- 0x87, 0x77, 0x57, 0xE9, +- +- 0x83, 0x38, 0x57, 0xE9, +- 0x35, 0x49, 0x51, 0xBD, +- +- 0x84, 0x31, 0x5E, 0xE9, +- 0x30, 0x1F, 0x5F, 0xE9, +- +- 0x85, 0x39, 0x5E, 0xE9, +- 0x57, 0x25, 0x20, 0xE9, +- +- 0x2B, 0x48, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x26, 0x77, +- +- 0x24, 0x49, 0x20, 0xE9, +- 0xAB, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x26, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x1C, 0x46, 0xA0, 0xE8, +- 0x23, 0x4E, 0xA0, 0xE8, +- +- 0x2B, 0x56, 0xA0, 0xE8, +- 0x1D, 0x47, 0xA0, 0xE8, +- +- 0x24, 0x4F, 0xA0, 0xE8, +- 0x2C, 0x57, 0xA0, 0xE8, +- +- 0x1C, 0x00, +- 0x23, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x1D, 0x00, +- 0x24, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x1C, 0x65, +- 0x23, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x1D, 0x65, +- 0x24, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x1C, 0x23, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x1D, 0x24, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x1C, 0x2B, 0xDE, 0xE8, +- 0x23, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x1C, 0xBD, +- 0x3B, 0xD7, 0x23, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x4F, 0x80, 0x4F, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0xD3, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x4E, 0x33, 0x4E, 0xCF, +- 0x57, 0x3B, 0x57, 0xCF, +- +- 0x99, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_tgzaf[] = { +- +- 0x00, 0x88, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x22, 0x40, 0x48, 0xBF, +- 0x2A, 0x40, 0x50, 0xBF, +- +- 0x32, 0x41, 0x49, 0xBF, +- 0x3A, 0x41, 0x51, 0xBF, +- +- 0xC3, 0x6B, +- 0xCB, 0x6B, +- 0x00, 0x88, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x4B, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x29, 0x9F, +- 0x00, 0xE0, +- 0x49, 0x04, +- +- 0x90, 0xE2, +- 0x51, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x49, 0x41, 0xC0, 0xEC, +- 0x39, 0x57, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0x51, 0x41, 0xC0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x61, 0x80, 0x15, 0xEA, +- 0x08, 0x04, +- 0x10, 0x04, +- +- 0x51, 0x49, 0xC0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x4A, 0xBF, +- 0x27, 0x4A, 0xA0, 0xE8, +- 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0x44, 0x54, 0xB0, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x34, 0x37, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3C, 0x3D, 0x20, 0xE9, +- +- 0x2A, 0x44, 0x4C, 0xB2, +- 0x1A, 0x44, 0x54, 0xB2, +- +- 0x26, 0x80, 0x3A, 0xEA, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x88, 0x73, 0x5E, 0xE9, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x3D, 0xCF, 0x74, 0xC2, +- 0x27, 0xCF, 0x74, 0xC6, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x32, 0x31, 0x5F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x33, 0x39, 0x5F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x9C, 0x27, 0x20, 0xE9, +- +- 0x0A, 0x44, 0x4C, 0xB4, +- 0x02, 0x44, 0x54, 0xB4, +- +- 0x2A, 0x44, 0x4C, 0xB6, +- 0x1A, 0x44, 0x54, 0xB6, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x38, 0x3D, 0x20, 0xE9, +- +- 0x0A, 0x20, +- 0x02, 0x20, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x3D, 0xCF, 0x75, 0xC6, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x3E, 0x30, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x3F, 0x38, 0x4F, 0xE9, +- +- 0x0A, 0x45, 0x4D, 0xB6, +- 0x02, 0x45, 0x55, 0xB6, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3A, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3B, 0x39, 0x4F, 0xE9, +- +- 0x31, 0x3D, 0x20, 0xE9, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x2A, 0x46, 0x4E, 0xBF, +- 0x1A, 0x46, 0x56, 0xBF, +- +- 0x0A, 0x47, 0x4F, 0xBF, +- 0x02, 0x47, 0x57, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x36, 0x30, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x37, 0x38, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x9D, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x9E, 0x39, 0x4F, 0xE9, +- +- 0x2A, 0x43, 0x4B, 0xBF, +- 0x1A, 0x43, 0x53, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x35, 0x30, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x39, 0x38, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x37, 0x48, 0x50, 0xBD, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8B, 0x3E, 0x20, 0xE9, +- +- 0x82, 0x30, 0x57, 0xE9, +- 0x87, 0x77, 0x57, 0xE9, +- +- 0x83, 0x38, 0x57, 0xE9, +- 0x35, 0x49, 0x51, 0xBD, +- +- 0x84, 0x31, 0x5E, 0xE9, +- 0x30, 0x1F, 0x5F, 0xE9, +- +- 0x85, 0x39, 0x5E, 0xE9, +- 0x57, 0x25, 0x20, 0xE9, +- +- 0x2B, 0x48, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x26, 0x77, +- +- 0x24, 0x49, 0x20, 0xE9, +- 0xA6, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x26, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x1C, 0x46, 0xA0, 0xE8, +- 0x23, 0x4E, 0xA0, 0xE8, +- +- 0x2B, 0x56, 0xA0, 0xE8, +- 0x1D, 0x47, 0xA0, 0xE8, +- +- 0x24, 0x4F, 0xA0, 0xE8, +- 0x2C, 0x57, 0xA0, 0xE8, +- +- 0x1C, 0x00, +- 0x23, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x1D, 0x00, +- 0x24, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x1C, 0x65, +- 0x23, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x1D, 0x65, +- 0x24, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x1C, 0x23, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x1D, 0x24, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x1C, 0x2B, 0xDE, 0xE8, +- 0x23, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x1C, 0xBD, +- 0x3B, 0xD7, 0x23, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x4F, 0x80, 0x4F, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0xCD, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x4E, 0x33, 0x4E, 0xCF, +- 0x57, 0x3B, 0x57, 0xCF, +- +- 0x94, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_tgzf[] = { +- +- 0x00, 0x88, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x22, 0x40, 0x48, 0xBF, +- 0x2A, 0x40, 0x50, 0xBF, +- +- 0x32, 0x41, 0x49, 0xBF, +- 0x3A, 0x41, 0x51, 0xBF, +- +- 0xC3, 0x6B, +- 0xCB, 0x6B, +- 0x00, 0x88, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x4B, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x29, 0x9F, +- 0x00, 0xE0, +- 0x49, 0x04, +- +- 0x90, 0xE2, +- 0x51, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x49, 0x41, 0xC0, 0xEC, +- 0x39, 0x57, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0x51, 0x41, 0xC0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x5D, 0x80, 0x15, 0xEA, +- 0x08, 0x04, +- 0x10, 0x04, +- +- 0x51, 0x49, 0xC0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x4A, 0xBF, +- 0x27, 0x4A, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x52, 0xBF, +- 0x1E, 0x49, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x26, 0x51, 0x60, 0xEA, +- +- 0x32, 0x40, 0x48, 0xBD, +- 0x22, 0x40, 0x50, 0xBD, +- +- 0x12, 0x41, 0x49, 0xBD, +- 0x3A, 0x41, 0x51, 0xBD, +- +- 0xBF, 0x2F, 0x26, 0xBD, +- 0x00, 0xE0, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x4E, 0x31, 0x4E, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x56, 0x31, 0x56, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x4F, 0x39, 0x4F, 0xBF, +- 0x57, 0x39, 0x57, 0xBF, +- +- 0x4F, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x42, 0x73, 0xF8, 0xEC, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0xA5, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x4B, 0x4B, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x26, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x53, 0x53, 0x2D, 0xDF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xB8, 0x38, 0x33, 0xBF, +- 0x00, 0xE0, +- 0x59, 0xE3, +- +- 0x1E, 0x12, 0x41, 0xE9, +- 0x1A, 0x22, 0x41, 0xE9, +- +- 0x2B, 0x40, 0x3D, 0xE9, +- 0x3F, 0x4B, 0xA0, 0xE8, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x53, 0xA0, 0xE8, +- +- 0x48, 0x70, 0xF8, 0xEC, +- 0x2B, 0x48, 0x3C, 0xE9, +- +- 0x1F, 0x27, 0xBC, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x18, 0x3A, 0x41, 0xE9, +- 0x1D, 0x32, 0x41, 0xE9, +- +- 0x2A, 0x40, 0x20, 0xE9, +- 0x56, 0x3D, 0x56, 0xDF, +- +- 0x46, 0x37, 0x46, 0xDF, +- 0x4E, 0x3F, 0x4E, 0xDF, +- +- 0x16, 0x30, 0x20, 0xE9, +- 0x4F, 0x3F, 0x4F, 0xDF, +- +- 0x32, 0x32, 0x2D, 0xDF, +- 0x22, 0x22, 0x2D, 0xDF, +- +- 0x12, 0x12, 0x2D, 0xDF, +- 0x3A, 0x3A, 0x2D, 0xDF, +- +- 0x47, 0x37, 0x47, 0xDF, +- 0x57, 0x3D, 0x57, 0xDF, +- +- 0x3D, 0xCF, 0x74, 0xC0, +- 0x37, 0xCF, 0x74, 0xC4, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x34, 0x80, 0x20, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x88, 0x73, 0x5E, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x27, 0xCF, 0x75, 0xC6, +- 0x3C, 0x3D, 0x20, 0xE9, +- +- 0x0A, 0x44, 0x4C, 0xB0, +- 0x02, 0x44, 0x54, 0xB0, +- +- 0x2A, 0x44, 0x4C, 0xB2, +- 0x1A, 0x44, 0x54, 0xB2, +- +- 0x20, 0x80, 0x3A, 0xEA, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x3D, 0xCF, 0x74, 0xC2, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x32, 0x31, 0x5F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x33, 0x39, 0x5F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x31, 0x27, 0x20, 0xE9, +- +- 0x0A, 0x44, 0x4C, 0xB4, +- 0x02, 0x44, 0x54, 0xB4, +- +- 0x2A, 0x45, 0x4D, 0xB6, +- 0x1A, 0x45, 0x55, 0xB6, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x38, 0x3D, 0x20, 0xE9, +- +- 0x0A, 0x20, +- 0x02, 0x20, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x0A, 0x47, 0x4F, 0xBF, +- 0x02, 0x47, 0x57, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x3E, 0x30, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x3F, 0x38, 0x4F, 0xE9, +- +- 0x2A, 0x46, 0x4E, 0xBF, +- 0x1A, 0x46, 0x56, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3A, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3B, 0x39, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x36, 0x30, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x37, 0x38, 0x4F, 0xE9, +- +- 0x2A, 0x43, 0x4B, 0xBF, +- 0x1A, 0x43, 0x53, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x35, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x39, 0x39, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x37, 0x48, 0x50, 0xBD, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8B, 0x3E, 0x20, 0xE9, +- +- 0x82, 0x30, 0x57, 0xE9, +- 0x87, 0x77, 0x57, 0xE9, +- +- 0x83, 0x38, 0x57, 0xE9, +- 0x35, 0x49, 0x51, 0xBD, +- +- 0x84, 0x31, 0x5E, 0xE9, +- 0x30, 0x1F, 0x5F, 0xE9, +- +- 0x85, 0x39, 0x5E, 0xE9, +- 0x57, 0x25, 0x20, 0xE9, +- +- 0x2B, 0x48, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x26, 0x77, +- +- 0x24, 0x49, 0x20, 0xE9, +- 0xAA, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x26, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x1C, 0x46, 0xA0, 0xE8, +- 0x23, 0x4E, 0xA0, 0xE8, +- +- 0x2B, 0x56, 0xA0, 0xE8, +- 0x1D, 0x47, 0xA0, 0xE8, +- +- 0x24, 0x4F, 0xA0, 0xE8, +- 0x2C, 0x57, 0xA0, 0xE8, +- +- 0x1C, 0x00, +- 0x23, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x1D, 0x00, +- 0x24, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x1C, 0x65, +- 0x23, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x1D, 0x65, +- 0x24, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x1C, 0x23, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x1D, 0x24, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x1C, 0x2B, 0xDE, 0xE8, +- 0x23, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x1C, 0xBD, +- 0x3B, 0xD7, 0x23, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x4F, 0x80, 0x4F, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0xD3, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x4E, 0x33, 0x4E, 0xCF, +- 0x57, 0x3B, 0x57, 0xCF, +- +- 0x98, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_tgzs[] = { +- +- 0x00, 0x88, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x22, 0x40, 0x48, 0xBF, +- 0x2A, 0x40, 0x50, 0xBF, +- +- 0x32, 0x41, 0x49, 0xBF, +- 0x3A, 0x41, 0x51, 0xBF, +- +- 0xC3, 0x6B, +- 0xCB, 0x6B, +- 0x00, 0x88, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x4B, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x29, 0x9F, +- 0x00, 0xE0, +- 0x49, 0x04, +- +- 0x90, 0xE2, +- 0x51, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x49, 0x41, 0xC0, 0xEC, +- 0x39, 0x57, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0x51, 0x41, 0xC0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x65, 0x80, 0x15, 0xEA, +- 0x08, 0x04, +- 0x10, 0x04, +- +- 0x51, 0x49, 0xC0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x4A, 0xBF, +- 0x27, 0x4A, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x52, 0xBF, +- 0x1E, 0x49, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x26, 0x51, 0x60, 0xEA, +- +- 0x32, 0x40, 0x48, 0xBD, +- 0x22, 0x40, 0x50, 0xBD, +- +- 0x12, 0x41, 0x49, 0xBD, +- 0x3A, 0x41, 0x51, 0xBD, +- +- 0xBF, 0x2F, 0x26, 0xBD, +- 0x00, 0xE0, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x4E, 0x31, 0x4E, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x56, 0x31, 0x56, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x4F, 0x39, 0x4F, 0xBF, +- 0x57, 0x39, 0x57, 0xBF, +- +- 0x57, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x42, 0x73, 0xF8, 0xEC, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0xA5, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x4B, 0x4B, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x26, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x53, 0x53, 0x2D, 0xDF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xB8, 0x38, 0x33, 0xBF, +- 0x00, 0xE0, +- 0x59, 0xE3, +- +- 0x1E, 0x12, 0x41, 0xE9, +- 0x1A, 0x22, 0x41, 0xE9, +- +- 0x2B, 0x40, 0x3D, 0xE9, +- 0x3F, 0x4B, 0xA0, 0xE8, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x53, 0xA0, 0xE8, +- +- 0x48, 0x70, 0xF8, 0xEC, +- 0x2B, 0x48, 0x3C, 0xE9, +- +- 0x1F, 0x27, 0xBC, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x18, 0x3A, 0x41, 0xE9, +- 0x1D, 0x32, 0x41, 0xE9, +- +- 0x2A, 0x40, 0x20, 0xE9, +- 0x56, 0x3D, 0x56, 0xDF, +- +- 0x46, 0x37, 0x46, 0xDF, +- 0x4E, 0x3F, 0x4E, 0xDF, +- +- 0x16, 0x30, 0x20, 0xE9, +- 0x4F, 0x3F, 0x4F, 0xDF, +- +- 0x47, 0x37, 0x47, 0xDF, +- 0x57, 0x3D, 0x57, 0xDF, +- +- 0x32, 0x32, 0x2D, 0xDF, +- 0x22, 0x22, 0x2D, 0xDF, +- +- 0x12, 0x12, 0x2D, 0xDF, +- 0x3A, 0x3A, 0x2D, 0xDF, +- +- 0x27, 0xCF, 0x74, 0xC2, +- 0x37, 0xCF, 0x74, 0xC4, +- +- 0x0A, 0x44, 0x4C, 0xB0, +- 0x02, 0x44, 0x54, 0xB0, +- +- 0x3D, 0xCF, 0x74, 0xC0, +- 0x34, 0x37, 0x20, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x38, 0x27, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3C, 0x3D, 0x20, 0xE9, +- +- 0x2A, 0x44, 0x4C, 0xB2, +- 0x1A, 0x44, 0x54, 0xB2, +- +- 0x29, 0x80, 0x3A, 0xEA, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x27, 0xCF, 0x75, 0xC0, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x32, 0x31, 0x5F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x33, 0x39, 0x5F, 0xE9, +- +- 0x3D, 0xCF, 0x75, 0xC2, +- 0x37, 0xCF, 0x75, 0xC4, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0xA6, 0x27, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA3, 0x3D, 0x20, 0xE9, +- +- 0x2A, 0x44, 0x4C, 0xB4, +- 0x1A, 0x44, 0x54, 0xB4, +- +- 0x0A, 0x45, 0x4D, 0xB0, +- 0x02, 0x45, 0x55, 0xB0, +- +- 0x88, 0x73, 0x5E, 0xE9, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0xA0, 0x37, 0x20, 0xE9, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3E, 0x30, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3F, 0x38, 0x4F, 0xE9, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x3A, 0x31, 0x4F, 0xE9, +- +- 0x2A, 0x45, 0x4D, 0xB2, +- 0x1A, 0x45, 0x55, 0xB2, +- +- 0x0A, 0x45, 0x4D, 0xB4, +- 0x02, 0x45, 0x55, 0xB4, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x3B, 0x39, 0x4F, 0xE9, +- +- 0x0A, 0x20, +- 0x02, 0x20, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x2A, 0x46, 0x4E, 0xBF, +- 0x1A, 0x46, 0x56, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x36, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x37, 0x39, 0x4F, 0xE9, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0xA7, 0x30, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0xA8, 0x38, 0x4F, 0xE9, +- +- 0x0A, 0x47, 0x4F, 0xBF, +- 0x02, 0x47, 0x57, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0xA4, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA5, 0x39, 0x4F, 0xE9, +- +- 0x2A, 0x43, 0x4B, 0xBF, +- 0x1A, 0x43, 0x53, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0xA1, 0x30, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0xA2, 0x38, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x37, 0x48, 0x50, 0xBD, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8B, 0x3E, 0x20, 0xE9, +- +- 0x82, 0x30, 0x57, 0xE9, +- 0x87, 0x77, 0x57, 0xE9, +- +- 0x83, 0x38, 0x57, 0xE9, +- 0x35, 0x49, 0x51, 0xBD, +- +- 0x84, 0x31, 0x5E, 0xE9, +- 0x30, 0x1F, 0x5F, 0xE9, +- +- 0x85, 0x39, 0x5E, 0xE9, +- 0x57, 0x25, 0x20, 0xE9, +- +- 0x2B, 0x48, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x26, 0x77, +- +- 0x24, 0x49, 0x20, 0xE9, +- 0xA2, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x26, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x1C, 0x46, 0xA0, 0xE8, +- 0x23, 0x4E, 0xA0, 0xE8, +- +- 0x2B, 0x56, 0xA0, 0xE8, +- 0x1D, 0x47, 0xA0, 0xE8, +- +- 0x24, 0x4F, 0xA0, 0xE8, +- 0x2C, 0x57, 0xA0, 0xE8, +- +- 0x1C, 0x00, +- 0x23, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x1D, 0x00, +- 0x24, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x1C, 0x65, +- 0x23, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x1D, 0x65, +- 0x24, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x1C, 0x23, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x1D, 0x24, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x1C, 0x2B, 0xDE, 0xE8, +- 0x23, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x1C, 0xBD, +- 0x3B, 0xD7, 0x23, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x4F, 0x80, 0x4F, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0xCA, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x4E, 0x33, 0x4E, 0xCF, +- 0x57, 0x3B, 0x57, 0xCF, +- +- 0x90, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_tgzsa[] = { +- +- 0x00, 0x88, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x22, 0x40, 0x48, 0xBF, +- 0x2A, 0x40, 0x50, 0xBF, +- +- 0x32, 0x41, 0x49, 0xBF, +- 0x3A, 0x41, 0x51, 0xBF, +- +- 0xC3, 0x6B, +- 0xCB, 0x6B, +- 0x00, 0x88, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x4B, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x29, 0x9F, +- 0x00, 0xE0, +- 0x49, 0x04, +- +- 0x90, 0xE2, +- 0x51, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x49, 0x41, 0xC0, 0xEC, +- 0x39, 0x57, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0x51, 0x41, 0xC0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x6A, 0x80, 0x15, 0xEA, +- 0x08, 0x04, +- 0x10, 0x04, +- +- 0x51, 0x49, 0xC0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x4A, 0xBF, +- 0x27, 0x4A, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x52, 0xBF, +- 0x1E, 0x49, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x26, 0x51, 0x60, 0xEA, +- +- 0x32, 0x40, 0x48, 0xBD, +- 0x22, 0x40, 0x50, 0xBD, +- +- 0x12, 0x41, 0x49, 0xBD, +- 0x3A, 0x41, 0x51, 0xBD, +- +- 0xBF, 0x2F, 0x26, 0xBD, +- 0x00, 0xE0, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x4E, 0x31, 0x4E, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x56, 0x31, 0x56, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x4F, 0x39, 0x4F, 0xBF, +- 0x57, 0x39, 0x57, 0xBF, +- +- 0x5C, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x42, 0x73, 0xF8, 0xEC, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0xA5, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x4B, 0x4B, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x26, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x53, 0x53, 0x2D, 0xDF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xB8, 0x38, 0x33, 0xBF, +- 0x00, 0xE0, +- 0x59, 0xE3, +- +- 0x1E, 0x12, 0x41, 0xE9, +- 0x1A, 0x22, 0x41, 0xE9, +- +- 0x2B, 0x40, 0x3D, 0xE9, +- 0x3F, 0x4B, 0xA0, 0xE8, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x53, 0xA0, 0xE8, +- +- 0x48, 0x70, 0xF8, 0xEC, +- 0x2B, 0x48, 0x3C, 0xE9, +- +- 0x1F, 0x27, 0xBC, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x18, 0x3A, 0x41, 0xE9, +- 0x1D, 0x32, 0x41, 0xE9, +- +- 0x2A, 0x40, 0x20, 0xE9, +- 0x56, 0x3D, 0x56, 0xDF, +- +- 0x46, 0x37, 0x46, 0xDF, +- 0x4E, 0x3F, 0x4E, 0xDF, +- +- 0x16, 0x30, 0x20, 0xE9, +- 0x4F, 0x3F, 0x4F, 0xDF, +- +- 0x47, 0x37, 0x47, 0xDF, +- 0x57, 0x3D, 0x57, 0xDF, +- +- 0x32, 0x32, 0x2D, 0xDF, +- 0x22, 0x22, 0x2D, 0xDF, +- +- 0x12, 0x12, 0x2D, 0xDF, +- 0x3A, 0x3A, 0x2D, 0xDF, +- +- 0x27, 0xCF, 0x74, 0xC2, +- 0x37, 0xCF, 0x74, 0xC4, +- +- 0x0A, 0x44, 0x4C, 0xB0, +- 0x02, 0x44, 0x54, 0xB0, +- +- 0x3D, 0xCF, 0x74, 0xC0, +- 0x34, 0x37, 0x20, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x38, 0x27, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3C, 0x3D, 0x20, 0xE9, +- +- 0x2A, 0x44, 0x4C, 0xB2, +- 0x1A, 0x44, 0x54, 0xB2, +- +- 0x2E, 0x80, 0x3A, 0xEA, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x27, 0xCF, 0x75, 0xC0, +- 0x2A, 0x20, +- 0x1A, 0x20, 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0x20, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8B, 0x3E, 0x20, 0xE9, +- +- 0x82, 0x30, 0x57, 0xE9, +- 0x87, 0x77, 0x57, 0xE9, +- +- 0x83, 0x38, 0x57, 0xE9, +- 0x35, 0x49, 0x51, 0xBD, +- +- 0x84, 0x31, 0x5E, 0xE9, +- 0x30, 0x1F, 0x5F, 0xE9, +- +- 0x85, 0x39, 0x5E, 0xE9, +- 0x57, 0x25, 0x20, 0xE9, +- +- 0x2B, 0x48, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x26, 0x77, +- +- 0x24, 0x49, 0x20, 0xE9, +- 0x9D, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x26, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x1C, 0x46, 0xA0, 0xE8, +- 0x23, 0x4E, 0xA0, 0xE8, +- +- 0x2B, 0x56, 0xA0, 0xE8, +- 0x1D, 0x47, 0xA0, 0xE8, +- +- 0x24, 0x4F, 0xA0, 0xE8, +- 0x2C, 0x57, 0xA0, 0xE8, +- +- 0x1C, 0x00, +- 0x23, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x1D, 0x00, +- 0x24, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x1C, 0x65, +- 0x23, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x1D, 0x65, +- 0x24, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x1C, 0x23, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x1D, 0x24, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x1C, 0x2B, 0xDE, 0xE8, +- 0x23, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x1C, 0xBD, +- 0x3B, 0xD7, 0x23, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x4F, 0x80, 0x4F, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0xC5, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x4E, 0x33, 0x4E, 0xCF, +- 0x57, 0x3B, 0x57, 0xCF, +- +- 0x8B, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_tgzsaf[] = { +- +- 0x00, 0x88, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x22, 0x40, 0x48, 0xBF, +- 0x2A, 0x40, 0x50, 0xBF, +- +- 0x32, 0x41, 0x49, 0xBF, +- 0x3A, 0x41, 0x51, 0xBF, +- +- 0xC3, 0x6B, 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+- +- 0x27, 0xCF, 0x75, 0xC0, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x32, 0x31, 0x5F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x33, 0x39, 0x5F, 0xE9, +- +- 0x3D, 0xCF, 0x75, 0xC2, +- 0x37, 0xCF, 0x75, 0xC4, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0xA6, 0x27, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA3, 0x3D, 0x20, 0xE9, +- +- 0x2A, 0x44, 0x4C, 0xB4, +- 0x1A, 0x44, 0x54, 0xB4, +- +- 0x0A, 0x45, 0x4D, 0xB0, +- 0x02, 0x45, 0x55, 0xB0, +- +- 0x88, 0x73, 0x5E, 0xE9, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0xA0, 0x37, 0x20, 0xE9, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3E, 0x30, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3F, 0x38, 0x4F, 0xE9, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x3A, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x3B, 0x39, 0x4F, 0xE9, +- +- 0x2A, 0x45, 0x4D, 0xB2, +- 0x1A, 0x45, 0x55, 0xB2, +- +- 0x0A, 0x45, 0x4D, 0xB4, +- 0x02, 0x45, 0x55, 0xB4, +- +- 0x27, 0xCF, 0x74, 0xC6, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0xA7, 0x30, 0x4F, 0xE9, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x9C, 0x27, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA8, 0x38, 0x4F, 0xE9, +- +- 0x2A, 0x44, 0x4C, 0xB6, +- 0x1A, 0x44, 0x54, 0xB6, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x36, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x37, 0x39, 0x4F, 0xE9, +- +- 0x0A, 0x45, 0x4D, 0xB6, +- 0x02, 0x45, 0x55, 0xB6, +- +- 0x3D, 0xCF, 0x75, 0xC6, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x2A, 0x46, 0x4E, 0xBF, +- 0x1A, 0x46, 0x56, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0xA4, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA5, 0x39, 0x4F, 0xE9, +- +- 0x31, 0x3D, 0x20, 0xE9, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x0A, 0x47, 0x4F, 0xBF, +- 0x02, 0x47, 0x57, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0xA1, 0x30, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0xA2, 0x38, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x9D, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x9E, 0x39, 0x4F, 0xE9, +- +- 0x2A, 0x43, 0x4B, 0xBF, +- 0x1A, 0x43, 0x53, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x35, 0x30, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x39, 0x38, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x37, 0x48, 0x50, 0xBD, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8B, 0x3E, 0x20, 0xE9, +- +- 0x82, 0x30, 0x57, 0xE9, +- 0x87, 0x77, 0x57, 0xE9, +- +- 0x83, 0x38, 0x57, 0xE9, +- 0x35, 0x49, 0x51, 0xBD, +- +- 0x84, 0x31, 0x5E, 0xE9, +- 0x30, 0x1F, 0x5F, 0xE9, +- +- 0x85, 0x39, 0x5E, 0xE9, +- 0x57, 0x25, 0x20, 0xE9, +- +- 0x2B, 0x48, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x26, 0x77, +- +- 0x24, 0x49, 0x20, 0xE9, +- 0x99, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x26, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x1C, 0x46, 0xA0, 0xE8, +- 0x23, 0x4E, 0xA0, 0xE8, +- +- 0x2B, 0x56, 0xA0, 0xE8, +- 0x1D, 0x47, 0xA0, 0xE8, +- +- 0x24, 0x4F, 0xA0, 0xE8, +- 0x2C, 0x57, 0xA0, 0xE8, +- +- 0x1C, 0x00, +- 0x23, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x1D, 0x00, +- 0x24, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x1C, 0x65, +- 0x23, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x1D, 0x65, +- 0x24, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x1C, 0x23, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x1D, 0x24, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x1C, 0x2B, 0xDE, 0xE8, +- 0x23, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x1C, 0xBD, +- 0x3B, 0xD7, 0x23, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x4F, 0x80, 0x4F, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0xC1, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x4E, 0x33, 0x4E, 0xCF, +- 0x57, 0x3B, 0x57, 0xCF, +- +- 0x87, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +- +-static unsigned char warp_g400_tgzsf[] = { +- +- 0x00, 0x88, 0x98, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +- 0xFF, 0x80, 0xC0, 0xE9, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x22, 0x40, 0x48, 0xBF, +- 0x2A, 0x40, 0x50, 0xBF, +- +- 0x32, 0x41, 0x49, 0xBF, +- 0x3A, 0x41, 0x51, 0xBF, +- +- 0xC3, 0x6B, +- 0xCB, 0x6B, +- 0x00, 0x88, 0x98, 0xE9, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x96, 0xE2, +- 0x41, 0x04, +- +- 0x7B, 0x43, 0xA0, 0xE8, +- 0x73, 0x4B, 0xA0, 0xE8, +- +- 0xAD, 0xEE, 0x29, 0x9F, +- 0x00, 0xE0, +- 0x49, 0x04, +- +- 0x90, 0xE2, +- 0x51, 0x04, +- 0x31, 0x46, 0xB1, 0xE8, +- +- 0x49, 0x41, 0xC0, 0xEC, +- 0x39, 0x57, 0xB1, 0xE8, +- +- 0x00, 0x04, +- 0x46, 0xE2, +- 0x73, 0x53, 0xA0, 0xE8, +- +- 0x51, 0x41, 0xC0, 0xEC, +- 0x31, 0x00, +- 0x39, 0x00, +- +- 0x6A, 0x80, 0x15, 0xEA, +- 0x08, 0x04, +- 0x10, 0x04, +- +- 0x51, 0x49, 0xC0, 0xEC, +- 0x2F, 0x41, 0x60, 0xEA, +- +- 0x31, 0x20, +- 0x39, 0x20, +- 0x1F, 0x42, 0xA0, 0xE8, +- +- 0x2A, 0x42, 0x4A, 0xBF, +- 0x27, 0x4A, 0xA0, 0xE8, +- +- 0x1A, 0x42, 0x52, 0xBF, +- 0x1E, 0x49, 0x60, 0xEA, +- +- 0x73, 0x7B, 0xC8, 0xEC, +- 0x26, 0x51, 0x60, 0xEA, +- +- 0x32, 0x40, 0x48, 0xBD, +- 0x22, 0x40, 0x50, 0xBD, +- +- 0x12, 0x41, 0x49, 0xBD, +- 0x3A, 0x41, 0x51, 0xBD, +- +- 0xBF, 0x2F, 0x26, 0xBD, +- 0x00, 0xE0, +- 0x7B, 0x72, +- +- 0x32, 0x20, +- 0x22, 0x20, +- 0x12, 0x20, +- 0x3A, 0x20, +- +- 0x46, 0x31, 0x46, 0xBF, +- 0x4E, 0x31, 0x4E, 0xBF, +- +- 0xB3, 0xE2, 0x2D, 0x9F, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x56, 0x31, 0x56, 0xBF, +- 0x47, 0x39, 0x47, 0xBF, +- +- 0x4F, 0x39, 0x4F, 0xBF, +- 0x57, 0x39, 0x57, 0xBF, +- +- 0x5C, 0x80, 0x07, 0xEA, +- 0x24, 0x41, 0x20, 0xE9, +- +- 0x42, 0x73, 0xF8, 0xEC, +- 0x00, 0xE0, +- 0x2D, 0x73, +- +- 0x33, 0x72, +- 0x0C, 0xE3, +- 0xA5, 0x2F, 0x1E, 0xBD, +- +- 0x43, 0x43, 0x2D, 0xDF, +- 0x4B, 0x4B, 0x2D, 0xDF, +- +- 0xAE, 0x1E, 0x26, 0xBD, +- 0x58, 0xE3, +- 0x33, 0x66, +- +- 0x53, 0x53, 0x2D, 0xDF, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0xB8, 0x38, 0x33, 0xBF, +- 0x00, 0xE0, +- 0x59, 0xE3, +- +- 0x1E, 0x12, 0x41, 0xE9, +- 0x1A, 0x22, 0x41, 0xE9, +- +- 0x2B, 0x40, 0x3D, 0xE9, +- 0x3F, 0x4B, 0xA0, 0xE8, +- +- 0x2D, 0x73, +- 0x30, 0x76, +- 0x05, 0x80, 0x3D, 0xEA, +- +- 0x37, 0x43, 0xA0, 0xE8, +- 0x3D, 0x53, 0xA0, 0xE8, +- +- 0x48, 0x70, 0xF8, 0xEC, +- 0x2B, 0x48, 0x3C, 0xE9, +- +- 0x1F, 0x27, 0xBC, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x15, 0xC0, 0x20, 0xE9, +- 0x15, 0xC0, 0x20, 0xE9, +- +- 0x18, 0x3A, 0x41, 0xE9, +- 0x1D, 0x32, 0x41, 0xE9, +- +- 0x2A, 0x40, 0x20, 0xE9, +- 0x56, 0x3D, 0x56, 0xDF, +- +- 0x46, 0x37, 0x46, 0xDF, +- 0x4E, 0x3F, 0x4E, 0xDF, +- +- 0x16, 0x30, 0x20, 0xE9, +- 0x4F, 0x3F, 0x4F, 0xDF, +- +- 0x47, 0x37, 0x47, 0xDF, +- 0x57, 0x3D, 0x57, 0xDF, +- +- 0x32, 0x32, 0x2D, 0xDF, +- 0x22, 0x22, 0x2D, 0xDF, +- +- 0x12, 0x12, 0x2D, 0xDF, +- 0x3A, 0x3A, 0x2D, 0xDF, +- +- 0x27, 0xCF, 0x74, 0xC2, +- 0x37, 0xCF, 0x74, 0xC4, +- +- 0x0A, 0x44, 0x4C, 0xB0, +- 0x02, 0x44, 0x54, 0xB0, +- +- 0x3D, 0xCF, 0x74, 0xC0, +- 0x34, 0x37, 0x20, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x38, 0x27, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3C, 0x3D, 0x20, 0xE9, +- +- 0x2A, 0x44, 0x4C, 0xB2, +- 0x1A, 0x44, 0x54, 0xB2, +- +- 0x2E, 0x80, 0x3A, 0xEA, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x27, 0xCF, 0x75, 0xC0, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x32, 0x31, 0x5F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x33, 0x39, 0x5F, 0xE9, +- +- 0x3D, 0xCF, 0x75, 0xC2, +- 0x37, 0xCF, 0x75, 0xC4, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0xA6, 0x27, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA3, 0x3D, 0x20, 0xE9, +- +- 0x2A, 0x44, 0x4C, 0xB4, +- 0x1A, 0x44, 0x54, 0xB4, +- +- 0x0A, 0x45, 0x4D, 0xB0, +- 0x02, 0x45, 0x55, 0xB0, +- +- 0x88, 0x73, 0x5E, 0xE9, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0xA0, 0x37, 0x20, 0xE9, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x3E, 0x30, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x3F, 0x38, 0x4F, 0xE9, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x3A, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x3B, 0x39, 0x4F, 0xE9, +- +- 0x2A, 0x45, 0x4D, 0xB2, +- 0x1A, 0x45, 0x55, 0xB2, +- +- 0x0A, 0x45, 0x4D, 0xB4, +- 0x02, 0x45, 0x55, 0xB4, +- +- 0x27, 0xCF, 0x75, 0xC6, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0xA7, 0x30, 0x4F, 0xE9, +- 0x0A, 0x20, +- 0x02, 0x20, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x31, 0x27, 0x20, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA8, 0x38, 0x4F, 0xE9, +- +- 0x2A, 0x45, 0x4D, 0xB6, +- 0x1A, 0x45, 0x55, 0xB6, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x36, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x37, 0x39, 0x4F, 0xE9, +- +- 0x00, 0x80, 0x00, 0xE8, +- 0x2A, 0x20, +- 0x1A, 0x20, +- +- 0x2A, 0x46, 0x4E, 0xBF, +- 0x1A, 0x46, 0x56, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0xA4, 0x31, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA5, 0x39, 0x4F, 0xE9, +- +- 0x0A, 0x47, 0x4F, 0xBF, +- 0x02, 0x47, 0x57, 0xBF, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0xA1, 0x30, 0x4F, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0xA2, 0x38, 0x4F, 0xE9, +- +- 0x2A, 0x43, 0x4B, 0xBF, +- 0x1A, 0x43, 0x53, 0xBF, +- +- 0x30, 0x50, 0x2E, 0x9F, +- 0x35, 0x31, 0x4F, 0xE9, +- +- 0x38, 0x21, 0x2C, 0x9F, +- 0x39, 0x39, 0x4F, 0xE9, +- +- 0x31, 0x53, 0x2F, 0x9F, +- 0x80, 0x31, 0x57, 0xE9, +- +- 0x39, 0xE5, 0x2C, 0x9F, +- 0x81, 0x39, 0x57, 0xE9, +- +- 0x37, 0x48, 0x50, 0xBD, +- 0x8A, 0x36, 0x20, 0xE9, +- +- 0x86, 0x76, 0x57, 0xE9, +- 0x8B, 0x3E, 0x20, 0xE9, +- +- 0x82, 0x30, 0x57, 0xE9, +- 0x87, 0x77, 0x57, 0xE9, +- +- 0x83, 0x38, 0x57, 0xE9, +- 0x35, 0x49, 0x51, 0xBD, +- +- 0x84, 0x31, 0x5E, 0xE9, +- 0x30, 0x1F, 0x5F, 0xE9, +- +- 0x85, 0x39, 0x5E, 0xE9, +- 0x57, 0x25, 0x20, 0xE9, +- +- 0x2B, 0x48, 0x20, 0xE9, +- 0x1D, 0x37, 0xE1, 0xEA, +- +- 0x1E, 0x35, 0xE1, 0xEA, +- 0x00, 0xE0, +- 0x26, 0x77, +- +- 0x24, 0x49, 0x20, 0xE9, +- 0x9D, 0xFF, 0x20, 0xEA, +- +- 0x16, 0x26, 0x20, 0xE9, +- 0x57, 0x2E, 0xBF, 0xEA, +- +- 0x1C, 0x46, 0xA0, 0xE8, +- 0x23, 0x4E, 0xA0, 0xE8, +- +- 0x2B, 0x56, 0xA0, 0xE8, +- 0x1D, 0x47, 0xA0, 0xE8, +- +- 0x24, 0x4F, 0xA0, 0xE8, +- 0x2C, 0x57, 0xA0, 0xE8, +- +- 0x1C, 0x00, +- 0x23, 0x00, +- 0x2B, 0x00, +- 0x00, 0xE0, +- +- 0x1D, 0x00, +- 0x24, 0x00, +- 0x2C, 0x00, +- 0x00, 0xE0, +- +- 0x1C, 0x65, +- 0x23, 0x65, +- 0x2B, 0x65, +- 0x00, 0xE0, +- +- 0x1D, 0x65, +- 0x24, 0x65, +- 0x2C, 0x65, +- 0x00, 0xE0, +- +- 0x1C, 0x23, 0x60, 0xEC, +- 0x36, 0xD7, 0x36, 0xAD, +- +- 0x2B, 0x80, 0x60, 0xEC, +- 0x1D, 0x24, 0x60, 0xEC, +- +- 0x3E, 0xD7, 0x3E, 0xAD, +- 0x2C, 0x80, 0x60, 0xEC, +- +- 0x1C, 0x2B, 0xDE, 0xE8, +- 0x23, 0x80, 0xDE, 0xE8, +- +- 0x36, 0x80, 0x36, 0xBD, +- 0x3E, 0x80, 0x3E, 0xBD, +- +- 0x33, 0xD7, 0x1C, 0xBD, +- 0x3B, 0xD7, 0x23, 0xBD, +- +- 0x46, 0x80, 0x46, 0xCF, +- 0x4F, 0x80, 0x4F, 0xCF, +- +- 0x56, 0x33, 0x56, 0xCF, +- 0x47, 0x3B, 0x47, 0xCF, +- +- 0xC5, 0xFF, 0x20, 0xEA, +- 0x00, 0x80, 0x00, 0xE8, +- +- 0x4E, 0x33, 0x4E, 0xCF, +- 0x57, 0x3B, 0x57, 0xCF, +- +- 0x8B, 0xFF, 0x20, 0xEA, +- 0x57, 0xC0, 0xBF, 0xEA, +- +- 0x00, 0x80, 0xA0, 0xE9, +- 0x00, 0x00, 0xD8, 0xEC, +- +-}; +diff --git a/drivers/gpu/drm/mga/mga_warp.c b/drivers/gpu/drm/mga/mga_warp.c +index 651b93c..9aad484 100644 +--- a/drivers/gpu/drm/mga/mga_warp.c ++++ b/drivers/gpu/drm/mga/mga_warp.c +@@ -27,132 +27,108 @@ + * Gareth Hughes <gareth@valinux.com> + */ + ++#include <linux/firmware.h> ++#include <linux/ihex.h> ++#include <linux/platform_device.h> ++ + #include "drmP.h" + #include "drm.h" + #include "mga_drm.h" + #include "mga_drv.h" +-#include "mga_ucode.h" ++ ++#define FIRMWARE_G200 "matrox/g200_warp.fw" ++#define FIRMWARE_G400 "matrox/g400_warp.fw" ++ ++MODULE_FIRMWARE(FIRMWARE_G200); ++MODULE_FIRMWARE(FIRMWARE_G400); + + #define MGA_WARP_CODE_ALIGN 256 /* in bytes */ + +-#define WARP_UCODE_SIZE( which ) \ +- ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) +- +-#define WARP_UCODE_INSTALL( which, where ) \ +-do { \ +- DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\ +- dev_priv->warp_pipe_phys[where] = pcbase; \ +- memcpy( vcbase, which, sizeof(which) ); \ +- pcbase += WARP_UCODE_SIZE( which ); \ +- vcbase += WARP_UCODE_SIZE( which ); \ +-} while (0) +- +-static const unsigned int mga_warp_g400_microcode_size = +- (WARP_UCODE_SIZE(warp_g400_tgz) + +- WARP_UCODE_SIZE(warp_g400_tgza) + +- WARP_UCODE_SIZE(warp_g400_tgzaf) + +- WARP_UCODE_SIZE(warp_g400_tgzf) + +- WARP_UCODE_SIZE(warp_g400_tgzs) + +- WARP_UCODE_SIZE(warp_g400_tgzsa) + +- WARP_UCODE_SIZE(warp_g400_tgzsaf) + +- WARP_UCODE_SIZE(warp_g400_tgzsf) + +- WARP_UCODE_SIZE(warp_g400_t2gz) + +- WARP_UCODE_SIZE(warp_g400_t2gza) + +- WARP_UCODE_SIZE(warp_g400_t2gzaf) + +- WARP_UCODE_SIZE(warp_g400_t2gzf) + +- WARP_UCODE_SIZE(warp_g400_t2gzs) + +- WARP_UCODE_SIZE(warp_g400_t2gzsa) + +- WARP_UCODE_SIZE(warp_g400_t2gzsaf) + WARP_UCODE_SIZE(warp_g400_t2gzsf)); +- +-static const unsigned int mga_warp_g200_microcode_size = +- (WARP_UCODE_SIZE(warp_g200_tgz) + +- WARP_UCODE_SIZE(warp_g200_tgza) + +- WARP_UCODE_SIZE(warp_g200_tgzaf) + +- WARP_UCODE_SIZE(warp_g200_tgzf) + +- WARP_UCODE_SIZE(warp_g200_tgzs) + +- WARP_UCODE_SIZE(warp_g200_tgzsa) + +- WARP_UCODE_SIZE(warp_g200_tgzsaf) + WARP_UCODE_SIZE(warp_g200_tgzsf)); +- +-unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv) ++#define WARP_UCODE_SIZE(size) ALIGN(size, MGA_WARP_CODE_ALIGN) ++ ++int mga_warp_install_microcode(drm_mga_private_t * dev_priv) + { ++ unsigned char *vcbase = dev_priv->warp->handle; ++ unsigned long pcbase = dev_priv->warp->offset; ++ const char *firmware_name; ++ struct platform_device *pdev; ++ const struct firmware *fw = NULL; ++ const struct ihex_binrec *rec; ++ unsigned int size; ++ int n_pipes, where; ++ int rc = 0; ++ + switch (dev_priv->chipset) { + case MGA_CARD_TYPE_G400: + case MGA_CARD_TYPE_G550: +- return PAGE_ALIGN(mga_warp_g400_microcode_size); ++ firmware_name = FIRMWARE_G400; ++ n_pipes = MGA_MAX_G400_PIPES; ++ break; + case MGA_CARD_TYPE_G200: +- return PAGE_ALIGN(mga_warp_g200_microcode_size); ++ firmware_name = FIRMWARE_G200; ++ n_pipes = MGA_MAX_G200_PIPES; ++ break; + default: +- return 0; ++ return -EINVAL; + } +-} +- +-static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv) +-{ +- unsigned char *vcbase = dev_priv->warp->handle; +- unsigned long pcbase = dev_priv->warp->offset; +- +- memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); +- +- WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ); +- WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF); +- WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA); +- WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF); +- WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS); +- WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF); +- WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA); +- WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF); +- +- WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ); +- WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF); +- WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA); +- WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF); +- WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS); +- WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF); +- WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA); +- WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF); +- +- return 0; +-} +- +-static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv) +-{ +- unsigned char *vcbase = dev_priv->warp->handle; +- unsigned long pcbase = dev_priv->warp->offset; +- +- memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); +- +- WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ); +- WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF); +- WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA); +- WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF); +- WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS); +- WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF); +- WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA); +- WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF); + +- return 0; +-} ++ pdev = platform_device_register_simple("mga_warp", 0, NULL, 0); ++ if (IS_ERR(pdev)) { ++ DRM_ERROR("mga: Failed to register microcode\n"); ++ return PTR_ERR(pdev); ++ } ++ rc = request_ihex_firmware(&fw, firmware_name, &pdev->dev); ++ platform_device_unregister(pdev); ++ if (rc) { ++ DRM_ERROR("mga: Failed to load microcode \"%s\"\n", ++ firmware_name); ++ return rc; ++ } + +-int mga_warp_install_microcode(drm_mga_private_t * dev_priv) +-{ +- const unsigned int size = mga_warp_microcode_size(dev_priv); ++ size = 0; ++ where = 0; ++ for (rec = (const struct ihex_binrec *)fw->data; ++ rec; ++ rec = ihex_next_binrec(rec)) { ++ size += WARP_UCODE_SIZE(be16_to_cpu(rec->len)); ++ where++; ++ } + ++ if (where != n_pipes) { ++ DRM_ERROR("mga: Invalid microcode \"%s\"\n", firmware_name); ++ rc = -EINVAL; ++ goto out; ++ } ++ size = PAGE_ALIGN(size); + DRM_DEBUG("MGA ucode size = %d bytes\n", size); + if (size > dev_priv->warp->size) { + DRM_ERROR("microcode too large! (%u > %lu)\n", + size, dev_priv->warp->size); +- return -ENOMEM; ++ rc = -ENOMEM; ++ goto out; + } + +- switch (dev_priv->chipset) { +- case MGA_CARD_TYPE_G400: +- case MGA_CARD_TYPE_G550: +- return mga_warp_install_g400_microcode(dev_priv); +- case MGA_CARD_TYPE_G200: +- return mga_warp_install_g200_microcode(dev_priv); +- default: +- return -EINVAL; ++ memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); ++ ++ where = 0; ++ for (rec = (const struct ihex_binrec *)fw->data; ++ rec; ++ rec = ihex_next_binrec(rec)) { ++ unsigned int src_size, dst_size; ++ ++ DRM_DEBUG(" pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase); ++ dev_priv->warp_pipe_phys[where] = pcbase; ++ src_size = be16_to_cpu(rec->len); ++ dst_size = WARP_UCODE_SIZE(src_size); ++ memcpy(vcbase, rec->data, src_size); ++ pcbase += dst_size; ++ vcbase += dst_size; ++ where++; + } ++ ++out: ++ release_firmware(fw); ++ return rc; + } + + #define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) +diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c +index c75fd35..4c39a40 100644 +--- a/drivers/gpu/drm/r128/r128_cce.c ++++ b/drivers/gpu/drm/r128/r128_cce.c +@@ -29,6 +29,9 @@ + * Gareth Hughes <gareth@valinux.com> + */ + ++#include <linux/firmware.h> ++#include <linux/platform_device.h> ++ + #include "drmP.h" + #include "drm.h" + #include "r128_drm.h" +@@ -36,50 +39,9 @@ + + #define R128_FIFO_DEBUG 0 + +-/* CCE microcode (from ATI) */ +-static u32 r128_cce_microcode[] = { +- 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, +- 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, +- 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, +- 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, +- 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, +- 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, +- 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, +- 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, +- 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, +- 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, +- 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, +- 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, +- 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, +- 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, +- 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, +- 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, +- 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, +- 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, +- 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, +- 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, +- 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, +- 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, +- 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, +- 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, +- 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, +- 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, +- 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, +- 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, +- 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, +- 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, +- 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, +- 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, +- 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, +- 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, +- 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +-}; ++#define FIRMWARE_NAME "r128/r128_cce.bin" ++ ++MODULE_FIRMWARE(FIRMWARE_NAME); + + static int R128_READ_PLL(struct drm_device * dev, int addr) + { +@@ -176,20 +138,50 @@ static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) + */ + + /* Load the microcode for the CCE */ +-static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) ++static int r128_cce_load_microcode(drm_r128_private_t *dev_priv) + { +- int i; ++ struct platform_device *pdev; ++ const struct firmware *fw; ++ const __be32 *fw_data; ++ int rc, i; + + DRM_DEBUG("\n"); + ++ pdev = platform_device_register_simple("r128_cce", 0, NULL, 0); ++ if (IS_ERR(pdev)) { ++ printk(KERN_ERR "r128_cce: Failed to register firmware\n"); ++ return PTR_ERR(pdev); ++ } ++ rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev); ++ platform_device_unregister(pdev); ++ if (rc) { ++ printk(KERN_ERR "r128_cce: Failed to load firmware \"%s\"\n", ++ FIRMWARE_NAME); ++ return rc; ++ } ++ ++ if (fw->size != 256 * 8) { ++ printk(KERN_ERR ++ "r128_cce: Bogus length %zu in firmware \"%s\"\n", ++ fw->size, FIRMWARE_NAME); ++ rc = -EINVAL; ++ goto out_release; ++ } ++ + r128_do_wait_for_idle(dev_priv); + ++ fw_data = (const __be32 *)fw->data; + R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); + for (i = 0; i < 256; i++) { +- R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); ++ R128_WRITE(R128_PM4_MICROCODE_DATAH, ++ be32_to_cpup(&fw_data[i * 2])); + R128_WRITE(R128_PM4_MICROCODE_DATAL, +- r128_cce_microcode[i * 2 + 1]); ++ be32_to_cpup(&fw_data[i * 2 + 1])); + } ++ ++out_release: ++ release_firmware(fw); ++ return rc; + } + + /* Flush any pending commands to the CCE. This should only be used just +@@ -350,9 +342,15 @@ static void r128_cce_init_ring_buffer(struct drm_device * dev, + static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) + { + drm_r128_private_t *dev_priv; ++ int rc; + + DRM_DEBUG("\n"); + ++ if (dev->dev_private) { ++ DRM_DEBUG("called when already initialized\n"); ++ return -EINVAL; ++ } ++ + dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL); + if (dev_priv == NULL) + return -ENOMEM; +@@ -575,13 +573,18 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) + #endif + + r128_cce_init_ring_buffer(dev, dev_priv); +- r128_cce_load_microcode(dev_priv); ++ rc = r128_cce_load_microcode(dev_priv); + + dev->dev_private = (void *)dev_priv; + + r128_do_engine_reset(dev); + +- return 0; ++ if (rc) { ++ DRM_ERROR("Failed to load firmware!\n"); ++ r128_do_cleanup_cce(dev); ++ } ++ ++ return rc; + } + + int r128_do_cleanup_cce(struct drm_device * dev) +@@ -649,6 +652,8 @@ int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_pri + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { + DRM_DEBUG("while CCE running\n"); + return 0; +@@ -671,6 +676,8 @@ int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + /* Flush any pending CCE commands. This ensures any outstanding + * commands are exectuted by the engine before we turn it off. + */ +@@ -708,10 +715,7 @@ int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_pri + + LOCK_TEST_WITH_RETURN(dev, file_priv); + +- if (!dev_priv) { +- DRM_DEBUG("called before init done\n"); +- return -EINVAL; +- } ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); + + r128_do_cce_reset(dev_priv); + +@@ -728,6 +732,8 @@ int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + if (dev_priv->cce_running) { + r128_do_cce_flush(dev_priv); + } +@@ -741,6 +747,8 @@ int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_ + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev->dev_private); ++ + return r128_do_engine_reset(dev); + } + +diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h +index 797a26c..3c60829 100644 +--- a/drivers/gpu/drm/r128/r128_drv.h ++++ b/drivers/gpu/drm/r128/r128_drv.h +@@ -422,6 +422,14 @@ static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) + * Misc helper macros + */ + ++#define DEV_INIT_TEST_WITH_RETURN(_dev_priv) \ ++do { \ ++ if (!_dev_priv) { \ ++ DRM_ERROR("called with no initialization\n"); \ ++ return -EINVAL; \ ++ } \ ++} while (0) ++ + #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ + do { \ + drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ +diff --git a/drivers/gpu/drm/r128/r128_state.c b/drivers/gpu/drm/r128/r128_state.c +index 026a48c..af2665c 100644 +--- a/drivers/gpu/drm/r128/r128_state.c ++++ b/drivers/gpu/drm/r128/r128_state.c +@@ -1244,14 +1244,18 @@ static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple) + static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) + { + drm_r128_private_t *dev_priv = dev->dev_private; +- drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; ++ drm_r128_sarea_t *sarea_priv; + drm_r128_clear_t *clear = data; + DRM_DEBUG("\n"); + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + RING_SPACE_TEST_WITH_RETURN(dev_priv); + ++ sarea_priv = dev_priv->sarea_priv; ++ + if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) + sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; + +@@ -1312,6 +1316,8 @@ static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *fi + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + RING_SPACE_TEST_WITH_RETURN(dev_priv); + + if (!dev_priv->page_flipping) +@@ -1331,6 +1337,8 @@ static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *fi + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + RING_SPACE_TEST_WITH_RETURN(dev_priv); + + if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) +@@ -1354,10 +1362,7 @@ static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file * + + LOCK_TEST_WITH_RETURN(dev, file_priv); + +- if (!dev_priv) { +- DRM_ERROR("called with no initialization\n"); +- return -EINVAL; +- } ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); + + DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", + DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); +@@ -1410,10 +1415,7 @@ static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file + + LOCK_TEST_WITH_RETURN(dev, file_priv); + +- if (!dev_priv) { +- DRM_ERROR("called with no initialization\n"); +- return -EINVAL; +- } ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); + + DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, + elts->idx, elts->start, elts->end, elts->discard); +@@ -1476,6 +1478,8 @@ static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *fi + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx); + + if (blit->idx < 0 || blit->idx >= dma->buf_count) { +@@ -1501,6 +1505,8 @@ static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *f + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + RING_SPACE_TEST_WITH_RETURN(dev_priv); + + ret = -EINVAL; +@@ -1531,6 +1537,8 @@ static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file + + LOCK_TEST_WITH_RETURN(dev, file_priv); + ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); ++ + if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) + return -EFAULT; + +@@ -1555,10 +1563,7 @@ static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file + + LOCK_TEST_WITH_RETURN(dev, file_priv); + +- if (!dev_priv) { +- DRM_ERROR("called with no initialization\n"); +- return -EINVAL; +- } ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); + + DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", + indirect->idx, indirect->start, indirect->end, +@@ -1620,10 +1625,7 @@ static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *fi + drm_r128_getparam_t *param = data; + int value; + +- if (!dev_priv) { +- DRM_ERROR("called with no initialization\n"); +- return -EINVAL; +- } ++ DEV_INIT_TEST_WITH_RETURN(dev_priv); + + DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); + +diff --git a/drivers/gpu/drm/radeon/.gitignore b/drivers/gpu/drm/radeon/.gitignore +new file mode 100644 +index 0000000..403eb3a +--- /dev/null ++++ b/drivers/gpu/drm/radeon/.gitignore +@@ -0,0 +1,3 @@ ++mkregtable ++*_reg_safe.h ++ +diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig +index 2168d67..5982321 100644 +--- a/drivers/gpu/drm/radeon/Kconfig ++++ b/drivers/gpu/drm/radeon/Kconfig +@@ -1,7 +1,6 @@ + config DRM_RADEON_KMS + bool "Enable modesetting on radeon by default" + depends on DRM_RADEON +- select DRM_TTM + help + Choose this option if you want kernel modesetting enabled by default, + and you have a new enough userspace to support this. Running old +diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile +index 013d380..09a2892 100644 +--- a/drivers/gpu/drm/radeon/Makefile ++++ b/drivers/gpu/drm/radeon/Makefile +@@ -3,18 +3,53 @@ + # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. + + ccflags-y := -Iinclude/drm ++ ++hostprogs-y := mkregtable ++ ++quiet_cmd_mkregtable = MKREGTABLE $@ ++ cmd_mkregtable = $(obj)/mkregtable $< > $@ ++ ++$(obj)/rn50_reg_safe.h: $(src)/reg_srcs/rn50 $(obj)/mkregtable ++ $(call if_changed,mkregtable) ++ ++$(obj)/r100_reg_safe.h: $(src)/reg_srcs/r100 $(obj)/mkregtable ++ $(call if_changed,mkregtable) ++ ++$(obj)/r200_reg_safe.h: $(src)/reg_srcs/r200 $(obj)/mkregtable ++ $(call if_changed,mkregtable) ++ ++$(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable ++ $(call if_changed,mkregtable) ++ ++$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable ++ $(call if_changed,mkregtable) ++ ++$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable ++ $(call if_changed,mkregtable) ++ ++$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h ++ ++$(obj)/r200.o: $(obj)/r200_reg_safe.h ++ ++$(obj)/rv515.o: $(obj)/rv515_reg_safe.h ++ ++$(obj)/r300.o: $(obj)/r300_reg_safe.h ++ ++$(obj)/rs600.o: $(obj)/rs600_reg_safe.h ++ + radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ + radeon_irq.o r300_cmdbuf.o r600_cp.o +- +-radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ ++# add KMS driver ++radeon-y += radeon_device.o radeon_kms.o \ + radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \ + atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \ + radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \ + radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \ + radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ + radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ +- rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ +- radeon_test.o ++ rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ ++ r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ ++ r600_blit_kms.o + + radeon-$(CONFIG_COMPAT) += radeon_ioc32.o + +diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h +index cf67928..5d40208 100644 +--- a/drivers/gpu/drm/radeon/atombios.h ++++ b/drivers/gpu/drm/radeon/atombios.h +@@ -2374,6 +2374,17 @@ typedef struct _ATOM_ANALOG_TV_INFO { + ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; + } ATOM_ANALOG_TV_INFO; + ++#define MAX_SUPPORTED_TV_TIMING_V1_2 3 ++ ++typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucTV_SupportedStandard; ++ UCHAR ucTV_BootUpDefaultStandard; ++ UCHAR ucExt_TV_ASIC_ID; ++ UCHAR ucExt_TV_ASIC_SlaveAddr; ++ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; ++} ATOM_ANALOG_TV_INFO_V1_2; ++ + /**************************************************************************/ + /* VRAM usage and their defintions */ + +diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c +index 74d034f..6a01592 100644 +--- a/drivers/gpu/drm/radeon/atombios_crtc.c ++++ b/drivers/gpu/drm/radeon/atombios_crtc.c +@@ -31,6 +31,10 @@ + #include "atom.h" + #include "atom-bits.h" + ++/* evil but including atombios.h is much worse */ ++bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, ++ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, ++ int32_t *pixel_clock); + static void atombios_overscan_setup(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +@@ -89,17 +93,32 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + ENABLE_SCALER_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); ++ + /* fixme - fill in enc_priv for atom dac */ + enum radeon_tv_std tv_std = TV_STD_NTSC; ++ bool is_tv = false, is_cv = false; ++ struct drm_encoder *encoder; + + if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) + return; + ++ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ++ /* find tv std */ ++ if (encoder->crtc == crtc) { ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { ++ struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; ++ tv_std = tv_dac->tv_std; ++ is_tv = true; ++ } ++ } ++ } ++ + memset(&args, 0, sizeof(args)); + + args.ucScaler = radeon_crtc->crtc_id; + +- if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) { ++ if (is_tv) { + switch (tv_std) { + case TV_STD_NTSC: + default: +@@ -128,7 +147,7 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) + break; + } + args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; +- } else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) { ++ } else if (is_cv) { + args.ucTVStandard = ATOM_TV_CV; + args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; + } else { +@@ -151,9 +170,9 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) + } + } + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); +- if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) +- && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) { +- atom_rv515_force_tv_scaler(rdev); ++ if ((is_tv || is_cv) ++ && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { ++ atom_rv515_force_tv_scaler(rdev, radeon_crtc); + } + } + +@@ -370,6 +389,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + pll_flags |= RADEON_PLL_USE_REF_DIV; + } + radeon_encoder = to_radeon_encoder(encoder); ++ break; + } + } + +@@ -468,6 +488,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, + } + + switch (crtc->fb->bits_per_pixel) { ++ case 8: ++ fb_format = ++ AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | ++ AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; ++ break; + case 15: + fb_format = + AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | +@@ -551,42 +576,68 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, + struct radeon_device *rdev = dev->dev_private; + struct drm_encoder *encoder; + SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; ++ int need_tv_timings = 0; ++ bool ret; + + /* TODO color tiling */ + memset(&crtc_timing, 0, sizeof(crtc_timing)); + +- /* TODO tv */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- ++ /* find tv std */ ++ if (encoder->crtc == crtc) { ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ ++ if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { ++ struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; ++ if (tv_dac) { ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M) ++ need_tv_timings = 1; ++ else ++ need_tv_timings = 2; ++ break; ++ } ++ } ++ } + } + + crtc_timing.ucCRTC = radeon_crtc->crtc_id; +- crtc_timing.usH_Total = adjusted_mode->crtc_htotal; +- crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; +- crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; +- crtc_timing.usH_SyncWidth = +- adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; ++ if (need_tv_timings) { ++ ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1, ++ &crtc_timing, &adjusted_mode->clock); ++ if (ret == false) ++ need_tv_timings = 0; ++ } + +- crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; +- crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; +- crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; +- crtc_timing.usV_SyncWidth = +- adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; ++ if (!need_tv_timings) { ++ crtc_timing.usH_Total = adjusted_mode->crtc_htotal; ++ crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; ++ crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; ++ crtc_timing.usH_SyncWidth = ++ adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; + +- if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) +- crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; ++ crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; ++ crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; ++ crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; ++ crtc_timing.usV_SyncWidth = ++ adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; + +- if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) +- crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; ++ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ++ crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; + +- if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) +- crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; ++ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ++ crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; + +- if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) +- crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; ++ if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) ++ crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; + +- if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) +- crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; ++ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ++ crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; ++ ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; ++ } + + atombios_crtc_set_pll(crtc, adjusted_mode); + atombios_crtc_set_timing(crtc, &crtc_timing); +diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h +new file mode 100644 +index 0000000..d4e6e6e +--- /dev/null ++++ b/drivers/gpu/drm/radeon/avivod.h +@@ -0,0 +1,60 @@ ++/* ++ * Copyright 2009 Advanced Micro Devices, Inc. ++ * Copyright 2009 Red Hat Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#ifndef AVIVOD_H ++#define AVIVOD_H ++ ++ ++#define D1CRTC_CONTROL 0x6080 ++#define CRTC_EN (1 << 0) ++#define D1CRTC_UPDATE_LOCK 0x60E8 ++#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 ++#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 ++ ++#define D2CRTC_CONTROL 0x6880 ++#define D2CRTC_UPDATE_LOCK 0x68E8 ++#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 ++#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 ++ ++#define D1VGA_CONTROL 0x0330 ++#define DVGA_CONTROL_MODE_ENABLE (1 << 0) ++#define DVGA_CONTROL_TIMING_SELECT (1 << 8) ++#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) ++#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) ++#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) ++#define DVGA_CONTROL_ROTATE (1 << 24) ++#define D2VGA_CONTROL 0x0338 ++ ++#define VGA_HDP_CONTROL 0x328 ++#define VGA_MEM_PAGE_SELECT_EN (1 << 0) ++#define VGA_MEMORY_DISABLE (1 << 4) ++#define VGA_RBBM_LOCK_DISABLE (1 << 8) ++#define VGA_SOFT_RESET (1 << 16) ++#define VGA_MEMORY_BASE_ADDRESS 0x0310 ++#define VGA_RENDER_CONTROL 0x0300 ++#define VGA_VSTATUS_CNTL_MASK 0x00030000 ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c +new file mode 100644 +index 0000000..fb211e5 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/mkregtable.c +@@ -0,0 +1,720 @@ ++/* utility to create the register check tables ++ * this includes inlined list.h safe for userspace. ++ * ++ * Copyright 2009 Jerome Glisse ++ * Copyright 2009 Red Hat Inc. ++ * ++ * Authors: ++ * Jerome Glisse ++ * Dave Airlie ++ */ ++ ++#include <sys/types.h> ++#include <stdlib.h> ++#include <string.h> ++#include <stdio.h> ++#include <regex.h> ++#include <libgen.h> ++ ++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) ++/** ++ * container_of - cast a member of a structure out to the containing structure ++ * @ptr: the pointer to the member. ++ * @type: the type of the container struct this is embedded in. ++ * @member: the name of the member within the struct. ++ * ++ */ ++#define container_of(ptr, type, member) ({ \ ++ const typeof(((type *)0)->member)*__mptr = (ptr); \ ++ (type *)((char *)__mptr - offsetof(type, member)); }) ++ ++/* ++ * Simple doubly linked list implementation. ++ * ++ * Some of the internal functions ("__xxx") are useful when ++ * manipulating whole lists rather than single entries, as ++ * sometimes we already know the next/prev entries and we can ++ * generate better code by using them directly rather than ++ * using the generic single-entry routines. ++ */ ++ ++struct list_head { ++ struct list_head *next, *prev; ++}; ++ ++#define LIST_HEAD_INIT(name) { &(name), &(name) } ++ ++#define LIST_HEAD(name) \ ++ struct list_head name = LIST_HEAD_INIT(name) ++ ++static inline void INIT_LIST_HEAD(struct list_head *list) ++{ ++ list->next = list; ++ list->prev = list; ++} ++ ++/* ++ * Insert a new entry between two known consecutive entries. ++ * ++ * This is only for internal list manipulation where we know ++ * the prev/next entries already! ++ */ ++#ifndef CONFIG_DEBUG_LIST ++static inline void __list_add(struct list_head *new, ++ struct list_head *prev, struct list_head *next) ++{ ++ next->prev = new; ++ new->next = next; ++ new->prev = prev; ++ prev->next = new; ++} ++#else ++extern void __list_add(struct list_head *new, ++ struct list_head *prev, struct list_head *next); ++#endif ++ ++/** ++ * list_add - add a new entry ++ * @new: new entry to be added ++ * @head: list head to add it after ++ * ++ * Insert a new entry after the specified head. ++ * This is good for implementing stacks. ++ */ ++static inline void list_add(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head, head->next); ++} ++ ++/** ++ * list_add_tail - add a new entry ++ * @new: new entry to be added ++ * @head: list head to add it before ++ * ++ * Insert a new entry before the specified head. ++ * This is useful for implementing queues. ++ */ ++static inline void list_add_tail(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head->prev, head); ++} ++ ++/* ++ * Delete a list entry by making the prev/next entries ++ * point to each other. ++ * ++ * This is only for internal list manipulation where we know ++ * the prev/next entries already! ++ */ ++static inline void __list_del(struct list_head *prev, struct list_head *next) ++{ ++ next->prev = prev; ++ prev->next = next; ++} ++ ++/** ++ * list_del - deletes entry from list. ++ * @entry: the element to delete from the list. ++ * Note: list_empty() on entry does not return true after this, the entry is ++ * in an undefined state. ++ */ ++#ifndef CONFIG_DEBUG_LIST ++static inline void list_del(struct list_head *entry) ++{ ++ __list_del(entry->prev, entry->next); ++ entry->next = (void *)0xDEADBEEF; ++ entry->prev = (void *)0xBEEFDEAD; ++} ++#else ++extern void list_del(struct list_head *entry); ++#endif ++ ++/** ++ * list_replace - replace old entry by new one ++ * @old : the element to be replaced ++ * @new : the new element to insert ++ * ++ * If @old was empty, it will be overwritten. ++ */ ++static inline void list_replace(struct list_head *old, struct list_head *new) ++{ ++ new->next = old->next; ++ new->next->prev = new; ++ new->prev = old->prev; ++ new->prev->next = new; ++} ++ ++static inline void list_replace_init(struct list_head *old, ++ struct list_head *new) ++{ ++ list_replace(old, new); ++ INIT_LIST_HEAD(old); ++} ++ ++/** ++ * list_del_init - deletes entry from list and reinitialize it. ++ * @entry: the element to delete from the list. ++ */ ++static inline void list_del_init(struct list_head *entry) ++{ ++ __list_del(entry->prev, entry->next); ++ INIT_LIST_HEAD(entry); ++} ++ ++/** ++ * list_move - delete from one list and add as another's head ++ * @list: the entry to move ++ * @head: the head that will precede our entry ++ */ ++static inline void list_move(struct list_head *list, struct list_head *head) ++{ ++ __list_del(list->prev, list->next); ++ list_add(list, head); ++} ++ ++/** ++ * list_move_tail - delete from one list and add as another's tail ++ * @list: the entry to move ++ * @head: the head that will follow our entry ++ */ ++static inline void list_move_tail(struct list_head *list, ++ struct list_head *head) ++{ ++ __list_del(list->prev, list->next); ++ list_add_tail(list, head); ++} ++ ++/** ++ * list_is_last - tests whether @list is the last entry in list @head ++ * @list: the entry to test ++ * @head: the head of the list ++ */ ++static inline int list_is_last(const struct list_head *list, ++ const struct list_head *head) ++{ ++ return list->next == head; ++} ++ ++/** ++ * list_empty - tests whether a list is empty ++ * @head: the list to test. ++ */ ++static inline int list_empty(const struct list_head *head) ++{ ++ return head->next == head; ++} ++ ++/** ++ * list_empty_careful - tests whether a list is empty and not being modified ++ * @head: the list to test ++ * ++ * Description: ++ * tests whether a list is empty _and_ checks that no other CPU might be ++ * in the process of modifying either member (next or prev) ++ * ++ * NOTE: using list_empty_careful() without synchronization ++ * can only be safe if the only activity that can happen ++ * to the list entry is list_del_init(). Eg. it cannot be used ++ * if another CPU could re-list_add() it. ++ */ ++static inline int list_empty_careful(const struct list_head *head) ++{ ++ struct list_head *next = head->next; ++ return (next == head) && (next == head->prev); ++} ++ ++/** ++ * list_is_singular - tests whether a list has just one entry. ++ * @head: the list to test. ++ */ ++static inline int list_is_singular(const struct list_head *head) ++{ ++ return !list_empty(head) && (head->next == head->prev); ++} ++ ++static inline void __list_cut_position(struct list_head *list, ++ struct list_head *head, ++ struct list_head *entry) ++{ ++ struct list_head *new_first = entry->next; ++ list->next = head->next; ++ list->next->prev = list; ++ list->prev = entry; ++ entry->next = list; ++ head->next = new_first; ++ new_first->prev = head; ++} ++ ++/** ++ * list_cut_position - cut a list into two ++ * @list: a new list to add all removed entries ++ * @head: a list with entries ++ * @entry: an entry within head, could be the head itself ++ * and if so we won't cut the list ++ * ++ * This helper moves the initial part of @head, up to and ++ * including @entry, from @head to @list. You should ++ * pass on @entry an element you know is on @head. @list ++ * should be an empty list or a list you do not care about ++ * losing its data. ++ * ++ */ ++static inline void list_cut_position(struct list_head *list, ++ struct list_head *head, ++ struct list_head *entry) ++{ ++ if (list_empty(head)) ++ return; ++ if (list_is_singular(head) && (head->next != entry && head != entry)) ++ return; ++ if (entry == head) ++ INIT_LIST_HEAD(list); ++ else ++ __list_cut_position(list, head, entry); ++} ++ ++static inline void __list_splice(const struct list_head *list, ++ struct list_head *prev, struct list_head *next) ++{ ++ struct list_head *first = list->next; ++ struct list_head *last = list->prev; ++ ++ first->prev = prev; ++ prev->next = first; ++ ++ last->next = next; ++ next->prev = last; ++} ++ ++/** ++ * list_splice - join two lists, this is designed for stacks ++ * @list: the new list to add. ++ * @head: the place to add it in the first list. ++ */ ++static inline void list_splice(const struct list_head *list, ++ struct list_head *head) ++{ ++ if (!list_empty(list)) ++ __list_splice(list, head, head->next); ++} ++ ++/** ++ * list_splice_tail - join two lists, each list being a queue ++ * @list: the new list to add. ++ * @head: the place to add it in the first list. ++ */ ++static inline void list_splice_tail(struct list_head *list, ++ struct list_head *head) ++{ ++ if (!list_empty(list)) ++ __list_splice(list, head->prev, head); ++} ++ ++/** ++ * list_splice_init - join two lists and reinitialise the emptied list. ++ * @list: the new list to add. ++ * @head: the place to add it in the first list. ++ * ++ * The list at @list is reinitialised ++ */ ++static inline void list_splice_init(struct list_head *list, ++ struct list_head *head) ++{ ++ if (!list_empty(list)) { ++ __list_splice(list, head, head->next); ++ INIT_LIST_HEAD(list); ++ } ++} ++ ++/** ++ * list_splice_tail_init - join two lists and reinitialise the emptied list ++ * @list: the new list to add. ++ * @head: the place to add it in the first list. ++ * ++ * Each of the lists is a queue. ++ * The list at @list is reinitialised ++ */ ++static inline void list_splice_tail_init(struct list_head *list, ++ struct list_head *head) ++{ ++ if (!list_empty(list)) { ++ __list_splice(list, head->prev, head); ++ INIT_LIST_HEAD(list); ++ } ++} ++ ++/** ++ * list_entry - get the struct for this entry ++ * @ptr: the &struct list_head pointer. ++ * @type: the type of the struct this is embedded in. ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_entry(ptr, type, member) \ ++ container_of(ptr, type, member) ++ ++/** ++ * list_first_entry - get the first element from a list ++ * @ptr: the list head to take the element from. ++ * @type: the type of the struct this is embedded in. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Note, that list is expected to be not empty. ++ */ ++#define list_first_entry(ptr, type, member) \ ++ list_entry((ptr)->next, type, member) ++ ++/** ++ * list_for_each - iterate over a list ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @head: the head for your list. ++ */ ++#define list_for_each(pos, head) \ ++ for (pos = (head)->next; prefetch(pos->next), pos != (head); \ ++ pos = pos->next) ++ ++/** ++ * __list_for_each - iterate over a list ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @head: the head for your list. ++ * ++ * This variant differs from list_for_each() in that it's the ++ * simplest possible list iteration code, no prefetching is done. ++ * Use this for code that knows the list to be very short (empty ++ * or 1 entry) most of the time. ++ */ ++#define __list_for_each(pos, head) \ ++ for (pos = (head)->next; pos != (head); pos = pos->next) ++ ++/** ++ * list_for_each_prev - iterate over a list backwards ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @head: the head for your list. ++ */ ++#define list_for_each_prev(pos, head) \ ++ for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ ++ pos = pos->prev) ++ ++/** ++ * list_for_each_safe - iterate over a list safe against removal of list entry ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @n: another &struct list_head to use as temporary storage ++ * @head: the head for your list. ++ */ ++#define list_for_each_safe(pos, n, head) \ ++ for (pos = (head)->next, n = pos->next; pos != (head); \ ++ pos = n, n = pos->next) ++ ++/** ++ * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @n: another &struct list_head to use as temporary storage ++ * @head: the head for your list. ++ */ ++#define list_for_each_prev_safe(pos, n, head) \ ++ for (pos = (head)->prev, n = pos->prev; \ ++ prefetch(pos->prev), pos != (head); \ ++ pos = n, n = pos->prev) ++ ++/** ++ * list_for_each_entry - iterate over list of given type ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_for_each_entry(pos, head, member) \ ++ for (pos = list_entry((head)->next, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = list_entry(pos->member.next, typeof(*pos), member)) ++ ++/** ++ * list_for_each_entry_reverse - iterate backwards over list of given type. ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_for_each_entry_reverse(pos, head, member) \ ++ for (pos = list_entry((head)->prev, typeof(*pos), member); \ ++ prefetch(pos->member.prev), &pos->member != (head); \ ++ pos = list_entry(pos->member.prev, typeof(*pos), member)) ++ ++/** ++ * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() ++ * @pos: the type * to use as a start point ++ * @head: the head of the list ++ * @member: the name of the list_struct within the struct. ++ * ++ * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). ++ */ ++#define list_prepare_entry(pos, head, member) \ ++ ((pos) ? : list_entry(head, typeof(*pos), member)) ++ ++/** ++ * list_for_each_entry_continue - continue iteration over list of given type ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Continue to iterate over list of given type, continuing after ++ * the current position. ++ */ ++#define list_for_each_entry_continue(pos, head, member) \ ++ for (pos = list_entry(pos->member.next, typeof(*pos), member); \ ++ prefetch(pos->member.next), &pos->member != (head); \ ++ pos = list_entry(pos->member.next, typeof(*pos), member)) ++ ++/** ++ * list_for_each_entry_continue_reverse - iterate backwards from the given point ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Start to iterate over list of given type backwards, continuing after ++ * the current position. ++ */ ++#define list_for_each_entry_continue_reverse(pos, head, member) \ ++ for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ ++ prefetch(pos->member.prev), &pos->member != (head); \ ++ pos = list_entry(pos->member.prev, typeof(*pos), member)) ++ ++/** ++ * list_for_each_entry_from - iterate over list of given type from the current point ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Iterate over list of given type, continuing from current position. ++ */ ++#define list_for_each_entry_from(pos, head, member) \ ++ for (; prefetch(pos->member.next), &pos->member != (head); \ ++ pos = list_entry(pos->member.next, typeof(*pos), member)) ++ ++/** ++ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry ++ * @pos: the type * to use as a loop cursor. ++ * @n: another type * to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_for_each_entry_safe(pos, n, head, member) \ ++ for (pos = list_entry((head)->next, typeof(*pos), member), \ ++ n = list_entry(pos->member.next, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_entry(n->member.next, typeof(*n), member)) ++ ++/** ++ * list_for_each_entry_safe_continue ++ * @pos: the type * to use as a loop cursor. ++ * @n: another type * to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Iterate over list of given type, continuing after current point, ++ * safe against removal of list entry. ++ */ ++#define list_for_each_entry_safe_continue(pos, n, head, member) \ ++ for (pos = list_entry(pos->member.next, typeof(*pos), member), \ ++ n = list_entry(pos->member.next, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_entry(n->member.next, typeof(*n), member)) ++ ++/** ++ * list_for_each_entry_safe_from ++ * @pos: the type * to use as a loop cursor. ++ * @n: another type * to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Iterate over list of given type from current point, safe against ++ * removal of list entry. ++ */ ++#define list_for_each_entry_safe_from(pos, n, head, member) \ ++ for (n = list_entry(pos->member.next, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_entry(n->member.next, typeof(*n), member)) ++ ++/** ++ * list_for_each_entry_safe_reverse ++ * @pos: the type * to use as a loop cursor. ++ * @n: another type * to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Iterate backwards over list of given type, safe against removal ++ * of list entry. ++ */ ++#define list_for_each_entry_safe_reverse(pos, n, head, member) \ ++ for (pos = list_entry((head)->prev, typeof(*pos), member), \ ++ n = list_entry(pos->member.prev, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_entry(n->member.prev, typeof(*n), member)) ++ ++struct offset { ++ struct list_head list; ++ unsigned offset; ++}; ++ ++struct table { ++ struct list_head offsets; ++ unsigned offset_max; ++ unsigned nentry; ++ unsigned *table; ++ char *gpu_prefix; ++}; ++ ++struct offset *offset_new(unsigned o) ++{ ++ struct offset *offset; ++ ++ offset = (struct offset *)malloc(sizeof(struct offset)); ++ if (offset) { ++ INIT_LIST_HEAD(&offset->list); ++ offset->offset = o; ++ } ++ return offset; ++} ++ ++void table_offset_add(struct table *t, struct offset *offset) ++{ ++ list_add_tail(&offset->list, &t->offsets); ++} ++ ++void table_init(struct table *t) ++{ ++ INIT_LIST_HEAD(&t->offsets); ++ t->offset_max = 0; ++ t->nentry = 0; ++ t->table = NULL; ++} ++ ++void table_print(struct table *t) ++{ ++ unsigned nlloop, i, j, n, c, id; ++ ++ nlloop = (t->nentry + 3) / 4; ++ c = t->nentry; ++ printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix, ++ t->nentry); ++ for (i = 0, id = 0; i < nlloop; i++) { ++ n = 4; ++ if (n > c) ++ n = c; ++ c -= n; ++ for (j = 0; j < n; j++) { ++ if (j == 0) ++ printf("\t"); ++ else ++ printf(" "); ++ printf("0x%08X,", t->table[id++]); ++ } ++ printf("\n"); ++ } ++ printf("};\n"); ++} ++ ++int table_build(struct table *t) ++{ ++ struct offset *offset; ++ unsigned i, m; ++ ++ t->nentry = ((t->offset_max >> 2) + 31) / 32; ++ t->table = (unsigned *)malloc(sizeof(unsigned) * t->nentry); ++ if (t->table == NULL) ++ return -1; ++ memset(t->table, 0xff, sizeof(unsigned) * t->nentry); ++ list_for_each_entry(offset, &t->offsets, list) { ++ i = (offset->offset >> 2) / 32; ++ m = (offset->offset >> 2) & 31; ++ m = 1 << m; ++ t->table[i] ^= m; ++ } ++ return 0; ++} ++ ++static char gpu_name[10]; ++int parser_auth(struct table *t, const char *filename) ++{ ++ FILE *file; ++ regex_t mask_rex; ++ regmatch_t match[4]; ++ char buf[1024]; ++ size_t end; ++ int len; ++ int done = 0; ++ int r; ++ unsigned o; ++ struct offset *offset; ++ char last_reg_s[10]; ++ int last_reg; ++ ++ if (regcomp ++ (&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) { ++ fprintf(stderr, "Failed to compile regular expression\n"); ++ return -1; ++ } ++ file = fopen(filename, "r"); ++ if (file == NULL) { ++ fprintf(stderr, "Failed to open: %s\n", filename); ++ return -1; ++ } ++ fseek(file, 0, SEEK_END); ++ end = ftell(file); ++ fseek(file, 0, SEEK_SET); ++ ++ /* get header */ ++ if (fgets(buf, 1024, file) == NULL) ++ return -1; ++ ++ /* first line will contain the last register ++ * and gpu name */ ++ sscanf(buf, "%s %s", gpu_name, last_reg_s); ++ t->gpu_prefix = gpu_name; ++ last_reg = strtol(last_reg_s, NULL, 16); ++ ++ do { ++ if (fgets(buf, 1024, file) == NULL) ++ return -1; ++ len = strlen(buf); ++ if (ftell(file) == end) ++ done = 1; ++ if (len) { ++ r = regexec(&mask_rex, buf, 4, match, 0); ++ if (r == REG_NOMATCH) { ++ } else if (r) { ++ fprintf(stderr, ++ "Error matching regular expression %d in %s\n", ++ r, filename); ++ return -1; ++ } else { ++ buf[match[0].rm_eo] = 0; ++ buf[match[1].rm_eo] = 0; ++ buf[match[2].rm_eo] = 0; ++ o = strtol(&buf[match[1].rm_so], NULL, 16); ++ offset = offset_new(o); ++ table_offset_add(t, offset); ++ if (o > t->offset_max) ++ t->offset_max = o; ++ } ++ } ++ } while (!done); ++ fclose(file); ++ if (t->offset_max < last_reg) ++ t->offset_max = last_reg; ++ return table_build(t); ++} ++ ++int main(int argc, char *argv[]) ++{ ++ struct table t; ++ ++ if (argc != 2) { ++ fprintf(stderr, "Usage: %s <authfile>\n", argv[0]); ++ exit(1); ++ } ++ table_init(&t); ++ if (parser_auth(&t, argv[1])) { ++ fprintf(stderr, "Failed to parse file %s\n", argv[1]); ++ return -1; ++ } ++ table_print(&t); ++ return 0; ++} +diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c +index 68e728e..d209914 100644 +--- a/drivers/gpu/drm/radeon/r100.c ++++ b/drivers/gpu/drm/radeon/r100.c +@@ -29,15 +29,41 @@ + #include "drmP.h" + #include "drm.h" + #include "radeon_drm.h" +-#include "radeon_microcode.h" + #include "radeon_reg.h" + #include "radeon.h" ++#include "r100d.h" ++ ++#include <linux/firmware.h> ++#include <linux/platform_device.h> ++ ++#include "r100_reg_safe.h" ++#include "rn50_reg_safe.h" ++ ++/* Firmware Names */ ++#define FIRMWARE_R100 "radeon/R100_cp.bin" ++#define FIRMWARE_R200 "radeon/R200_cp.bin" ++#define FIRMWARE_R300 "radeon/R300_cp.bin" ++#define FIRMWARE_R420 "radeon/R420_cp.bin" ++#define FIRMWARE_RS690 "radeon/RS690_cp.bin" ++#define FIRMWARE_RS600 "radeon/RS600_cp.bin" ++#define FIRMWARE_R520 "radeon/R520_cp.bin" ++ ++MODULE_FIRMWARE(FIRMWARE_R100); ++MODULE_FIRMWARE(FIRMWARE_R200); ++MODULE_FIRMWARE(FIRMWARE_R300); ++MODULE_FIRMWARE(FIRMWARE_R420); ++MODULE_FIRMWARE(FIRMWARE_RS690); ++MODULE_FIRMWARE(FIRMWARE_RS600); ++MODULE_FIRMWARE(FIRMWARE_R520); ++ ++#include "r100_track.h" + + /* This files gather functions specifics to: + * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 + * + * Some of these functions might be used by newer ASICs. + */ ++int r200_init(struct radeon_device *rdev); + void r100_hdp_reset(struct radeon_device *rdev); + void r100_gpu_init(struct radeon_device *rdev); + int r100_gui_wait_for_idle(struct radeon_device *rdev); +@@ -58,23 +84,28 @@ void r100_pci_gart_tlb_flush(struct radeon_device *rdev) + * could end up in wrong address. */ + } + +-int r100_pci_gart_enable(struct radeon_device *rdev) ++int r100_pci_gart_init(struct radeon_device *rdev) + { +- uint32_t tmp; + int r; + ++ if (rdev->gart.table.ram.ptr) { ++ WARN(1, "R100 PCI GART already initialized.\n"); ++ return 0; ++ } + /* Initialize common gart structure */ + r = radeon_gart_init(rdev); +- if (r) { ++ if (r) + return r; +- } +- if (rdev->gart.table.ram.ptr == NULL) { +- rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; +- r = radeon_gart_table_ram_alloc(rdev); +- if (r) { +- return r; +- } +- } ++ rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; ++ rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; ++ rdev->asic->gart_set_page = &r100_pci_gart_set_page; ++ return radeon_gart_table_ram_alloc(rdev); ++} ++ ++int r100_pci_gart_enable(struct radeon_device *rdev) ++{ ++ uint32_t tmp; ++ + /* discard memory request outside of configured range */ + tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; + WREG32(RADEON_AIC_CNTL, tmp); +@@ -114,13 +145,11 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) + return 0; + } + +-int r100_gart_enable(struct radeon_device *rdev) ++void r100_pci_gart_fini(struct radeon_device *rdev) + { +- if (rdev->flags & RADEON_IS_AGP) { +- r100_pci_gart_disable(rdev); +- return 0; +- } +- return r100_pci_gart_enable(rdev); ++ r100_pci_gart_disable(rdev); ++ radeon_gart_table_ram_free(rdev); ++ radeon_gart_fini(rdev); + } + + +@@ -247,9 +276,6 @@ int r100_mc_init(struct radeon_device *rdev) + + void r100_mc_fini(struct radeon_device *rdev) + { +- r100_pci_gart_disable(rdev); +- radeon_gart_table_ram_free(rdev); +- radeon_gart_fini(rdev); + } + + +@@ -273,6 +299,17 @@ int r100_irq_set(struct radeon_device *rdev) + return 0; + } + ++void r100_irq_disable(struct radeon_device *rdev) ++{ ++ u32 tmp; ++ ++ WREG32(R_000040_GEN_INT_CNTL, 0); ++ /* Wait and acknowledge irq */ ++ mdelay(1); ++ tmp = RREG32(R_000044_GEN_INT_STATUS); ++ WREG32(R_000044_GEN_INT_STATUS, tmp); ++} ++ + static inline uint32_t r100_irq_ack(struct radeon_device *rdev) + { + uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); +@@ -293,6 +330,9 @@ int r100_irq_process(struct radeon_device *rdev) + if (!status) { + return IRQ_NONE; + } ++ if (rdev->shutdown) { ++ return IRQ_NONE; ++ } + while (status) { + /* SW interrupt */ + if (status & RADEON_SW_INT_TEST) { +@@ -367,14 +407,21 @@ int r100_wb_init(struct radeon_device *rdev) + return r; + } + } +- WREG32(0x774, rdev->wb.gpu_addr); +- WREG32(0x70C, rdev->wb.gpu_addr + 1024); +- WREG32(0x770, 0xff); ++ WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr); ++ WREG32(R_00070C_CP_RB_RPTR_ADDR, ++ S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2)); ++ WREG32(R_000770_SCRATCH_UMSK, 0xff); + return 0; + } + ++void r100_wb_disable(struct radeon_device *rdev) ++{ ++ WREG32(R_000770_SCRATCH_UMSK, 0); ++} ++ + void r100_wb_fini(struct radeon_device *rdev) + { ++ r100_wb_disable(rdev); + if (rdev->wb.wb_obj) { + radeon_object_kunmap(rdev->wb.wb_obj); + radeon_object_unpin(rdev->wb.wb_obj); +@@ -461,6 +508,21 @@ int r100_copy_blit(struct radeon_device *rdev, + /* + * CP + */ ++static int r100_cp_wait_for_idle(struct radeon_device *rdev) ++{ ++ unsigned i; ++ u32 tmp; ++ ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ tmp = RREG32(R_000E40_RBBM_STATUS); ++ if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { ++ return 0; ++ } ++ udelay(1); ++ } ++ return -1; ++} ++ + void r100_ring_start(struct radeon_device *rdev) + { + int r; +@@ -478,33 +540,33 @@ void r100_ring_start(struct radeon_device *rdev) + radeon_ring_unlock_commit(rdev); + } + +-static void r100_cp_load_microcode(struct radeon_device *rdev) ++ ++/* Load the microcode for the CP */ ++static int r100_cp_init_microcode(struct radeon_device *rdev) + { +- int i; ++ struct platform_device *pdev; ++ const char *fw_name = NULL; ++ int err; + +- if (r100_gui_wait_for_idle(rdev)) { +- printk(KERN_WARNING "Failed to wait GUI idle while " +- "programming pipes. Bad things might happen.\n"); +- } ++ DRM_DEBUG("\n"); + +- WREG32(RADEON_CP_ME_RAM_ADDR, 0); ++ pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); ++ err = IS_ERR(pdev); ++ if (err) { ++ printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); ++ return -EINVAL; ++ } + if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || + (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || + (rdev->family == CHIP_RS200)) { + DRM_INFO("Loading R100 Microcode\n"); +- for (i = 0; i < 256; i++) { +- WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]); +- WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_R100; + } else if ((rdev->family == CHIP_R200) || + (rdev->family == CHIP_RV250) || + (rdev->family == CHIP_RV280) || + (rdev->family == CHIP_RS300)) { + DRM_INFO("Loading R200 Microcode\n"); +- for (i = 0; i < 256; i++) { +- WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]); +- WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_R200; + } else if ((rdev->family == CHIP_R300) || + (rdev->family == CHIP_R350) || + (rdev->family == CHIP_RV350) || +@@ -512,31 +574,19 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) + (rdev->family == CHIP_RS400) || + (rdev->family == CHIP_RS480)) { + DRM_INFO("Loading R300 Microcode\n"); +- for (i = 0; i < 256; i++) { +- WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); +- WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_R300; + } else if ((rdev->family == CHIP_R420) || + (rdev->family == CHIP_R423) || + (rdev->family == CHIP_RV410)) { + DRM_INFO("Loading R400 Microcode\n"); +- for (i = 0; i < 256; i++) { +- WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]); +- WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_R420; + } else if ((rdev->family == CHIP_RS690) || + (rdev->family == CHIP_RS740)) { + DRM_INFO("Loading RS690/RS740 Microcode\n"); +- for (i = 0; i < 256; i++) { +- WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]); +- WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_RS690; + } else if (rdev->family == CHIP_RS600) { + DRM_INFO("Loading RS600 Microcode\n"); +- for (i = 0; i < 256; i++) { +- WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]); +- WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_RS600; + } else if ((rdev->family == CHIP_RV515) || + (rdev->family == CHIP_R520) || + (rdev->family == CHIP_RV530) || +@@ -544,9 +594,43 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) + (rdev->family == CHIP_RV560) || + (rdev->family == CHIP_RV570)) { + DRM_INFO("Loading R500 Microcode\n"); +- for (i = 0; i < 256; i++) { +- WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); +- WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); ++ fw_name = FIRMWARE_R520; ++ } ++ ++ err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); ++ platform_device_unregister(pdev); ++ if (err) { ++ printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", ++ fw_name); ++ } else if (rdev->me_fw->size % 8) { ++ printk(KERN_ERR ++ "radeon_cp: Bogus length %zu in firmware \"%s\"\n", ++ rdev->me_fw->size, fw_name); ++ err = -EINVAL; ++ release_firmware(rdev->me_fw); ++ rdev->me_fw = NULL; ++ } ++ return err; ++} ++static void r100_cp_load_microcode(struct radeon_device *rdev) ++{ ++ const __be32 *fw_data; ++ int i, size; ++ ++ if (r100_gui_wait_for_idle(rdev)) { ++ printk(KERN_WARNING "Failed to wait GUI idle while " ++ "programming pipes. Bad things might happen.\n"); ++ } ++ ++ if (rdev->me_fw) { ++ size = rdev->me_fw->size / 4; ++ fw_data = (const __be32 *)&rdev->me_fw->data[0]; ++ WREG32(RADEON_CP_ME_RAM_ADDR, 0); ++ for (i = 0; i < size; i += 2) { ++ WREG32(RADEON_CP_ME_RAM_DATAH, ++ be32_to_cpup(&fw_data[i])); ++ WREG32(RADEON_CP_ME_RAM_DATAL, ++ be32_to_cpup(&fw_data[i + 1])); + } + } + } +@@ -585,6 +669,15 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) + } else { + DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); + } ++ ++ if (!rdev->me_fw) { ++ r = r100_cp_init_microcode(rdev); ++ if (r) { ++ DRM_ERROR("Failed to load firmware!\n"); ++ return r; ++ } ++ } ++ + /* Align ring size */ + rb_bufsz = drm_order(ring_size / 8); + ring_size = (1 << (rb_bufsz + 1)) * 4; +@@ -658,9 +751,11 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) + + void r100_cp_fini(struct radeon_device *rdev) + { ++ if (r100_cp_wait_for_idle(rdev)) { ++ DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); ++ } + /* Disable ring */ +- rdev->cp.ready = false; +- WREG32(RADEON_CP_CSQ_CNTL, 0); ++ r100_cp_disable(rdev); + radeon_ring_fini(rdev); + DRM_INFO("radeon: cp finalized\n"); + } +@@ -710,6 +805,12 @@ int r100_cp_reset(struct radeon_device *rdev) + return -1; + } + ++void r100_cp_commit(struct radeon_device *rdev) ++{ ++ WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); ++ (void)RREG32(RADEON_CP_RB_WPTR); ++} ++ + + /* + * CS functions +@@ -762,13 +863,11 @@ int r100_cs_parse_packet0(struct radeon_cs_parser *p, + void r100_cs_dump_packet(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt) + { +- struct radeon_cs_chunk *ib_chunk; + volatile uint32_t *ib; + unsigned i; + unsigned idx; + + ib = p->ib->ptr; +- ib_chunk = &p->chunks[p->chunk_ib_idx]; + idx = pkt->idx; + for (i = 0; i <= (pkt->count + 1); i++, idx++) { + DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); +@@ -795,7 +894,7 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p, + idx, ib_chunk->length_dw); + return -EINVAL; + } +- header = ib_chunk->kdata[idx]; ++ header = radeon_get_ib_value(p, idx); + pkt->idx = idx; + pkt->type = CP_PACKET_GET_TYPE(header); + pkt->count = CP_PACKET_GET_COUNT(header); +@@ -838,7 +937,6 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p, + */ + int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) + { +- struct radeon_cs_chunk *ib_chunk; + struct drm_mode_object *obj; + struct drm_crtc *crtc; + struct radeon_crtc *radeon_crtc; +@@ -846,8 +944,9 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) + int crtc_id; + int r; + uint32_t header, h_idx, reg; ++ volatile uint32_t *ib; + +- ib_chunk = &p->chunks[p->chunk_ib_idx]; ++ ib = p->ib->ptr; + + /* parse the wait until */ + r = r100_cs_packet_parse(p, &waitreloc, p->idx); +@@ -862,24 +961,24 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) + return r; + } + +- if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) { ++ if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { + DRM_ERROR("vline wait had illegal wait until\n"); + r = -EINVAL; + return r; + } + + /* jump over the NOP */ +- r = r100_cs_packet_parse(p, &p3reloc, p->idx); ++ r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); + if (r) + return r; + + h_idx = p->idx - 2; +- p->idx += waitreloc.count; +- p->idx += p3reloc.count; ++ p->idx += waitreloc.count + 2; ++ p->idx += p3reloc.count + 2; + +- header = ib_chunk->kdata[h_idx]; +- crtc_id = ib_chunk->kdata[h_idx + 5]; +- reg = ib_chunk->kdata[h_idx] >> 2; ++ header = radeon_get_ib_value(p, h_idx); ++ crtc_id = radeon_get_ib_value(p, h_idx + 5); ++ reg = header >> 2; + mutex_lock(&p->rdev->ddev->mode_config.mutex); + obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); + if (!obj) { +@@ -893,16 +992,16 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) + + if (!crtc->enabled) { + /* if the CRTC isn't enabled - we need to nop out the wait until */ +- ib_chunk->kdata[h_idx + 2] = PACKET2(0); +- ib_chunk->kdata[h_idx + 3] = PACKET2(0); ++ ib[h_idx + 2] = PACKET2(0); ++ ib[h_idx + 3] = PACKET2(0); + } else if (crtc_id == 1) { + switch (reg) { + case AVIVO_D1MODE_VLINE_START_END: +- header &= R300_CP_PACKET0_REG_MASK; ++ header &= ~R300_CP_PACKET0_REG_MASK; + header |= AVIVO_D2MODE_VLINE_START_END >> 2; + break; + case RADEON_CRTC_GUI_TRIG_VLINE: +- header &= R300_CP_PACKET0_REG_MASK; ++ header &= ~R300_CP_PACKET0_REG_MASK; + header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; + break; + default: +@@ -910,8 +1009,8 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) + r = -EINVAL; + goto out; + } +- ib_chunk->kdata[h_idx] = header; +- ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; ++ ib[h_idx] = header; ++ ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; + } + out: + mutex_unlock(&p->rdev->ddev->mode_config.mutex); +@@ -932,7 +1031,6 @@ out: + int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc) + { +- struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_chunk *relocs_chunk; + struct radeon_cs_packet p3reloc; + unsigned idx; +@@ -943,7 +1041,6 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, + return -EINVAL; + } + *cs_reloc = NULL; +- ib_chunk = &p->chunks[p->chunk_ib_idx]; + relocs_chunk = &p->chunks[p->chunk_relocs_idx]; + r = r100_cs_packet_parse(p, &p3reloc, p->idx); + if (r) { +@@ -956,7 +1053,7 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, + r100_cs_dump_packet(p, &p3reloc); + return -EINVAL; + } +- idx = ib_chunk->kdata[p3reloc.idx + 1]; ++ idx = radeon_get_ib_value(p, p3reloc.idx + 1); + if (idx >= relocs_chunk->length_dw) { + DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", + idx, relocs_chunk->length_dw); +@@ -968,147 +1065,357 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, + return 0; + } + ++static int r100_get_vtx_size(uint32_t vtx_fmt) ++{ ++ int vtx_size; ++ vtx_size = 2; ++ /* ordered according to bits in spec */ ++ if (vtx_fmt & RADEON_SE_VTX_FMT_W0) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) ++ vtx_size += 3; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) ++ vtx_size += 3; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) ++ vtx_size += 2; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) ++ vtx_size += 2; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) ++ vtx_size += 2; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) ++ vtx_size += 2; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) ++ vtx_size++; ++ /* blend weight */ ++ if (vtx_fmt & (0x7 << 15)) ++ vtx_size += (vtx_fmt >> 15) & 0x7; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_N0) ++ vtx_size += 3; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) ++ vtx_size += 2; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_W1) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_N1) ++ vtx_size++; ++ if (vtx_fmt & RADEON_SE_VTX_FMT_Z) ++ vtx_size++; ++ return vtx_size; ++} ++ + static int r100_packet0_check(struct radeon_cs_parser *p, +- struct radeon_cs_packet *pkt) ++ struct radeon_cs_packet *pkt, ++ unsigned idx, unsigned reg) + { +- struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; ++ struct r100_cs_track *track; + volatile uint32_t *ib; + uint32_t tmp; +- unsigned reg; +- unsigned i; +- unsigned idx; +- bool onereg; + int r; ++ int i, face; + u32 tile_flags = 0; ++ u32 idx_value; + + ib = p->ib->ptr; +- ib_chunk = &p->chunks[p->chunk_ib_idx]; +- idx = pkt->idx + 1; +- reg = pkt->reg; +- onereg = false; +- if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) { +- onereg = true; +- } +- for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { +- switch (reg) { +- case RADEON_CRTC_GUI_TRIG_VLINE: +- r = r100_cs_packet_parse_vline(p); +- if (r) { +- DRM_ERROR("No reloc for ib[%d]=0x%04X\n", +- idx, reg); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- break; ++ track = (struct r100_cs_track *)p->track; ++ ++ idx_value = radeon_get_ib_value(p, idx); ++ ++ switch (reg) { ++ case RADEON_CRTC_GUI_TRIG_VLINE: ++ r = r100_cs_packet_parse_vline(p); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ break; + /* FIXME: only allow PACKET3 blit? easier to check for out of + * range access */ +- case RADEON_DST_PITCH_OFFSET: +- case RADEON_SRC_PITCH_OFFSET: +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for ib[%d]=0x%04X\n", +- idx, reg); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- tmp = ib_chunk->kdata[idx] & 0x003fffff; +- tmp += (((u32)reloc->lobj.gpu_offset) >> 10); +- +- if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) +- tile_flags |= RADEON_DST_TILE_MACRO; +- if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { +- if (reg == RADEON_SRC_PITCH_OFFSET) { +- DRM_ERROR("Cannot src blit from microtiled surface\n"); +- r100_cs_dump_packet(p, pkt); +- return -EINVAL; +- } +- tile_flags |= RADEON_DST_TILE_MICRO; +- } ++ case RADEON_DST_PITCH_OFFSET: ++ case RADEON_SRC_PITCH_OFFSET: ++ r = r100_reloc_pitch_offset(p, pkt, idx, reg); ++ if (r) ++ return r; ++ break; ++ case RADEON_RB3D_DEPTHOFFSET: ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ track->zb.robj = reloc->robj; ++ track->zb.offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ break; ++ case RADEON_RB3D_COLOROFFSET: ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ track->cb[0].robj = reloc->robj; ++ track->cb[0].offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ break; ++ case RADEON_PP_TXOFFSET_0: ++ case RADEON_PP_TXOFFSET_1: ++ case RADEON_PP_TXOFFSET_2: ++ i = (reg - RADEON_PP_TXOFFSET_0) / 24; ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ track->textures[i].robj = reloc->robj; ++ break; ++ case RADEON_PP_CUBIC_OFFSET_T0_0: ++ case RADEON_PP_CUBIC_OFFSET_T0_1: ++ case RADEON_PP_CUBIC_OFFSET_T0_2: ++ case RADEON_PP_CUBIC_OFFSET_T0_3: ++ case RADEON_PP_CUBIC_OFFSET_T0_4: ++ i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ track->textures[0].cube_info[i].offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ track->textures[0].cube_info[i].robj = reloc->robj; ++ break; ++ case RADEON_PP_CUBIC_OFFSET_T1_0: ++ case RADEON_PP_CUBIC_OFFSET_T1_1: ++ case RADEON_PP_CUBIC_OFFSET_T1_2: ++ case RADEON_PP_CUBIC_OFFSET_T1_3: ++ case RADEON_PP_CUBIC_OFFSET_T1_4: ++ i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ track->textures[1].cube_info[i].offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ track->textures[1].cube_info[i].robj = reloc->robj; ++ break; ++ case RADEON_PP_CUBIC_OFFSET_T2_0: ++ case RADEON_PP_CUBIC_OFFSET_T2_1: ++ case RADEON_PP_CUBIC_OFFSET_T2_2: ++ case RADEON_PP_CUBIC_OFFSET_T2_3: ++ case RADEON_PP_CUBIC_OFFSET_T2_4: ++ i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ track->textures[2].cube_info[i].offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ track->textures[2].cube_info[i].robj = reloc->robj; ++ break; ++ case RADEON_RE_WIDTH_HEIGHT: ++ track->maxy = ((idx_value >> 16) & 0x7FF); ++ break; ++ case RADEON_RB3D_COLORPITCH: ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } + +- tmp |= tile_flags; +- ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; +- break; +- case RADEON_RB3D_DEPTHOFFSET: +- case RADEON_RB3D_COLOROFFSET: +- case R300_RB3D_COLOROFFSET0: +- case R300_ZB_DEPTHOFFSET: +- case R200_PP_TXOFFSET_0: +- case R200_PP_TXOFFSET_1: +- case R200_PP_TXOFFSET_2: +- case R200_PP_TXOFFSET_3: +- case R200_PP_TXOFFSET_4: +- case R200_PP_TXOFFSET_5: +- case RADEON_PP_TXOFFSET_0: +- case RADEON_PP_TXOFFSET_1: +- case RADEON_PP_TXOFFSET_2: +- case R300_TX_OFFSET_0: +- case R300_TX_OFFSET_0+4: +- case R300_TX_OFFSET_0+8: +- case R300_TX_OFFSET_0+12: +- case R300_TX_OFFSET_0+16: +- case R300_TX_OFFSET_0+20: +- case R300_TX_OFFSET_0+24: +- case R300_TX_OFFSET_0+28: +- case R300_TX_OFFSET_0+32: +- case R300_TX_OFFSET_0+36: +- case R300_TX_OFFSET_0+40: +- case R300_TX_OFFSET_0+44: +- case R300_TX_OFFSET_0+48: +- case R300_TX_OFFSET_0+52: +- case R300_TX_OFFSET_0+56: +- case R300_TX_OFFSET_0+60: +- /* rn50 has no 3D engine so fail on any 3d setup */ +- if (ASIC_IS_RN50(p->rdev)) { +- DRM_ERROR("attempt to use RN50 3D engine failed\n"); +- return -EINVAL; +- } +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for ib[%d]=0x%04X\n", +- idx, reg); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); +- break; +- case R300_RB3D_COLORPITCH0: +- case RADEON_RB3D_COLORPITCH: +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for ib[%d]=0x%04X\n", +- idx, reg); +- r100_cs_dump_packet(p, pkt); +- return r; +- } ++ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) ++ tile_flags |= RADEON_COLOR_TILE_ENABLE; ++ if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) ++ tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; + +- if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) +- tile_flags |= RADEON_COLOR_TILE_ENABLE; +- if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) +- tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; ++ tmp = idx_value & ~(0x7 << 16); ++ tmp |= tile_flags; ++ ib[idx] = tmp; + +- tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); +- tmp |= tile_flags; +- ib[idx] = tmp; ++ track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; ++ break; ++ case RADEON_RB3D_DEPTHPITCH: ++ track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; ++ break; ++ case RADEON_RB3D_CNTL: ++ switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { ++ case 7: ++ case 8: ++ case 9: ++ case 11: ++ case 12: ++ track->cb[0].cpp = 1; + break; +- case RADEON_RB3D_ZPASS_ADDR: +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for ib[%d]=0x%04X\n", +- idx, reg); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); ++ case 3: ++ case 4: ++ case 15: ++ track->cb[0].cpp = 2; ++ break; ++ case 6: ++ track->cb[0].cpp = 4; ++ break; ++ default: ++ DRM_ERROR("Invalid color buffer format (%d) !\n", ++ ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); ++ return -EINVAL; ++ } ++ track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); ++ break; ++ case RADEON_RB3D_ZSTENCILCNTL: ++ switch (idx_value & 0xf) { ++ case 0: ++ track->zb.cpp = 2; ++ break; ++ case 2: ++ case 3: ++ case 4: ++ case 5: ++ case 9: ++ case 11: ++ track->zb.cpp = 4; + break; + default: +- /* FIXME: we don't want to allow anyothers packet */ + break; + } +- if (onereg) { +- /* FIXME: forbid onereg write to register on relocate */ ++ break; ++ case RADEON_RB3D_ZPASS_ADDR: ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ break; ++ case RADEON_PP_CNTL: ++ { ++ uint32_t temp = idx_value >> 4; ++ for (i = 0; i < track->num_texture; i++) ++ track->textures[i].enabled = !!(temp & (1 << i)); ++ } ++ break; ++ case RADEON_SE_VF_CNTL: ++ track->vap_vf_cntl = idx_value; ++ break; ++ case RADEON_SE_VTX_FMT: ++ track->vtx_size = r100_get_vtx_size(idx_value); ++ break; ++ case RADEON_PP_TEX_SIZE_0: ++ case RADEON_PP_TEX_SIZE_1: ++ case RADEON_PP_TEX_SIZE_2: ++ i = (reg - RADEON_PP_TEX_SIZE_0) / 8; ++ track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; ++ track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; ++ break; ++ case RADEON_PP_TEX_PITCH_0: ++ case RADEON_PP_TEX_PITCH_1: ++ case RADEON_PP_TEX_PITCH_2: ++ i = (reg - RADEON_PP_TEX_PITCH_0) / 8; ++ track->textures[i].pitch = idx_value + 32; ++ break; ++ case RADEON_PP_TXFILTER_0: ++ case RADEON_PP_TXFILTER_1: ++ case RADEON_PP_TXFILTER_2: ++ i = (reg - RADEON_PP_TXFILTER_0) / 24; ++ track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) ++ >> RADEON_MAX_MIP_LEVEL_SHIFT); ++ tmp = (idx_value >> 23) & 0x7; ++ if (tmp == 2 || tmp == 6) ++ track->textures[i].roundup_w = false; ++ tmp = (idx_value >> 27) & 0x7; ++ if (tmp == 2 || tmp == 6) ++ track->textures[i].roundup_h = false; ++ break; ++ case RADEON_PP_TXFORMAT_0: ++ case RADEON_PP_TXFORMAT_1: ++ case RADEON_PP_TXFORMAT_2: ++ i = (reg - RADEON_PP_TXFORMAT_0) / 24; ++ if (idx_value & RADEON_TXFORMAT_NON_POWER2) { ++ track->textures[i].use_pitch = 1; ++ } else { ++ track->textures[i].use_pitch = 0; ++ track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); ++ track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); ++ } ++ if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) ++ track->textures[i].tex_coord_type = 2; ++ switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { ++ case RADEON_TXFORMAT_I8: ++ case RADEON_TXFORMAT_RGB332: ++ case RADEON_TXFORMAT_Y8: ++ track->textures[i].cpp = 1; ++ break; ++ case RADEON_TXFORMAT_AI88: ++ case RADEON_TXFORMAT_ARGB1555: ++ case RADEON_TXFORMAT_RGB565: ++ case RADEON_TXFORMAT_ARGB4444: ++ case RADEON_TXFORMAT_VYUY422: ++ case RADEON_TXFORMAT_YVYU422: ++ case RADEON_TXFORMAT_DXT1: ++ case RADEON_TXFORMAT_SHADOW16: ++ case RADEON_TXFORMAT_LDUDV655: ++ case RADEON_TXFORMAT_DUDV88: ++ track->textures[i].cpp = 2; ++ break; ++ case RADEON_TXFORMAT_ARGB8888: ++ case RADEON_TXFORMAT_RGBA8888: ++ case RADEON_TXFORMAT_DXT23: ++ case RADEON_TXFORMAT_DXT45: ++ case RADEON_TXFORMAT_SHADOW32: ++ case RADEON_TXFORMAT_LDUDUV8888: ++ track->textures[i].cpp = 4; + break; + } ++ track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); ++ track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); ++ break; ++ case RADEON_PP_CUBIC_FACES_0: ++ case RADEON_PP_CUBIC_FACES_1: ++ case RADEON_PP_CUBIC_FACES_2: ++ tmp = idx_value; ++ i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; ++ for (face = 0; face < 4; face++) { ++ track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); ++ track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); ++ } ++ break; ++ default: ++ printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", ++ reg, idx); ++ return -EINVAL; + } + return 0; + } +@@ -1117,15 +1424,14 @@ int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + struct radeon_object *robj) + { +- struct radeon_cs_chunk *ib_chunk; + unsigned idx; +- +- ib_chunk = &p->chunks[p->chunk_ib_idx]; ++ u32 value; + idx = pkt->idx + 1; +- if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) { ++ value = radeon_get_ib_value(p, idx + 2); ++ if ((value + 1) > radeon_object_size(robj)) { + DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " + "(need %u have %lu) !\n", +- ib_chunk->kdata[idx+2] + 1, ++ value + 1, + radeon_object_size(robj)); + return -EINVAL; + } +@@ -1135,47 +1441,20 @@ int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, + static int r100_packet3_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt) + { +- struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; ++ struct r100_cs_track *track; + unsigned idx; +- unsigned i, c; + volatile uint32_t *ib; + int r; + + ib = p->ib->ptr; +- ib_chunk = &p->chunks[p->chunk_ib_idx]; + idx = pkt->idx + 1; ++ track = (struct r100_cs_track *)p->track; + switch (pkt->opcode) { + case PACKET3_3D_LOAD_VBPNTR: +- c = ib_chunk->kdata[idx++]; +- for (i = 0; i < (c - 1); i += 2, idx += 3) { +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for packet3 %d\n", +- pkt->opcode); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for packet3 %d\n", +- pkt->opcode); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); +- } +- if (c & 1) { +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for packet3 %d\n", +- pkt->opcode); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); +- } ++ r = r100_packet3_load_vbpntr(p, pkt, idx); ++ if (r) ++ return r; + break; + case PACKET3_INDX_BUFFER: + r = r100_cs_packet_next_reloc(p, &reloc); +@@ -1184,14 +1463,13 @@ static int r100_packet3_check(struct radeon_cs_parser *p, + r100_cs_dump_packet(p, pkt); + return r; + } +- ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); ++ ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); + r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); + if (r) { + return r; + } + break; + case 0x23: +- /* FIXME: cleanup */ + /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { +@@ -1199,19 +1477,72 @@ static int r100_packet3_check(struct radeon_cs_parser *p, + r100_cs_dump_packet(p, pkt); + return r; + } +- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); ++ ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); ++ track->num_arrays = 1; ++ track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); ++ ++ track->arrays[0].robj = reloc->robj; ++ track->arrays[0].esize = track->vtx_size; ++ ++ track->max_indx = radeon_get_ib_value(p, idx+1); ++ ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); ++ track->immd_dwords = pkt->count - 1; ++ r = r100_cs_track_check(p->rdev, track); ++ if (r) ++ return r; + break; + case PACKET3_3D_DRAW_IMMD: ++ if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { ++ DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); ++ return -EINVAL; ++ } ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); ++ track->immd_dwords = pkt->count - 1; ++ r = r100_cs_track_check(p->rdev, track); ++ if (r) ++ return r; ++ break; + /* triggers drawing using in-packet vertex data */ + case PACKET3_3D_DRAW_IMMD_2: ++ if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { ++ DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); ++ return -EINVAL; ++ } ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx); ++ track->immd_dwords = pkt->count; ++ r = r100_cs_track_check(p->rdev, track); ++ if (r) ++ return r; ++ break; + /* triggers drawing using in-packet vertex data */ + case PACKET3_3D_DRAW_VBUF_2: ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx); ++ r = r100_cs_track_check(p->rdev, track); ++ if (r) ++ return r; ++ break; + /* triggers drawing of vertex buffers setup elsewhere */ + case PACKET3_3D_DRAW_INDX_2: ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx); ++ r = r100_cs_track_check(p->rdev, track); ++ if (r) ++ return r; ++ break; + /* triggers drawing using indices to vertex buffer */ + case PACKET3_3D_DRAW_VBUF: ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); ++ r = r100_cs_track_check(p->rdev, track); ++ if (r) ++ return r; ++ break; + /* triggers drawing of vertex buffers setup elsewhere */ + case PACKET3_3D_DRAW_INDX: ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); ++ r = r100_cs_track_check(p->rdev, track); ++ if (r) ++ return r; ++ break; + /* triggers drawing using indices to vertex buffer */ + case PACKET3_NOP: + break; +@@ -1225,8 +1556,12 @@ static int r100_packet3_check(struct radeon_cs_parser *p, + int r100_cs_parse(struct radeon_cs_parser *p) + { + struct radeon_cs_packet pkt; ++ struct r100_cs_track *track; + int r; + ++ track = kzalloc(sizeof(*track), GFP_KERNEL); ++ r100_cs_track_clear(p->rdev, track); ++ p->track = track; + do { + r = r100_cs_packet_parse(p, &pkt, p->idx); + if (r) { +@@ -1235,7 +1570,16 @@ int r100_cs_parse(struct radeon_cs_parser *p) + p->idx += pkt.count + 2; + switch (pkt.type) { + case PACKET_TYPE0: +- r = r100_packet0_check(p, &pkt); ++ if (p->rdev->family >= CHIP_R200) ++ r = r100_cs_parse_packet0(p, &pkt, ++ p->rdev->config.r100.reg_safe_bm, ++ p->rdev->config.r100.reg_safe_bm_size, ++ &r200_packet0_check); ++ else ++ r = r100_cs_parse_packet0(p, &pkt, ++ p->rdev->config.r100.reg_safe_bm, ++ p->rdev->config.r100.reg_safe_bm_size, ++ &r100_packet0_check); + break; + case PACKET_TYPE2: + break; +@@ -1634,6 +1978,15 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) + + int r100_init(struct radeon_device *rdev) + { ++ if (ASIC_IS_RN50(rdev)) { ++ rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; ++ rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); ++ } else if (rdev->family < CHIP_R200) { ++ rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; ++ rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); ++ } else { ++ return r200_init(rdev); ++ } + return 0; + } + +@@ -1839,6 +2192,11 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg, + flags |= R300_SURF_TILE_MICRO; + } + ++ if (tiling_flags & RADEON_TILING_SWAP_16BIT) ++ flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; ++ if (tiling_flags & RADEON_TILING_SWAP_32BIT) ++ flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; ++ + DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); + WREG32(RADEON_SURFACE0_INFO + surf_index, flags); + WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); +@@ -2334,3 +2692,460 @@ void r100_bandwidth_update(struct radeon_device *rdev) + (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); + } + } ++ ++static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) ++{ ++ DRM_ERROR("pitch %d\n", t->pitch); ++ DRM_ERROR("width %d\n", t->width); ++ DRM_ERROR("height %d\n", t->height); ++ DRM_ERROR("num levels %d\n", t->num_levels); ++ DRM_ERROR("depth %d\n", t->txdepth); ++ DRM_ERROR("bpp %d\n", t->cpp); ++ DRM_ERROR("coordinate type %d\n", t->tex_coord_type); ++ DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); ++ DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); ++} ++ ++static int r100_cs_track_cube(struct radeon_device *rdev, ++ struct r100_cs_track *track, unsigned idx) ++{ ++ unsigned face, w, h; ++ struct radeon_object *cube_robj; ++ unsigned long size; ++ ++ for (face = 0; face < 5; face++) { ++ cube_robj = track->textures[idx].cube_info[face].robj; ++ w = track->textures[idx].cube_info[face].width; ++ h = track->textures[idx].cube_info[face].height; ++ ++ size = w * h; ++ size *= track->textures[idx].cpp; ++ ++ size += track->textures[idx].cube_info[face].offset; ++ ++ if (size > radeon_object_size(cube_robj)) { ++ DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", ++ size, radeon_object_size(cube_robj)); ++ r100_cs_track_texture_print(&track->textures[idx]); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++static int r100_cs_track_texture_check(struct radeon_device *rdev, ++ struct r100_cs_track *track) ++{ ++ struct radeon_object *robj; ++ unsigned long size; ++ unsigned u, i, w, h; ++ int ret; ++ ++ for (u = 0; u < track->num_texture; u++) { ++ if (!track->textures[u].enabled) ++ continue; ++ robj = track->textures[u].robj; ++ if (robj == NULL) { ++ DRM_ERROR("No texture bound to unit %u\n", u); ++ return -EINVAL; ++ } ++ size = 0; ++ for (i = 0; i <= track->textures[u].num_levels; i++) { ++ if (track->textures[u].use_pitch) { ++ if (rdev->family < CHIP_R300) ++ w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); ++ else ++ w = track->textures[u].pitch / (1 << i); ++ } else { ++ w = track->textures[u].width / (1 << i); ++ if (rdev->family >= CHIP_RV515) ++ w |= track->textures[u].width_11; ++ if (track->textures[u].roundup_w) ++ w = roundup_pow_of_two(w); ++ } ++ h = track->textures[u].height / (1 << i); ++ if (rdev->family >= CHIP_RV515) ++ h |= track->textures[u].height_11; ++ if (track->textures[u].roundup_h) ++ h = roundup_pow_of_two(h); ++ size += w * h; ++ } ++ size *= track->textures[u].cpp; ++ switch (track->textures[u].tex_coord_type) { ++ case 0: ++ break; ++ case 1: ++ size *= (1 << track->textures[u].txdepth); ++ break; ++ case 2: ++ if (track->separate_cube) { ++ ret = r100_cs_track_cube(rdev, track, u); ++ if (ret) ++ return ret; ++ } else ++ size *= 6; ++ break; ++ default: ++ DRM_ERROR("Invalid texture coordinate type %u for unit " ++ "%u\n", track->textures[u].tex_coord_type, u); ++ return -EINVAL; ++ } ++ if (size > radeon_object_size(robj)) { ++ DRM_ERROR("Texture of unit %u needs %lu bytes but is " ++ "%lu\n", u, size, radeon_object_size(robj)); ++ r100_cs_track_texture_print(&track->textures[u]); ++ return -EINVAL; ++ } ++ } ++ return 0; ++} ++ ++int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) ++{ ++ unsigned i; ++ unsigned long size; ++ unsigned prim_walk; ++ unsigned nverts; ++ ++ for (i = 0; i < track->num_cb; i++) { ++ if (track->cb[i].robj == NULL) { ++ DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); ++ return -EINVAL; ++ } ++ size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; ++ size += track->cb[i].offset; ++ if (size > radeon_object_size(track->cb[i].robj)) { ++ DRM_ERROR("[drm] Buffer too small for color buffer %d " ++ "(need %lu have %lu) !\n", i, size, ++ radeon_object_size(track->cb[i].robj)); ++ DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", ++ i, track->cb[i].pitch, track->cb[i].cpp, ++ track->cb[i].offset, track->maxy); ++ return -EINVAL; ++ } ++ } ++ if (track->z_enabled) { ++ if (track->zb.robj == NULL) { ++ DRM_ERROR("[drm] No buffer for z buffer !\n"); ++ return -EINVAL; ++ } ++ size = track->zb.pitch * track->zb.cpp * track->maxy; ++ size += track->zb.offset; ++ if (size > radeon_object_size(track->zb.robj)) { ++ DRM_ERROR("[drm] Buffer too small for z buffer " ++ "(need %lu have %lu) !\n", size, ++ radeon_object_size(track->zb.robj)); ++ DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", ++ track->zb.pitch, track->zb.cpp, ++ track->zb.offset, track->maxy); ++ return -EINVAL; ++ } ++ } ++ prim_walk = (track->vap_vf_cntl >> 4) & 0x3; ++ nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; ++ switch (prim_walk) { ++ case 1: ++ for (i = 0; i < track->num_arrays; i++) { ++ size = track->arrays[i].esize * track->max_indx * 4; ++ if (track->arrays[i].robj == NULL) { ++ DRM_ERROR("(PW %u) Vertex array %u no buffer " ++ "bound\n", prim_walk, i); ++ return -EINVAL; ++ } ++ if (size > radeon_object_size(track->arrays[i].robj)) { ++ DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " ++ "have %lu dwords\n", prim_walk, i, ++ size >> 2, ++ radeon_object_size(track->arrays[i].robj) >> 2); ++ DRM_ERROR("Max indices %u\n", track->max_indx); ++ return -EINVAL; ++ } ++ } ++ break; ++ case 2: ++ for (i = 0; i < track->num_arrays; i++) { ++ size = track->arrays[i].esize * (nverts - 1) * 4; ++ if (track->arrays[i].robj == NULL) { ++ DRM_ERROR("(PW %u) Vertex array %u no buffer " ++ "bound\n", prim_walk, i); ++ return -EINVAL; ++ } ++ if (size > radeon_object_size(track->arrays[i].robj)) { ++ DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " ++ "have %lu dwords\n", prim_walk, i, size >> 2, ++ radeon_object_size(track->arrays[i].robj) >> 2); ++ return -EINVAL; ++ } ++ } ++ break; ++ case 3: ++ size = track->vtx_size * nverts; ++ if (size != track->immd_dwords) { ++ DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", ++ track->immd_dwords, size); ++ DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", ++ nverts, track->vtx_size); ++ return -EINVAL; ++ } ++ break; ++ default: ++ DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", ++ prim_walk); ++ return -EINVAL; ++ } ++ return r100_cs_track_texture_check(rdev, track); ++} ++ ++void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) ++{ ++ unsigned i, face; ++ ++ if (rdev->family < CHIP_R300) { ++ track->num_cb = 1; ++ if (rdev->family <= CHIP_RS200) ++ track->num_texture = 3; ++ else ++ track->num_texture = 6; ++ track->maxy = 2048; ++ track->separate_cube = 1; ++ } else { ++ track->num_cb = 4; ++ track->num_texture = 16; ++ track->maxy = 4096; ++ track->separate_cube = 0; ++ } ++ ++ for (i = 0; i < track->num_cb; i++) { ++ track->cb[i].robj = NULL; ++ track->cb[i].pitch = 8192; ++ track->cb[i].cpp = 16; ++ track->cb[i].offset = 0; ++ } ++ track->z_enabled = true; ++ track->zb.robj = NULL; ++ track->zb.pitch = 8192; ++ track->zb.cpp = 4; ++ track->zb.offset = 0; ++ track->vtx_size = 0x7F; ++ track->immd_dwords = 0xFFFFFFFFUL; ++ track->num_arrays = 11; ++ track->max_indx = 0x00FFFFFFUL; ++ for (i = 0; i < track->num_arrays; i++) { ++ track->arrays[i].robj = NULL; ++ track->arrays[i].esize = 0x7F; ++ } ++ for (i = 0; i < track->num_texture; i++) { ++ track->textures[i].pitch = 16536; ++ track->textures[i].width = 16536; ++ track->textures[i].height = 16536; ++ track->textures[i].width_11 = 1 << 11; ++ track->textures[i].height_11 = 1 << 11; ++ track->textures[i].num_levels = 12; ++ if (rdev->family <= CHIP_RS200) { ++ track->textures[i].tex_coord_type = 0; ++ track->textures[i].txdepth = 0; ++ } else { ++ track->textures[i].txdepth = 16; ++ track->textures[i].tex_coord_type = 1; ++ } ++ track->textures[i].cpp = 64; ++ track->textures[i].robj = NULL; ++ /* CS IB emission code makes sure texture unit are disabled */ ++ track->textures[i].enabled = false; ++ track->textures[i].roundup_w = true; ++ track->textures[i].roundup_h = true; ++ if (track->separate_cube) ++ for (face = 0; face < 5; face++) { ++ track->textures[i].cube_info[face].robj = NULL; ++ track->textures[i].cube_info[face].width = 16536; ++ track->textures[i].cube_info[face].height = 16536; ++ track->textures[i].cube_info[face].offset = 0; ++ } ++ } ++} ++ ++int r100_ring_test(struct radeon_device *rdev) ++{ ++ uint32_t scratch; ++ uint32_t tmp = 0; ++ unsigned i; ++ int r; ++ ++ r = radeon_scratch_get(rdev, &scratch); ++ if (r) { ++ DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); ++ return r; ++ } ++ WREG32(scratch, 0xCAFEDEAD); ++ r = radeon_ring_lock(rdev, 2); ++ if (r) { ++ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); ++ radeon_scratch_free(rdev, scratch); ++ return r; ++ } ++ radeon_ring_write(rdev, PACKET0(scratch, 0)); ++ radeon_ring_write(rdev, 0xDEADBEEF); ++ radeon_ring_unlock_commit(rdev); ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ tmp = RREG32(scratch); ++ if (tmp == 0xDEADBEEF) { ++ break; ++ } ++ DRM_UDELAY(1); ++ } ++ if (i < rdev->usec_timeout) { ++ DRM_INFO("ring test succeeded in %d usecs\n", i); ++ } else { ++ DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", ++ scratch, tmp); ++ r = -EINVAL; ++ } ++ radeon_scratch_free(rdev, scratch); ++ return r; ++} ++ ++void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) ++{ ++ radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); ++ radeon_ring_write(rdev, ib->gpu_addr); ++ radeon_ring_write(rdev, ib->length_dw); ++} ++ ++int r100_ib_test(struct radeon_device *rdev) ++{ ++ struct radeon_ib *ib; ++ uint32_t scratch; ++ uint32_t tmp = 0; ++ unsigned i; ++ int r; ++ ++ r = radeon_scratch_get(rdev, &scratch); ++ if (r) { ++ DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); ++ return r; ++ } ++ WREG32(scratch, 0xCAFEDEAD); ++ r = radeon_ib_get(rdev, &ib); ++ if (r) { ++ return r; ++ } ++ ib->ptr[0] = PACKET0(scratch, 0); ++ ib->ptr[1] = 0xDEADBEEF; ++ ib->ptr[2] = PACKET2(0); ++ ib->ptr[3] = PACKET2(0); ++ ib->ptr[4] = PACKET2(0); ++ ib->ptr[5] = PACKET2(0); ++ ib->ptr[6] = PACKET2(0); ++ ib->ptr[7] = PACKET2(0); ++ ib->length_dw = 8; ++ r = radeon_ib_schedule(rdev, ib); ++ if (r) { ++ radeon_scratch_free(rdev, scratch); ++ radeon_ib_free(rdev, &ib); ++ return r; ++ } ++ r = radeon_fence_wait(ib->fence, false); ++ if (r) { ++ return r; ++ } ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ tmp = RREG32(scratch); ++ if (tmp == 0xDEADBEEF) { ++ break; ++ } ++ DRM_UDELAY(1); ++ } ++ if (i < rdev->usec_timeout) { ++ DRM_INFO("ib test succeeded in %u usecs\n", i); ++ } else { ++ DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", ++ scratch, tmp); ++ r = -EINVAL; ++ } ++ radeon_scratch_free(rdev, scratch); ++ radeon_ib_free(rdev, &ib); ++ return r; ++} ++ ++void r100_ib_fini(struct radeon_device *rdev) ++{ ++ radeon_ib_pool_fini(rdev); ++} ++ ++int r100_ib_init(struct radeon_device *rdev) ++{ ++ int r; ++ ++ r = radeon_ib_pool_init(rdev); ++ if (r) { ++ dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r); ++ r100_ib_fini(rdev); ++ return r; ++ } ++ r = r100_ib_test(rdev); ++ if (r) { ++ dev_err(rdev->dev, "failled testing IB (%d).\n", r); ++ r100_ib_fini(rdev); ++ return r; ++ } ++ return 0; ++} ++ ++void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) ++{ ++ /* Shutdown CP we shouldn't need to do that but better be safe than ++ * sorry ++ */ ++ rdev->cp.ready = false; ++ WREG32(R_000740_CP_CSQ_CNTL, 0); ++ ++ /* Save few CRTC registers */ ++ save->GENMO_WT = RREG32(R_0003C0_GENMO_WT); ++ save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); ++ save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); ++ save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); ++ if (!(rdev->flags & RADEON_SINGLE_CRTC)) { ++ save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); ++ save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); ++ } ++ ++ /* Disable VGA aperture access */ ++ WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT); ++ /* Disable cursor, overlay, crtc */ ++ WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); ++ WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | ++ S_000054_CRTC_DISPLAY_DIS(1)); ++ WREG32(R_000050_CRTC_GEN_CNTL, ++ (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | ++ S_000050_CRTC_DISP_REQ_EN_B(1)); ++ WREG32(R_000420_OV0_SCALE_CNTL, ++ C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); ++ WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); ++ if (!(rdev->flags & RADEON_SINGLE_CRTC)) { ++ WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | ++ S_000360_CUR2_LOCK(1)); ++ WREG32(R_0003F8_CRTC2_GEN_CNTL, ++ (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | ++ S_0003F8_CRTC2_DISPLAY_DIS(1) | ++ S_0003F8_CRTC2_DISP_REQ_EN_B(1)); ++ WREG32(R_000360_CUR2_OFFSET, ++ C_000360_CUR2_LOCK & save->CUR2_OFFSET); ++ } ++} ++ ++void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) ++{ ++ /* Update base address for crtc */ ++ WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location); ++ if (!(rdev->flags & RADEON_SINGLE_CRTC)) { ++ WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, ++ rdev->mc.vram_location); ++ } ++ /* Restore CRTC registers */ ++ WREG32(R_0003C0_GENMO_WT, save->GENMO_WT); ++ WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); ++ WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); ++ if (!(rdev->flags & RADEON_SINGLE_CRTC)) { ++ WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); ++ } ++} +diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h +new file mode 100644 +index 0000000..0daf0d7 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r100_track.h +@@ -0,0 +1,183 @@ ++ ++#define R100_TRACK_MAX_TEXTURE 3 ++#define R200_TRACK_MAX_TEXTURE 6 ++#define R300_TRACK_MAX_TEXTURE 16 ++ ++#define R100_MAX_CB 1 ++#define R300_MAX_CB 4 ++ ++/* ++ * CS functions ++ */ ++struct r100_cs_track_cb { ++ struct radeon_object *robj; ++ unsigned pitch; ++ unsigned cpp; ++ unsigned offset; ++}; ++ ++struct r100_cs_track_array { ++ struct radeon_object *robj; ++ unsigned esize; ++}; ++ ++struct r100_cs_cube_info { ++ struct radeon_object *robj; ++ unsigned offset; ++ unsigned width; ++ unsigned height; ++}; ++ ++struct r100_cs_track_texture { ++ struct radeon_object *robj; ++ struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ ++ unsigned pitch; ++ unsigned width; ++ unsigned height; ++ unsigned num_levels; ++ unsigned cpp; ++ unsigned tex_coord_type; ++ unsigned txdepth; ++ unsigned width_11; ++ unsigned height_11; ++ bool use_pitch; ++ bool enabled; ++ bool roundup_w; ++ bool roundup_h; ++}; ++ ++struct r100_cs_track_limits { ++ unsigned num_cb; ++ unsigned num_texture; ++ unsigned max_levels; ++}; ++ ++struct r100_cs_track { ++ struct radeon_device *rdev; ++ unsigned num_cb; ++ unsigned num_texture; ++ unsigned maxy; ++ unsigned vtx_size; ++ unsigned vap_vf_cntl; ++ unsigned immd_dwords; ++ unsigned num_arrays; ++ unsigned max_indx; ++ struct r100_cs_track_array arrays[11]; ++ struct r100_cs_track_cb cb[R300_MAX_CB]; ++ struct r100_cs_track_cb zb; ++ struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; ++ bool z_enabled; ++ bool separate_cube; ++ ++}; ++ ++int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); ++void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); ++int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, ++ struct radeon_cs_reloc **cs_reloc); ++void r100_cs_dump_packet(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt); ++ ++int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); ++ ++int r200_packet0_check(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt, ++ unsigned idx, unsigned reg); ++ ++ ++ ++static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt, ++ unsigned idx, ++ unsigned reg) ++{ ++ int r; ++ u32 tile_flags = 0; ++ u32 tmp; ++ struct radeon_cs_reloc *reloc; ++ u32 value; ++ ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ value = radeon_get_ib_value(p, idx); ++ tmp = value & 0x003fffff; ++ tmp += (((u32)reloc->lobj.gpu_offset) >> 10); ++ ++ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) ++ tile_flags |= RADEON_DST_TILE_MACRO; ++ if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { ++ if (reg == RADEON_SRC_PITCH_OFFSET) { ++ DRM_ERROR("Cannot src blit from microtiled surface\n"); ++ r100_cs_dump_packet(p, pkt); ++ return -EINVAL; ++ } ++ tile_flags |= RADEON_DST_TILE_MICRO; ++ } ++ ++ tmp |= tile_flags; ++ p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; ++ return 0; ++} ++ ++static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt, ++ int idx) ++{ ++ unsigned c, i; ++ struct radeon_cs_reloc *reloc; ++ struct r100_cs_track *track; ++ int r = 0; ++ volatile uint32_t *ib; ++ u32 idx_value; ++ ++ ib = p->ib->ptr; ++ track = (struct r100_cs_track *)p->track; ++ c = radeon_get_ib_value(p, idx++) & 0x1F; ++ track->num_arrays = c; ++ for (i = 0; i < (c - 1); i+=2, idx+=3) { ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for packet3 %d\n", ++ pkt->opcode); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ idx_value = radeon_get_ib_value(p, idx); ++ ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); ++ ++ track->arrays[i + 0].esize = idx_value >> 8; ++ track->arrays[i + 0].robj = reloc->robj; ++ track->arrays[i + 0].esize &= 0x7F; ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for packet3 %d\n", ++ pkt->opcode); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); ++ track->arrays[i + 1].robj = reloc->robj; ++ track->arrays[i + 1].esize = idx_value >> 24; ++ track->arrays[i + 1].esize &= 0x7F; ++ } ++ if (c & 1) { ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for packet3 %d\n", ++ pkt->opcode); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ idx_value = radeon_get_ib_value(p, idx); ++ ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); ++ track->arrays[i + 0].robj = reloc->robj; ++ track->arrays[i + 0].esize = idx_value >> 8; ++ track->arrays[i + 0].esize &= 0x7F; ++ } ++ return r; ++} +diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h +new file mode 100644 +index 0000000..c4b257e +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r100d.h +@@ -0,0 +1,607 @@ ++/* ++ * Copyright 2008 Advanced Micro Devices, Inc. ++ * Copyright 2008 Red Hat Inc. ++ * Copyright 2009 Jerome Glisse. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#ifndef __R100D_H__ ++#define __R100D_H__ ++ ++#define CP_PACKET0 0x00000000 ++#define PACKET0_BASE_INDEX_SHIFT 0 ++#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) ++#define PACKET0_COUNT_SHIFT 16 ++#define PACKET0_COUNT_MASK (0x3fff << 16) ++#define CP_PACKET1 0x40000000 ++#define CP_PACKET2 0x80000000 ++#define PACKET2_PAD_SHIFT 0 ++#define PACKET2_PAD_MASK (0x3fffffff << 0) ++#define CP_PACKET3 0xC0000000 ++#define PACKET3_IT_OPCODE_SHIFT 8 ++#define PACKET3_IT_OPCODE_MASK (0xff << 8) ++#define PACKET3_COUNT_SHIFT 16 ++#define PACKET3_COUNT_MASK (0x3fff << 16) ++/* PACKET3 op code */ ++#define PACKET3_NOP 0x10 ++#define PACKET3_3D_DRAW_VBUF 0x28 ++#define PACKET3_3D_DRAW_IMMD 0x29 ++#define PACKET3_3D_DRAW_INDX 0x2A ++#define PACKET3_3D_LOAD_VBPNTR 0x2F ++#define PACKET3_INDX_BUFFER 0x33 ++#define PACKET3_3D_DRAW_VBUF_2 0x34 ++#define PACKET3_3D_DRAW_IMMD_2 0x35 ++#define PACKET3_3D_DRAW_INDX_2 0x36 ++#define PACKET3_BITBLT_MULTI 0x9B ++ ++#define PACKET0(reg, n) (CP_PACKET0 | \ ++ REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ ++ REG_SET(PACKET0_COUNT, (n))) ++#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) ++#define PACKET3(op, n) (CP_PACKET3 | \ ++ REG_SET(PACKET3_IT_OPCODE, (op)) | \ ++ REG_SET(PACKET3_COUNT, (n))) ++ ++#define PACKET_TYPE0 0 ++#define PACKET_TYPE1 1 ++#define PACKET_TYPE2 2 ++#define PACKET_TYPE3 3 ++ ++#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) ++#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) ++#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) ++#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) ++#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) ++ ++/* Registers */ ++#define R_000040_GEN_INT_CNTL 0x000040 ++#define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) ++#define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) ++#define C_000040_CRTC_VBLANK 0xFFFFFFFE ++#define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) ++#define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) ++#define C_000040_CRTC_VLINE 0xFFFFFFFD ++#define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) ++#define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) ++#define C_000040_CRTC_VSYNC 0xFFFFFFFB ++#define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) ++#define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) ++#define C_000040_SNAPSHOT 0xFFFFFFF7 ++#define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) ++#define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) ++#define C_000040_FP_DETECT 0xFFFFFFEF ++#define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) ++#define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) ++#define C_000040_CRTC2_VLINE 0xFFFFFFDF ++#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) ++#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) ++#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF ++#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) ++#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) ++#define C_000040_CRTC2_VSYNC 0xFFFFFFBF ++#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) ++#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) ++#define C_000040_SNAPSHOT2 0xFFFFFF7F ++#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) ++#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) ++#define C_000040_CRTC2_VBLANK 0xFFFFFDFF ++#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) ++#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) ++#define C_000040_FP2_DETECT 0xFFFFFBFF ++#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) ++#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) ++#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF ++#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) ++#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) ++#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF ++#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) ++#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) ++#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF ++#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) ++#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) ++#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF ++#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) ++#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) ++#define C_000040_I2C_INT_EN 0xFFFDFFFF ++#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) ++#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) ++#define C_000040_GUI_IDLE 0xFFF7FFFF ++#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) ++#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) ++#define C_000040_VIPH_INT_EN 0xFEFFFFFF ++#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) ++#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) ++#define C_000040_SW_INT_EN 0xFDFFFFFF ++#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) ++#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) ++#define C_000040_GEYSERVILLE 0xF7FFFFFF ++#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) ++#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) ++#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF ++#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) ++#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) ++#define C_000040_DVI_I2C_INT 0xDFFFFFFF ++#define S_000040_GUIDMA(x) (((x) & 0x1) << 30) ++#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) ++#define C_000040_GUIDMA 0xBFFFFFFF ++#define S_000040_VIDDMA(x) (((x) & 0x1) << 31) ++#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) ++#define C_000040_VIDDMA 0x7FFFFFFF ++#define R_000044_GEN_INT_STATUS 0x000044 ++#define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) ++#define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) ++#define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE ++#define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) ++#define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) ++#define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE ++#define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) ++#define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) ++#define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD ++#define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) ++#define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) ++#define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD ++#define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) ++#define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) ++#define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB ++#define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) ++#define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) ++#define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB ++#define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) ++#define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) ++#define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 ++#define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) ++#define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) ++#define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 ++#define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) ++#define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) ++#define C_000044_FP_DETECT_STAT 0xFFFFFFEF ++#define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) ++#define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) ++#define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF ++#define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) ++#define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) ++#define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF ++#define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) ++#define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) ++#define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF ++#define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) ++#define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) ++#define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF ++#define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) ++#define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) ++#define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF ++#define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) ++#define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) ++#define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F ++#define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) ++#define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) ++#define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F ++#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) ++#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) ++#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF ++#define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) ++#define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) ++#define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF ++#define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) ++#define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) ++#define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF ++#define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) ++#define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) ++#define C_000044_FP2_DETECT_STAT 0xFFFFFBFF ++#define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) ++#define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) ++#define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF ++#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) ++#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) ++#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF ++#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) ++#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) ++#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF ++#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) ++#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) ++#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF ++#define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) ++#define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) ++#define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF ++#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) ++#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) ++#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF ++#define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) ++#define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) ++#define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF ++#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) ++#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) ++#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF ++#define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) ++#define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) ++#define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF ++#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) ++#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) ++#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF ++#define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) ++#define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) ++#define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF ++#define S_000044_I2C_INT(x) (((x) & 0x1) << 17) ++#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) ++#define C_000044_I2C_INT 0xFFFDFFFF ++#define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) ++#define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) ++#define C_000044_I2C_INT_AK 0xFFFDFFFF ++#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) ++#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) ++#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF ++#define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) ++#define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) ++#define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF ++#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) ++#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) ++#define C_000044_VIPH_INT 0xFEFFFFFF ++#define S_000044_SW_INT(x) (((x) & 0x1) << 25) ++#define G_000044_SW_INT(x) (((x) >> 25) & 0x1) ++#define C_000044_SW_INT 0xFDFFFFFF ++#define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) ++#define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) ++#define C_000044_SW_INT_AK 0xFDFFFFFF ++#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) ++#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) ++#define C_000044_SW_INT_SET 0xFBFFFFFF ++#define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) ++#define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) ++#define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF ++#define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) ++#define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) ++#define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF ++#define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) ++#define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) ++#define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF ++#define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) ++#define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) ++#define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF ++#define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) ++#define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) ++#define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF ++#define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) ++#define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) ++#define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF ++#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) ++#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) ++#define C_000044_GUIDMA_STAT 0xBFFFFFFF ++#define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) ++#define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) ++#define C_000044_GUIDMA_AK 0xBFFFFFFF ++#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) ++#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) ++#define C_000044_VIDDMA_STAT 0x7FFFFFFF ++#define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) ++#define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) ++#define C_000044_VIDDMA_AK 0x7FFFFFFF ++#define R_000050_CRTC_GEN_CNTL 0x000050 ++#define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) ++#define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) ++#define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE ++#define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) ++#define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) ++#define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD ++#define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) ++#define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) ++#define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF ++#define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) ++#define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) ++#define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF ++#define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) ++#define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) ++#define C_000050_CRTC_ICON_EN 0xFFFF7FFF ++#define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) ++#define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) ++#define C_000050_CRTC_CUR_EN 0xFFFEFFFF ++#define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) ++#define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) ++#define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF ++#define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) ++#define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) ++#define C_000050_CRTC_CUR_MODE 0xFF8FFFFF ++#define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) ++#define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) ++#define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF ++#define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) ++#define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) ++#define C_000050_CRTC_EN 0xFDFFFFFF ++#define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) ++#define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) ++#define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF ++#define R_000054_CRTC_EXT_CNTL 0x000054 ++#define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) ++#define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) ++#define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE ++#define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) ++#define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) ++#define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 ++#define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) ++#define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) ++#define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 ++#define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) ++#define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) ++#define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF ++#define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) ++#define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) ++#define C_000054_VGA_TEXT_132 0xFFFFFFDF ++#define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) ++#define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) ++#define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF ++#define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) ++#define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) ++#define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF ++#define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) ++#define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) ++#define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF ++#define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) ++#define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) ++#define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF ++#define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) ++#define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) ++#define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF ++#define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) ++#define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) ++#define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF ++#define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) ++#define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) ++#define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF ++#define S_000054_CRT_ON(x) (((x) & 0x1) << 15) ++#define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) ++#define C_000054_CRT_ON 0xFFFF7FFF ++#define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) ++#define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) ++#define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF ++#define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) ++#define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) ++#define C_000054_VGA_PACK_DIS 0xFFFBFFFF ++#define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) ++#define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) ++#define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF ++#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) ++#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) ++#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF ++#define R_00023C_DISPLAY_BASE_ADDR 0x00023C ++#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_00023C_DISPLAY_BASE_ADDR 0x00000000 ++#define R_000260_CUR_OFFSET 0x000260 ++#define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) ++#define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) ++#define C_000260_CUR_OFFSET 0xF8000000 ++#define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) ++#define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) ++#define C_000260_CUR_LOCK 0x7FFFFFFF ++#define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C ++#define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 ++#define R_000360_CUR2_OFFSET 0x000360 ++#define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) ++#define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) ++#define C_000360_CUR2_OFFSET 0xF8000000 ++#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) ++#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) ++#define C_000360_CUR2_LOCK 0x7FFFFFFF ++#define R_0003C0_GENMO_WT 0x0003C0 ++#define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) ++#define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) ++#define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE ++#define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1) ++#define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1) ++#define C_0003C0_VGA_RAM_EN 0xFFFFFFFD ++#define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2) ++#define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3) ++#define C_0003C0_VGA_CKSEL 0xFFFFFFF3 ++#define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) ++#define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) ++#define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF ++#define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) ++#define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) ++#define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF ++#define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) ++#define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) ++#define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F ++#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 ++#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) ++#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) ++#define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE ++#define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) ++#define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) ++#define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD ++#define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) ++#define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) ++#define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF ++#define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) ++#define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) ++#define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF ++#define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) ++#define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) ++#define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF ++#define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) ++#define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) ++#define C_0003F8_CRT2_ON 0xFFFFFF7F ++#define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) ++#define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) ++#define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF ++#define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) ++#define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) ++#define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF ++#define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) ++#define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) ++#define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF ++#define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) ++#define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) ++#define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF ++#define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) ++#define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) ++#define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF ++#define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) ++#define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) ++#define C_0003F8_CRTC2_EN 0xFDFFFFFF ++#define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) ++#define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) ++#define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF ++#define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) ++#define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) ++#define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF ++#define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) ++#define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) ++#define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF ++#define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) ++#define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) ++#define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF ++#define R_000420_OV0_SCALE_CNTL 0x000420 ++#define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) ++#define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) ++#define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD ++#define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) ++#define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) ++#define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB ++#define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) ++#define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) ++#define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 ++#define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) ++#define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) ++#define C_000420_OV0_SIGNED_UV 0xFFFFFFEF ++#define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) ++#define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) ++#define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F ++#define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) ++#define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) ++#define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF ++#define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) ++#define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) ++#define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF ++#define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) ++#define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) ++#define C_000420_OV0_CRTC_SEL 0xFFFFBFFF ++#define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) ++#define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) ++#define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF ++#define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) ++#define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) ++#define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF ++#define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) ++#define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) ++#define C_000420_OV0_BANDWIDTH 0xFBFFFFFF ++#define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) ++#define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) ++#define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF ++#define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) ++#define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) ++#define C_000420_OV0_INT_EMU 0xDFFFFFFF ++#define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) ++#define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) ++#define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF ++#define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) ++#define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) ++#define C_000420_OV0_SOFT_RESET 0x7FFFFFFF ++#define R_00070C_CP_RB_RPTR_ADDR 0x00070C ++#define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) ++#define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) ++#define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC ++#define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) ++#define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) ++#define C_00070C_RB_RPTR_ADDR 0x00000003 ++#define R_000740_CP_CSQ_CNTL 0x000740 ++#define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) ++#define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) ++#define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 ++#define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) ++#define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) ++#define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF ++#define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) ++#define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) ++#define C_000740_CSQ_MODE 0x0FFFFFFF ++#define R_000770_SCRATCH_UMSK 0x000770 ++#define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) ++#define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) ++#define C_000770_SCRATCH_UMSK 0xFFFFFFC0 ++#define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) ++#define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) ++#define C_000770_SCRATCH_SWAP 0xFFFCFFFF ++#define R_000774_SCRATCH_ADDR 0x000774 ++#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) ++#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) ++#define C_000774_SCRATCH_ADDR 0x0000001F ++#define R_000E40_RBBM_STATUS 0x000E40 ++#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) ++#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) ++#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 ++#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) ++#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) ++#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF ++#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) ++#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) ++#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF ++#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) ++#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) ++#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF ++#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) ++#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) ++#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF ++#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) ++#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) ++#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF ++#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) ++#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) ++#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF ++#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) ++#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) ++#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF ++#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) ++#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) ++#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF ++#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) ++#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) ++#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF ++#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) ++#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) ++#define C_000E40_E2_BUSY 0xFFFDFFFF ++#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) ++#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) ++#define C_000E40_RB2D_BUSY 0xFFFBFFFF ++#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) ++#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) ++#define C_000E40_RB3D_BUSY 0xFFF7FFFF ++#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) ++#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) ++#define C_000E40_SE_BUSY 0xFFEFFFFF ++#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) ++#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) ++#define C_000E40_RE_BUSY 0xFFDFFFFF ++#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) ++#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) ++#define C_000E40_TAM_BUSY 0xFFBFFFFF ++#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) ++#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) ++#define C_000E40_TDM_BUSY 0xFF7FFFFF ++#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) ++#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) ++#define C_000E40_PB_BUSY 0xFEFFFFFF ++#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) ++#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) ++#define C_000E40_GUI_ACTIVE 0x7FFFFFFF ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c +new file mode 100644 +index 0000000..cf7fea5 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r200.c +@@ -0,0 +1,455 @@ ++/* ++ * Copyright 2008 Advanced Micro Devices, Inc. ++ * Copyright 2008 Red Hat Inc. ++ * Copyright 2009 Jerome Glisse. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#include "drmP.h" ++#include "drm.h" ++#include "radeon_drm.h" ++#include "radeon_reg.h" ++#include "radeon.h" ++ ++#include "r200_reg_safe.h" ++ ++#include "r100_track.h" ++ ++static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) ++{ ++ int vtx_size, i; ++ vtx_size = 2; ++ ++ if (vtx_fmt_0 & R200_VTX_Z0) ++ vtx_size++; ++ if (vtx_fmt_0 & R200_VTX_W0) ++ vtx_size++; ++ /* blend weight */ ++ if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT)) ++ vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7; ++ if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL) ++ vtx_size++; ++ if (vtx_fmt_0 & R200_VTX_N0) ++ vtx_size += 3; ++ if (vtx_fmt_0 & R200_VTX_POINT_SIZE) ++ vtx_size++; ++ if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG) ++ vtx_size++; ++ if (vtx_fmt_0 & R200_VTX_SHININESS_0) ++ vtx_size++; ++ if (vtx_fmt_0 & R200_VTX_SHININESS_1) ++ vtx_size++; ++ for (i = 0; i < 8; i++) { ++ int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3; ++ switch (color_size) { ++ case 0: break; ++ case 1: vtx_size++; break; ++ case 2: vtx_size += 3; break; ++ case 3: vtx_size += 4; break; ++ } ++ } ++ if (vtx_fmt_0 & R200_VTX_XY1) ++ vtx_size += 2; ++ if (vtx_fmt_0 & R200_VTX_Z1) ++ vtx_size++; ++ if (vtx_fmt_0 & R200_VTX_W1) ++ vtx_size++; ++ if (vtx_fmt_0 & R200_VTX_N1) ++ vtx_size += 3; ++ return vtx_size; ++} ++ ++static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) ++{ ++ int vtx_size, i, tex_size; ++ vtx_size = 0; ++ for (i = 0; i < 6; i++) { ++ tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7; ++ if (tex_size > 4) ++ continue; ++ vtx_size += tex_size; ++ } ++ return vtx_size; ++} ++ ++int r200_packet0_check(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt, ++ unsigned idx, unsigned reg) ++{ ++ struct radeon_cs_reloc *reloc; ++ struct r100_cs_track *track; ++ volatile uint32_t *ib; ++ uint32_t tmp; ++ int r; ++ int i; ++ int face; ++ u32 tile_flags = 0; ++ u32 idx_value; ++ ++ ib = p->ib->ptr; ++ track = (struct r100_cs_track *)p->track; ++ idx_value = radeon_get_ib_value(p, idx); ++ switch (reg) { ++ case RADEON_CRTC_GUI_TRIG_VLINE: ++ r = r100_cs_packet_parse_vline(p); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ break; ++ /* FIXME: only allow PACKET3 blit? easier to check for out of ++ * range access */ ++ case RADEON_DST_PITCH_OFFSET: ++ case RADEON_SRC_PITCH_OFFSET: ++ r = r100_reloc_pitch_offset(p, pkt, idx, reg); ++ if (r) ++ return r; ++ break; ++ case RADEON_RB3D_DEPTHOFFSET: ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ track->zb.robj = reloc->robj; ++ track->zb.offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ break; ++ case RADEON_RB3D_COLOROFFSET: ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ track->cb[0].robj = reloc->robj; ++ track->cb[0].offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ break; ++ case R200_PP_TXOFFSET_0: ++ case R200_PP_TXOFFSET_1: ++ case R200_PP_TXOFFSET_2: ++ case R200_PP_TXOFFSET_3: ++ case R200_PP_TXOFFSET_4: ++ case R200_PP_TXOFFSET_5: ++ i = (reg - R200_PP_TXOFFSET_0) / 24; ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ track->textures[i].robj = reloc->robj; ++ break; ++ case R200_PP_CUBIC_OFFSET_F1_0: ++ case R200_PP_CUBIC_OFFSET_F2_0: ++ case R200_PP_CUBIC_OFFSET_F3_0: ++ case R200_PP_CUBIC_OFFSET_F4_0: ++ case R200_PP_CUBIC_OFFSET_F5_0: ++ case R200_PP_CUBIC_OFFSET_F1_1: ++ case R200_PP_CUBIC_OFFSET_F2_1: ++ case R200_PP_CUBIC_OFFSET_F3_1: ++ case R200_PP_CUBIC_OFFSET_F4_1: ++ case R200_PP_CUBIC_OFFSET_F5_1: ++ case R200_PP_CUBIC_OFFSET_F1_2: ++ case R200_PP_CUBIC_OFFSET_F2_2: ++ case R200_PP_CUBIC_OFFSET_F3_2: ++ case R200_PP_CUBIC_OFFSET_F4_2: ++ case R200_PP_CUBIC_OFFSET_F5_2: ++ case R200_PP_CUBIC_OFFSET_F1_3: ++ case R200_PP_CUBIC_OFFSET_F2_3: ++ case R200_PP_CUBIC_OFFSET_F3_3: ++ case R200_PP_CUBIC_OFFSET_F4_3: ++ case R200_PP_CUBIC_OFFSET_F5_3: ++ case R200_PP_CUBIC_OFFSET_F1_4: ++ case R200_PP_CUBIC_OFFSET_F2_4: ++ case R200_PP_CUBIC_OFFSET_F3_4: ++ case R200_PP_CUBIC_OFFSET_F4_4: ++ case R200_PP_CUBIC_OFFSET_F5_4: ++ case R200_PP_CUBIC_OFFSET_F1_5: ++ case R200_PP_CUBIC_OFFSET_F2_5: ++ case R200_PP_CUBIC_OFFSET_F3_5: ++ case R200_PP_CUBIC_OFFSET_F4_5: ++ case R200_PP_CUBIC_OFFSET_F5_5: ++ i = (reg - R200_PP_TXOFFSET_0) / 24; ++ face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ track->textures[i].cube_info[face - 1].offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ track->textures[i].cube_info[face - 1].robj = reloc->robj; ++ break; ++ case RADEON_RE_WIDTH_HEIGHT: ++ track->maxy = ((idx_value >> 16) & 0x7FF); ++ break; ++ case RADEON_RB3D_COLORPITCH: ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ ++ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) ++ tile_flags |= RADEON_COLOR_TILE_ENABLE; ++ if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) ++ tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; ++ ++ tmp = idx_value & ~(0x7 << 16); ++ tmp |= tile_flags; ++ ib[idx] = tmp; ++ ++ track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; ++ break; ++ case RADEON_RB3D_DEPTHPITCH: ++ track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; ++ break; ++ case RADEON_RB3D_CNTL: ++ switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { ++ case 7: ++ case 8: ++ case 9: ++ case 11: ++ case 12: ++ track->cb[0].cpp = 1; ++ break; ++ case 3: ++ case 4: ++ case 15: ++ track->cb[0].cpp = 2; ++ break; ++ case 6: ++ track->cb[0].cpp = 4; ++ break; ++ default: ++ DRM_ERROR("Invalid color buffer format (%d) !\n", ++ ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); ++ return -EINVAL; ++ } ++ if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) { ++ DRM_ERROR("No support for depth xy offset in kms\n"); ++ return -EINVAL; ++ } ++ ++ track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); ++ break; ++ case RADEON_RB3D_ZSTENCILCNTL: ++ switch (idx_value & 0xf) { ++ case 0: ++ track->zb.cpp = 2; ++ break; ++ case 2: ++ case 3: ++ case 4: ++ case 5: ++ case 9: ++ case 11: ++ track->zb.cpp = 4; ++ break; ++ default: ++ break; ++ } ++ break; ++ case RADEON_RB3D_ZPASS_ADDR: ++ r = r100_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ r100_cs_dump_packet(p, pkt); ++ return r; ++ } ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); ++ break; ++ case RADEON_PP_CNTL: ++ { ++ uint32_t temp = idx_value >> 4; ++ for (i = 0; i < track->num_texture; i++) ++ track->textures[i].enabled = !!(temp & (1 << i)); ++ } ++ break; ++ case RADEON_SE_VF_CNTL: ++ track->vap_vf_cntl = idx_value; ++ break; ++ case 0x210c: ++ /* VAP_VF_MAX_VTX_INDX */ ++ track->max_indx = idx_value & 0x00FFFFFFUL; ++ break; ++ case R200_SE_VTX_FMT_0: ++ track->vtx_size = r200_get_vtx_size_0(idx_value); ++ break; ++ case R200_SE_VTX_FMT_1: ++ track->vtx_size += r200_get_vtx_size_1(idx_value); ++ break; ++ case R200_PP_TXSIZE_0: ++ case R200_PP_TXSIZE_1: ++ case R200_PP_TXSIZE_2: ++ case R200_PP_TXSIZE_3: ++ case R200_PP_TXSIZE_4: ++ case R200_PP_TXSIZE_5: ++ i = (reg - R200_PP_TXSIZE_0) / 32; ++ track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; ++ track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; ++ break; ++ case R200_PP_TXPITCH_0: ++ case R200_PP_TXPITCH_1: ++ case R200_PP_TXPITCH_2: ++ case R200_PP_TXPITCH_3: ++ case R200_PP_TXPITCH_4: ++ case R200_PP_TXPITCH_5: ++ i = (reg - R200_PP_TXPITCH_0) / 32; ++ track->textures[i].pitch = idx_value + 32; ++ break; ++ case R200_PP_TXFILTER_0: ++ case R200_PP_TXFILTER_1: ++ case R200_PP_TXFILTER_2: ++ case R200_PP_TXFILTER_3: ++ case R200_PP_TXFILTER_4: ++ case R200_PP_TXFILTER_5: ++ i = (reg - R200_PP_TXFILTER_0) / 32; ++ track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) ++ >> R200_MAX_MIP_LEVEL_SHIFT); ++ tmp = (idx_value >> 23) & 0x7; ++ if (tmp == 2 || tmp == 6) ++ track->textures[i].roundup_w = false; ++ tmp = (idx_value >> 27) & 0x7; ++ if (tmp == 2 || tmp == 6) ++ track->textures[i].roundup_h = false; ++ break; ++ case R200_PP_TXMULTI_CTL_0: ++ case R200_PP_TXMULTI_CTL_1: ++ case R200_PP_TXMULTI_CTL_2: ++ case R200_PP_TXMULTI_CTL_3: ++ case R200_PP_TXMULTI_CTL_4: ++ case R200_PP_TXMULTI_CTL_5: ++ i = (reg - R200_PP_TXMULTI_CTL_0) / 32; ++ break; ++ case R200_PP_TXFORMAT_X_0: ++ case R200_PP_TXFORMAT_X_1: ++ case R200_PP_TXFORMAT_X_2: ++ case R200_PP_TXFORMAT_X_3: ++ case R200_PP_TXFORMAT_X_4: ++ case R200_PP_TXFORMAT_X_5: ++ i = (reg - R200_PP_TXFORMAT_X_0) / 32; ++ track->textures[i].txdepth = idx_value & 0x7; ++ tmp = (idx_value >> 16) & 0x3; ++ /* 2D, 3D, CUBE */ ++ switch (tmp) { ++ case 0: ++ case 5: ++ case 6: ++ case 7: ++ track->textures[i].tex_coord_type = 0; ++ break; ++ case 1: ++ track->textures[i].tex_coord_type = 1; ++ break; ++ case 2: ++ track->textures[i].tex_coord_type = 2; ++ break; ++ } ++ break; ++ case R200_PP_TXFORMAT_0: ++ case R200_PP_TXFORMAT_1: ++ case R200_PP_TXFORMAT_2: ++ case R200_PP_TXFORMAT_3: ++ case R200_PP_TXFORMAT_4: ++ case R200_PP_TXFORMAT_5: ++ i = (reg - R200_PP_TXFORMAT_0) / 32; ++ if (idx_value & R200_TXFORMAT_NON_POWER2) { ++ track->textures[i].use_pitch = 1; ++ } else { ++ track->textures[i].use_pitch = 0; ++ track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); ++ track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); ++ } ++ switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { ++ case R200_TXFORMAT_I8: ++ case R200_TXFORMAT_RGB332: ++ case R200_TXFORMAT_Y8: ++ track->textures[i].cpp = 1; ++ break; ++ case R200_TXFORMAT_DXT1: ++ case R200_TXFORMAT_AI88: ++ case R200_TXFORMAT_ARGB1555: ++ case R200_TXFORMAT_RGB565: ++ case R200_TXFORMAT_ARGB4444: ++ case R200_TXFORMAT_VYUY422: ++ case R200_TXFORMAT_YVYU422: ++ case R200_TXFORMAT_LDVDU655: ++ case R200_TXFORMAT_DVDU88: ++ case R200_TXFORMAT_AVYU4444: ++ track->textures[i].cpp = 2; ++ break; ++ case R200_TXFORMAT_ARGB8888: ++ case R200_TXFORMAT_RGBA8888: ++ case R200_TXFORMAT_ABGR8888: ++ case R200_TXFORMAT_BGR111110: ++ case R200_TXFORMAT_LDVDU8888: ++ case R200_TXFORMAT_DXT23: ++ case R200_TXFORMAT_DXT45: ++ track->textures[i].cpp = 4; ++ break; ++ } ++ track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); ++ track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); ++ break; ++ case R200_PP_CUBIC_FACES_0: ++ case R200_PP_CUBIC_FACES_1: ++ case R200_PP_CUBIC_FACES_2: ++ case R200_PP_CUBIC_FACES_3: ++ case R200_PP_CUBIC_FACES_4: ++ case R200_PP_CUBIC_FACES_5: ++ tmp = idx_value; ++ i = (reg - R200_PP_CUBIC_FACES_0) / 32; ++ for (face = 0; face < 4; face++) { ++ track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); ++ track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); ++ } ++ break; ++ default: ++ printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", ++ reg, idx); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++int r200_init(struct radeon_device *rdev) ++{ ++ rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; ++ rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); ++ return 0; ++} +diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c +index 051bca6..1ebea8c 100644 +--- a/drivers/gpu/drm/radeon/r300.c ++++ b/drivers/gpu/drm/radeon/r300.c +@@ -31,7 +31,10 @@ + #include "radeon_reg.h" + #include "radeon.h" + #include "radeon_drm.h" +-#include "radeon_share.h" ++#include "r100_track.h" ++#include "r300d.h" ++ ++#include "r300_reg_safe.h" + + /* r300,r350,rv350,rv370,rv380 depends on : */ + void r100_hdp_reset(struct radeon_device *rdev); +@@ -39,7 +42,6 @@ int r100_cp_reset(struct radeon_device *rdev); + int r100_rb2d_reset(struct radeon_device *rdev); + int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); + int r100_pci_gart_enable(struct radeon_device *rdev); +-void r100_pci_gart_disable(struct radeon_device *rdev); + void r100_mc_setup(struct radeon_device *rdev); + void r100_mc_disable_clients(struct radeon_device *rdev); + int r100_gui_wait_for_idle(struct radeon_device *rdev); +@@ -47,14 +49,10 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx); + int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); +-int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, +- struct radeon_cs_reloc **cs_reloc); + int r100_cs_parse_packet0(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + const unsigned *auth, unsigned n, + radeon_packet0_check_t check); +-void r100_cs_dump_packet(struct radeon_cs_parser *p, +- struct radeon_cs_packet *pkt); + int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + struct radeon_object *robj); +@@ -87,26 +85,57 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) + mb(); + } + +-int rv370_pcie_gart_enable(struct radeon_device *rdev) ++int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) ++{ ++ void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; ++ ++ if (i < 0 || i > rdev->gart.num_gpu_pages) { ++ return -EINVAL; ++ } ++ addr = (lower_32_bits(addr) >> 8) | ++ ((upper_32_bits(addr) & 0xff) << 24) | ++ 0xc; ++ /* on x86 we want this to be CPU endian, on powerpc ++ * on powerpc without HW swappers, it'll get swapped on way ++ * into VRAM - so no need for cpu_to_le32 on VRAM tables */ ++ writel(addr, ((void __iomem *)ptr) + (i * 4)); ++ return 0; ++} ++ ++int rv370_pcie_gart_init(struct radeon_device *rdev) + { +- uint32_t table_addr; +- uint32_t tmp; + int r; + ++ if (rdev->gart.table.vram.robj) { ++ WARN(1, "RV370 PCIE GART already initialized.\n"); ++ return 0; ++ } + /* Initialize common gart structure */ + r = radeon_gart_init(rdev); +- if (r) { ++ if (r) + return r; +- } + r = rv370_debugfs_pcie_gart_info_init(rdev); +- if (r) { ++ if (r) + DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); +- } + rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; +- r = radeon_gart_table_vram_alloc(rdev); +- if (r) { +- return r; ++ rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; ++ rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; ++ return radeon_gart_table_vram_alloc(rdev); ++} ++ ++int rv370_pcie_gart_enable(struct radeon_device *rdev) ++{ ++ uint32_t table_addr; ++ uint32_t tmp; ++ int r; ++ ++ if (rdev->gart.table.vram.robj == NULL) { ++ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); ++ return -EINVAL; + } ++ r = radeon_gart_table_vram_pin(rdev); ++ if (r) ++ return r; + /* discard memory request outside of configured range */ + tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; + WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); +@@ -128,7 +157,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) + WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); + rv370_pcie_gart_tlb_flush(rdev); + DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", +- rdev->mc.gtt_size >> 20, table_addr); ++ (unsigned)(rdev->mc.gtt_size >> 20), table_addr); + rdev->gart.ready = true; + return 0; + } +@@ -146,45 +175,13 @@ void rv370_pcie_gart_disable(struct radeon_device *rdev) + } + } + +-int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) +-{ +- void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; +- +- if (i < 0 || i > rdev->gart.num_gpu_pages) { +- return -EINVAL; +- } +- addr = (lower_32_bits(addr) >> 8) | +- ((upper_32_bits(addr) & 0xff) << 24) | +- 0xc; +- /* on x86 we want this to be CPU endian, on powerpc +- * on powerpc without HW swappers, it'll get swapped on way +- * into VRAM - so no need for cpu_to_le32 on VRAM tables */ +- writel(addr, ((void __iomem *)ptr) + (i * 4)); +- return 0; +-} +- +-int r300_gart_enable(struct radeon_device *rdev) ++void rv370_pcie_gart_fini(struct radeon_device *rdev) + { +-#if __OS_HAS_AGP +- if (rdev->flags & RADEON_IS_AGP) { +- if (rdev->family > CHIP_RV350) { +- rv370_pcie_gart_disable(rdev); +- } else { +- r100_pci_gart_disable(rdev); +- } +- return 0; +- } +-#endif +- if (rdev->flags & RADEON_IS_PCIE) { +- rdev->asic->gart_disable = &rv370_pcie_gart_disable; +- rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; +- rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; +- return rv370_pcie_gart_enable(rdev); +- } +- return r100_pci_gart_enable(rdev); ++ rv370_pcie_gart_disable(rdev); ++ radeon_gart_table_vram_free(rdev); ++ radeon_gart_fini(rdev); + } + +- + /* + * MC + */ +@@ -232,14 +229,6 @@ int r300_mc_init(struct radeon_device *rdev) + + void r300_mc_fini(struct radeon_device *rdev) + { +- if (rdev->flags & RADEON_IS_PCIE) { +- rv370_pcie_gart_disable(rdev); +- radeon_gart_table_vram_free(rdev); +- } else { +- r100_pci_gart_disable(rdev); +- radeon_gart_table_ram_free(rdev); +- } +- radeon_gart_fini(rdev); + } + + +@@ -704,315 +693,22 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) + /* + * CS functions + */ +-struct r300_cs_track_cb { +- struct radeon_object *robj; +- unsigned pitch; +- unsigned cpp; +- unsigned offset; +-}; +- +-struct r300_cs_track_array { +- struct radeon_object *robj; +- unsigned esize; +-}; +- +-struct r300_cs_track_texture { +- struct radeon_object *robj; +- unsigned pitch; +- unsigned width; +- unsigned height; +- unsigned num_levels; +- unsigned cpp; +- unsigned tex_coord_type; +- unsigned txdepth; +- unsigned width_11; +- unsigned height_11; +- bool use_pitch; +- bool enabled; +- bool roundup_w; +- bool roundup_h; +-}; +- +-struct r300_cs_track { +- unsigned num_cb; +- unsigned maxy; +- unsigned vtx_size; +- unsigned vap_vf_cntl; +- unsigned immd_dwords; +- unsigned num_arrays; +- unsigned max_indx; +- struct r300_cs_track_array arrays[11]; +- struct r300_cs_track_cb cb[4]; +- struct r300_cs_track_cb zb; +- struct r300_cs_track_texture textures[16]; +- bool z_enabled; +-}; +- +-static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t) +-{ +- DRM_ERROR("pitch %d\n", t->pitch); +- DRM_ERROR("width %d\n", t->width); +- DRM_ERROR("height %d\n", t->height); +- DRM_ERROR("num levels %d\n", t->num_levels); +- DRM_ERROR("depth %d\n", t->txdepth); +- DRM_ERROR("bpp %d\n", t->cpp); +- DRM_ERROR("coordinate type %d\n", t->tex_coord_type); +- DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); +- DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); +-} +- +-static inline int r300_cs_track_texture_check(struct radeon_device *rdev, +- struct r300_cs_track *track) +-{ +- struct radeon_object *robj; +- unsigned long size; +- unsigned u, i, w, h; +- +- for (u = 0; u < 16; u++) { +- if (!track->textures[u].enabled) +- continue; +- robj = track->textures[u].robj; +- if (robj == NULL) { +- DRM_ERROR("No texture bound to unit %u\n", u); +- return -EINVAL; +- } +- size = 0; +- for (i = 0; i <= track->textures[u].num_levels; i++) { +- if (track->textures[u].use_pitch) { +- w = track->textures[u].pitch / (1 << i); +- } else { +- w = track->textures[u].width / (1 << i); +- if (rdev->family >= CHIP_RV515) +- w |= track->textures[u].width_11; +- if (track->textures[u].roundup_w) +- w = roundup_pow_of_two(w); +- } +- h = track->textures[u].height / (1 << i); +- if (rdev->family >= CHIP_RV515) +- h |= track->textures[u].height_11; +- if (track->textures[u].roundup_h) +- h = roundup_pow_of_two(h); +- size += w * h; +- } +- size *= track->textures[u].cpp; +- switch (track->textures[u].tex_coord_type) { +- case 0: +- break; +- case 1: +- size *= (1 << track->textures[u].txdepth); +- break; +- case 2: +- size *= 6; +- break; +- default: +- DRM_ERROR("Invalid texture coordinate type %u for unit " +- "%u\n", track->textures[u].tex_coord_type, u); +- return -EINVAL; +- } +- if (size > radeon_object_size(robj)) { +- DRM_ERROR("Texture of unit %u needs %lu bytes but is " +- "%lu\n", u, size, radeon_object_size(robj)); +- r300_cs_track_texture_print(&track->textures[u]); +- return -EINVAL; +- } +- } +- return 0; +-} +- +-int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track) +-{ +- unsigned i; +- unsigned long size; +- unsigned prim_walk; +- unsigned nverts; +- +- for (i = 0; i < track->num_cb; i++) { +- if (track->cb[i].robj == NULL) { +- DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); +- return -EINVAL; +- } +- size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; +- size += track->cb[i].offset; +- if (size > radeon_object_size(track->cb[i].robj)) { +- DRM_ERROR("[drm] Buffer too small for color buffer %d " +- "(need %lu have %lu) !\n", i, size, +- radeon_object_size(track->cb[i].robj)); +- DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", +- i, track->cb[i].pitch, track->cb[i].cpp, +- track->cb[i].offset, track->maxy); +- return -EINVAL; +- } +- } +- if (track->z_enabled) { +- if (track->zb.robj == NULL) { +- DRM_ERROR("[drm] No buffer for z buffer !\n"); +- return -EINVAL; +- } +- size = track->zb.pitch * track->zb.cpp * track->maxy; +- size += track->zb.offset; +- if (size > radeon_object_size(track->zb.robj)) { +- DRM_ERROR("[drm] Buffer too small for z buffer " +- "(need %lu have %lu) !\n", size, +- radeon_object_size(track->zb.robj)); +- return -EINVAL; +- } +- } +- prim_walk = (track->vap_vf_cntl >> 4) & 0x3; +- nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; +- switch (prim_walk) { +- case 1: +- for (i = 0; i < track->num_arrays; i++) { +- size = track->arrays[i].esize * track->max_indx * 4; +- if (track->arrays[i].robj == NULL) { +- DRM_ERROR("(PW %u) Vertex array %u no buffer " +- "bound\n", prim_walk, i); +- return -EINVAL; +- } +- if (size > radeon_object_size(track->arrays[i].robj)) { +- DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " +- "have %lu dwords\n", prim_walk, i, +- size >> 2, +- radeon_object_size(track->arrays[i].robj) >> 2); +- DRM_ERROR("Max indices %u\n", track->max_indx); +- return -EINVAL; +- } +- } +- break; +- case 2: +- for (i = 0; i < track->num_arrays; i++) { +- size = track->arrays[i].esize * (nverts - 1) * 4; +- if (track->arrays[i].robj == NULL) { +- DRM_ERROR("(PW %u) Vertex array %u no buffer " +- "bound\n", prim_walk, i); +- return -EINVAL; +- } +- if (size > radeon_object_size(track->arrays[i].robj)) { +- DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " +- "have %lu dwords\n", prim_walk, i, size >> 2, +- radeon_object_size(track->arrays[i].robj) >> 2); +- return -EINVAL; +- } +- } +- break; +- case 3: +- size = track->vtx_size * nverts; +- if (size != track->immd_dwords) { +- DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", +- track->immd_dwords, size); +- DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", +- nverts, track->vtx_size); +- return -EINVAL; +- } +- break; +- default: +- DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", +- prim_walk); +- return -EINVAL; +- } +- return r300_cs_track_texture_check(rdev, track); +-} +- +-static inline void r300_cs_track_clear(struct r300_cs_track *track) +-{ +- unsigned i; +- +- track->num_cb = 4; +- track->maxy = 4096; +- for (i = 0; i < track->num_cb; i++) { +- track->cb[i].robj = NULL; +- track->cb[i].pitch = 8192; +- track->cb[i].cpp = 16; +- track->cb[i].offset = 0; +- } +- track->z_enabled = true; +- track->zb.robj = NULL; +- track->zb.pitch = 8192; +- track->zb.cpp = 4; +- track->zb.offset = 0; +- track->vtx_size = 0x7F; +- track->immd_dwords = 0xFFFFFFFFUL; +- track->num_arrays = 11; +- track->max_indx = 0x00FFFFFFUL; +- for (i = 0; i < track->num_arrays; i++) { +- track->arrays[i].robj = NULL; +- track->arrays[i].esize = 0x7F; +- } +- for (i = 0; i < 16; i++) { +- track->textures[i].pitch = 16536; +- track->textures[i].width = 16536; +- track->textures[i].height = 16536; +- track->textures[i].width_11 = 1 << 11; +- track->textures[i].height_11 = 1 << 11; +- track->textures[i].num_levels = 12; +- track->textures[i].txdepth = 16; +- track->textures[i].cpp = 64; +- track->textures[i].tex_coord_type = 1; +- track->textures[i].robj = NULL; +- /* CS IB emission code makes sure texture unit are disabled */ +- track->textures[i].enabled = false; +- track->textures[i].roundup_w = true; +- track->textures[i].roundup_h = true; +- } +-} +- +-static const unsigned r300_reg_safe_bm[159] = { +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, +- 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, +- 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF, +- 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF, +- 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, +- 0x00000000, 0x0000C100, 0x00000000, 0x00000000, +- 0x00000000, 0x00000000, 0x00000000, 0x00000000, +- 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF, +- 0x00000000, 0x00000000, 0x00000000, 0x00000000, +- 0x0003FC01, 0xFFFFFCF8, 0xFF800B19, +-}; +- + static int r300_packet0_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg) + { +- struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; +- struct r300_cs_track *track; ++ struct r100_cs_track *track; + volatile uint32_t *ib; + uint32_t tmp, tile_flags = 0; + unsigned i; + int r; ++ u32 idx_value; + + ib = p->ib->ptr; +- ib_chunk = &p->chunks[p->chunk_ib_idx]; +- track = (struct r300_cs_track*)p->track; ++ track = (struct r100_cs_track *)p->track; ++ idx_value = radeon_get_ib_value(p, idx); ++ + switch(reg) { + case AVIVO_D1MODE_VLINE_START_END: + case RADEON_CRTC_GUI_TRIG_VLINE: +@@ -1026,28 +722,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + break; + case RADEON_DST_PITCH_OFFSET: + case RADEON_SRC_PITCH_OFFSET: +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for ib[%d]=0x%04X\n", +- idx, reg); +- r100_cs_dump_packet(p, pkt); ++ r = r100_reloc_pitch_offset(p, pkt, idx, reg); ++ if (r) + return r; +- } +- tmp = ib_chunk->kdata[idx] & 0x003fffff; +- tmp += (((u32)reloc->lobj.gpu_offset) >> 10); +- +- if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) +- tile_flags |= RADEON_DST_TILE_MACRO; +- if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { +- if (reg == RADEON_SRC_PITCH_OFFSET) { +- DRM_ERROR("Cannot src blit from microtiled surface\n"); +- r100_cs_dump_packet(p, pkt); +- return -EINVAL; +- } +- tile_flags |= RADEON_DST_TILE_MICRO; +- } +- tmp |= tile_flags; +- ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; + break; + case R300_RB3D_COLOROFFSET0: + case R300_RB3D_COLOROFFSET1: +@@ -1062,8 +739,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + return r; + } + track->cb[i].robj = reloc->robj; +- track->cb[i].offset = ib_chunk->kdata[idx]; +- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); ++ track->cb[i].offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); + break; + case R300_ZB_DEPTHOFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); +@@ -1074,8 +751,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + return r; + } + track->zb.robj = reloc->robj; +- track->zb.offset = ib_chunk->kdata[idx]; +- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); ++ track->zb.offset = idx_value; ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); + break; + case R300_TX_OFFSET_0: + case R300_TX_OFFSET_0+4: +@@ -1101,32 +778,32 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + r100_cs_dump_packet(p, pkt); + return r; + } +- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); + track->textures[i].robj = reloc->robj; + break; + /* Tracked registers */ + case 0x2084: + /* VAP_VF_CNTL */ +- track->vap_vf_cntl = ib_chunk->kdata[idx]; ++ track->vap_vf_cntl = idx_value; + break; + case 0x20B4: + /* VAP_VTX_SIZE */ +- track->vtx_size = ib_chunk->kdata[idx] & 0x7F; ++ track->vtx_size = idx_value & 0x7F; + break; + case 0x2134: + /* VAP_VF_MAX_VTX_INDX */ +- track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; ++ track->max_indx = idx_value & 0x00FFFFFFUL; + break; + case 0x43E4: + /* SC_SCISSOR1 */ +- track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1; ++ track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; + if (p->rdev->family < CHIP_RV515) { + track->maxy -= 1440; + } + break; + case 0x4E00: + /* RB3D_CCTL */ +- track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1; ++ track->num_cb = ((idx_value >> 5) & 0x3) + 1; + break; + case 0x4E38: + case 0x4E3C: +@@ -1149,13 +826,13 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) + tile_flags |= R300_COLOR_MICROTILE_ENABLE; + +- tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); ++ tmp = idx_value & ~(0x7 << 16); + tmp |= tile_flags; + ib[idx] = tmp; + + i = (reg - 0x4E38) >> 2; +- track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; +- switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { ++ track->cb[i].pitch = idx_value & 0x3FFE; ++ switch (((idx_value >> 21) & 0xF)) { + case 9: + case 11: + case 12: +@@ -1178,13 +855,13 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + break; + default: + DRM_ERROR("Invalid color buffer format (%d) !\n", +- ((ib_chunk->kdata[idx] >> 21) & 0xF)); ++ ((idx_value >> 21) & 0xF)); + return -EINVAL; + } + break; + case 0x4F00: + /* ZB_CNTL */ +- if (ib_chunk->kdata[idx] & 2) { ++ if (idx_value & 2) { + track->z_enabled = true; + } else { + track->z_enabled = false; +@@ -1192,7 +869,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + break; + case 0x4F10: + /* ZB_FORMAT */ +- switch ((ib_chunk->kdata[idx] & 0xF)) { ++ switch ((idx_value & 0xF)) { + case 0: + case 1: + track->zb.cpp = 2; +@@ -1202,7 +879,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + break; + default: + DRM_ERROR("Invalid z buffer format (%d) !\n", +- (ib_chunk->kdata[idx] & 0xF)); ++ (idx_value & 0xF)); + return -EINVAL; + } + break; +@@ -1221,17 +898,17 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) + tile_flags |= R300_DEPTHMICROTILE_TILED;; + +- tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); ++ tmp = idx_value & ~(0x7 << 16); + tmp |= tile_flags; + ib[idx] = tmp; + +- track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; ++ track->zb.pitch = idx_value & 0x3FFC; + break; + case 0x4104: + for (i = 0; i < 16; i++) { + bool enabled; + +- enabled = !!(ib_chunk->kdata[idx] & (1 << i)); ++ enabled = !!(idx_value & (1 << i)); + track->textures[i].enabled = enabled; + } + break; +@@ -1253,50 +930,49 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + case 0x44FC: + /* TX_FORMAT1_[0-15] */ + i = (reg - 0x44C0) >> 2; +- tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; ++ tmp = (idx_value >> 25) & 0x3; + track->textures[i].tex_coord_type = tmp; +- switch ((ib_chunk->kdata[idx] & 0x1F)) { +- case 0: +- case 2: +- case 5: +- case 18: +- case 20: +- case 21: ++ switch ((idx_value & 0x1F)) { ++ case R300_TX_FORMAT_X8: ++ case R300_TX_FORMAT_Y4X4: ++ case R300_TX_FORMAT_Z3Y3X2: + track->textures[i].cpp = 1; + break; +- case 1: +- case 3: +- case 6: +- case 7: +- case 10: +- case 11: +- case 19: +- case 22: +- case 24: ++ case R300_TX_FORMAT_X16: ++ case R300_TX_FORMAT_Y8X8: ++ case R300_TX_FORMAT_Z5Y6X5: ++ case R300_TX_FORMAT_Z6Y5X5: ++ case R300_TX_FORMAT_W4Z4Y4X4: ++ case R300_TX_FORMAT_W1Z5Y5X5: ++ case R300_TX_FORMAT_DXT1: ++ case R300_TX_FORMAT_D3DMFT_CxV8U8: ++ case R300_TX_FORMAT_B8G8_B8G8: ++ case R300_TX_FORMAT_G8R8_G8B8: + track->textures[i].cpp = 2; + break; +- case 4: +- case 8: +- case 9: +- case 12: +- case 13: +- case 23: +- case 25: +- case 27: +- case 30: ++ case R300_TX_FORMAT_Y16X16: ++ case R300_TX_FORMAT_Z11Y11X10: ++ case R300_TX_FORMAT_Z10Y11X11: ++ case R300_TX_FORMAT_W8Z8Y8X8: ++ case R300_TX_FORMAT_W2Z10Y10X10: ++ case 0x17: ++ case R300_TX_FORMAT_FL_I32: ++ case 0x1e: ++ case R300_TX_FORMAT_DXT3: ++ case R300_TX_FORMAT_DXT5: + track->textures[i].cpp = 4; + break; +- case 14: +- case 26: +- case 28: ++ case R300_TX_FORMAT_W16Z16Y16X16: ++ case R300_TX_FORMAT_FL_R16G16B16A16: ++ case R300_TX_FORMAT_FL_I32A32: + track->textures[i].cpp = 8; + break; +- case 29: ++ case R300_TX_FORMAT_FL_R32G32B32A32: + track->textures[i].cpp = 16; + break; + default: + DRM_ERROR("Invalid texture format %u\n", +- (ib_chunk->kdata[idx] & 0x1F)); ++ (idx_value & 0x1F)); + return -EINVAL; + break; + } +@@ -1319,11 +995,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + case 0x443C: + /* TX_FILTER0_[0-15] */ + i = (reg - 0x4400) >> 2; +- tmp = ib_chunk->kdata[idx] & 0x7;; ++ tmp = idx_value & 0x7; + if (tmp == 2 || tmp == 4 || tmp == 6) { + track->textures[i].roundup_w = false; + } +- tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; ++ tmp = (idx_value >> 3) & 0x7; + if (tmp == 2 || tmp == 4 || tmp == 6) { + track->textures[i].roundup_h = false; + } +@@ -1346,12 +1022,12 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + case 0x453C: + /* TX_FORMAT2_[0-15] */ + i = (reg - 0x4500) >> 2; +- tmp = ib_chunk->kdata[idx] & 0x3FFF; ++ tmp = idx_value & 0x3FFF; + track->textures[i].pitch = tmp + 1; + if (p->rdev->family >= CHIP_RV515) { +- tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11; ++ tmp = ((idx_value >> 15) & 1) << 11; + track->textures[i].width_11 = tmp; +- tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11; ++ tmp = ((idx_value >> 16) & 1) << 11; + track->textures[i].height_11 = tmp; + } + break; +@@ -1373,15 +1049,15 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + case 0x44BC: + /* TX_FORMAT0_[0-15] */ + i = (reg - 0x4480) >> 2; +- tmp = ib_chunk->kdata[idx] & 0x7FF; ++ tmp = idx_value & 0x7FF; + track->textures[i].width = tmp + 1; +- tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF; ++ tmp = (idx_value >> 11) & 0x7FF; + track->textures[i].height = tmp + 1; +- tmp = (ib_chunk->kdata[idx] >> 26) & 0xF; ++ tmp = (idx_value >> 26) & 0xF; + track->textures[i].num_levels = tmp; +- tmp = ib_chunk->kdata[idx] & (1 << 31); ++ tmp = idx_value & (1 << 31); + track->textures[i].use_pitch = !!tmp; +- tmp = (ib_chunk->kdata[idx] >> 22) & 0xF; ++ tmp = (idx_value >> 22) & 0xF; + track->textures[i].txdepth = tmp; + break; + case R300_ZB_ZPASS_ADDR: +@@ -1392,7 +1068,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + r100_cs_dump_packet(p, pkt); + return r; + } +- ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); ++ ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); + break; + case 0x4be8: + /* valid register only on RV530 */ +@@ -1410,59 +1086,20 @@ static int r300_packet0_check(struct radeon_cs_parser *p, + static int r300_packet3_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt) + { +- struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; +- struct r300_cs_track *track; ++ struct r100_cs_track *track; + volatile uint32_t *ib; + unsigned idx; +- unsigned i, c; + int r; + + ib = p->ib->ptr; +- ib_chunk = &p->chunks[p->chunk_ib_idx]; + idx = pkt->idx + 1; +- track = (struct r300_cs_track*)p->track; ++ track = (struct r100_cs_track *)p->track; + switch(pkt->opcode) { + case PACKET3_3D_LOAD_VBPNTR: +- c = ib_chunk->kdata[idx++] & 0x1F; +- track->num_arrays = c; +- for (i = 0; i < (c - 1); i+=2, idx+=3) { +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for packet3 %d\n", +- pkt->opcode); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); +- track->arrays[i + 0].robj = reloc->robj; +- track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; +- track->arrays[i + 0].esize &= 0x7F; +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for packet3 %d\n", +- pkt->opcode); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); +- track->arrays[i + 1].robj = reloc->robj; +- track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; +- track->arrays[i + 1].esize &= 0x7F; +- } +- if (c & 1) { +- r = r100_cs_packet_next_reloc(p, &reloc); +- if (r) { +- DRM_ERROR("No reloc for packet3 %d\n", +- pkt->opcode); +- r100_cs_dump_packet(p, pkt); +- return r; +- } +- ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); +- track->arrays[i + 0].robj = reloc->robj; +- track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; +- track->arrays[i + 0].esize &= 0x7F; +- } ++ r = r100_packet3_load_vbpntr(p, pkt, idx); ++ if (r) ++ return r; + break; + case PACKET3_INDX_BUFFER: + r = r100_cs_packet_next_reloc(p, &reloc); +@@ -1471,7 +1108,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p, + r100_cs_dump_packet(p, pkt); + return r; + } +- ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); ++ ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); + r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); + if (r) { + return r; +@@ -1482,13 +1119,13 @@ static int r300_packet3_check(struct radeon_cs_parser *p, + /* Number of dwords is vtx_size * (num_vertices - 1) + * PRIM_WALK must be equal to 3 vertex data in embedded + * in cmd stream */ +- if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { ++ if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { + DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); + return -EINVAL; + } +- track->vap_vf_cntl = ib_chunk->kdata[idx+1]; ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); + track->immd_dwords = pkt->count - 1; +- r = r300_cs_track_check(p->rdev, track); ++ r = r100_cs_track_check(p->rdev, track); + if (r) { + return r; + } +@@ -1497,41 +1134,41 @@ static int r300_packet3_check(struct radeon_cs_parser *p, + /* Number of dwords is vtx_size * (num_vertices - 1) + * PRIM_WALK must be equal to 3 vertex data in embedded + * in cmd stream */ +- if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { ++ if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { + DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); + return -EINVAL; + } +- track->vap_vf_cntl = ib_chunk->kdata[idx]; ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx); + track->immd_dwords = pkt->count; +- r = r300_cs_track_check(p->rdev, track); ++ r = r100_cs_track_check(p->rdev, track); + if (r) { + return r; + } + break; + case PACKET3_3D_DRAW_VBUF: +- track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; +- r = r300_cs_track_check(p->rdev, track); ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); ++ r = r100_cs_track_check(p->rdev, track); + if (r) { + return r; + } + break; + case PACKET3_3D_DRAW_VBUF_2: +- track->vap_vf_cntl = ib_chunk->kdata[idx]; +- r = r300_cs_track_check(p->rdev, track); ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx); ++ r = r100_cs_track_check(p->rdev, track); + if (r) { + return r; + } + break; + case PACKET3_3D_DRAW_INDX: +- track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; +- r = r300_cs_track_check(p->rdev, track); ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); ++ r = r100_cs_track_check(p->rdev, track); + if (r) { + return r; + } + break; + case PACKET3_3D_DRAW_INDX_2: +- track->vap_vf_cntl = ib_chunk->kdata[idx]; +- r = r300_cs_track_check(p->rdev, track); ++ track->vap_vf_cntl = radeon_get_ib_value(p, idx); ++ r = r100_cs_track_check(p->rdev, track); + if (r) { + return r; + } +@@ -1548,11 +1185,12 @@ static int r300_packet3_check(struct radeon_cs_parser *p, + int r300_cs_parse(struct radeon_cs_parser *p) + { + struct radeon_cs_packet pkt; +- struct r300_cs_track track; ++ struct r100_cs_track *track; + int r; + +- r300_cs_track_clear(&track); +- p->track = &track; ++ track = kzalloc(sizeof(*track), GFP_KERNEL); ++ r100_cs_track_clear(p->rdev, track); ++ p->track = track; + do { + r = r100_cs_packet_parse(p, &pkt, p->idx); + if (r) { +@@ -1582,9 +1220,48 @@ int r300_cs_parse(struct radeon_cs_parser *p) + return 0; + } + +-int r300_init(struct radeon_device *rdev) ++void r300_set_reg_safe(struct radeon_device *rdev) + { + rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; + rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); ++} ++ ++int r300_init(struct radeon_device *rdev) ++{ ++ r300_set_reg_safe(rdev); + return 0; + } ++ ++void r300_mc_program(struct radeon_device *rdev) ++{ ++ struct r100_mc_save save; ++ int r; ++ ++ r = r100_debugfs_mc_info_init(rdev); ++ if (r) { ++ dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); ++ } ++ ++ /* Stops all mc clients */ ++ r100_mc_stop(rdev, &save); ++ if (rdev->flags & RADEON_IS_AGP) { ++ WREG32(R_00014C_MC_AGP_LOCATION, ++ S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | ++ S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); ++ WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); ++ WREG32(R_00015C_AGP_BASE_2, ++ upper_32_bits(rdev->mc.agp_base) & 0xff); ++ } else { ++ WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); ++ WREG32(R_000170_AGP_BASE, 0); ++ WREG32(R_00015C_AGP_BASE_2, 0); ++ } ++ /* Wait for mc idle */ ++ if (r300_mc_wait_for_idle(rdev)) ++ DRM_INFO("Failed to wait MC idle before programming MC.\n"); ++ /* Program MC, should be a 32bits limited address space */ ++ WREG32(R_000148_MC_FB_LOCATION, ++ S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | ++ S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); ++ r100_mc_resume(rdev, &save); ++} +diff --git a/drivers/gpu/drm/radeon/r300.h b/drivers/gpu/drm/radeon/r300.h +deleted file mode 100644 +index 8486b4d..0000000 +--- a/drivers/gpu/drm/radeon/r300.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* +- * Copyright 2008 Advanced Micro Devices, Inc. +- * Copyright 2008 Red Hat Inc. +- * Copyright 2009 Jerome Glisse. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Dave Airlie +- * Alex Deucher +- * Jerome Glisse +- */ +-#ifndef R300_H +-#define R300_H +- +-struct r300_asic { +- const unsigned *reg_safe_bm; +- unsigned reg_safe_bm_size; +-}; +- +-#endif +diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h +new file mode 100644 +index 0000000..d4fa3eb +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r300d.h +@@ -0,0 +1,101 @@ ++/* ++ * Copyright 2008 Advanced Micro Devices, Inc. ++ * Copyright 2008 Red Hat Inc. ++ * Copyright 2009 Jerome Glisse. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#ifndef __R300D_H__ ++#define __R300D_H__ ++ ++#define CP_PACKET0 0x00000000 ++#define PACKET0_BASE_INDEX_SHIFT 0 ++#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) ++#define PACKET0_COUNT_SHIFT 16 ++#define PACKET0_COUNT_MASK (0x3fff << 16) ++#define CP_PACKET1 0x40000000 ++#define CP_PACKET2 0x80000000 ++#define PACKET2_PAD_SHIFT 0 ++#define PACKET2_PAD_MASK (0x3fffffff << 0) ++#define CP_PACKET3 0xC0000000 ++#define PACKET3_IT_OPCODE_SHIFT 8 ++#define PACKET3_IT_OPCODE_MASK (0xff << 8) ++#define PACKET3_COUNT_SHIFT 16 ++#define PACKET3_COUNT_MASK (0x3fff << 16) ++/* PACKET3 op code */ ++#define PACKET3_NOP 0x10 ++#define PACKET3_3D_DRAW_VBUF 0x28 ++#define PACKET3_3D_DRAW_IMMD 0x29 ++#define PACKET3_3D_DRAW_INDX 0x2A ++#define PACKET3_3D_LOAD_VBPNTR 0x2F ++#define PACKET3_INDX_BUFFER 0x33 ++#define PACKET3_3D_DRAW_VBUF_2 0x34 ++#define PACKET3_3D_DRAW_IMMD_2 0x35 ++#define PACKET3_3D_DRAW_INDX_2 0x36 ++#define PACKET3_BITBLT_MULTI 0x9B ++ ++#define PACKET0(reg, n) (CP_PACKET0 | \ ++ REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ ++ REG_SET(PACKET0_COUNT, (n))) ++#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) ++#define PACKET3(op, n) (CP_PACKET3 | \ ++ REG_SET(PACKET3_IT_OPCODE, (op)) | \ ++ REG_SET(PACKET3_COUNT, (n))) ++ ++#define PACKET_TYPE0 0 ++#define PACKET_TYPE1 1 ++#define PACKET_TYPE2 2 ++#define PACKET_TYPE3 3 ++ ++#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) ++#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) ++#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) ++#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) ++#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) ++ ++/* Registers */ ++#define R_000148_MC_FB_LOCATION 0x000148 ++#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) ++#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) ++#define C_000148_MC_FB_START 0xFFFF0000 ++#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) ++#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) ++#define C_000148_MC_FB_TOP 0x0000FFFF ++#define R_00014C_MC_AGP_LOCATION 0x00014C ++#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) ++#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) ++#define C_00014C_MC_AGP_START 0xFFFF0000 ++#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) ++#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) ++#define C_00014C_MC_AGP_TOP 0x0000FFFF ++#define R_00015C_AGP_BASE_2 0x00015C ++#define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) ++#define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) ++#define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0 ++#define R_000170_AGP_BASE 0x000170 ++#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_000170_AGP_BASE_ADDR 0x00000000 ++ ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c +index 97426a6..49a2fdc 100644 +--- a/drivers/gpu/drm/radeon/r420.c ++++ b/drivers/gpu/drm/radeon/r420.c +@@ -29,47 +29,13 @@ + #include "drmP.h" + #include "radeon_reg.h" + #include "radeon.h" ++#include "atom.h" ++#include "r420d.h" + +-/* r420,r423,rv410 depends on : */ +-void r100_pci_gart_disable(struct radeon_device *rdev); +-void r100_hdp_reset(struct radeon_device *rdev); +-void r100_mc_setup(struct radeon_device *rdev); +-int r100_gui_wait_for_idle(struct radeon_device *rdev); +-void r100_mc_disable_clients(struct radeon_device *rdev); +-void r300_vram_info(struct radeon_device *rdev); +-int r300_mc_wait_for_idle(struct radeon_device *rdev); +-int rv370_pcie_gart_enable(struct radeon_device *rdev); +-void rv370_pcie_gart_disable(struct radeon_device *rdev); +- +-/* This files gather functions specifics to : +- * r420,r423,rv410 +- * +- * Some of these functions might be used by newer ASICs. +- */ +-void r420_gpu_init(struct radeon_device *rdev); +-int r420_debugfs_pipes_info_init(struct radeon_device *rdev); +- +- +-/* +- * MC +- */ + int r420_mc_init(struct radeon_device *rdev) + { + int r; + +- if (r100_debugfs_rbbm_init(rdev)) { +- DRM_ERROR("Failed to register debugfs file for RBBM !\n"); +- } +- if (r420_debugfs_pipes_info_init(rdev)) { +- DRM_ERROR("Failed to register debugfs file for pipes !\n"); +- } +- +- r420_gpu_init(rdev); +- r100_pci_gart_disable(rdev); +- if (rdev->flags & RADEON_IS_PCIE) { +- rv370_pcie_gart_disable(rdev); +- } +- + /* Setup GPU memory space */ + rdev->mc.vram_location = 0xFFFFFFFFUL; + rdev->mc.gtt_location = 0xFFFFFFFFUL; +@@ -87,33 +53,9 @@ int r420_mc_init(struct radeon_device *rdev) + if (r) { + return r; + } +- +- /* Program GPU memory space */ +- r100_mc_disable_clients(rdev); +- if (r300_mc_wait_for_idle(rdev)) { +- printk(KERN_WARNING "Failed to wait MC idle while " +- "programming pipes. Bad things might happen.\n"); +- } +- r100_mc_setup(rdev); + return 0; + } + +-void r420_mc_fini(struct radeon_device *rdev) +-{ +- rv370_pcie_gart_disable(rdev); +- radeon_gart_table_vram_free(rdev); +- radeon_gart_fini(rdev); +-} +- +- +-/* +- * Global GPU functions +- */ +-void r420_errata(struct radeon_device *rdev) +-{ +- rdev->pll_errata = 0; +-} +- + void r420_pipes_init(struct radeon_device *rdev) + { + unsigned tmp; +@@ -122,6 +64,11 @@ void r420_pipes_init(struct radeon_device *rdev) + + /* GA_ENHANCE workaround TCL deadlock issue */ + WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); ++ /* add idle wait as per freedesktop.org bug 24041 */ ++ if (r100_gui_wait_for_idle(rdev)) { ++ printk(KERN_WARNING "Failed to wait GUI idle while " ++ "programming pipes. Bad things might happen.\n"); ++ } + /* get max number of pipes */ + gb_pipe_select = RREG32(0x402C); + num_pipes = ((gb_pipe_select >> 12) & 3) + 1; +@@ -179,25 +126,239 @@ void r420_pipes_init(struct radeon_device *rdev) + rdev->num_gb_pipes, rdev->num_z_pipes); + } + +-void r420_gpu_init(struct radeon_device *rdev) ++u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) ++{ ++ u32 r; ++ ++ WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); ++ r = RREG32(R_0001FC_MC_IND_DATA); ++ return r; ++} ++ ++void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) ++{ ++ WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | ++ S_0001F8_MC_IND_WR_EN(1)); ++ WREG32(R_0001FC_MC_IND_DATA, v); ++} ++ ++static void r420_debugfs(struct radeon_device *rdev) ++{ ++ if (r100_debugfs_rbbm_init(rdev)) { ++ DRM_ERROR("Failed to register debugfs file for RBBM !\n"); ++ } ++ if (r420_debugfs_pipes_info_init(rdev)) { ++ DRM_ERROR("Failed to register debugfs file for pipes !\n"); ++ } ++} ++ ++static void r420_clock_resume(struct radeon_device *rdev) ++{ ++ u32 sclk_cntl; ++ sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); ++ sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); ++ if (rdev->family == CHIP_R420) ++ sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); ++ WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); ++} ++ ++static int r420_startup(struct radeon_device *rdev) + { +- r100_hdp_reset(rdev); ++ int r; ++ ++ r300_mc_program(rdev); ++ /* Initialize GART (initialize after TTM so we can allocate ++ * memory through TTM but finalize after TTM) */ ++ if (rdev->flags & RADEON_IS_PCIE) { ++ r = rv370_pcie_gart_enable(rdev); ++ if (r) ++ return r; ++ } ++ if (rdev->flags & RADEON_IS_PCI) { ++ r = r100_pci_gart_enable(rdev); ++ if (r) ++ return r; ++ } + r420_pipes_init(rdev); +- if (r300_mc_wait_for_idle(rdev)) { +- printk(KERN_WARNING "Failed to wait MC idle while " +- "programming pipes. Bad things might happen.\n"); ++ /* Enable IRQ */ ++ rdev->irq.sw_int = true; ++ r100_irq_set(rdev); ++ /* 1M ring buffer */ ++ r = r100_cp_init(rdev, 1024 * 1024); ++ if (r) { ++ dev_err(rdev->dev, "failled initializing CP (%d).\n", r); ++ return r; ++ } ++ r = r100_wb_init(rdev); ++ if (r) { ++ dev_err(rdev->dev, "failled initializing WB (%d).\n", r); ++ } ++ r = r100_ib_init(rdev); ++ if (r) { ++ dev_err(rdev->dev, "failled initializing IB (%d).\n", r); ++ return r; + } ++ return 0; + } + ++int r420_resume(struct radeon_device *rdev) ++{ ++ /* Make sur GART are not working */ ++ if (rdev->flags & RADEON_IS_PCIE) ++ rv370_pcie_gart_disable(rdev); ++ if (rdev->flags & RADEON_IS_PCI) ++ r100_pci_gart_disable(rdev); ++ /* Resume clock before doing reset */ ++ r420_clock_resume(rdev); ++ /* Reset gpu before posting otherwise ATOM will enter infinite loop */ ++ if (radeon_gpu_reset(rdev)) { ++ dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", ++ RREG32(R_000E40_RBBM_STATUS), ++ RREG32(R_0007C0_CP_STAT)); ++ } ++ /* check if cards are posted or not */ ++ if (rdev->is_atom_bios) { ++ atom_asic_init(rdev->mode_info.atom_context); ++ } else { ++ radeon_combios_asic_init(rdev->ddev); ++ } ++ /* Resume clock after posting */ ++ r420_clock_resume(rdev); + +-/* +- * r420,r423,rv410 VRAM info +- */ +-void r420_vram_info(struct radeon_device *rdev) ++ return r420_startup(rdev); ++} ++ ++int r420_suspend(struct radeon_device *rdev) + { +- r300_vram_info(rdev); ++ r100_cp_disable(rdev); ++ r100_wb_disable(rdev); ++ r100_irq_disable(rdev); ++ if (rdev->flags & RADEON_IS_PCIE) ++ rv370_pcie_gart_disable(rdev); ++ if (rdev->flags & RADEON_IS_PCI) ++ r100_pci_gart_disable(rdev); ++ return 0; ++} ++ ++void r420_fini(struct radeon_device *rdev) ++{ ++ r100_cp_fini(rdev); ++ r100_wb_fini(rdev); ++ r100_ib_fini(rdev); ++ radeon_gem_fini(rdev); ++ if (rdev->flags & RADEON_IS_PCIE) ++ rv370_pcie_gart_fini(rdev); ++ if (rdev->flags & RADEON_IS_PCI) ++ r100_pci_gart_fini(rdev); ++ radeon_agp_fini(rdev); ++ radeon_irq_kms_fini(rdev); ++ radeon_fence_driver_fini(rdev); ++ radeon_object_fini(rdev); ++ if (rdev->is_atom_bios) { ++ radeon_atombios_fini(rdev); ++ } else { ++ radeon_combios_fini(rdev); ++ } ++ kfree(rdev->bios); ++ rdev->bios = NULL; + } + ++int r420_init(struct radeon_device *rdev) ++{ ++ int r; ++ ++ rdev->new_init_path = true; ++ /* Initialize scratch registers */ ++ radeon_scratch_init(rdev); ++ /* Initialize surface registers */ ++ radeon_surface_init(rdev); ++ /* TODO: disable VGA need to use VGA request */ ++ /* BIOS*/ ++ if (!radeon_get_bios(rdev)) { ++ if (ASIC_IS_AVIVO(rdev)) ++ return -EINVAL; ++ } ++ if (rdev->is_atom_bios) { ++ r = radeon_atombios_init(rdev); ++ if (r) { ++ return r; ++ } ++ } else { ++ r = radeon_combios_init(rdev); ++ if (r) { ++ return r; ++ } ++ } ++ /* Reset gpu before posting otherwise ATOM will enter infinite loop */ ++ if (radeon_gpu_reset(rdev)) { ++ dev_warn(rdev->dev, ++ "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", ++ RREG32(R_000E40_RBBM_STATUS), ++ RREG32(R_0007C0_CP_STAT)); ++ } ++ /* check if cards are posted or not */ ++ if (!radeon_card_posted(rdev) && rdev->bios) { ++ DRM_INFO("GPU not posted. posting now...\n"); ++ if (rdev->is_atom_bios) { ++ atom_asic_init(rdev->mode_info.atom_context); ++ } else { ++ radeon_combios_asic_init(rdev->ddev); ++ } ++ } ++ /* Initialize clocks */ ++ radeon_get_clock_info(rdev->ddev); ++ /* Get vram informations */ ++ r300_vram_info(rdev); ++ /* Initialize memory controller (also test AGP) */ ++ r = r420_mc_init(rdev); ++ if (r) { ++ return r; ++ } ++ r420_debugfs(rdev); ++ /* Fence driver */ ++ r = radeon_fence_driver_init(rdev); ++ if (r) { ++ return r; ++ } ++ r = radeon_irq_kms_init(rdev); ++ if (r) { ++ return r; ++ } ++ /* Memory manager */ ++ r = radeon_object_init(rdev); ++ if (r) { ++ return r; ++ } ++ if (rdev->flags & RADEON_IS_PCIE) { ++ r = rv370_pcie_gart_init(rdev); ++ if (r) ++ return r; ++ } ++ if (rdev->flags & RADEON_IS_PCI) { ++ r = r100_pci_gart_init(rdev); ++ if (r) ++ return r; ++ } ++ r300_set_reg_safe(rdev); ++ rdev->accel_working = true; ++ r = r420_startup(rdev); ++ if (r) { ++ /* Somethings want wront with the accel init stop accel */ ++ dev_err(rdev->dev, "Disabling GPU acceleration\n"); ++ r420_suspend(rdev); ++ r100_cp_fini(rdev); ++ r100_wb_fini(rdev); ++ r100_ib_fini(rdev); ++ if (rdev->flags & RADEON_IS_PCIE) ++ rv370_pcie_gart_fini(rdev); ++ if (rdev->flags & RADEON_IS_PCI) ++ r100_pci_gart_fini(rdev); ++ radeon_agp_fini(rdev); ++ radeon_irq_kms_fini(rdev); ++ rdev->accel_working = false; ++ } ++ return 0; ++} + + /* + * Debugfs info +diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h +new file mode 100644 +index 0000000..a48a7db +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r420d.h +@@ -0,0 +1,249 @@ ++/* ++ * Copyright 2008 Advanced Micro Devices, Inc. ++ * Copyright 2008 Red Hat Inc. ++ * Copyright 2009 Jerome Glisse. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#ifndef R420D_H ++#define R420D_H ++ ++#define R_0001F8_MC_IND_INDEX 0x0001F8 ++#define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) ++#define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) ++#define C_0001F8_MC_IND_ADDR 0xFFFFFF80 ++#define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) ++#define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) ++#define C_0001F8_MC_IND_WR_EN 0xFFFFFEFF ++#define R_0001FC_MC_IND_DATA 0x0001FC ++#define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_0001FC_MC_IND_DATA 0x00000000 ++#define R_0007C0_CP_STAT 0x0007C0 ++#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) ++#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) ++#define C_0007C0_MRU_BUSY 0xFFFFFFFE ++#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) ++#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) ++#define C_0007C0_MWU_BUSY 0xFFFFFFFD ++#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) ++#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) ++#define C_0007C0_RSIU_BUSY 0xFFFFFFFB ++#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) ++#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) ++#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 ++#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) ++#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) ++#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF ++#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) ++#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) ++#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF ++#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) ++#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) ++#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF ++#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) ++#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) ++#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF ++#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) ++#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) ++#define C_0007C0_CSI_BUSY 0xFFFFDFFF ++#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) ++#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) ++#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF ++#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) ++#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) ++#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF ++#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) ++#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) ++#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF ++#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) ++#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) ++#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF ++#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) ++#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) ++#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF ++#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) ++#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) ++#define C_0007C0_CP_BUSY 0x7FFFFFFF ++#define R_000E40_RBBM_STATUS 0x000E40 ++#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) ++#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) ++#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 ++#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) ++#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) ++#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF ++#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) ++#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) ++#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF ++#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) ++#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) ++#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF ++#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) ++#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) ++#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF ++#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) ++#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) ++#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF ++#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) ++#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) ++#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF ++#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) ++#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) ++#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF ++#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) ++#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) ++#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF ++#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) ++#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) ++#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF ++#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) ++#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) ++#define C_000E40_E2_BUSY 0xFFFDFFFF ++#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) ++#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) ++#define C_000E40_RB2D_BUSY 0xFFFBFFFF ++#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) ++#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) ++#define C_000E40_RB3D_BUSY 0xFFF7FFFF ++#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) ++#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) ++#define C_000E40_VAP_BUSY 0xFFEFFFFF ++#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) ++#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) ++#define C_000E40_RE_BUSY 0xFFDFFFFF ++#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) ++#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) ++#define C_000E40_TAM_BUSY 0xFFBFFFFF ++#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) ++#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) ++#define C_000E40_TDM_BUSY 0xFF7FFFFF ++#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) ++#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) ++#define C_000E40_PB_BUSY 0xFEFFFFFF ++#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) ++#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) ++#define C_000E40_TIM_BUSY 0xFDFFFFFF ++#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) ++#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) ++#define C_000E40_GA_BUSY 0xFBFFFFFF ++#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) ++#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) ++#define C_000E40_CBA2D_BUSY 0xF7FFFFFF ++#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) ++#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) ++#define C_000E40_GUI_ACTIVE 0x7FFFFFFF ++ ++/* CLK registers */ ++#define R_00000D_SCLK_CNTL 0x00000D ++#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) ++#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) ++#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 ++#define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) ++#define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) ++#define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7 ++#define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) ++#define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) ++#define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF ++#define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) ++#define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) ++#define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF ++#define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) ++#define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) ++#define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF ++#define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7) ++#define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1) ++#define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F ++#define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8) ++#define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1) ++#define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF ++#define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9) ++#define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1) ++#define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF ++#define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10) ++#define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1) ++#define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF ++#define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11) ++#define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1) ++#define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF ++#define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12) ++#define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1) ++#define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF ++#define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13) ++#define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1) ++#define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF ++#define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14) ++#define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1) ++#define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF ++#define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15) ++#define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1) ++#define C_00000D_FORCE_DISP2 0xFFFF7FFF ++#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) ++#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) ++#define C_00000D_FORCE_CP 0xFFFEFFFF ++#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) ++#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) ++#define C_00000D_FORCE_HDP 0xFFFDFFFF ++#define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18) ++#define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1) ++#define C_00000D_FORCE_DISP1 0xFFFBFFFF ++#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) ++#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) ++#define C_00000D_FORCE_TOP 0xFFF7FFFF ++#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) ++#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) ++#define C_00000D_FORCE_E2 0xFFEFFFFF ++#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) ++#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) ++#define C_00000D_FORCE_SE 0xFFDFFFFF ++#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) ++#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) ++#define C_00000D_FORCE_IDCT 0xFFBFFFFF ++#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) ++#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) ++#define C_00000D_FORCE_VIP 0xFF7FFFFF ++#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) ++#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) ++#define C_00000D_FORCE_RE 0xFEFFFFFF ++#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) ++#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) ++#define C_00000D_FORCE_PB 0xFDFFFFFF ++#define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) ++#define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) ++#define C_00000D_FORCE_PX 0xFBFFFFFF ++#define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) ++#define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) ++#define C_00000D_FORCE_TX 0xF7FFFFFF ++#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) ++#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) ++#define C_00000D_FORCE_RB 0xEFFFFFFF ++#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29) ++#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1) ++#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF ++#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30) ++#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1) ++#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF ++#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31) ++#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1) ++#define C_00000D_FORCE_OV0 0x7FFFFFFF ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h +index e1d5e03..868add6 100644 +--- a/drivers/gpu/drm/radeon/r500_reg.h ++++ b/drivers/gpu/drm/radeon/r500_reg.h +@@ -445,6 +445,8 @@ + #define AVIVO_D1MODE_VBLANK_STATUS 0x6534 + # define AVIVO_VBLANK_ACK (1 << 4) + #define AVIVO_D1MODE_VLINE_START_END 0x6538 ++#define AVIVO_D1MODE_VLINE_STATUS 0x653c ++# define AVIVO_D1MODE_VLINE_STAT (1 << 12) + #define AVIVO_DxMODE_INT_MASK 0x6540 + # define AVIVO_D1MODE_INT_MASK (1 << 0) + # define AVIVO_D2MODE_INT_MASK (1 << 8) +@@ -502,6 +504,7 @@ + + #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 + #define AVIVO_D2MODE_VLINE_START_END 0x6d38 ++#define AVIVO_D2MODE_VLINE_STATUS 0x6d3c + #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 + #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 + #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 +diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c +index ebd6b0f..0bf13fc 100644 +--- a/drivers/gpu/drm/radeon/r520.c ++++ b/drivers/gpu/drm/radeon/r520.c +@@ -26,114 +26,13 @@ + * Jerome Glisse + */ + #include "drmP.h" +-#include "radeon_reg.h" + #include "radeon.h" +-#include "radeon_share.h" +- +-/* r520,rv530,rv560,rv570,r580 depends on : */ +-void r100_hdp_reset(struct radeon_device *rdev); +-int rv370_pcie_gart_enable(struct radeon_device *rdev); +-void rv370_pcie_gart_disable(struct radeon_device *rdev); +-void r420_pipes_init(struct radeon_device *rdev); +-void rs600_mc_disable_clients(struct radeon_device *rdev); +-void rs600_disable_vga(struct radeon_device *rdev); +-int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); +-int rv515_debugfs_ga_info_init(struct radeon_device *rdev); +- +-/* This files gather functions specifics to: +- * r520,rv530,rv560,rv570,r580 +- * +- * Some of these functions might be used by newer ASICs. +- */ +-void r520_gpu_init(struct radeon_device *rdev); +-int r520_mc_wait_for_idle(struct radeon_device *rdev); +- +- +-/* +- * MC +- */ +-int r520_mc_init(struct radeon_device *rdev) +-{ +- uint32_t tmp; +- int r; +- +- if (r100_debugfs_rbbm_init(rdev)) { +- DRM_ERROR("Failed to register debugfs file for RBBM !\n"); +- } +- if (rv515_debugfs_pipes_info_init(rdev)) { +- DRM_ERROR("Failed to register debugfs file for pipes !\n"); +- } +- if (rv515_debugfs_ga_info_init(rdev)) { +- DRM_ERROR("Failed to register debugfs file for pipes !\n"); +- } +- +- r520_gpu_init(rdev); +- rv370_pcie_gart_disable(rdev); +- +- /* Setup GPU memory space */ +- rdev->mc.vram_location = 0xFFFFFFFFUL; +- rdev->mc.gtt_location = 0xFFFFFFFFUL; +- if (rdev->flags & RADEON_IS_AGP) { +- r = radeon_agp_init(rdev); +- if (r) { +- printk(KERN_WARNING "[drm] Disabling AGP\n"); +- rdev->flags &= ~RADEON_IS_AGP; +- rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; +- } else { +- rdev->mc.gtt_location = rdev->mc.agp_base; +- } +- } +- r = radeon_mc_setup(rdev); +- if (r) { +- return r; +- } +- +- /* Program GPU memory space */ +- rs600_mc_disable_clients(rdev); +- if (r520_mc_wait_for_idle(rdev)) { +- printk(KERN_WARNING "Failed to wait MC idle while " +- "programming pipes. Bad things might happen.\n"); +- } +- /* Write VRAM size in case we are limiting it */ +- WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); +- tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; +- tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); +- tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); +- WREG32_MC(R520_MC_FB_LOCATION, tmp); +- WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); +- WREG32(0x310, rdev->mc.vram_location); +- if (rdev->flags & RADEON_IS_AGP) { +- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; +- tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); +- tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); +- WREG32_MC(R520_MC_AGP_LOCATION, tmp); +- WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); +- WREG32_MC(R520_MC_AGP_BASE_2, 0); +- } else { +- WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); +- WREG32_MC(R520_MC_AGP_BASE, 0); +- WREG32_MC(R520_MC_AGP_BASE_2, 0); +- } +- return 0; +-} +- +-void r520_mc_fini(struct radeon_device *rdev) +-{ +- rv370_pcie_gart_disable(rdev); +- radeon_gart_table_vram_free(rdev); +- radeon_gart_fini(rdev); +-} ++#include "atom.h" ++#include "r520d.h" + ++/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ + +-/* +- * Global GPU functions +- */ +-void r520_errata(struct radeon_device *rdev) +-{ +- rdev->pll_errata = 0; +-} +- +-int r520_mc_wait_for_idle(struct radeon_device *rdev) ++static int r520_mc_wait_for_idle(struct radeon_device *rdev) + { + unsigned i; + uint32_t tmp; +@@ -149,12 +48,12 @@ int r520_mc_wait_for_idle(struct radeon_device *rdev) + return -1; + } + +-void r520_gpu_init(struct radeon_device *rdev) ++static void r520_gpu_init(struct radeon_device *rdev) + { + unsigned pipe_select_current, gb_pipe_select, tmp; + + r100_hdp_reset(rdev); +- rs600_disable_vga(rdev); ++ rv515_vga_render_disable(rdev); + /* + * DST_PIPE_CONFIG 0x170C + * GB_TILE_CONFIG 0x4018 +@@ -192,10 +91,6 @@ void r520_gpu_init(struct radeon_device *rdev) + } + } + +- +-/* +- * VRAM info +- */ + static void r520_vram_get_type(struct radeon_device *rdev) + { + uint32_t tmp; +@@ -239,7 +134,168 @@ void r520_vram_info(struct radeon_device *rdev) + rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); + } + +-void r520_bandwidth_update(struct radeon_device *rdev) ++void r520_mc_program(struct radeon_device *rdev) + { +- rv515_bandwidth_avivo_update(rdev); ++ struct rv515_mc_save save; ++ ++ /* Stops all mc clients */ ++ rv515_mc_stop(rdev, &save); ++ ++ /* Wait for mc idle */ ++ if (r520_mc_wait_for_idle(rdev)) ++ dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); ++ /* Write VRAM size in case we are limiting it */ ++ WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); ++ /* Program MC, should be a 32bits limited address space */ ++ WREG32_MC(R_000004_MC_FB_LOCATION, ++ S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | ++ S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); ++ WREG32(R_000134_HDP_FB_LOCATION, ++ S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); ++ if (rdev->flags & RADEON_IS_AGP) { ++ WREG32_MC(R_000005_MC_AGP_LOCATION, ++ S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | ++ S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); ++ WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); ++ WREG32_MC(R_000007_AGP_BASE_2, ++ S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); ++ } else { ++ WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); ++ WREG32_MC(R_000006_AGP_BASE, 0); ++ WREG32_MC(R_000007_AGP_BASE_2, 0); ++ } ++ ++ rv515_mc_resume(rdev, &save); ++} ++ ++static int r520_startup(struct radeon_device *rdev) ++{ ++ int r; ++ ++ r520_mc_program(rdev); ++ /* Resume clock */ ++ rv515_clock_startup(rdev); ++ /* Initialize GPU configuration (# pipes, ...) */ ++ r520_gpu_init(rdev); ++ /* Initialize GART (initialize after TTM so we can allocate ++ * memory through TTM but finalize after TTM) */ ++ if (rdev->flags & RADEON_IS_PCIE) { ++ r = rv370_pcie_gart_enable(rdev); ++ if (r) ++ return r; ++ } ++ /* Enable IRQ */ ++ rdev->irq.sw_int = true; ++ r100_irq_set(rdev); ++ /* 1M ring buffer */ ++ r = r100_cp_init(rdev, 1024 * 1024); ++ if (r) { ++ dev_err(rdev->dev, "failled initializing CP (%d).\n", r); ++ return r; ++ } ++ r = r100_wb_init(rdev); ++ if (r) ++ dev_err(rdev->dev, "failled initializing WB (%d).\n", r); ++ r = r100_ib_init(rdev); ++ if (r) { ++ dev_err(rdev->dev, "failled initializing IB (%d).\n", r); ++ return r; ++ } ++ return 0; ++} ++ ++int r520_resume(struct radeon_device *rdev) ++{ ++ /* Make sur GART are not working */ ++ if (rdev->flags & RADEON_IS_PCIE) ++ rv370_pcie_gart_disable(rdev); ++ /* Resume clock before doing reset */ ++ rv515_clock_startup(rdev); ++ /* Reset gpu before posting otherwise ATOM will enter infinite loop */ ++ if (radeon_gpu_reset(rdev)) { ++ dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", ++ RREG32(R_000E40_RBBM_STATUS), ++ RREG32(R_0007C0_CP_STAT)); ++ } ++ /* post */ ++ atom_asic_init(rdev->mode_info.atom_context); ++ /* Resume clock after posting */ ++ rv515_clock_startup(rdev); ++ return r520_startup(rdev); ++} ++ ++int r520_init(struct radeon_device *rdev) ++{ ++ int r; ++ ++ rdev->new_init_path = true; ++ /* Initialize scratch registers */ ++ radeon_scratch_init(rdev); ++ /* Initialize surface registers */ ++ radeon_surface_init(rdev); ++ /* TODO: disable VGA need to use VGA request */ ++ /* BIOS*/ ++ if (!radeon_get_bios(rdev)) { ++ if (ASIC_IS_AVIVO(rdev)) ++ return -EINVAL; ++ } ++ if (rdev->is_atom_bios) { ++ r = radeon_atombios_init(rdev); ++ if (r) ++ return r; ++ } else { ++ dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); ++ return -EINVAL; ++ } ++ /* Reset gpu before posting otherwise ATOM will enter infinite loop */ ++ if (radeon_gpu_reset(rdev)) { ++ dev_warn(rdev->dev, ++ "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", ++ RREG32(R_000E40_RBBM_STATUS), ++ RREG32(R_0007C0_CP_STAT)); ++ } ++ /* check if cards are posted or not */ ++ if (!radeon_card_posted(rdev) && rdev->bios) { ++ DRM_INFO("GPU not posted. posting now...\n"); ++ atom_asic_init(rdev->mode_info.atom_context); ++ } ++ /* Initialize clocks */ ++ radeon_get_clock_info(rdev->ddev); ++ /* Get vram informations */ ++ r520_vram_info(rdev); ++ /* Initialize memory controller (also test AGP) */ ++ r = r420_mc_init(rdev); ++ if (r) ++ return r; ++ rv515_debugfs(rdev); ++ /* Fence driver */ ++ r = radeon_fence_driver_init(rdev); ++ if (r) ++ return r; ++ r = radeon_irq_kms_init(rdev); ++ if (r) ++ return r; ++ /* Memory manager */ ++ r = radeon_object_init(rdev); ++ if (r) ++ return r; ++ r = rv370_pcie_gart_init(rdev); ++ if (r) ++ return r; ++ rv515_set_safe_registers(rdev); ++ rdev->accel_working = true; ++ r = r520_startup(rdev); ++ if (r) { ++ /* Somethings want wront with the accel init stop accel */ ++ dev_err(rdev->dev, "Disabling GPU acceleration\n"); ++ rv515_suspend(rdev); ++ r100_cp_fini(rdev); ++ r100_wb_fini(rdev); ++ r100_ib_fini(rdev); ++ rv370_pcie_gart_fini(rdev); ++ radeon_agp_fini(rdev); ++ radeon_irq_kms_fini(rdev); ++ rdev->accel_working = false; ++ } ++ return 0; + } +diff --git a/drivers/gpu/drm/radeon/r520d.h b/drivers/gpu/drm/radeon/r520d.h +new file mode 100644 +index 0000000..61af61f +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r520d.h +@@ -0,0 +1,187 @@ ++/* ++ * Copyright 2008 Advanced Micro Devices, Inc. ++ * Copyright 2008 Red Hat Inc. ++ * Copyright 2009 Jerome Glisse. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#ifndef __R520D_H__ ++#define __R520D_H__ ++ ++/* Registers */ ++#define R_0000F8_CONFIG_MEMSIZE 0x0000F8 ++#define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_0000F8_CONFIG_MEMSIZE 0x00000000 ++#define R_000134_HDP_FB_LOCATION 0x000134 ++#define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) ++#define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) ++#define C_000134_HDP_FB_START 0xFFFF0000 ++#define R_0007C0_CP_STAT 0x0007C0 ++#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) ++#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) ++#define C_0007C0_MRU_BUSY 0xFFFFFFFE ++#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) ++#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) ++#define C_0007C0_MWU_BUSY 0xFFFFFFFD ++#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) ++#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) ++#define C_0007C0_RSIU_BUSY 0xFFFFFFFB ++#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) ++#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) ++#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 ++#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) ++#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) ++#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF ++#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) ++#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) ++#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF ++#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) ++#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) ++#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF ++#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) ++#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) ++#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF ++#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) ++#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) ++#define C_0007C0_CSI_BUSY 0xFFFFDFFF ++#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) ++#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) ++#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF ++#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) ++#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) ++#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF ++#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) ++#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) ++#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF ++#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) ++#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) ++#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF ++#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) ++#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) ++#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF ++#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) ++#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) ++#define C_0007C0_CP_BUSY 0x7FFFFFFF ++#define R_000E40_RBBM_STATUS 0x000E40 ++#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) ++#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) ++#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 ++#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) ++#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) ++#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF ++#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) ++#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) ++#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF ++#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) ++#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) ++#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF ++#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) ++#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) ++#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF ++#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) ++#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) ++#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF ++#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) ++#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) ++#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF ++#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) ++#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) ++#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF ++#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) ++#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) ++#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF ++#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) ++#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) ++#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF ++#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) ++#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) ++#define C_000E40_E2_BUSY 0xFFFDFFFF ++#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) ++#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) ++#define C_000E40_RB2D_BUSY 0xFFFBFFFF ++#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) ++#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) ++#define C_000E40_RB3D_BUSY 0xFFF7FFFF ++#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) ++#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) ++#define C_000E40_VAP_BUSY 0xFFEFFFFF ++#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) ++#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) ++#define C_000E40_RE_BUSY 0xFFDFFFFF ++#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) ++#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) ++#define C_000E40_TAM_BUSY 0xFFBFFFFF ++#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) ++#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) ++#define C_000E40_TDM_BUSY 0xFF7FFFFF ++#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) ++#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) ++#define C_000E40_PB_BUSY 0xFEFFFFFF ++#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) ++#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) ++#define C_000E40_TIM_BUSY 0xFDFFFFFF ++#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) ++#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) ++#define C_000E40_GA_BUSY 0xFBFFFFFF ++#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) ++#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) ++#define C_000E40_CBA2D_BUSY 0xF7FFFFFF ++#define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) ++#define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) ++#define C_000E40_RBBM_HIBUSY 0xEFFFFFFF ++#define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) ++#define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) ++#define C_000E40_SKID_CFBUSY 0xDFFFFFFF ++#define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) ++#define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) ++#define C_000E40_VAP_VF_BUSY 0xBFFFFFFF ++#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) ++#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) ++#define C_000E40_GUI_ACTIVE 0x7FFFFFFF ++ ++ ++#define R_000004_MC_FB_LOCATION 0x000004 ++#define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0) ++#define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF) ++#define C_000004_MC_FB_START 0xFFFF0000 ++#define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) ++#define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) ++#define C_000004_MC_FB_TOP 0x0000FFFF ++#define R_000005_MC_AGP_LOCATION 0x000005 ++#define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0) ++#define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) ++#define C_000005_MC_AGP_START 0xFFFF0000 ++#define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) ++#define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) ++#define C_000005_MC_AGP_TOP 0x0000FFFF ++#define R_000006_AGP_BASE 0x000006 ++#define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_000006_AGP_BASE_ADDR 0x00000000 ++#define R_000007_AGP_BASE_2 0x000007 ++#define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) ++#define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) ++#define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0 ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c +index 538cd90..6b7a40b 100644 +--- a/drivers/gpu/drm/radeon/r600.c ++++ b/drivers/gpu/drm/radeon/r600.c +@@ -25,12 +25,45 @@ + * Alex Deucher + * Jerome Glisse + */ ++#include <linux/seq_file.h> ++#include <linux/firmware.h> ++#include <linux/platform_device.h> + #include "drmP.h" +-#include "radeon_reg.h" ++#include "radeon_drm.h" + #include "radeon.h" ++#include "radeon_mode.h" ++#include "r600d.h" ++#include "atom.h" ++#include "avivod.h" + +-/* r600,rv610,rv630,rv620,rv635,rv670 depends on : */ +-void rs600_mc_disable_clients(struct radeon_device *rdev); ++#define PFP_UCODE_SIZE 576 ++#define PM4_UCODE_SIZE 1792 ++#define R700_PFP_UCODE_SIZE 848 ++#define R700_PM4_UCODE_SIZE 1360 ++ ++/* Firmware Names */ ++MODULE_FIRMWARE("radeon/R600_pfp.bin"); ++MODULE_FIRMWARE("radeon/R600_me.bin"); ++MODULE_FIRMWARE("radeon/RV610_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV610_me.bin"); ++MODULE_FIRMWARE("radeon/RV630_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV630_me.bin"); ++MODULE_FIRMWARE("radeon/RV620_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV620_me.bin"); ++MODULE_FIRMWARE("radeon/RV635_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV635_me.bin"); ++MODULE_FIRMWARE("radeon/RV670_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV670_me.bin"); ++MODULE_FIRMWARE("radeon/RS780_pfp.bin"); ++MODULE_FIRMWARE("radeon/RS780_me.bin"); ++MODULE_FIRMWARE("radeon/RV770_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV770_me.bin"); ++MODULE_FIRMWARE("radeon/RV730_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV730_me.bin"); ++MODULE_FIRMWARE("radeon/RV710_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV710_me.bin"); ++ ++int r600_debugfs_mc_info_init(struct radeon_device *rdev); + + /* This files gather functions specifics to: + * r600,rv610,rv630,rv620,rv635,rv670 +@@ -39,87 +72,293 @@ void rs600_mc_disable_clients(struct radeon_device *rdev); + */ + int r600_mc_wait_for_idle(struct radeon_device *rdev); + void r600_gpu_init(struct radeon_device *rdev); ++void r600_fini(struct radeon_device *rdev); + + + /* +- * MC ++ * R600 PCIE GART + */ +-int r600_mc_init(struct radeon_device *rdev) ++int r600_gart_clear_page(struct radeon_device *rdev, int i) + { +- uint32_t tmp; ++ void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; ++ u64 pte; + +- r600_gpu_init(rdev); ++ if (i < 0 || i > rdev->gart.num_gpu_pages) ++ return -EINVAL; ++ pte = 0; ++ writeq(pte, ((void __iomem *)ptr) + (i * 8)); ++ return 0; ++} + +- /* setup the gart before changing location so we can ask to +- * discard unmapped mc request +- */ +- /* FIXME: disable out of gart access */ +- tmp = rdev->mc.gtt_location / 4096; +- tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); +- WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); +- tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; +- tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); +- WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); +- +- rs600_mc_disable_clients(rdev); +- if (r600_mc_wait_for_idle(rdev)) { +- printk(KERN_WARNING "Failed to wait MC idle while " +- "programming pipes. Bad things might happen.\n"); ++void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) ++{ ++ unsigned i; ++ u32 tmp; ++ ++ WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); ++ WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); ++ WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ /* read MC_STATUS */ ++ tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); ++ tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; ++ if (tmp == 2) { ++ printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); ++ return; ++ } ++ if (tmp) { ++ return; ++ } ++ udelay(1); + } ++} + +- tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; +- tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); +- tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); +- WREG32(R600_MC_VM_FB_LOCATION, tmp); +- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; +- tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22); +- WREG32(R600_MC_VM_AGP_TOP, tmp); +- tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22); +- WREG32(R600_MC_VM_AGP_BOT, tmp); +- return 0; ++int r600_pcie_gart_init(struct radeon_device *rdev) ++{ ++ int r; ++ ++ if (rdev->gart.table.vram.robj) { ++ WARN(1, "R600 PCIE GART already initialized.\n"); ++ return 0; ++ } ++ /* Initialize common gart structure */ ++ r = radeon_gart_init(rdev); ++ if (r) ++ return r; ++ rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; ++ return radeon_gart_table_vram_alloc(rdev); + } + +-void r600_mc_fini(struct radeon_device *rdev) ++int r600_pcie_gart_enable(struct radeon_device *rdev) + { +- /* FIXME: implement */ ++ u32 tmp; ++ int r, i; ++ ++ if (rdev->gart.table.vram.robj == NULL) { ++ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); ++ return -EINVAL; ++ } ++ r = radeon_gart_table_vram_pin(rdev); ++ if (r) ++ return r; ++ ++ /* Setup L2 cache */ ++ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | ++ ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | ++ EFFECTIVE_L2_QUEUE_SIZE(7)); ++ WREG32(VM_L2_CNTL2, 0); ++ WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); ++ /* Setup TLB control */ ++ tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | ++ SYSTEM_ACCESS_MODE_NOT_IN_SYS | ++ EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | ++ ENABLE_WAIT_L2_QUERY; ++ WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); ++ WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); ++ WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); ++ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | ++ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); ++ WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, ++ (u32)(rdev->dummy_page.addr >> 12)); ++ for (i = 1; i < 7; i++) ++ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); ++ ++ r600_pcie_gart_tlb_flush(rdev); ++ rdev->gart.ready = true; ++ return 0; + } + ++void r600_pcie_gart_disable(struct radeon_device *rdev) ++{ ++ u32 tmp; ++ int i; + +-/* +- * Global GPU functions +- */ +-void r600_errata(struct radeon_device *rdev) ++ /* Disable all tables */ ++ for (i = 0; i < 7; i++) ++ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); ++ ++ /* Disable L2 cache */ ++ WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | ++ EFFECTIVE_L2_QUEUE_SIZE(7)); ++ WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); ++ /* Setup L1 TLB control */ ++ tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | ++ ENABLE_WAIT_L2_QUERY; ++ WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); ++ WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); ++ if (rdev->gart.table.vram.robj) { ++ radeon_object_kunmap(rdev->gart.table.vram.robj); ++ radeon_object_unpin(rdev->gart.table.vram.robj); ++ } ++} ++ ++void r600_pcie_gart_fini(struct radeon_device *rdev) + { +- rdev->pll_errata = 0; ++ r600_pcie_gart_disable(rdev); ++ radeon_gart_table_vram_free(rdev); ++ radeon_gart_fini(rdev); + } + + int r600_mc_wait_for_idle(struct radeon_device *rdev) + { +- /* FIXME: implement */ +- return 0; ++ unsigned i; ++ u32 tmp; ++ ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ /* read MC_STATUS */ ++ tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; ++ if (!tmp) ++ return 0; ++ udelay(1); ++ } ++ return -1; + } + +-void r600_gpu_init(struct radeon_device *rdev) ++static void r600_mc_resume(struct radeon_device *rdev) + { +- /* FIXME: implement */ +-} ++ u32 d1vga_control, d2vga_control; ++ u32 vga_render_control, vga_hdp_control; ++ u32 d1crtc_control, d2crtc_control; ++ u32 new_d1grph_primary, new_d1grph_secondary; ++ u32 new_d2grph_primary, new_d2grph_secondary; ++ u64 old_vram_start; ++ u32 tmp; ++ int i, j; + ++ /* Initialize HDP */ ++ for (i = 0, j = 0; i < 32; i++, j += 0x18) { ++ WREG32((0x2c14 + j), 0x00000000); ++ WREG32((0x2c18 + j), 0x00000000); ++ WREG32((0x2c1c + j), 0x00000000); ++ WREG32((0x2c20 + j), 0x00000000); ++ WREG32((0x2c24 + j), 0x00000000); ++ } ++ WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); + +-/* +- * VRAM info +- */ +-void r600_vram_get_type(struct radeon_device *rdev) ++ d1vga_control = RREG32(D1VGA_CONTROL); ++ d2vga_control = RREG32(D2VGA_CONTROL); ++ vga_render_control = RREG32(VGA_RENDER_CONTROL); ++ vga_hdp_control = RREG32(VGA_HDP_CONTROL); ++ d1crtc_control = RREG32(D1CRTC_CONTROL); ++ d2crtc_control = RREG32(D2CRTC_CONTROL); ++ old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; ++ new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS); ++ new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS); ++ new_d1grph_primary += rdev->mc.vram_start - old_vram_start; ++ new_d1grph_secondary += rdev->mc.vram_start - old_vram_start; ++ new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS); ++ new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS); ++ new_d2grph_primary += rdev->mc.vram_start - old_vram_start; ++ new_d2grph_secondary += rdev->mc.vram_start - old_vram_start; ++ ++ /* Stop all video */ ++ WREG32(D1VGA_CONTROL, 0); ++ WREG32(D2VGA_CONTROL, 0); ++ WREG32(VGA_RENDER_CONTROL, 0); ++ WREG32(D1CRTC_UPDATE_LOCK, 1); ++ WREG32(D2CRTC_UPDATE_LOCK, 1); ++ WREG32(D1CRTC_CONTROL, 0); ++ WREG32(D2CRTC_CONTROL, 0); ++ WREG32(D1CRTC_UPDATE_LOCK, 0); ++ WREG32(D2CRTC_UPDATE_LOCK, 0); ++ ++ mdelay(1); ++ if (r600_mc_wait_for_idle(rdev)) { ++ printk(KERN_WARNING "[drm] MC not idle !\n"); ++ } ++ ++ /* Lockout access through VGA aperture*/ ++ WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); ++ ++ /* Update configuration */ ++ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); ++ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12); ++ WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); ++ tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16; ++ tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); ++ WREG32(MC_VM_FB_LOCATION, tmp); ++ WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); ++ WREG32(HDP_NONSURFACE_INFO, (2 << 7)); ++ WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); ++ if (rdev->flags & RADEON_IS_AGP) { ++ WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16); ++ WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); ++ WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); ++ } else { ++ WREG32(MC_VM_AGP_BASE, 0); ++ WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); ++ WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); ++ } ++ WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary); ++ WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary); ++ WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary); ++ WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary); ++ WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); ++ ++ /* Unlock host access */ ++ WREG32(VGA_HDP_CONTROL, vga_hdp_control); ++ ++ mdelay(1); ++ if (r600_mc_wait_for_idle(rdev)) { ++ printk(KERN_WARNING "[drm] MC not idle !\n"); ++ } ++ ++ /* Restore video state */ ++ WREG32(D1CRTC_UPDATE_LOCK, 1); ++ WREG32(D2CRTC_UPDATE_LOCK, 1); ++ WREG32(D1CRTC_CONTROL, d1crtc_control); ++ WREG32(D2CRTC_CONTROL, d2crtc_control); ++ WREG32(D1CRTC_UPDATE_LOCK, 0); ++ WREG32(D2CRTC_UPDATE_LOCK, 0); ++ WREG32(D1VGA_CONTROL, d1vga_control); ++ WREG32(D2VGA_CONTROL, d2vga_control); ++ WREG32(VGA_RENDER_CONTROL, vga_render_control); ++ ++ /* we need to own VRAM, so turn off the VGA renderer here ++ * to stop it overwriting our objects */ ++ rv515_vga_render_disable(rdev); ++} ++ ++int r600_mc_init(struct radeon_device *rdev) + { +- uint32_t tmp; ++ fixed20_12 a; ++ u32 tmp; + int chansize; ++ int r; + ++ /* Get VRAM informations */ + rdev->mc.vram_width = 128; + rdev->mc.vram_is_ddr = true; +- +- tmp = RREG32(R600_RAMCFG); +- if (tmp & R600_CHANSIZE_OVERRIDE) { ++ tmp = RREG32(RAMCFG); ++ if (tmp & CHANSIZE_OVERRIDE) { + chansize = 16; +- } else if (tmp & R600_CHANSIZE) { ++ } else if (tmp & CHANSIZE_MASK) { + chansize = 64; + } else { + chansize = 32; +@@ -135,36 +374,1452 @@ void r600_vram_get_type(struct radeon_device *rdev) + (rdev->family == CHIP_RV635)) { + rdev->mc.vram_width = 2 * chansize; + } ++ /* Could aper size report 0 ? */ ++ rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); ++ rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); ++ /* Setup GPU memory space */ ++ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); ++ rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); ++ ++ if (rdev->mc.mc_vram_size > rdev->mc.aper_size) ++ rdev->mc.mc_vram_size = rdev->mc.aper_size; ++ ++ if (rdev->mc.real_vram_size > rdev->mc.aper_size) ++ rdev->mc.real_vram_size = rdev->mc.aper_size; ++ ++ if (rdev->flags & RADEON_IS_AGP) { ++ r = radeon_agp_init(rdev); ++ if (r) ++ return r; ++ /* gtt_size is setup by radeon_agp_init */ ++ rdev->mc.gtt_location = rdev->mc.agp_base; ++ tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; ++ /* Try to put vram before or after AGP because we ++ * we want SYSTEM_APERTURE to cover both VRAM and ++ * AGP so that GPU can catch out of VRAM/AGP access ++ */ ++ if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { ++ /* Enought place before */ ++ rdev->mc.vram_location = rdev->mc.gtt_location - ++ rdev->mc.mc_vram_size; ++ } else if (tmp > rdev->mc.mc_vram_size) { ++ /* Enought place after */ ++ rdev->mc.vram_location = rdev->mc.gtt_location + ++ rdev->mc.gtt_size; ++ } else { ++ /* Try to setup VRAM then AGP might not ++ * not work on some card ++ */ ++ rdev->mc.vram_location = 0x00000000UL; ++ rdev->mc.gtt_location = rdev->mc.mc_vram_size; ++ } ++ } else { ++ if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { ++ rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & ++ 0xFFFF) << 24; ++ rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; ++ tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; ++ if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { ++ /* Enough place after vram */ ++ rdev->mc.gtt_location = tmp; ++ } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { ++ /* Enough place before vram */ ++ rdev->mc.gtt_location = 0; ++ } else { ++ /* Not enough place after or before shrink ++ * gart size ++ */ ++ if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) { ++ rdev->mc.gtt_location = 0; ++ rdev->mc.gtt_size = rdev->mc.vram_location; ++ } else { ++ rdev->mc.gtt_location = tmp; ++ rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp; ++ } ++ } ++ rdev->mc.gtt_location = rdev->mc.mc_vram_size; ++ } else { ++ rdev->mc.vram_location = 0x00000000UL; ++ rdev->mc.gtt_location = rdev->mc.mc_vram_size; ++ rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; ++ } ++ } ++ rdev->mc.vram_start = rdev->mc.vram_location; ++ rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size; ++ rdev->mc.gtt_start = rdev->mc.gtt_location; ++ rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size; ++ /* FIXME: we should enforce default clock in case GPU is not in ++ * default setup ++ */ ++ a.full = rfixed_const(100); ++ rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); ++ rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); ++ return 0; + } + +-void r600_vram_info(struct radeon_device *rdev) ++/* We doesn't check that the GPU really needs a reset we simply do the ++ * reset, it's up to the caller to determine if the GPU needs one. We ++ * might add an helper function to check that. ++ */ ++int r600_gpu_soft_reset(struct radeon_device *rdev) + { +- r600_vram_get_type(rdev); +- rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE); +- rdev->mc.mc_vram_size = rdev->mc.real_vram_size; ++ u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | ++ S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | ++ S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | ++ S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | ++ S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | ++ S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | ++ S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | ++ S_008010_GUI_ACTIVE(1); ++ u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | ++ S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | ++ S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | ++ S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | ++ S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | ++ S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | ++ S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | ++ S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); ++ u32 srbm_reset = 0; + +- /* Could aper size report 0 ? */ +- rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); +- rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); ++ /* Disable CP parsing/prefetching */ ++ WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff)); ++ /* Check if any of the rendering block is busy and reset it */ ++ if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || ++ (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { ++ WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) | ++ S_008020_SOFT_RESET_DB(1) | ++ S_008020_SOFT_RESET_CB(1) | ++ S_008020_SOFT_RESET_PA(1) | ++ S_008020_SOFT_RESET_SC(1) | ++ S_008020_SOFT_RESET_SMX(1) | ++ S_008020_SOFT_RESET_SPI(1) | ++ S_008020_SOFT_RESET_SX(1) | ++ S_008020_SOFT_RESET_SH(1) | ++ S_008020_SOFT_RESET_TC(1) | ++ S_008020_SOFT_RESET_TA(1) | ++ S_008020_SOFT_RESET_VC(1) | ++ S_008020_SOFT_RESET_VGT(1)); ++ (void)RREG32(R_008020_GRBM_SOFT_RESET); ++ udelay(50); ++ WREG32(R_008020_GRBM_SOFT_RESET, 0); ++ (void)RREG32(R_008020_GRBM_SOFT_RESET); ++ } ++ /* Reset CP (we always reset CP) */ ++ WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1)); ++ (void)RREG32(R_008020_GRBM_SOFT_RESET); ++ udelay(50); ++ WREG32(R_008020_GRBM_SOFT_RESET, 0); ++ (void)RREG32(R_008020_GRBM_SOFT_RESET); ++ /* Reset others GPU block if necessary */ ++ if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_RLC(1); ++ if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_GRBM(1); ++ if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_IH(1); ++ if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_VMC(1); ++ if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_MC(1); ++ if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_MC(1); ++ if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_MC(1); ++ if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_MC(1); ++ if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_MC(1); ++ if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_RLC(1); ++ if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS))) ++ srbm_reset |= S_000E60_SOFT_RESET_SEM(1); ++ WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); ++ (void)RREG32(R_000E60_SRBM_SOFT_RESET); ++ udelay(50); ++ WREG32(R_000E60_SRBM_SOFT_RESET, 0); ++ (void)RREG32(R_000E60_SRBM_SOFT_RESET); ++ /* Wait a little for things to settle down */ ++ udelay(50); ++ return 0; ++} ++ ++int r600_gpu_reset(struct radeon_device *rdev) ++{ ++ return r600_gpu_soft_reset(rdev); + } + ++static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, ++ u32 num_backends, ++ u32 backend_disable_mask) ++{ ++ u32 backend_map = 0; ++ u32 enabled_backends_mask; ++ u32 enabled_backends_count; ++ u32 cur_pipe; ++ u32 swizzle_pipe[R6XX_MAX_PIPES]; ++ u32 cur_backend; ++ u32 i; ++ ++ if (num_tile_pipes > R6XX_MAX_PIPES) ++ num_tile_pipes = R6XX_MAX_PIPES; ++ if (num_tile_pipes < 1) ++ num_tile_pipes = 1; ++ if (num_backends > R6XX_MAX_BACKENDS) ++ num_backends = R6XX_MAX_BACKENDS; ++ if (num_backends < 1) ++ num_backends = 1; ++ ++ enabled_backends_mask = 0; ++ enabled_backends_count = 0; ++ for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { ++ if (((backend_disable_mask >> i) & 1) == 0) { ++ enabled_backends_mask |= (1 << i); ++ ++enabled_backends_count; ++ } ++ if (enabled_backends_count == num_backends) ++ break; ++ } ++ ++ if (enabled_backends_count == 0) { ++ enabled_backends_mask = 1; ++ enabled_backends_count = 1; ++ } ++ ++ if (enabled_backends_count != num_backends) ++ num_backends = enabled_backends_count; ++ ++ memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); ++ switch (num_tile_pipes) { ++ case 1: ++ swizzle_pipe[0] = 0; ++ break; ++ case 2: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 1; ++ break; ++ case 3: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 1; ++ swizzle_pipe[2] = 2; ++ break; ++ case 4: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 1; ++ swizzle_pipe[2] = 2; ++ swizzle_pipe[3] = 3; ++ break; ++ case 5: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 1; ++ swizzle_pipe[2] = 2; ++ swizzle_pipe[3] = 3; ++ swizzle_pipe[4] = 4; ++ break; ++ case 6: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 4; ++ swizzle_pipe[3] = 5; ++ swizzle_pipe[4] = 1; ++ swizzle_pipe[5] = 3; ++ break; ++ case 7: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 4; ++ swizzle_pipe[3] = 6; ++ swizzle_pipe[4] = 1; ++ swizzle_pipe[5] = 3; ++ swizzle_pipe[6] = 5; ++ break; ++ case 8: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 4; ++ swizzle_pipe[3] = 6; ++ swizzle_pipe[4] = 1; ++ swizzle_pipe[5] = 3; ++ swizzle_pipe[6] = 5; ++ swizzle_pipe[7] = 7; ++ break; ++ } ++ ++ cur_backend = 0; ++ for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { ++ while (((1 << cur_backend) & enabled_backends_mask) == 0) ++ cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; ++ ++ backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); ++ ++ cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; ++ } ++ ++ return backend_map; ++} ++ ++int r600_count_pipe_bits(uint32_t val) ++{ ++ int i, ret = 0; ++ ++ for (i = 0; i < 32; i++) { ++ ret += val & 1; ++ val >>= 1; ++ } ++ return ret; ++} ++ ++void r600_gpu_init(struct radeon_device *rdev) ++{ ++ u32 tiling_config; ++ u32 ramcfg; ++ u32 tmp; ++ int i, j; ++ u32 sq_config; ++ u32 sq_gpr_resource_mgmt_1 = 0; ++ u32 sq_gpr_resource_mgmt_2 = 0; ++ u32 sq_thread_resource_mgmt = 0; ++ u32 sq_stack_resource_mgmt_1 = 0; ++ u32 sq_stack_resource_mgmt_2 = 0; ++ ++ /* FIXME: implement */ ++ switch (rdev->family) { ++ case CHIP_R600: ++ rdev->config.r600.max_pipes = 4; ++ rdev->config.r600.max_tile_pipes = 8; ++ rdev->config.r600.max_simds = 4; ++ rdev->config.r600.max_backends = 4; ++ rdev->config.r600.max_gprs = 256; ++ rdev->config.r600.max_threads = 192; ++ rdev->config.r600.max_stack_entries = 256; ++ rdev->config.r600.max_hw_contexts = 8; ++ rdev->config.r600.max_gs_threads = 16; ++ rdev->config.r600.sx_max_export_size = 128; ++ rdev->config.r600.sx_max_export_pos_size = 16; ++ rdev->config.r600.sx_max_export_smx_size = 128; ++ rdev->config.r600.sq_num_cf_insts = 2; ++ break; ++ case CHIP_RV630: ++ case CHIP_RV635: ++ rdev->config.r600.max_pipes = 2; ++ rdev->config.r600.max_tile_pipes = 2; ++ rdev->config.r600.max_simds = 3; ++ rdev->config.r600.max_backends = 1; ++ rdev->config.r600.max_gprs = 128; ++ rdev->config.r600.max_threads = 192; ++ rdev->config.r600.max_stack_entries = 128; ++ rdev->config.r600.max_hw_contexts = 8; ++ rdev->config.r600.max_gs_threads = 4; ++ rdev->config.r600.sx_max_export_size = 128; ++ rdev->config.r600.sx_max_export_pos_size = 16; ++ rdev->config.r600.sx_max_export_smx_size = 128; ++ rdev->config.r600.sq_num_cf_insts = 2; ++ break; ++ case CHIP_RV610: ++ case CHIP_RV620: ++ case CHIP_RS780: ++ case CHIP_RS880: ++ rdev->config.r600.max_pipes = 1; ++ rdev->config.r600.max_tile_pipes = 1; ++ rdev->config.r600.max_simds = 2; ++ rdev->config.r600.max_backends = 1; ++ rdev->config.r600.max_gprs = 128; ++ rdev->config.r600.max_threads = 192; ++ rdev->config.r600.max_stack_entries = 128; ++ rdev->config.r600.max_hw_contexts = 4; ++ rdev->config.r600.max_gs_threads = 4; ++ rdev->config.r600.sx_max_export_size = 128; ++ rdev->config.r600.sx_max_export_pos_size = 16; ++ rdev->config.r600.sx_max_export_smx_size = 128; ++ rdev->config.r600.sq_num_cf_insts = 1; ++ break; ++ case CHIP_RV670: ++ rdev->config.r600.max_pipes = 4; ++ rdev->config.r600.max_tile_pipes = 4; ++ rdev->config.r600.max_simds = 4; ++ rdev->config.r600.max_backends = 4; ++ rdev->config.r600.max_gprs = 192; ++ rdev->config.r600.max_threads = 192; ++ rdev->config.r600.max_stack_entries = 256; ++ rdev->config.r600.max_hw_contexts = 8; ++ rdev->config.r600.max_gs_threads = 16; ++ rdev->config.r600.sx_max_export_size = 128; ++ rdev->config.r600.sx_max_export_pos_size = 16; ++ rdev->config.r600.sx_max_export_smx_size = 128; ++ rdev->config.r600.sq_num_cf_insts = 2; ++ break; ++ default: ++ break; ++ } ++ ++ /* Initialize HDP */ ++ for (i = 0, j = 0; i < 32; i++, j += 0x18) { ++ WREG32((0x2c14 + j), 0x00000000); ++ WREG32((0x2c18 + j), 0x00000000); ++ WREG32((0x2c1c + j), 0x00000000); ++ WREG32((0x2c20 + j), 0x00000000); ++ WREG32((0x2c24 + j), 0x00000000); ++ } ++ ++ WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); ++ ++ /* Setup tiling */ ++ tiling_config = 0; ++ ramcfg = RREG32(RAMCFG); ++ switch (rdev->config.r600.max_tile_pipes) { ++ case 1: ++ tiling_config |= PIPE_TILING(0); ++ break; ++ case 2: ++ tiling_config |= PIPE_TILING(1); ++ break; ++ case 4: ++ tiling_config |= PIPE_TILING(2); ++ break; ++ case 8: ++ tiling_config |= PIPE_TILING(3); ++ break; ++ default: ++ break; ++ } ++ tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); ++ tiling_config |= GROUP_SIZE(0); ++ tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; ++ if (tmp > 3) { ++ tiling_config |= ROW_TILING(3); ++ tiling_config |= SAMPLE_SPLIT(3); ++ } else { ++ tiling_config |= ROW_TILING(tmp); ++ tiling_config |= SAMPLE_SPLIT(tmp); ++ } ++ tiling_config |= BANK_SWAPS(1); ++ tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, ++ rdev->config.r600.max_backends, ++ (0xff << rdev->config.r600.max_backends) & 0xff); ++ tiling_config |= BACKEND_MAP(tmp); ++ WREG32(GB_TILING_CONFIG, tiling_config); ++ WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); ++ WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); ++ ++ tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); ++ WREG32(CC_RB_BACKEND_DISABLE, tmp); ++ ++ /* Setup pipes */ ++ tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); ++ tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); ++ WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp); ++ WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp); ++ ++ tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK); ++ WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); ++ WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); ++ ++ /* Setup some CP states */ ++ WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); ++ WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); ++ ++ WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | ++ SYNC_WALKER | SYNC_ALIGNER)); ++ /* Setup various GPU states */ ++ if (rdev->family == CHIP_RV670) ++ WREG32(ARB_GDEC_RD_CNTL, 0x00000021); ++ ++ tmp = RREG32(SX_DEBUG_1); ++ tmp |= SMX_EVENT_RELEASE; ++ if ((rdev->family > CHIP_R600)) ++ tmp |= ENABLE_NEW_SMX_ADDRESS; ++ WREG32(SX_DEBUG_1, tmp); ++ ++ if (((rdev->family) == CHIP_R600) || ++ ((rdev->family) == CHIP_RV630) || ++ ((rdev->family) == CHIP_RV610) || ++ ((rdev->family) == CHIP_RV620) || ++ ((rdev->family) == CHIP_RS780)) { ++ WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); ++ } else { ++ WREG32(DB_DEBUG, 0); ++ } ++ WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | ++ DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); ++ ++ WREG32(PA_SC_MULTI_CHIP_CNTL, 0); ++ WREG32(VGT_NUM_INSTANCES, 0); ++ ++ WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); ++ WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); ++ ++ tmp = RREG32(SQ_MS_FIFO_SIZES); ++ if (((rdev->family) == CHIP_RV610) || ++ ((rdev->family) == CHIP_RV620) || ++ ((rdev->family) == CHIP_RS780)) { ++ tmp = (CACHE_FIFO_SIZE(0xa) | ++ FETCH_FIFO_HIWATER(0xa) | ++ DONE_FIFO_HIWATER(0xe0) | ++ ALU_UPDATE_FIFO_HIWATER(0x8)); ++ } else if (((rdev->family) == CHIP_R600) || ++ ((rdev->family) == CHIP_RV630)) { ++ tmp &= ~DONE_FIFO_HIWATER(0xff); ++ tmp |= DONE_FIFO_HIWATER(0x4); ++ } ++ WREG32(SQ_MS_FIFO_SIZES, tmp); ++ ++ /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT ++ * should be adjusted as needed by the 2D/3D drivers. This just sets default values ++ */ ++ sq_config = RREG32(SQ_CONFIG); ++ sq_config &= ~(PS_PRIO(3) | ++ VS_PRIO(3) | ++ GS_PRIO(3) | ++ ES_PRIO(3)); ++ sq_config |= (DX9_CONSTS | ++ VC_ENABLE | ++ PS_PRIO(0) | ++ VS_PRIO(1) | ++ GS_PRIO(2) | ++ ES_PRIO(3)); ++ ++ if ((rdev->family) == CHIP_R600) { ++ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | ++ NUM_VS_GPRS(124) | ++ NUM_CLAUSE_TEMP_GPRS(4)); ++ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | ++ NUM_ES_GPRS(0)); ++ sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | ++ NUM_VS_THREADS(48) | ++ NUM_GS_THREADS(4) | ++ NUM_ES_THREADS(4)); ++ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | ++ NUM_VS_STACK_ENTRIES(128)); ++ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | ++ NUM_ES_STACK_ENTRIES(0)); ++ } else if (((rdev->family) == CHIP_RV610) || ++ ((rdev->family) == CHIP_RV620) || ++ ((rdev->family) == CHIP_RS780)) { ++ /* no vertex cache */ ++ sq_config &= ~VC_ENABLE; ++ ++ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | ++ NUM_VS_GPRS(44) | ++ NUM_CLAUSE_TEMP_GPRS(2)); ++ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | ++ NUM_ES_GPRS(17)); ++ sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | ++ NUM_VS_THREADS(78) | ++ NUM_GS_THREADS(4) | ++ NUM_ES_THREADS(31)); ++ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | ++ NUM_VS_STACK_ENTRIES(40)); ++ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | ++ NUM_ES_STACK_ENTRIES(16)); ++ } else if (((rdev->family) == CHIP_RV630) || ++ ((rdev->family) == CHIP_RV635)) { ++ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | ++ NUM_VS_GPRS(44) | ++ NUM_CLAUSE_TEMP_GPRS(2)); ++ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | ++ NUM_ES_GPRS(18)); ++ sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | ++ NUM_VS_THREADS(78) | ++ NUM_GS_THREADS(4) | ++ NUM_ES_THREADS(31)); ++ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | ++ NUM_VS_STACK_ENTRIES(40)); ++ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | ++ NUM_ES_STACK_ENTRIES(16)); ++ } else if ((rdev->family) == CHIP_RV670) { ++ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | ++ NUM_VS_GPRS(44) | ++ NUM_CLAUSE_TEMP_GPRS(2)); ++ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | ++ NUM_ES_GPRS(17)); ++ sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | ++ NUM_VS_THREADS(78) | ++ NUM_GS_THREADS(4) | ++ NUM_ES_THREADS(31)); ++ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | ++ NUM_VS_STACK_ENTRIES(64)); ++ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | ++ NUM_ES_STACK_ENTRIES(64)); ++ } ++ ++ WREG32(SQ_CONFIG, sq_config); ++ WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); ++ WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); ++ WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); ++ WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); ++ WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); ++ ++ if (((rdev->family) == CHIP_RV610) || ++ ((rdev->family) == CHIP_RV620) || ++ ((rdev->family) == CHIP_RS780)) { ++ WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); ++ } else { ++ WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); ++ } ++ ++ /* More default values. 2D/3D driver should adjust as needed */ ++ WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | ++ S1_X(0x4) | S1_Y(0xc))); ++ WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | ++ S1_X(0x2) | S1_Y(0x2) | ++ S2_X(0xa) | S2_Y(0x6) | ++ S3_X(0x6) | S3_Y(0xa))); ++ WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | ++ S1_X(0x4) | S1_Y(0xc) | ++ S2_X(0x1) | S2_Y(0x6) | ++ S3_X(0xa) | S3_Y(0xe))); ++ WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | ++ S5_X(0x0) | S5_Y(0x0) | ++ S6_X(0xb) | S6_Y(0x4) | ++ S7_X(0x7) | S7_Y(0x8))); ++ ++ WREG32(VGT_STRMOUT_EN, 0); ++ tmp = rdev->config.r600.max_pipes * 16; ++ switch (rdev->family) { ++ case CHIP_RV610: ++ case CHIP_RS780: ++ case CHIP_RV620: ++ tmp += 32; ++ break; ++ case CHIP_RV670: ++ tmp += 128; ++ break; ++ default: ++ break; ++ } ++ if (tmp > 256) { ++ tmp = 256; ++ } ++ WREG32(VGT_ES_PER_GS, 128); ++ WREG32(VGT_GS_PER_ES, tmp); ++ WREG32(VGT_GS_PER_VS, 2); ++ WREG32(VGT_GS_VERTEX_REUSE, 16); ++ ++ /* more default values. 2D/3D driver should adjust as needed */ ++ WREG32(PA_SC_LINE_STIPPLE_STATE, 0); ++ WREG32(VGT_STRMOUT_EN, 0); ++ WREG32(SX_MISC, 0); ++ WREG32(PA_SC_MODE_CNTL, 0); ++ WREG32(PA_SC_AA_CONFIG, 0); ++ WREG32(PA_SC_LINE_STIPPLE, 0); ++ WREG32(SPI_INPUT_Z, 0); ++ WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); ++ WREG32(CB_COLOR7_FRAG, 0); ++ ++ /* Clear render buffer base addresses */ ++ WREG32(CB_COLOR0_BASE, 0); ++ WREG32(CB_COLOR1_BASE, 0); ++ WREG32(CB_COLOR2_BASE, 0); ++ WREG32(CB_COLOR3_BASE, 0); ++ WREG32(CB_COLOR4_BASE, 0); ++ WREG32(CB_COLOR5_BASE, 0); ++ WREG32(CB_COLOR6_BASE, 0); ++ WREG32(CB_COLOR7_BASE, 0); ++ WREG32(CB_COLOR7_FRAG, 0); ++ ++ switch (rdev->family) { ++ case CHIP_RV610: ++ case CHIP_RS780: ++ case CHIP_RV620: ++ tmp = TC_L2_SIZE(8); ++ break; ++ case CHIP_RV630: ++ case CHIP_RV635: ++ tmp = TC_L2_SIZE(4); ++ break; ++ case CHIP_R600: ++ tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; ++ break; ++ default: ++ tmp = TC_L2_SIZE(0); ++ break; ++ } ++ WREG32(TC_CNTL, tmp); ++ ++ tmp = RREG32(HDP_HOST_PATH_CNTL); ++ WREG32(HDP_HOST_PATH_CNTL, tmp); ++ ++ tmp = RREG32(ARB_POP); ++ tmp |= ENABLE_TC128; ++ WREG32(ARB_POP, tmp); ++ ++ WREG32(PA_SC_MULTI_CHIP_CNTL, 0); ++ WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | ++ NUM_CLIP_SEQ(3))); ++ WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); ++} ++ ++ + /* + * Indirect registers accessor + */ +-uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg) ++u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) ++{ ++ u32 r; ++ ++ WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); ++ (void)RREG32(PCIE_PORT_INDEX); ++ r = RREG32(PCIE_PORT_DATA); ++ return r; ++} ++ ++void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) ++{ ++ WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); ++ (void)RREG32(PCIE_PORT_INDEX); ++ WREG32(PCIE_PORT_DATA, (v)); ++ (void)RREG32(PCIE_PORT_DATA); ++} ++ ++ ++/* ++ * CP & Ring ++ */ ++void r600_cp_stop(struct radeon_device *rdev) ++{ ++ WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); ++} ++ ++int r600_cp_init_microcode(struct radeon_device *rdev) ++{ ++ struct platform_device *pdev; ++ const char *chip_name; ++ size_t pfp_req_size, me_req_size; ++ char fw_name[30]; ++ int err; ++ ++ DRM_DEBUG("\n"); ++ ++ pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); ++ err = IS_ERR(pdev); ++ if (err) { ++ printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); ++ return -EINVAL; ++ } ++ ++ switch (rdev->family) { ++ case CHIP_R600: chip_name = "R600"; break; ++ case CHIP_RV610: chip_name = "RV610"; break; ++ case CHIP_RV630: chip_name = "RV630"; break; ++ case CHIP_RV620: chip_name = "RV620"; break; ++ case CHIP_RV635: chip_name = "RV635"; break; ++ case CHIP_RV670: chip_name = "RV670"; break; ++ case CHIP_RS780: ++ case CHIP_RS880: chip_name = "RS780"; break; ++ case CHIP_RV770: chip_name = "RV770"; break; ++ case CHIP_RV730: ++ case CHIP_RV740: chip_name = "RV730"; break; ++ case CHIP_RV710: chip_name = "RV710"; break; ++ default: BUG(); ++ } ++ ++ if (rdev->family >= CHIP_RV770) { ++ pfp_req_size = R700_PFP_UCODE_SIZE * 4; ++ me_req_size = R700_PM4_UCODE_SIZE * 4; ++ } else { ++ pfp_req_size = PFP_UCODE_SIZE * 4; ++ me_req_size = PM4_UCODE_SIZE * 12; ++ } ++ ++ DRM_INFO("Loading %s CP Microcode\n", chip_name); ++ ++ snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); ++ err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); ++ if (err) ++ goto out; ++ if (rdev->pfp_fw->size != pfp_req_size) { ++ printk(KERN_ERR ++ "r600_cp: Bogus length %zu in firmware \"%s\"\n", ++ rdev->pfp_fw->size, fw_name); ++ err = -EINVAL; ++ goto out; ++ } ++ ++ snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); ++ err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); ++ if (err) ++ goto out; ++ if (rdev->me_fw->size != me_req_size) { ++ printk(KERN_ERR ++ "r600_cp: Bogus length %zu in firmware \"%s\"\n", ++ rdev->me_fw->size, fw_name); ++ err = -EINVAL; ++ } ++out: ++ platform_device_unregister(pdev); ++ ++ if (err) { ++ if (err != -EINVAL) ++ printk(KERN_ERR ++ "r600_cp: Failed to load firmware \"%s\"\n", ++ fw_name); ++ release_firmware(rdev->pfp_fw); ++ rdev->pfp_fw = NULL; ++ release_firmware(rdev->me_fw); ++ rdev->me_fw = NULL; ++ } ++ return err; ++} ++ ++static int r600_cp_load_microcode(struct radeon_device *rdev) ++{ ++ const __be32 *fw_data; ++ int i; ++ ++ if (!rdev->me_fw || !rdev->pfp_fw) ++ return -EINVAL; ++ ++ r600_cp_stop(rdev); ++ ++ WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); ++ ++ /* Reset cp */ ++ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); ++ RREG32(GRBM_SOFT_RESET); ++ mdelay(15); ++ WREG32(GRBM_SOFT_RESET, 0); ++ ++ WREG32(CP_ME_RAM_WADDR, 0); ++ ++ fw_data = (const __be32 *)rdev->me_fw->data; ++ WREG32(CP_ME_RAM_WADDR, 0); ++ for (i = 0; i < PM4_UCODE_SIZE * 3; i++) ++ WREG32(CP_ME_RAM_DATA, ++ be32_to_cpup(fw_data++)); ++ ++ fw_data = (const __be32 *)rdev->pfp_fw->data; ++ WREG32(CP_PFP_UCODE_ADDR, 0); ++ for (i = 0; i < PFP_UCODE_SIZE; i++) ++ WREG32(CP_PFP_UCODE_DATA, ++ be32_to_cpup(fw_data++)); ++ ++ WREG32(CP_PFP_UCODE_ADDR, 0); ++ WREG32(CP_ME_RAM_WADDR, 0); ++ WREG32(CP_ME_RAM_RADDR, 0); ++ return 0; ++} ++ ++int r600_cp_start(struct radeon_device *rdev) ++{ ++ int r; ++ uint32_t cp_me; ++ ++ r = radeon_ring_lock(rdev, 7); ++ if (r) { ++ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); ++ return r; ++ } ++ radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); ++ radeon_ring_write(rdev, 0x1); ++ if (rdev->family < CHIP_RV770) { ++ radeon_ring_write(rdev, 0x3); ++ radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); ++ } else { ++ radeon_ring_write(rdev, 0x0); ++ radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); ++ } ++ radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); ++ radeon_ring_write(rdev, 0); ++ radeon_ring_write(rdev, 0); ++ radeon_ring_unlock_commit(rdev); ++ ++ cp_me = 0xff; ++ WREG32(R_0086D8_CP_ME_CNTL, cp_me); ++ return 0; ++} ++ ++int r600_cp_resume(struct radeon_device *rdev) ++{ ++ u32 tmp; ++ u32 rb_bufsz; ++ int r; ++ ++ /* Reset cp */ ++ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); ++ RREG32(GRBM_SOFT_RESET); ++ mdelay(15); ++ WREG32(GRBM_SOFT_RESET, 0); ++ ++ /* Set ring buffer size */ ++ rb_bufsz = drm_order(rdev->cp.ring_size / 8); ++#ifdef __BIG_ENDIAN ++ WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE | ++ (drm_order(4096/8) << 8) | rb_bufsz); ++#else ++ WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz); ++#endif ++ WREG32(CP_SEM_WAIT_TIMER, 0x4); ++ ++ /* Set the write pointer delay */ ++ WREG32(CP_RB_WPTR_DELAY, 0); ++ ++ /* Initialize the ring buffer's read and write pointers */ ++ tmp = RREG32(CP_RB_CNTL); ++ WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); ++ WREG32(CP_RB_RPTR_WR, 0); ++ WREG32(CP_RB_WPTR, 0); ++ WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); ++ WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); ++ mdelay(1); ++ WREG32(CP_RB_CNTL, tmp); ++ ++ WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); ++ WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); ++ ++ rdev->cp.rptr = RREG32(CP_RB_RPTR); ++ rdev->cp.wptr = RREG32(CP_RB_WPTR); ++ ++ r600_cp_start(rdev); ++ rdev->cp.ready = true; ++ r = radeon_ring_test(rdev); ++ if (r) { ++ rdev->cp.ready = false; ++ return r; ++ } ++ return 0; ++} ++ ++void r600_cp_commit(struct radeon_device *rdev) ++{ ++ WREG32(CP_RB_WPTR, rdev->cp.wptr); ++ (void)RREG32(CP_RB_WPTR); ++} ++ ++void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) ++{ ++ u32 rb_bufsz; ++ ++ /* Align ring size */ ++ rb_bufsz = drm_order(ring_size / 8); ++ ring_size = (1 << (rb_bufsz + 1)) * 4; ++ rdev->cp.ring_size = ring_size; ++ rdev->cp.align_mask = 16 - 1; ++} ++ ++ ++/* ++ * GPU scratch registers helpers function. ++ */ ++void r600_scratch_init(struct radeon_device *rdev) + { +- uint32_t r; ++ int i; + +- WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); +- (void)RREG32(R600_PCIE_PORT_INDEX); +- r = RREG32(R600_PCIE_PORT_DATA); ++ rdev->scratch.num_reg = 7; ++ for (i = 0; i < rdev->scratch.num_reg; i++) { ++ rdev->scratch.free[i] = true; ++ rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); ++ } ++} ++ ++int r600_ring_test(struct radeon_device *rdev) ++{ ++ uint32_t scratch; ++ uint32_t tmp = 0; ++ unsigned i; ++ int r; ++ ++ r = radeon_scratch_get(rdev, &scratch); ++ if (r) { ++ DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); ++ return r; ++ } ++ WREG32(scratch, 0xCAFEDEAD); ++ r = radeon_ring_lock(rdev, 3); ++ if (r) { ++ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); ++ radeon_scratch_free(rdev, scratch); ++ return r; ++ } ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); ++ radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); ++ radeon_ring_write(rdev, 0xDEADBEEF); ++ radeon_ring_unlock_commit(rdev); ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ tmp = RREG32(scratch); ++ if (tmp == 0xDEADBEEF) ++ break; ++ DRM_UDELAY(1); ++ } ++ if (i < rdev->usec_timeout) { ++ DRM_INFO("ring test succeeded in %d usecs\n", i); ++ } else { ++ DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", ++ scratch, tmp); ++ r = -EINVAL; ++ } ++ radeon_scratch_free(rdev, scratch); + return r; + } + +-void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) ++/* ++ * Writeback ++ */ ++int r600_wb_init(struct radeon_device *rdev) + { +- WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); +- (void)RREG32(R600_PCIE_PORT_INDEX); +- WREG32(R600_PCIE_PORT_DATA, (v)); +- (void)RREG32(R600_PCIE_PORT_DATA); ++ int r; ++ ++ if (rdev->wb.wb_obj == NULL) { ++ r = radeon_object_create(rdev, NULL, 4096, ++ true, ++ RADEON_GEM_DOMAIN_GTT, ++ false, &rdev->wb.wb_obj); ++ if (r) { ++ DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r); ++ return r; ++ } ++ r = radeon_object_pin(rdev->wb.wb_obj, ++ RADEON_GEM_DOMAIN_GTT, ++ &rdev->wb.gpu_addr); ++ if (r) { ++ DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r); ++ return r; ++ } ++ r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); ++ if (r) { ++ DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r); ++ return r; ++ } ++ } ++ WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); ++ WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); ++ WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); ++ WREG32(SCRATCH_UMSK, 0xff); ++ return 0; ++} ++ ++void r600_wb_fini(struct radeon_device *rdev) ++{ ++ if (rdev->wb.wb_obj) { ++ radeon_object_kunmap(rdev->wb.wb_obj); ++ radeon_object_unpin(rdev->wb.wb_obj); ++ radeon_object_unref(&rdev->wb.wb_obj); ++ rdev->wb.wb = NULL; ++ rdev->wb.wb_obj = NULL; ++ } ++} ++ ++ ++/* ++ * CS ++ */ ++void r600_fence_ring_emit(struct radeon_device *rdev, ++ struct radeon_fence *fence) ++{ ++ /* Emit fence sequence & fire IRQ */ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); ++ radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); ++ radeon_ring_write(rdev, fence->seq); ++} ++ ++int r600_copy_dma(struct radeon_device *rdev, ++ uint64_t src_offset, ++ uint64_t dst_offset, ++ unsigned num_pages, ++ struct radeon_fence *fence) ++{ ++ /* FIXME: implement */ ++ return 0; ++} ++ ++int r600_copy_blit(struct radeon_device *rdev, ++ uint64_t src_offset, uint64_t dst_offset, ++ unsigned num_pages, struct radeon_fence *fence) ++{ ++ r600_blit_prepare_copy(rdev, num_pages * 4096); ++ r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096); ++ r600_blit_done_copy(rdev, fence); ++ return 0; ++} ++ ++int r600_irq_process(struct radeon_device *rdev) ++{ ++ /* FIXME: implement */ ++ return 0; ++} ++ ++int r600_irq_set(struct radeon_device *rdev) ++{ ++ /* FIXME: implement */ ++ return 0; ++} ++ ++int r600_set_surface_reg(struct radeon_device *rdev, int reg, ++ uint32_t tiling_flags, uint32_t pitch, ++ uint32_t offset, uint32_t obj_size) ++{ ++ /* FIXME: implement */ ++ return 0; ++} ++ ++void r600_clear_surface_reg(struct radeon_device *rdev, int reg) ++{ ++ /* FIXME: implement */ ++} ++ ++ ++bool r600_card_posted(struct radeon_device *rdev) ++{ ++ uint32_t reg; ++ ++ /* first check CRTCs */ ++ reg = RREG32(D1CRTC_CONTROL) | ++ RREG32(D2CRTC_CONTROL); ++ if (reg & CRTC_EN) ++ return true; ++ ++ /* then check MEM_SIZE, in case the crtcs are off */ ++ if (RREG32(CONFIG_MEMSIZE)) ++ return true; ++ ++ return false; ++} ++ ++int r600_startup(struct radeon_device *rdev) ++{ ++ int r; ++ ++ r600_gpu_reset(rdev); ++ r600_mc_resume(rdev); ++ r = r600_pcie_gart_enable(rdev); ++ if (r) ++ return r; ++ r600_gpu_init(rdev); ++ ++ r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, ++ &rdev->r600_blit.shader_gpu_addr); ++ if (r) { ++ DRM_ERROR("failed to pin blit object %d\n", r); ++ return r; ++ } ++ ++ r = radeon_ring_init(rdev, rdev->cp.ring_size); ++ if (r) ++ return r; ++ r = r600_cp_load_microcode(rdev); ++ if (r) ++ return r; ++ r = r600_cp_resume(rdev); ++ if (r) ++ return r; ++ r = r600_wb_init(rdev); ++ if (r) ++ return r; ++ return 0; ++} ++ ++int r600_resume(struct radeon_device *rdev) ++{ ++ int r; ++ ++ if (radeon_gpu_reset(rdev)) { ++ /* FIXME: what do we want to do here ? */ ++ } ++ /* post card */ ++ if (rdev->is_atom_bios) { ++ atom_asic_init(rdev->mode_info.atom_context); ++ } else { ++ radeon_combios_asic_init(rdev->ddev); ++ } ++ /* Initialize clocks */ ++ r = radeon_clocks_init(rdev); ++ if (r) { ++ return r; ++ } ++ ++ r = r600_startup(rdev); ++ if (r) { ++ DRM_ERROR("r600 startup failed on resume\n"); ++ return r; ++ } ++ ++ r = radeon_ib_test(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled testing IB (%d).\n", r); ++ return r; ++ } ++ return r; ++} ++ ++ ++int r600_suspend(struct radeon_device *rdev) ++{ ++ /* FIXME: we should wait for ring to be empty */ ++ r600_cp_stop(rdev); ++ rdev->cp.ready = false; ++ ++ r600_pcie_gart_disable(rdev); ++ /* unpin shaders bo */ ++ radeon_object_unpin(rdev->r600_blit.shader_obj); ++ return 0; ++} ++ ++/* Plan is to move initialization in that function and use ++ * helper function so that radeon_device_init pretty much ++ * do nothing more than calling asic specific function. This ++ * should also allow to remove a bunch of callback function ++ * like vram_info. ++ */ ++int r600_init(struct radeon_device *rdev) ++{ ++ int r; ++ ++ rdev->new_init_path = true; ++ r = radeon_dummy_page_init(rdev); ++ if (r) ++ return r; ++ if (r600_debugfs_mc_info_init(rdev)) { ++ DRM_ERROR("Failed to register debugfs file for mc !\n"); ++ } ++ /* This don't do much */ ++ r = radeon_gem_init(rdev); ++ if (r) ++ return r; ++ /* Read BIOS */ ++ if (!radeon_get_bios(rdev)) { ++ if (ASIC_IS_AVIVO(rdev)) ++ return -EINVAL; ++ } ++ /* Must be an ATOMBIOS */ ++ if (!rdev->is_atom_bios) ++ return -EINVAL; ++ r = radeon_atombios_init(rdev); ++ if (r) ++ return r; ++ /* Post card if necessary */ ++ if (!r600_card_posted(rdev) && rdev->bios) { ++ DRM_INFO("GPU not posted. posting now...\n"); ++ atom_asic_init(rdev->mode_info.atom_context); ++ } ++ /* Initialize scratch registers */ ++ r600_scratch_init(rdev); ++ /* Initialize surface registers */ ++ radeon_surface_init(rdev); ++ radeon_get_clock_info(rdev->ddev); ++ r = radeon_clocks_init(rdev); ++ if (r) ++ return r; ++ /* Fence driver */ ++ r = radeon_fence_driver_init(rdev); ++ if (r) ++ return r; ++ r = r600_mc_init(rdev); ++ if (r) { ++ if (rdev->flags & RADEON_IS_AGP) { ++ /* Retry with disabling AGP */ ++ r600_fini(rdev); ++ rdev->flags &= ~RADEON_IS_AGP; ++ return r600_init(rdev); ++ } ++ return r; ++ } ++ /* Memory manager */ ++ r = radeon_object_init(rdev); ++ if (r) ++ return r; ++ rdev->cp.ring_obj = NULL; ++ r600_ring_init(rdev, 1024 * 1024); ++ ++ if (!rdev->me_fw || !rdev->pfp_fw) { ++ r = r600_cp_init_microcode(rdev); ++ if (r) { ++ DRM_ERROR("Failed to load firmware!\n"); ++ return r; ++ } ++ } ++ ++ r = r600_pcie_gart_init(rdev); ++ if (r) ++ return r; ++ ++ rdev->accel_working = true; ++ r = r600_blit_init(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled blitter (%d).\n", r); ++ return r; ++ } ++ ++ r = r600_startup(rdev); ++ if (r) { ++ if (rdev->flags & RADEON_IS_AGP) { ++ /* Retry with disabling AGP */ ++ r600_fini(rdev); ++ rdev->flags &= ~RADEON_IS_AGP; ++ return r600_init(rdev); ++ } ++ rdev->accel_working = false; ++ } ++ if (rdev->accel_working) { ++ r = radeon_ib_pool_init(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); ++ rdev->accel_working = false; ++ } ++ r = radeon_ib_test(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled testing IB (%d).\n", r); ++ rdev->accel_working = false; ++ } ++ } ++ return 0; ++} ++ ++void r600_fini(struct radeon_device *rdev) ++{ ++ /* Suspend operations */ ++ r600_suspend(rdev); ++ ++ r600_blit_fini(rdev); ++ radeon_ring_fini(rdev); ++ r600_pcie_gart_fini(rdev); ++ radeon_gem_fini(rdev); ++ radeon_fence_driver_fini(rdev); ++ radeon_clocks_fini(rdev); ++#if __OS_HAS_AGP ++ if (rdev->flags & RADEON_IS_AGP) ++ radeon_agp_fini(rdev); ++#endif ++ radeon_object_fini(rdev); ++ if (rdev->is_atom_bios) ++ radeon_atombios_fini(rdev); ++ else ++ radeon_combios_fini(rdev); ++ kfree(rdev->bios); ++ rdev->bios = NULL; ++ radeon_dummy_page_fini(rdev); ++} ++ ++ ++/* ++ * CS stuff ++ */ ++void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) ++{ ++ /* FIXME: implement */ ++ radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); ++ radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); ++ radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); ++ radeon_ring_write(rdev, ib->length_dw); ++} ++ ++int r600_ib_test(struct radeon_device *rdev) ++{ ++ struct radeon_ib *ib; ++ uint32_t scratch; ++ uint32_t tmp = 0; ++ unsigned i; ++ int r; ++ ++ r = radeon_scratch_get(rdev, &scratch); ++ if (r) { ++ DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); ++ return r; ++ } ++ WREG32(scratch, 0xCAFEDEAD); ++ r = radeon_ib_get(rdev, &ib); ++ if (r) { ++ DRM_ERROR("radeon: failed to get ib (%d).\n", r); ++ return r; ++ } ++ ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); ++ ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); ++ ib->ptr[2] = 0xDEADBEEF; ++ ib->ptr[3] = PACKET2(0); ++ ib->ptr[4] = PACKET2(0); ++ ib->ptr[5] = PACKET2(0); ++ ib->ptr[6] = PACKET2(0); ++ ib->ptr[7] = PACKET2(0); ++ ib->ptr[8] = PACKET2(0); ++ ib->ptr[9] = PACKET2(0); ++ ib->ptr[10] = PACKET2(0); ++ ib->ptr[11] = PACKET2(0); ++ ib->ptr[12] = PACKET2(0); ++ ib->ptr[13] = PACKET2(0); ++ ib->ptr[14] = PACKET2(0); ++ ib->ptr[15] = PACKET2(0); ++ ib->length_dw = 16; ++ r = radeon_ib_schedule(rdev, ib); ++ if (r) { ++ radeon_scratch_free(rdev, scratch); ++ radeon_ib_free(rdev, &ib); ++ DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); ++ return r; ++ } ++ r = radeon_fence_wait(ib->fence, false); ++ if (r) { ++ DRM_ERROR("radeon: fence wait failed (%d).\n", r); ++ return r; ++ } ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ tmp = RREG32(scratch); ++ if (tmp == 0xDEADBEEF) ++ break; ++ DRM_UDELAY(1); ++ } ++ if (i < rdev->usec_timeout) { ++ DRM_INFO("ib test succeeded in %u usecs\n", i); ++ } else { ++ DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", ++ scratch, tmp); ++ r = -EINVAL; ++ } ++ radeon_scratch_free(rdev, scratch); ++ radeon_ib_free(rdev, &ib); ++ return r; ++} ++ ++ ++ ++ ++/* ++ * Debugfs info ++ */ ++#if defined(CONFIG_DEBUG_FS) ++ ++static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ uint32_t rdp, wdp; ++ unsigned count, i, j; ++ ++ radeon_ring_free_size(rdev); ++ rdp = RREG32(CP_RB_RPTR); ++ wdp = RREG32(CP_RB_WPTR); ++ count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; ++ seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); ++ seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); ++ seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); ++ seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); ++ seq_printf(m, "%u dwords in ring\n", count); ++ for (j = 0; j <= count; j++) { ++ i = (rdp + j) & rdev->cp.ptr_mask; ++ seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); ++ } ++ return 0; ++} ++ ++static int r600_debugfs_mc_info(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *) m->private; ++ struct drm_device *dev = node->minor->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ ++ DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); ++ DREG32_SYS(m, rdev, VM_L2_STATUS); ++ return 0; ++} ++ ++static struct drm_info_list r600_mc_info_list[] = { ++ {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, ++ {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, ++}; ++#endif ++ ++int r600_debugfs_mc_info_init(struct radeon_device *rdev) ++{ ++#if defined(CONFIG_DEBUG_FS) ++ return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); ++#else ++ return 0; ++#endif + } +diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c +new file mode 100644 +index 0000000..d988eec +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r600_blit.c +@@ -0,0 +1,850 @@ ++/* ++ * Copyright 2009 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Alex Deucher <alexander.deucher@amd.com> ++ */ ++#include "drmP.h" ++#include "drm.h" ++#include "radeon_drm.h" ++#include "radeon_drv.h" ++ ++#include "r600_blit_shaders.h" ++ ++#define DI_PT_RECTLIST 0x11 ++#define DI_INDEX_SIZE_16_BIT 0x0 ++#define DI_SRC_SEL_AUTO_INDEX 0x2 ++ ++#define FMT_8 0x1 ++#define FMT_5_6_5 0x8 ++#define FMT_8_8_8_8 0x1a ++#define COLOR_8 0x1 ++#define COLOR_5_6_5 0x8 ++#define COLOR_8_8_8_8 0x1a ++ ++static inline void ++set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) ++{ ++ u32 cb_color_info; ++ int pitch, slice; ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ h = (h + 7) & ~7; ++ if (h < 8) ++ h = 8; ++ ++ cb_color_info = ((format << 2) | (1 << 27)); ++ pitch = (w / 8) - 1; ++ slice = ((w * h) / 64) - 1; ++ ++ if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) && ++ ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) { ++ BEGIN_RING(21 + 2); ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(gpu_addr >> 8); ++ OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); ++ OUT_RING(2 << 0); ++ } else { ++ BEGIN_RING(21); ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(gpu_addr >> 8); ++ } ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING((pitch << 0) | (slice << 10)); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(0); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(cb_color_info); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(0); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(0); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(0); ++ ++ ADVANCE_RING(); ++} ++ ++static inline void ++cp_set_surface_sync(drm_radeon_private_t *dev_priv, ++ u32 sync_type, u32 size, u64 mc_addr) ++{ ++ u32 cp_coher_size; ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ if (size == 0xffffffff) ++ cp_coher_size = 0xffffffff; ++ else ++ cp_coher_size = ((size + 255) >> 8); ++ ++ BEGIN_RING(5); ++ OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); ++ OUT_RING(sync_type); ++ OUT_RING(cp_coher_size); ++ OUT_RING((mc_addr >> 8)); ++ OUT_RING(10); /* poll interval */ ++ ADVANCE_RING(); ++} ++ ++static inline void ++set_shaders(struct drm_device *dev) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ u64 gpu_addr; ++ int i; ++ u32 *vs, *ps; ++ uint32_t sq_pgm_resources; ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ /* load shaders */ ++ vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset); ++ ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); ++ ++ for (i = 0; i < r6xx_vs_size; i++) ++ vs[i] = r6xx_vs[i]; ++ for (i = 0; i < r6xx_ps_size; i++) ++ ps[i] = r6xx_ps[i]; ++ ++ dev_priv->blit_vb->used = 512; ++ ++ gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; ++ ++ /* setup shader regs */ ++ sq_pgm_resources = (1 << 0); ++ ++ BEGIN_RING(9 + 12); ++ /* VS */ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(gpu_addr >> 8); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(sq_pgm_resources); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(0); ++ ++ /* PS */ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING((gpu_addr + 256) >> 8); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(sq_pgm_resources | (1 << 28)); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(2); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); ++ OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING(0); ++ ADVANCE_RING(); ++ ++ cp_set_surface_sync(dev_priv, ++ R600_SH_ACTION_ENA, 512, gpu_addr); ++} ++ ++static inline void ++set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) ++{ ++ uint32_t sq_vtx_constant_word2; ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); ++ ++ BEGIN_RING(9); ++ OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); ++ OUT_RING(0x460); ++ OUT_RING(gpu_addr & 0xffffffff); ++ OUT_RING(48 - 1); ++ OUT_RING(sq_vtx_constant_word2); ++ OUT_RING(1 << 0); ++ OUT_RING(0); ++ OUT_RING(0); ++ OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30); ++ ADVANCE_RING(); ++ ++ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || ++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || ++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || ++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) || ++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) ++ cp_set_surface_sync(dev_priv, ++ R600_TC_ACTION_ENA, 48, gpu_addr); ++ else ++ cp_set_surface_sync(dev_priv, ++ R600_VC_ACTION_ENA, 48, gpu_addr); ++} ++ ++static inline void ++set_tex_resource(drm_radeon_private_t *dev_priv, ++ int format, int w, int h, int pitch, u64 gpu_addr) ++{ ++ uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ if (h < 1) ++ h = 1; ++ ++ sq_tex_resource_word0 = (1 << 0); ++ sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | ++ ((w - 1) << 19)); ++ ++ sq_tex_resource_word1 = (format << 26); ++ sq_tex_resource_word1 |= ((h - 1) << 0); ++ ++ sq_tex_resource_word4 = ((1 << 14) | ++ (0 << 16) | ++ (1 << 19) | ++ (2 << 22) | ++ (3 << 25)); ++ ++ BEGIN_RING(9); ++ OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); ++ OUT_RING(0); ++ OUT_RING(sq_tex_resource_word0); ++ OUT_RING(sq_tex_resource_word1); ++ OUT_RING(gpu_addr >> 8); ++ OUT_RING(gpu_addr >> 8); ++ OUT_RING(sq_tex_resource_word4); ++ OUT_RING(0); ++ OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30); ++ ADVANCE_RING(); ++ ++} ++ ++static inline void ++set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2) ++{ ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ BEGIN_RING(12); ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); ++ OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING((x1 << 0) | (y1 << 16)); ++ OUT_RING((x2 << 0) | (y2 << 16)); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); ++ OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); ++ OUT_RING((x2 << 0) | (y2 << 16)); ++ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); ++ OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); ++ OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); ++ OUT_RING((x2 << 0) | (y2 << 16)); ++ ADVANCE_RING(); ++} ++ ++static inline void ++draw_auto(drm_radeon_private_t *dev_priv) ++{ ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ BEGIN_RING(10); ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); ++ OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2); ++ OUT_RING(DI_PT_RECTLIST); ++ ++ OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); ++ OUT_RING(DI_INDEX_SIZE_16_BIT); ++ ++ OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); ++ OUT_RING(1); ++ ++ OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1)); ++ OUT_RING(3); ++ OUT_RING(DI_SRC_SEL_AUTO_INDEX); ++ ++ ADVANCE_RING(); ++ COMMIT_RING(); ++} ++ ++static inline void ++set_default_state(drm_radeon_private_t *dev_priv) ++{ ++ int i; ++ u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; ++ u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; ++ int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; ++ int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; ++ int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; ++ RING_LOCALS; ++ ++ switch ((dev_priv->flags & RADEON_FAMILY_MASK)) { ++ case CHIP_R600: ++ num_ps_gprs = 192; ++ num_vs_gprs = 56; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 136; ++ num_vs_threads = 48; ++ num_gs_threads = 4; ++ num_es_threads = 4; ++ num_ps_stack_entries = 128; ++ num_vs_stack_entries = 128; ++ num_gs_stack_entries = 0; ++ num_es_stack_entries = 0; ++ break; ++ case CHIP_RV630: ++ case CHIP_RV635: ++ num_ps_gprs = 84; ++ num_vs_gprs = 36; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 144; ++ num_vs_threads = 40; ++ num_gs_threads = 4; ++ num_es_threads = 4; ++ num_ps_stack_entries = 40; ++ num_vs_stack_entries = 40; ++ num_gs_stack_entries = 32; ++ num_es_stack_entries = 16; ++ break; ++ case CHIP_RV610: ++ case CHIP_RV620: ++ case CHIP_RS780: ++ case CHIP_RS880: ++ default: ++ num_ps_gprs = 84; ++ num_vs_gprs = 36; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 136; ++ num_vs_threads = 48; ++ num_gs_threads = 4; ++ num_es_threads = 4; ++ num_ps_stack_entries = 40; ++ num_vs_stack_entries = 40; ++ num_gs_stack_entries = 32; ++ num_es_stack_entries = 16; ++ break; ++ case CHIP_RV670: ++ num_ps_gprs = 144; ++ num_vs_gprs = 40; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 136; ++ num_vs_threads = 48; ++ num_gs_threads = 4; ++ num_es_threads = 4; ++ num_ps_stack_entries = 40; ++ num_vs_stack_entries = 40; ++ num_gs_stack_entries = 32; ++ num_es_stack_entries = 16; ++ break; ++ case CHIP_RV770: ++ num_ps_gprs = 192; ++ num_vs_gprs = 56; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 188; ++ num_vs_threads = 60; ++ num_gs_threads = 0; ++ num_es_threads = 0; ++ num_ps_stack_entries = 256; ++ num_vs_stack_entries = 256; ++ num_gs_stack_entries = 0; ++ num_es_stack_entries = 0; ++ break; ++ case CHIP_RV730: ++ case CHIP_RV740: ++ num_ps_gprs = 84; ++ num_vs_gprs = 36; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 188; ++ num_vs_threads = 60; ++ num_gs_threads = 0; ++ num_es_threads = 0; ++ num_ps_stack_entries = 128; ++ num_vs_stack_entries = 128; ++ num_gs_stack_entries = 0; ++ num_es_stack_entries = 0; ++ break; ++ case CHIP_RV710: ++ num_ps_gprs = 192; ++ num_vs_gprs = 56; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 144; ++ num_vs_threads = 48; ++ num_gs_threads = 0; ++ num_es_threads = 0; ++ num_ps_stack_entries = 128; ++ num_vs_stack_entries = 128; ++ num_gs_stack_entries = 0; ++ num_es_stack_entries = 0; ++ break; ++ } ++ ++ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || ++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || ++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || ++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) || ++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) ++ sq_config = 0; ++ else ++ sq_config = R600_VC_ENABLE; ++ ++ sq_config |= (R600_DX9_CONSTS | ++ R600_ALU_INST_PREFER_VECTOR | ++ R600_PS_PRIO(0) | ++ R600_VS_PRIO(1) | ++ R600_GS_PRIO(2) | ++ R600_ES_PRIO(3)); ++ ++ sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) | ++ R600_NUM_VS_GPRS(num_vs_gprs) | ++ R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); ++ sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) | ++ R600_NUM_ES_GPRS(num_es_gprs)); ++ sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) | ++ R600_NUM_VS_THREADS(num_vs_threads) | ++ R600_NUM_GS_THREADS(num_gs_threads) | ++ R600_NUM_ES_THREADS(num_es_threads)); ++ sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | ++ R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); ++ sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | ++ R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries)); ++ ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { ++ BEGIN_RING(r7xx_default_size + 10); ++ for (i = 0; i < r7xx_default_size; i++) ++ OUT_RING(r7xx_default_state[i]); ++ } else { ++ BEGIN_RING(r6xx_default_size + 10); ++ for (i = 0; i < r6xx_default_size; i++) ++ OUT_RING(r6xx_default_state[i]); ++ } ++ OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); ++ OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); ++ /* SQ config */ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6)); ++ OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2); ++ OUT_RING(sq_config); ++ OUT_RING(sq_gpr_resource_mgmt_1); ++ OUT_RING(sq_gpr_resource_mgmt_2); ++ OUT_RING(sq_thread_resource_mgmt); ++ OUT_RING(sq_stack_resource_mgmt_1); ++ OUT_RING(sq_stack_resource_mgmt_2); ++ ADVANCE_RING(); ++} ++ ++static inline uint32_t i2f(uint32_t input) ++{ ++ u32 result, i, exponent, fraction; ++ ++ if ((input & 0x3fff) == 0) ++ result = 0; /* 0 is a special case */ ++ else { ++ exponent = 140; /* exponent biased by 127; */ ++ fraction = (input & 0x3fff) << 10; /* cheat and only ++ handle numbers below 2^^15 */ ++ for (i = 0; i < 14; i++) { ++ if (fraction & 0x800000) ++ break; ++ else { ++ fraction = fraction << 1; /* keep ++ shifting left until top bit = 1 */ ++ exponent = exponent - 1; ++ } ++ } ++ result = exponent << 23 | (fraction & 0x7fffff); /* mask ++ off top bit; assumed 1 */ ++ } ++ return result; ++} ++ ++ ++static inline int r600_nomm_get_vb(struct drm_device *dev) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ dev_priv->blit_vb = radeon_freelist_get(dev); ++ if (!dev_priv->blit_vb) { ++ DRM_ERROR("Unable to allocate vertex buffer for blit\n"); ++ return -EAGAIN; ++ } ++ return 0; ++} ++ ++static inline void r600_nomm_put_vb(struct drm_device *dev) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ ++ dev_priv->blit_vb->used = 0; ++ radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb); ++} ++ ++static inline void *r600_nomm_get_vb_ptr(struct drm_device *dev) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ return (((char *)dev->agp_buffer_map->handle + ++ dev_priv->blit_vb->offset + dev_priv->blit_vb->used)); ++} ++ ++int ++r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ DRM_DEBUG("\n"); ++ ++ r600_nomm_get_vb(dev); ++ ++ dev_priv->blit_vb->file_priv = file_priv; ++ ++ set_default_state(dev_priv); ++ set_shaders(dev); ++ ++ return 0; ++} ++ ++ ++void ++r600_done_blit_copy(struct drm_device *dev) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ BEGIN_RING(5); ++ OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); ++ OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); ++ /* wait for 3D idle clean */ ++ OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); ++ OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); ++ OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); ++ ++ ADVANCE_RING(); ++ COMMIT_RING(); ++ ++ r600_nomm_put_vb(dev); ++} ++ ++void ++r600_blit_copy(struct drm_device *dev, ++ uint64_t src_gpu_addr, uint64_t dst_gpu_addr, ++ int size_bytes) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ int max_bytes; ++ u64 vb_addr; ++ u32 *vb; ++ ++ vb = r600_nomm_get_vb_ptr(dev); ++ ++ if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { ++ max_bytes = 8192; ++ ++ while (size_bytes) { ++ int cur_size = size_bytes; ++ int src_x = src_gpu_addr & 255; ++ int dst_x = dst_gpu_addr & 255; ++ int h = 1; ++ src_gpu_addr = src_gpu_addr & ~255; ++ dst_gpu_addr = dst_gpu_addr & ~255; ++ ++ if (!src_x && !dst_x) { ++ h = (cur_size / max_bytes); ++ if (h > 8192) ++ h = 8192; ++ if (h == 0) ++ h = 1; ++ else ++ cur_size = max_bytes; ++ } else { ++ if (cur_size > max_bytes) ++ cur_size = max_bytes; ++ if (cur_size > (max_bytes - dst_x)) ++ cur_size = (max_bytes - dst_x); ++ if (cur_size > (max_bytes - src_x)) ++ cur_size = (max_bytes - src_x); ++ } ++ ++ if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { ++ ++ r600_nomm_put_vb(dev); ++ r600_nomm_get_vb(dev); ++ if (!dev_priv->blit_vb) ++ return; ++ set_shaders(dev); ++ vb = r600_nomm_get_vb_ptr(dev); ++ } ++ ++ vb[0] = i2f(dst_x); ++ vb[1] = 0; ++ vb[2] = i2f(src_x); ++ vb[3] = 0; ++ ++ vb[4] = i2f(dst_x); ++ vb[5] = i2f(h); ++ vb[6] = i2f(src_x); ++ vb[7] = i2f(h); ++ ++ vb[8] = i2f(dst_x + cur_size); ++ vb[9] = i2f(h); ++ vb[10] = i2f(src_x + cur_size); ++ vb[11] = i2f(h); ++ ++ /* src */ ++ set_tex_resource(dev_priv, FMT_8, ++ src_x + cur_size, h, src_x + cur_size, ++ src_gpu_addr); ++ ++ cp_set_surface_sync(dev_priv, ++ R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); ++ ++ /* dst */ ++ set_render_target(dev_priv, COLOR_8, ++ dst_x + cur_size, h, ++ dst_gpu_addr); ++ ++ /* scissors */ ++ set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h); ++ ++ /* Vertex buffer setup */ ++ vb_addr = dev_priv->gart_buffers_offset + ++ dev_priv->blit_vb->offset + ++ dev_priv->blit_vb->used; ++ set_vtx_resource(dev_priv, vb_addr); ++ ++ /* draw */ ++ draw_auto(dev_priv); ++ ++ cp_set_surface_sync(dev_priv, ++ R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, ++ cur_size * h, dst_gpu_addr); ++ ++ vb += 12; ++ dev_priv->blit_vb->used += 12 * 4; ++ ++ src_gpu_addr += cur_size * h; ++ dst_gpu_addr += cur_size * h; ++ size_bytes -= cur_size * h; ++ } ++ } else { ++ max_bytes = 8192 * 4; ++ ++ while (size_bytes) { ++ int cur_size = size_bytes; ++ int src_x = (src_gpu_addr & 255); ++ int dst_x = (dst_gpu_addr & 255); ++ int h = 1; ++ src_gpu_addr = src_gpu_addr & ~255; ++ dst_gpu_addr = dst_gpu_addr & ~255; ++ ++ if (!src_x && !dst_x) { ++ h = (cur_size / max_bytes); ++ if (h > 8192) ++ h = 8192; ++ if (h == 0) ++ h = 1; ++ else ++ cur_size = max_bytes; ++ } else { ++ if (cur_size > max_bytes) ++ cur_size = max_bytes; ++ if (cur_size > (max_bytes - dst_x)) ++ cur_size = (max_bytes - dst_x); ++ if (cur_size > (max_bytes - src_x)) ++ cur_size = (max_bytes - src_x); ++ } ++ ++ if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { ++ r600_nomm_put_vb(dev); ++ r600_nomm_get_vb(dev); ++ if (!dev_priv->blit_vb) ++ return; ++ ++ set_shaders(dev); ++ vb = r600_nomm_get_vb_ptr(dev); ++ } ++ ++ vb[0] = i2f(dst_x / 4); ++ vb[1] = 0; ++ vb[2] = i2f(src_x / 4); ++ vb[3] = 0; ++ ++ vb[4] = i2f(dst_x / 4); ++ vb[5] = i2f(h); ++ vb[6] = i2f(src_x / 4); ++ vb[7] = i2f(h); ++ ++ vb[8] = i2f((dst_x + cur_size) / 4); ++ vb[9] = i2f(h); ++ vb[10] = i2f((src_x + cur_size) / 4); ++ vb[11] = i2f(h); ++ ++ /* src */ ++ set_tex_resource(dev_priv, FMT_8_8_8_8, ++ (src_x + cur_size) / 4, ++ h, (src_x + cur_size) / 4, ++ src_gpu_addr); ++ ++ cp_set_surface_sync(dev_priv, ++ R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); ++ ++ /* dst */ ++ set_render_target(dev_priv, COLOR_8_8_8_8, ++ (dst_x + cur_size) / 4, h, ++ dst_gpu_addr); ++ ++ /* scissors */ ++ set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h); ++ ++ /* Vertex buffer setup */ ++ vb_addr = dev_priv->gart_buffers_offset + ++ dev_priv->blit_vb->offset + ++ dev_priv->blit_vb->used; ++ set_vtx_resource(dev_priv, vb_addr); ++ ++ /* draw */ ++ draw_auto(dev_priv); ++ ++ cp_set_surface_sync(dev_priv, ++ R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, ++ cur_size * h, dst_gpu_addr); ++ ++ vb += 12; ++ dev_priv->blit_vb->used += 12 * 4; ++ ++ src_gpu_addr += cur_size * h; ++ dst_gpu_addr += cur_size * h; ++ size_bytes -= cur_size * h; ++ } ++ } ++} ++ ++void ++r600_blit_swap(struct drm_device *dev, ++ uint64_t src_gpu_addr, uint64_t dst_gpu_addr, ++ int sx, int sy, int dx, int dy, ++ int w, int h, int src_pitch, int dst_pitch, int cpp) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ int cb_format, tex_format; ++ u64 vb_addr; ++ u32 *vb; ++ ++ vb = r600_nomm_get_vb_ptr(dev); ++ ++ if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { ++ ++ r600_nomm_put_vb(dev); ++ r600_nomm_get_vb(dev); ++ if (!dev_priv->blit_vb) ++ return; ++ ++ set_shaders(dev); ++ vb = r600_nomm_get_vb_ptr(dev); ++ } ++ ++ if (cpp == 4) { ++ cb_format = COLOR_8_8_8_8; ++ tex_format = FMT_8_8_8_8; ++ } else if (cpp == 2) { ++ cb_format = COLOR_5_6_5; ++ tex_format = FMT_5_6_5; ++ } else { ++ cb_format = COLOR_8; ++ tex_format = FMT_8; ++ } ++ ++ vb[0] = i2f(dx); ++ vb[1] = i2f(dy); ++ vb[2] = i2f(sx); ++ vb[3] = i2f(sy); ++ ++ vb[4] = i2f(dx); ++ vb[5] = i2f(dy + h); ++ vb[6] = i2f(sx); ++ vb[7] = i2f(sy + h); ++ ++ vb[8] = i2f(dx + w); ++ vb[9] = i2f(dy + h); ++ vb[10] = i2f(sx + w); ++ vb[11] = i2f(sy + h); ++ ++ /* src */ ++ set_tex_resource(dev_priv, tex_format, ++ src_pitch / cpp, ++ sy + h, src_pitch / cpp, ++ src_gpu_addr); ++ ++ cp_set_surface_sync(dev_priv, ++ R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr); ++ ++ /* dst */ ++ set_render_target(dev_priv, cb_format, ++ dst_pitch / cpp, dy + h, ++ dst_gpu_addr); ++ ++ /* scissors */ ++ set_scissors(dev_priv, dx, dy, dx + w, dy + h); ++ ++ /* Vertex buffer setup */ ++ vb_addr = dev_priv->gart_buffers_offset + ++ dev_priv->blit_vb->offset + ++ dev_priv->blit_vb->used; ++ set_vtx_resource(dev_priv, vb_addr); ++ ++ /* draw */ ++ draw_auto(dev_priv); ++ ++ cp_set_surface_sync(dev_priv, ++ R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, ++ dst_pitch * (dy + h), dst_gpu_addr); ++ ++ dev_priv->blit_vb->used += 12 * 4; ++} +diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c +new file mode 100644 +index 0000000..acae33e +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r600_blit_kms.c +@@ -0,0 +1,805 @@ ++#include "drmP.h" ++#include "drm.h" ++#include "radeon_drm.h" ++#include "radeon.h" ++ ++#include "r600d.h" ++#include "r600_blit_shaders.h" ++ ++#define DI_PT_RECTLIST 0x11 ++#define DI_INDEX_SIZE_16_BIT 0x0 ++#define DI_SRC_SEL_AUTO_INDEX 0x2 ++ ++#define FMT_8 0x1 ++#define FMT_5_6_5 0x8 ++#define FMT_8_8_8_8 0x1a ++#define COLOR_8 0x1 ++#define COLOR_5_6_5 0x8 ++#define COLOR_8_8_8_8 0x1a ++ ++/* emits 21 on rv770+, 23 on r600 */ ++static void ++set_render_target(struct radeon_device *rdev, int format, ++ int w, int h, u64 gpu_addr) ++{ ++ u32 cb_color_info; ++ int pitch, slice; ++ ++ h = (h + 7) & ~7; ++ if (h < 8) ++ h = 8; ++ ++ cb_color_info = ((format << 2) | (1 << 27)); ++ pitch = (w / 8) - 1; ++ slice = ((w * h) / 64) - 1; ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, gpu_addr >> 8); ++ ++ if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { ++ radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); ++ radeon_ring_write(rdev, 2 << 0); ++ } ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, 0); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, cb_color_info); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, 0); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, 0); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, 0); ++} ++ ++/* emits 5dw */ ++static void ++cp_set_surface_sync(struct radeon_device *rdev, ++ u32 sync_type, u32 size, ++ u64 mc_addr) ++{ ++ u32 cp_coher_size; ++ ++ if (size == 0xffffffff) ++ cp_coher_size = 0xffffffff; ++ else ++ cp_coher_size = ((size + 255) >> 8); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); ++ radeon_ring_write(rdev, sync_type); ++ radeon_ring_write(rdev, cp_coher_size); ++ radeon_ring_write(rdev, mc_addr >> 8); ++ radeon_ring_write(rdev, 10); /* poll interval */ ++} ++ ++/* emits 21dw + 1 surface sync = 26dw */ ++static void ++set_shaders(struct radeon_device *rdev) ++{ ++ u64 gpu_addr; ++ u32 sq_pgm_resources; ++ ++ /* setup shader regs */ ++ sq_pgm_resources = (1 << 0); ++ ++ /* VS */ ++ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, gpu_addr >> 8); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, sq_pgm_resources); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, 0); ++ ++ /* PS */ ++ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, gpu_addr >> 8); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, 2); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, 0); ++ ++ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; ++ cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); ++} ++ ++/* emits 9 + 1 sync (5) = 14*/ ++static void ++set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) ++{ ++ u32 sq_vtx_constant_word2; ++ ++ sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); ++ radeon_ring_write(rdev, 0x460); ++ radeon_ring_write(rdev, gpu_addr & 0xffffffff); ++ radeon_ring_write(rdev, 48 - 1); ++ radeon_ring_write(rdev, sq_vtx_constant_word2); ++ radeon_ring_write(rdev, 1 << 0); ++ radeon_ring_write(rdev, 0); ++ radeon_ring_write(rdev, 0); ++ radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); ++ ++ if ((rdev->family == CHIP_RV610) || ++ (rdev->family == CHIP_RV620) || ++ (rdev->family == CHIP_RS780) || ++ (rdev->family == CHIP_RS880) || ++ (rdev->family == CHIP_RV710)) ++ cp_set_surface_sync(rdev, ++ PACKET3_TC_ACTION_ENA, 48, gpu_addr); ++ else ++ cp_set_surface_sync(rdev, ++ PACKET3_VC_ACTION_ENA, 48, gpu_addr); ++} ++ ++/* emits 9 */ ++static void ++set_tex_resource(struct radeon_device *rdev, ++ int format, int w, int h, int pitch, ++ u64 gpu_addr) ++{ ++ uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; ++ ++ if (h < 1) ++ h = 1; ++ ++ sq_tex_resource_word0 = (1 << 0); ++ sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | ++ ((w - 1) << 19)); ++ ++ sq_tex_resource_word1 = (format << 26); ++ sq_tex_resource_word1 |= ((h - 1) << 0); ++ ++ sq_tex_resource_word4 = ((1 << 14) | ++ (0 << 16) | ++ (1 << 19) | ++ (2 << 22) | ++ (3 << 25)); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); ++ radeon_ring_write(rdev, 0); ++ radeon_ring_write(rdev, sq_tex_resource_word0); ++ radeon_ring_write(rdev, sq_tex_resource_word1); ++ radeon_ring_write(rdev, gpu_addr >> 8); ++ radeon_ring_write(rdev, gpu_addr >> 8); ++ radeon_ring_write(rdev, sq_tex_resource_word4); ++ radeon_ring_write(rdev, 0); ++ radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); ++} ++ ++/* emits 12 */ ++static void ++set_scissors(struct radeon_device *rdev, int x1, int y1, ++ int x2, int y2) ++{ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); ++ radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); ++ radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); ++ radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); ++ radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); ++ radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); ++ radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); ++} ++ ++/* emits 10 */ ++static void ++draw_auto(struct radeon_device *rdev) ++{ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); ++ radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, DI_PT_RECTLIST); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); ++ radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); ++ radeon_ring_write(rdev, 1); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); ++ radeon_ring_write(rdev, 3); ++ radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); ++ ++} ++ ++/* emits 14 */ ++static void ++set_default_state(struct radeon_device *rdev) ++{ ++ u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; ++ u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; ++ int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; ++ int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; ++ int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; ++ u64 gpu_addr; ++ int dwords; ++ ++ switch (rdev->family) { ++ case CHIP_R600: ++ num_ps_gprs = 192; ++ num_vs_gprs = 56; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 136; ++ num_vs_threads = 48; ++ num_gs_threads = 4; ++ num_es_threads = 4; ++ num_ps_stack_entries = 128; ++ num_vs_stack_entries = 128; ++ num_gs_stack_entries = 0; ++ num_es_stack_entries = 0; ++ break; ++ case CHIP_RV630: ++ case CHIP_RV635: ++ num_ps_gprs = 84; ++ num_vs_gprs = 36; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 144; ++ num_vs_threads = 40; ++ num_gs_threads = 4; ++ num_es_threads = 4; ++ num_ps_stack_entries = 40; ++ num_vs_stack_entries = 40; ++ num_gs_stack_entries = 32; ++ num_es_stack_entries = 16; ++ break; ++ case CHIP_RV610: ++ case CHIP_RV620: ++ case CHIP_RS780: ++ case CHIP_RS880: ++ default: ++ num_ps_gprs = 84; ++ num_vs_gprs = 36; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 136; ++ num_vs_threads = 48; ++ num_gs_threads = 4; ++ num_es_threads = 4; ++ num_ps_stack_entries = 40; ++ num_vs_stack_entries = 40; ++ num_gs_stack_entries = 32; ++ num_es_stack_entries = 16; ++ break; ++ case CHIP_RV670: ++ num_ps_gprs = 144; ++ num_vs_gprs = 40; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 136; ++ num_vs_threads = 48; ++ num_gs_threads = 4; ++ num_es_threads = 4; ++ num_ps_stack_entries = 40; ++ num_vs_stack_entries = 40; ++ num_gs_stack_entries = 32; ++ num_es_stack_entries = 16; ++ break; ++ case CHIP_RV770: ++ num_ps_gprs = 192; ++ num_vs_gprs = 56; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 188; ++ num_vs_threads = 60; ++ num_gs_threads = 0; ++ num_es_threads = 0; ++ num_ps_stack_entries = 256; ++ num_vs_stack_entries = 256; ++ num_gs_stack_entries = 0; ++ num_es_stack_entries = 0; ++ break; ++ case CHIP_RV730: ++ case CHIP_RV740: ++ num_ps_gprs = 84; ++ num_vs_gprs = 36; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 188; ++ num_vs_threads = 60; ++ num_gs_threads = 0; ++ num_es_threads = 0; ++ num_ps_stack_entries = 128; ++ num_vs_stack_entries = 128; ++ num_gs_stack_entries = 0; ++ num_es_stack_entries = 0; ++ break; ++ case CHIP_RV710: ++ num_ps_gprs = 192; ++ num_vs_gprs = 56; ++ num_temp_gprs = 4; ++ num_gs_gprs = 0; ++ num_es_gprs = 0; ++ num_ps_threads = 144; ++ num_vs_threads = 48; ++ num_gs_threads = 0; ++ num_es_threads = 0; ++ num_ps_stack_entries = 128; ++ num_vs_stack_entries = 128; ++ num_gs_stack_entries = 0; ++ num_es_stack_entries = 0; ++ break; ++ } ++ ++ if ((rdev->family == CHIP_RV610) || ++ (rdev->family == CHIP_RV620) || ++ (rdev->family == CHIP_RS780) || ++ (rdev->family == CHIP_RS780) || ++ (rdev->family == CHIP_RV710)) ++ sq_config = 0; ++ else ++ sq_config = VC_ENABLE; ++ ++ sq_config |= (DX9_CONSTS | ++ ALU_INST_PREFER_VECTOR | ++ PS_PRIO(0) | ++ VS_PRIO(1) | ++ GS_PRIO(2) | ++ ES_PRIO(3)); ++ ++ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | ++ NUM_VS_GPRS(num_vs_gprs) | ++ NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); ++ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | ++ NUM_ES_GPRS(num_es_gprs)); ++ sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | ++ NUM_VS_THREADS(num_vs_threads) | ++ NUM_GS_THREADS(num_gs_threads) | ++ NUM_ES_THREADS(num_es_threads)); ++ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | ++ NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); ++ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | ++ NUM_ES_STACK_ENTRIES(num_es_stack_entries)); ++ ++ /* emit an IB pointing at default state */ ++ dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf; ++ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; ++ radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); ++ radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); ++ radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); ++ radeon_ring_write(rdev, dwords); ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); ++ radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); ++ /* SQ config */ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); ++ radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, sq_config); ++ radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); ++ radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); ++ radeon_ring_write(rdev, sq_thread_resource_mgmt); ++ radeon_ring_write(rdev, sq_stack_resource_mgmt_1); ++ radeon_ring_write(rdev, sq_stack_resource_mgmt_2); ++} ++ ++static inline uint32_t i2f(uint32_t input) ++{ ++ u32 result, i, exponent, fraction; ++ ++ if ((input & 0x3fff) == 0) ++ result = 0; /* 0 is a special case */ ++ else { ++ exponent = 140; /* exponent biased by 127; */ ++ fraction = (input & 0x3fff) << 10; /* cheat and only ++ handle numbers below 2^^15 */ ++ for (i = 0; i < 14; i++) { ++ if (fraction & 0x800000) ++ break; ++ else { ++ fraction = fraction << 1; /* keep ++ shifting left until top bit = 1 */ ++ exponent = exponent - 1; ++ } ++ } ++ result = exponent << 23 | (fraction & 0x7fffff); /* mask ++ off top bit; assumed 1 */ ++ } ++ return result; ++} ++ ++int r600_blit_init(struct radeon_device *rdev) ++{ ++ u32 obj_size; ++ int r, dwords; ++ void *ptr; ++ u32 packet2s[16]; ++ int num_packet2s = 0; ++ ++ rdev->r600_blit.state_offset = 0; ++ ++ if (rdev->family >= CHIP_RV770) ++ rdev->r600_blit.state_len = r7xx_default_size; ++ else ++ rdev->r600_blit.state_len = r6xx_default_size; ++ ++ dwords = rdev->r600_blit.state_len; ++ while (dwords & 0xf) { ++ packet2s[num_packet2s++] = PACKET2(0); ++ dwords++; ++ } ++ ++ obj_size = dwords * 4; ++ obj_size = ALIGN(obj_size, 256); ++ ++ rdev->r600_blit.vs_offset = obj_size; ++ obj_size += r6xx_vs_size * 4; ++ obj_size = ALIGN(obj_size, 256); ++ ++ rdev->r600_blit.ps_offset = obj_size; ++ obj_size += r6xx_ps_size * 4; ++ obj_size = ALIGN(obj_size, 256); ++ ++ r = radeon_object_create(rdev, NULL, obj_size, ++ true, RADEON_GEM_DOMAIN_VRAM, ++ false, &rdev->r600_blit.shader_obj); ++ if (r) { ++ DRM_ERROR("r600 failed to allocate shader\n"); ++ return r; ++ } ++ ++ DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", ++ obj_size, ++ rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); ++ ++ r = radeon_object_kmap(rdev->r600_blit.shader_obj, &ptr); ++ if (r) { ++ DRM_ERROR("failed to map blit object %d\n", r); ++ return r; ++ } ++ ++ if (rdev->family >= CHIP_RV770) ++ memcpy_toio(ptr + rdev->r600_blit.state_offset, ++ r7xx_default_state, rdev->r600_blit.state_len * 4); ++ else ++ memcpy_toio(ptr + rdev->r600_blit.state_offset, ++ r6xx_default_state, rdev->r600_blit.state_len * 4); ++ if (num_packet2s) ++ memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), ++ packet2s, num_packet2s * 4); ++ ++ ++ memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4); ++ memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); ++ ++ radeon_object_kunmap(rdev->r600_blit.shader_obj); ++ return 0; ++} ++ ++void r600_blit_fini(struct radeon_device *rdev) ++{ ++ radeon_object_unpin(rdev->r600_blit.shader_obj); ++ radeon_object_unref(&rdev->r600_blit.shader_obj); ++} ++ ++int r600_vb_ib_get(struct radeon_device *rdev) ++{ ++ int r; ++ r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); ++ if (r) { ++ DRM_ERROR("failed to get IB for vertex buffer\n"); ++ return r; ++ } ++ ++ rdev->r600_blit.vb_total = 64*1024; ++ rdev->r600_blit.vb_used = 0; ++ return 0; ++} ++ ++void r600_vb_ib_put(struct radeon_device *rdev) ++{ ++ radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); ++ mutex_lock(&rdev->ib_pool.mutex); ++ list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs); ++ mutex_unlock(&rdev->ib_pool.mutex); ++ radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); ++} ++ ++int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) ++{ ++ int r; ++ int ring_size, line_size; ++ int max_size; ++ /* loops of emits 64 + fence emit possible */ ++ int dwords_per_loop = 76, num_loops; ++ ++ r = r600_vb_ib_get(rdev); ++ WARN_ON(r); ++ ++ /* set_render_target emits 2 extra dwords on rv6xx */ ++ if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) ++ dwords_per_loop += 2; ++ ++ /* 8 bpp vs 32 bpp for xfer unit */ ++ if (size_bytes & 3) ++ line_size = 8192; ++ else ++ line_size = 8192*4; ++ ++ max_size = 8192 * line_size; ++ ++ /* major loops cover the max size transfer */ ++ num_loops = ((size_bytes + max_size) / max_size); ++ /* minor loops cover the extra non aligned bits */ ++ num_loops += ((size_bytes % line_size) ? 1 : 0); ++ /* calculate number of loops correctly */ ++ ring_size = num_loops * dwords_per_loop; ++ /* set default + shaders */ ++ ring_size += 40; /* shaders + def state */ ++ ring_size += 3; /* fence emit for VB IB */ ++ ring_size += 5; /* done copy */ ++ ring_size += 3; /* fence emit for done copy */ ++ r = radeon_ring_lock(rdev, ring_size); ++ WARN_ON(r); ++ ++ set_default_state(rdev); /* 14 */ ++ set_shaders(rdev); /* 26 */ ++ return 0; ++} ++ ++void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) ++{ ++ int r; ++ ++ radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); ++ radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); ++ /* wait for 3D idle clean */ ++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); ++ radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); ++ radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); ++ ++ if (rdev->r600_blit.vb_ib) ++ r600_vb_ib_put(rdev); ++ ++ if (fence) ++ r = radeon_fence_emit(rdev, fence); ++ ++ radeon_ring_unlock_commit(rdev); ++} ++ ++void r600_kms_blit_copy(struct radeon_device *rdev, ++ u64 src_gpu_addr, u64 dst_gpu_addr, ++ int size_bytes) ++{ ++ int max_bytes; ++ u64 vb_gpu_addr; ++ u32 *vb; ++ ++ DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, ++ size_bytes, rdev->r600_blit.vb_used); ++ vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); ++ if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { ++ max_bytes = 8192; ++ ++ while (size_bytes) { ++ int cur_size = size_bytes; ++ int src_x = src_gpu_addr & 255; ++ int dst_x = dst_gpu_addr & 255; ++ int h = 1; ++ src_gpu_addr = src_gpu_addr & ~255; ++ dst_gpu_addr = dst_gpu_addr & ~255; ++ ++ if (!src_x && !dst_x) { ++ h = (cur_size / max_bytes); ++ if (h > 8192) ++ h = 8192; ++ if (h == 0) ++ h = 1; ++ else ++ cur_size = max_bytes; ++ } else { ++ if (cur_size > max_bytes) ++ cur_size = max_bytes; ++ if (cur_size > (max_bytes - dst_x)) ++ cur_size = (max_bytes - dst_x); ++ if (cur_size > (max_bytes - src_x)) ++ cur_size = (max_bytes - src_x); ++ } ++ ++ if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { ++ WARN_ON(1); ++ ++#if 0 ++ r600_vb_ib_put(rdev); ++ ++ r600_nomm_put_vb(dev); ++ r600_nomm_get_vb(dev); ++ if (!dev_priv->blit_vb) ++ return; ++ set_shaders(dev); ++ vb = r600_nomm_get_vb_ptr(dev); ++#endif ++ } ++ ++ vb[0] = i2f(dst_x); ++ vb[1] = 0; ++ vb[2] = i2f(src_x); ++ vb[3] = 0; ++ ++ vb[4] = i2f(dst_x); ++ vb[5] = i2f(h); ++ vb[6] = i2f(src_x); ++ vb[7] = i2f(h); ++ ++ vb[8] = i2f(dst_x + cur_size); ++ vb[9] = i2f(h); ++ vb[10] = i2f(src_x + cur_size); ++ vb[11] = i2f(h); ++ ++ /* src 9 */ ++ set_tex_resource(rdev, FMT_8, ++ src_x + cur_size, h, src_x + cur_size, ++ src_gpu_addr); ++ ++ /* 5 */ ++ cp_set_surface_sync(rdev, ++ PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); ++ ++ /* dst 23 */ ++ set_render_target(rdev, COLOR_8, ++ dst_x + cur_size, h, ++ dst_gpu_addr); ++ ++ /* scissors 12 */ ++ set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); ++ ++ /* 14 */ ++ vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; ++ set_vtx_resource(rdev, vb_gpu_addr); ++ ++ /* draw 10 */ ++ draw_auto(rdev); ++ ++ /* 5 */ ++ cp_set_surface_sync(rdev, ++ PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, ++ cur_size * h, dst_gpu_addr); ++ ++ vb += 12; ++ rdev->r600_blit.vb_used += 12 * 4; ++ ++ src_gpu_addr += cur_size * h; ++ dst_gpu_addr += cur_size * h; ++ size_bytes -= cur_size * h; ++ } ++ } else { ++ max_bytes = 8192 * 4; ++ ++ while (size_bytes) { ++ int cur_size = size_bytes; ++ int src_x = (src_gpu_addr & 255); ++ int dst_x = (dst_gpu_addr & 255); ++ int h = 1; ++ src_gpu_addr = src_gpu_addr & ~255; ++ dst_gpu_addr = dst_gpu_addr & ~255; ++ ++ if (!src_x && !dst_x) { ++ h = (cur_size / max_bytes); ++ if (h > 8192) ++ h = 8192; ++ if (h == 0) ++ h = 1; ++ else ++ cur_size = max_bytes; ++ } else { ++ if (cur_size > max_bytes) ++ cur_size = max_bytes; ++ if (cur_size > (max_bytes - dst_x)) ++ cur_size = (max_bytes - dst_x); ++ if (cur_size > (max_bytes - src_x)) ++ cur_size = (max_bytes - src_x); ++ } ++ ++ if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { ++ WARN_ON(1); ++ } ++#if 0 ++ if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) { ++ r600_nomm_put_vb(dev); ++ r600_nomm_get_vb(dev); ++ if (!rdev->blit_vb) ++ return; ++ ++ set_shaders(dev); ++ vb = r600_nomm_get_vb_ptr(dev); ++ } ++#endif ++ ++ vb[0] = i2f(dst_x / 4); ++ vb[1] = 0; ++ vb[2] = i2f(src_x / 4); ++ vb[3] = 0; ++ ++ vb[4] = i2f(dst_x / 4); ++ vb[5] = i2f(h); ++ vb[6] = i2f(src_x / 4); ++ vb[7] = i2f(h); ++ ++ vb[8] = i2f((dst_x + cur_size) / 4); ++ vb[9] = i2f(h); ++ vb[10] = i2f((src_x + cur_size) / 4); ++ vb[11] = i2f(h); ++ ++ /* src 9 */ ++ set_tex_resource(rdev, FMT_8_8_8_8, ++ (src_x + cur_size) / 4, ++ h, (src_x + cur_size) / 4, ++ src_gpu_addr); ++ /* 5 */ ++ cp_set_surface_sync(rdev, ++ PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); ++ ++ /* dst 23 */ ++ set_render_target(rdev, COLOR_8_8_8_8, ++ (dst_x + cur_size) / 4, h, ++ dst_gpu_addr); ++ ++ /* scissors 12 */ ++ set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); ++ ++ /* Vertex buffer setup 14 */ ++ vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; ++ set_vtx_resource(rdev, vb_gpu_addr); ++ ++ /* draw 10 */ ++ draw_auto(rdev); ++ ++ /* 5 */ ++ cp_set_surface_sync(rdev, ++ PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, ++ cur_size * h, dst_gpu_addr); ++ ++ /* 78 ring dwords per loop */ ++ vb += 12; ++ rdev->r600_blit.vb_used += 12 * 4; ++ ++ src_gpu_addr += cur_size * h; ++ dst_gpu_addr += cur_size * h; ++ size_bytes -= cur_size * h; ++ } ++ } ++} ++ +diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c +new file mode 100644 +index 0000000..d745e81 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c +@@ -0,0 +1,1072 @@ ++ ++#include <linux/types.h> ++#include <linux/kernel.h> ++ ++const u32 r6xx_default_state[] = ++{ ++ 0xc0002400, ++ 0x00000000, ++ 0xc0012800, ++ 0x80000000, ++ 0x80000000, ++ 0xc0004600, ++ 0x00000016, ++ 0xc0016800, ++ 0x00000010, ++ 0x00028000, ++ 0xc0016800, ++ 0x00000010, ++ 0x00008000, ++ 0xc0016800, ++ 0x00000542, ++ 0x07000003, ++ 0xc0016800, ++ 0x000005c5, ++ 0x00000000, ++ 0xc0016800, ++ 0x00000363, ++ 0x00000000, ++ 0xc0016800, ++ 0x0000060c, ++ 0x82000000, ++ 0xc0016800, ++ 0x0000060e, ++ 0x01020204, ++ 0xc0016f00, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016f00, ++ 0x00000001, ++ 0x00000000, ++ 0xc0096900, ++ 0x0000022a, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000004, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000000a, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000000b, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000010c, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000010d, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000200, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000343, ++ 0x00000060, ++ 0xc0016900, ++ 0x00000344, ++ 0x00000040, ++ 0xc0016900, ++ 0x00000351, ++ 0x0000aa00, ++ 0xc0016900, ++ 0x00000104, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000010e, ++ 0x00000000, ++ 0xc0046900, ++ 0x00000105, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0036900, ++ 0x00000109, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0046900, ++ 0x0000030c, ++ 0x01000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0046900, ++ 0x00000048, ++ 0x3f800000, ++ 0x00000000, ++ 0x3f800000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x0000008e, ++ 0x0000000f, ++ 0xc0016900, ++ 0x00000080, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000083, ++ 0x0000ffff, ++ 0xc0016900, ++ 0x00000084, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000085, ++ 0x20002000, ++ 0xc0016900, ++ 0x00000086, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000087, ++ 0x20002000, ++ 0xc0016900, ++ 0x00000088, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000089, ++ 0x20002000, ++ 0xc0016900, ++ 0x0000008a, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000008b, ++ 0x20002000, ++ 0xc0016900, ++ 0x0000008c, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000094, ++ 0x80000000, ++ 0xc0016900, ++ 0x00000095, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000b4, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x00000096, ++ 0x80000000, ++ 0xc0016900, ++ 0x00000097, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000b6, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x00000098, ++ 0x80000000, ++ 0xc0016900, ++ 0x00000099, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000b8, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x0000009a, ++ 0x80000000, ++ 0xc0016900, ++ 0x0000009b, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000ba, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x0000009c, ++ 0x80000000, ++ 0xc0016900, ++ 0x0000009d, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000bc, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x0000009e, ++ 0x80000000, ++ 0xc0016900, ++ 0x0000009f, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000be, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a0, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a1, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c0, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a2, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a3, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c2, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a4, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a5, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c4, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a6, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a7, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c6, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a8, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a9, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c8, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000aa, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000ab, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000ca, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000ac, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000ad, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000cc, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000ae, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000af, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000ce, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000b0, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000b1, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000d0, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000b2, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000b3, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000d2, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x00000293, ++ 0x00004010, ++ 0xc0016900, ++ 0x00000300, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000301, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000312, ++ 0xffffffff, ++ 0xc0016900, ++ 0x00000307, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000308, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000283, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000292, ++ 0x00000000, ++ 0xc0066900, ++ 0x0000010f, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000206, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000207, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000208, ++ 0x00000000, ++ 0xc0046900, ++ 0x00000303, ++ 0x3f800000, ++ 0x3f800000, ++ 0x3f800000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x00000205, ++ 0x00000004, ++ 0xc0016900, ++ 0x00000280, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000281, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000037e, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000382, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000380, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000383, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000381, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000282, ++ 0x00000008, ++ 0xc0016900, ++ 0x00000302, ++ 0x0000002d, ++ 0xc0016900, ++ 0x0000037f, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b2, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b6, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b7, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b8, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b9, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000225, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000229, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000237, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000100, ++ 0x00000800, ++ 0xc0016900, ++ 0x00000101, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000102, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002a8, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002a9, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000103, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000284, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000290, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000285, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000286, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000287, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000288, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000289, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028a, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028b, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028c, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028d, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028e, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028f, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002a1, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002a5, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002ac, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002ad, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002ae, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002c8, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000206, ++ 0x00000100, ++ 0xc0016900, ++ 0x00000204, ++ 0x00010000, ++ 0xc0036e00, ++ 0x00000000, ++ 0x00000012, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000008f, ++ 0x0000000f, ++ 0xc0016900, ++ 0x000001e8, ++ 0x00000001, ++ 0xc0016900, ++ 0x00000202, ++ 0x00cc0000, ++ 0xc0016900, ++ 0x00000205, ++ 0x00000244, ++ 0xc0016900, ++ 0x00000203, ++ 0x00000210, ++ 0xc0016900, ++ 0x000001b1, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000185, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b3, ++ 0x00000001, ++ 0xc0016900, ++ 0x000001b4, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000191, ++ 0x00000b00, ++ 0xc0016900, ++ 0x000001b5, ++ 0x00000000, ++}; ++ ++const u32 r7xx_default_state[] = ++{ ++ 0xc0012800, ++ 0x80000000, ++ 0x80000000, ++ 0xc0004600, ++ 0x00000016, ++ 0xc0016800, ++ 0x00000010, ++ 0x00028000, ++ 0xc0016800, ++ 0x00000010, ++ 0x00008000, ++ 0xc0016800, ++ 0x00000542, ++ 0x07000002, ++ 0xc0016800, ++ 0x000005c5, ++ 0x00000000, ++ 0xc0016800, ++ 0x00000363, ++ 0x00004000, ++ 0xc0016800, ++ 0x0000060c, ++ 0x00000000, ++ 0xc0016800, ++ 0x0000060e, ++ 0x00420204, ++ 0xc0016f00, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016f00, ++ 0x00000001, ++ 0x00000000, ++ 0xc0096900, ++ 0x0000022a, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000004, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000000a, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000000b, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000010c, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000010d, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000200, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000343, ++ 0x00000060, ++ 0xc0016900, ++ 0x00000344, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000351, ++ 0x0000aa00, ++ 0xc0016900, ++ 0x00000104, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000010e, ++ 0x00000000, ++ 0xc0046900, ++ 0x00000105, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0046900, ++ 0x0000030c, ++ 0x01000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000008e, ++ 0x0000000f, ++ 0xc0016900, ++ 0x00000080, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000083, ++ 0x0000ffff, ++ 0xc0016900, ++ 0x00000084, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000085, ++ 0x20002000, ++ 0xc0016900, ++ 0x00000086, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000087, ++ 0x20002000, ++ 0xc0016900, ++ 0x00000088, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000089, ++ 0x20002000, ++ 0xc0016900, ++ 0x0000008a, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000008b, ++ 0x20002000, ++ 0xc0016900, ++ 0x0000008c, ++ 0xaaaaaaaa, ++ 0xc0016900, ++ 0x00000094, ++ 0x80000000, ++ 0xc0016900, ++ 0x00000095, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000b4, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x00000096, ++ 0x80000000, ++ 0xc0016900, ++ 0x00000097, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000b6, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x00000098, ++ 0x80000000, ++ 0xc0016900, ++ 0x00000099, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000b8, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x0000009a, ++ 0x80000000, ++ 0xc0016900, ++ 0x0000009b, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000ba, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x0000009c, ++ 0x80000000, ++ 0xc0016900, ++ 0x0000009d, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000bc, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x0000009e, ++ 0x80000000, ++ 0xc0016900, ++ 0x0000009f, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000be, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a0, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a1, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c0, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a2, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a3, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c2, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a4, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a5, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c4, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a6, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a7, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c6, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000a8, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000a9, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000c8, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000aa, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000ab, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000ca, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000ac, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000ad, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000cc, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000ae, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000af, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000ce, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000b0, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000b1, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000d0, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x000000b2, ++ 0x80000000, ++ 0xc0016900, ++ 0x000000b3, ++ 0x20002000, ++ 0xc0026900, ++ 0x000000d2, ++ 0x00000000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x00000293, ++ 0x00514000, ++ 0xc0016900, ++ 0x00000300, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000301, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000312, ++ 0xffffffff, ++ 0xc0016900, ++ 0x00000307, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000308, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000283, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000292, ++ 0x00000000, ++ 0xc0066900, ++ 0x0000010f, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000206, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000207, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000208, ++ 0x00000000, ++ 0xc0046900, ++ 0x00000303, ++ 0x3f800000, ++ 0x3f800000, ++ 0x3f800000, ++ 0x3f800000, ++ 0xc0016900, ++ 0x00000205, ++ 0x00000004, ++ 0xc0016900, ++ 0x00000280, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000281, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000037e, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000382, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000380, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000383, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000381, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000282, ++ 0x00000008, ++ 0xc0016900, ++ 0x00000302, ++ 0x0000002d, ++ 0xc0016900, ++ 0x0000037f, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b2, ++ 0x00000001, ++ 0xc0016900, ++ 0x000001b6, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b7, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b8, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b9, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000225, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000229, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000237, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000100, ++ 0x00000800, ++ 0xc0016900, ++ 0x00000101, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000102, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002a8, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002a9, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000103, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000284, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000290, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000285, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000286, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000287, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000288, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000289, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028a, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028b, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028c, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028d, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028e, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000028f, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002a1, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002a5, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002ac, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002ad, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002ae, ++ 0x00000000, ++ 0xc0016900, ++ 0x000002c8, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000206, ++ 0x00000100, ++ 0xc0016900, ++ 0x00000204, ++ 0x00010000, ++ 0xc0036e00, ++ 0x00000000, ++ 0x00000012, ++ 0x00000000, ++ 0x00000000, ++ 0xc0016900, ++ 0x0000008f, ++ 0x0000000f, ++ 0xc0016900, ++ 0x000001e8, ++ 0x00000001, ++ 0xc0016900, ++ 0x00000202, ++ 0x00cc0000, ++ 0xc0016900, ++ 0x00000205, ++ 0x00000244, ++ 0xc0016900, ++ 0x00000203, ++ 0x00000210, ++ 0xc0016900, ++ 0x000001b1, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000185, ++ 0x00000000, ++ 0xc0016900, ++ 0x000001b3, ++ 0x00000001, ++ 0xc0016900, ++ 0x000001b4, ++ 0x00000000, ++ 0xc0016900, ++ 0x00000191, ++ 0x00000b00, ++ 0xc0016900, ++ 0x000001b5, ++ 0x00000000, ++}; ++ ++/* same for r6xx/r7xx */ ++const u32 r6xx_vs[] = ++{ ++ 0x00000004, ++ 0x81000000, ++ 0x0000203c, ++ 0x94000b08, ++ 0x00004000, ++ 0x14200b1a, ++ 0x00000000, ++ 0x00000000, ++ 0x3c000000, ++ 0x68cd1000, ++ 0x00080000, ++ 0x00000000, ++}; ++ ++const u32 r6xx_ps[] = ++{ ++ 0x00000002, ++ 0x80800000, ++ 0x00000000, ++ 0x94200688, ++ 0x00000010, ++ 0x000d1000, ++ 0xb0800000, ++ 0x00000000, ++}; ++ ++const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps); ++const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs); ++const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state); ++const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); +diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h +new file mode 100644 +index 0000000..fdc3b37 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h +@@ -0,0 +1,14 @@ ++ ++#ifndef R600_BLIT_SHADERS_H ++#define R600_BLIT_SHADERS_H ++ ++extern const u32 r6xx_ps[]; ++extern const u32 r6xx_vs[]; ++extern const u32 r7xx_default_state[]; ++extern const u32 r6xx_default_state[]; ++ ++ ++extern const u32 r6xx_ps_size, r6xx_vs_size; ++extern const u32 r6xx_default_size, r7xx_default_size; ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c +index 20f1790..6d5a711 100644 +--- a/drivers/gpu/drm/radeon/r600_cp.c ++++ b/drivers/gpu/drm/radeon/r600_cp.c +@@ -31,7 +31,38 @@ + #include "radeon_drm.h" + #include "radeon_drv.h" + +-#include "r600_microcode.h" ++#define PFP_UCODE_SIZE 576 ++#define PM4_UCODE_SIZE 1792 ++#define R700_PFP_UCODE_SIZE 848 ++#define R700_PM4_UCODE_SIZE 1360 ++ ++/* Firmware Names */ ++MODULE_FIRMWARE("radeon/R600_pfp.bin"); ++MODULE_FIRMWARE("radeon/R600_me.bin"); ++MODULE_FIRMWARE("radeon/RV610_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV610_me.bin"); ++MODULE_FIRMWARE("radeon/RV630_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV630_me.bin"); ++MODULE_FIRMWARE("radeon/RV620_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV620_me.bin"); ++MODULE_FIRMWARE("radeon/RV635_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV635_me.bin"); ++MODULE_FIRMWARE("radeon/RV670_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV670_me.bin"); ++MODULE_FIRMWARE("radeon/RS780_pfp.bin"); ++MODULE_FIRMWARE("radeon/RS780_me.bin"); ++MODULE_FIRMWARE("radeon/RV770_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV770_me.bin"); ++MODULE_FIRMWARE("radeon/RV730_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV730_me.bin"); ++MODULE_FIRMWARE("radeon/RV710_pfp.bin"); ++MODULE_FIRMWARE("radeon/RV710_me.bin"); ++ ++ ++int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, ++ unsigned family, u32 *ib, int *l); ++void r600_cs_legacy_init(void); ++ + + # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ + # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) +@@ -275,11 +306,93 @@ static void r600_vm_init(struct drm_device *dev) + r600_vm_flush_gart_range(dev); + } + +-/* load r600 microcode */ ++static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) ++{ ++ struct platform_device *pdev; ++ const char *chip_name; ++ size_t pfp_req_size, me_req_size; ++ char fw_name[30]; ++ int err; ++ ++ pdev = platform_device_register_simple("r600_cp", 0, NULL, 0); ++ err = IS_ERR(pdev); ++ if (err) { ++ printk(KERN_ERR "r600_cp: Failed to register firmware\n"); ++ return -EINVAL; ++ } ++ ++ switch (dev_priv->flags & RADEON_FAMILY_MASK) { ++ case CHIP_R600: chip_name = "R600"; break; ++ case CHIP_RV610: chip_name = "RV610"; break; ++ case CHIP_RV630: chip_name = "RV630"; break; ++ case CHIP_RV620: chip_name = "RV620"; break; ++ case CHIP_RV635: chip_name = "RV635"; break; ++ case CHIP_RV670: chip_name = "RV670"; break; ++ case CHIP_RS780: ++ case CHIP_RS880: chip_name = "RS780"; break; ++ case CHIP_RV770: chip_name = "RV770"; break; ++ case CHIP_RV730: ++ case CHIP_RV740: chip_name = "RV730"; break; ++ case CHIP_RV710: chip_name = "RV710"; break; ++ default: BUG(); ++ } ++ ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { ++ pfp_req_size = R700_PFP_UCODE_SIZE * 4; ++ me_req_size = R700_PM4_UCODE_SIZE * 4; ++ } else { ++ pfp_req_size = PFP_UCODE_SIZE * 4; ++ me_req_size = PM4_UCODE_SIZE * 12; ++ } ++ ++ DRM_INFO("Loading %s CP Microcode\n", chip_name); ++ ++ snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); ++ err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); ++ if (err) ++ goto out; ++ if (dev_priv->pfp_fw->size != pfp_req_size) { ++ printk(KERN_ERR ++ "r600_cp: Bogus length %zu in firmware \"%s\"\n", ++ dev_priv->pfp_fw->size, fw_name); ++ err = -EINVAL; ++ goto out; ++ } ++ ++ snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); ++ err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); ++ if (err) ++ goto out; ++ if (dev_priv->me_fw->size != me_req_size) { ++ printk(KERN_ERR ++ "r600_cp: Bogus length %zu in firmware \"%s\"\n", ++ dev_priv->me_fw->size, fw_name); ++ err = -EINVAL; ++ } ++out: ++ platform_device_unregister(pdev); ++ ++ if (err) { ++ if (err != -EINVAL) ++ printk(KERN_ERR ++ "r600_cp: Failed to load firmware \"%s\"\n", ++ fw_name); ++ release_firmware(dev_priv->pfp_fw); ++ dev_priv->pfp_fw = NULL; ++ release_firmware(dev_priv->me_fw); ++ dev_priv->me_fw = NULL; ++ } ++ return err; ++} ++ + static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) + { ++ const __be32 *fw_data; + int i; + ++ if (!dev_priv->me_fw || !dev_priv->pfp_fw) ++ return; ++ + r600_do_cp_stop(dev_priv); + + RADEON_WRITE(R600_CP_RB_CNTL, +@@ -292,115 +405,18 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) + DRM_UDELAY(15000); + RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + ++ fw_data = (const __be32 *)dev_priv->me_fw->data; + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); ++ for (i = 0; i < PM4_UCODE_SIZE * 3; i++) ++ RADEON_WRITE(R600_CP_ME_RAM_DATA, ++ be32_to_cpup(fw_data++)); + +- if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) { +- DRM_INFO("Loading R600 CP Microcode\n"); +- for (i = 0; i < PM4_UCODE_SIZE; i++) { +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- R600_cp_microcode[i][0]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- R600_cp_microcode[i][1]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- R600_cp_microcode[i][2]); +- } +- +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading R600 PFP Microcode\n"); +- for (i = 0; i < PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]); +- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) { +- DRM_INFO("Loading RV610 CP Microcode\n"); +- for (i = 0; i < PM4_UCODE_SIZE; i++) { +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV610_cp_microcode[i][0]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV610_cp_microcode[i][1]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV610_cp_microcode[i][2]); +- } +- +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RV610 PFP Microcode\n"); +- for (i = 0; i < PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]); +- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { +- DRM_INFO("Loading RV630 CP Microcode\n"); +- for (i = 0; i < PM4_UCODE_SIZE; i++) { +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV630_cp_microcode[i][0]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV630_cp_microcode[i][1]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV630_cp_microcode[i][2]); +- } +- +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RV630 PFP Microcode\n"); +- for (i = 0; i < PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]); +- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) { +- DRM_INFO("Loading RV620 CP Microcode\n"); +- for (i = 0; i < PM4_UCODE_SIZE; i++) { +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV620_cp_microcode[i][0]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV620_cp_microcode[i][1]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV620_cp_microcode[i][2]); +- } +- +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RV620 PFP Microcode\n"); +- for (i = 0; i < PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]); +- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { +- DRM_INFO("Loading RV635 CP Microcode\n"); +- for (i = 0; i < PM4_UCODE_SIZE; i++) { +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV635_cp_microcode[i][0]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV635_cp_microcode[i][1]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV635_cp_microcode[i][2]); +- } +- +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RV635 PFP Microcode\n"); +- for (i = 0; i < PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]); +- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) { +- DRM_INFO("Loading RV670 CP Microcode\n"); +- for (i = 0; i < PM4_UCODE_SIZE; i++) { +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV670_cp_microcode[i][0]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV670_cp_microcode[i][1]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RV670_cp_microcode[i][2]); +- } +- +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RV670 PFP Microcode\n"); +- for (i = 0; i < PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); +- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || +- ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { +- DRM_INFO("Loading RS780/RS880 CP Microcode\n"); +- for (i = 0; i < PM4_UCODE_SIZE; i++) { +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RS780_cp_microcode[i][0]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RS780_cp_microcode[i][1]); +- RADEON_WRITE(R600_CP_ME_RAM_DATA, +- RS780_cp_microcode[i][2]); +- } ++ fw_data = (const __be32 *)dev_priv->pfp_fw->data; ++ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); ++ for (i = 0; i < PFP_UCODE_SIZE; i++) ++ RADEON_WRITE(R600_CP_PFP_UCODE_DATA, ++ be32_to_cpup(fw_data++)); + +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RS780/RS880 PFP Microcode\n"); +- for (i = 0; i < PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]); +- } + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); +@@ -459,11 +475,14 @@ static void r700_vm_init(struct drm_device *dev) + r600_vm_flush_gart_range(dev); + } + +-/* load r600 microcode */ + static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) + { ++ const __be32 *fw_data; + int i; + ++ if (!dev_priv->me_fw || !dev_priv->pfp_fw) ++ return; ++ + r600_do_cp_stop(dev_priv); + + RADEON_WRITE(R600_CP_RB_CNTL, +@@ -476,48 +495,18 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) + DRM_UDELAY(15000); + RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + ++ fw_data = (const __be32 *)dev_priv->pfp_fw->data; ++ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); ++ for (i = 0; i < R700_PFP_UCODE_SIZE; i++) ++ RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); ++ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); + +- if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RV770/RV790 PFP Microcode\n"); +- for (i = 0; i < R700_PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- +- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); +- DRM_INFO("Loading RV770/RV790 CP Microcode\n"); +- for (i = 0; i < R700_PM4_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]); +- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); +- +- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) || +- ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) { +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RV730/RV740 PFP Microcode\n"); +- for (i = 0; i < R700_PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- +- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); +- DRM_INFO("Loading RV730/RV740 CP Microcode\n"); +- for (i = 0; i < R700_PM4_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); +- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); +- +- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) { +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- DRM_INFO("Loading RV710 PFP Microcode\n"); +- for (i = 0; i < R700_PFP_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]); +- RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); +- +- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); +- DRM_INFO("Loading RV710 CP Microcode\n"); +- for (i = 0; i < R700_PM4_UCODE_SIZE; i++) +- RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]); +- RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); ++ fw_data = (const __be32 *)dev_priv->me_fw->data; ++ RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); ++ for (i = 0; i < R700_PM4_UCODE_SIZE; i++) ++ RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); ++ RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + +- } + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); +@@ -1874,6 +1863,8 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, + + DRM_DEBUG("\n"); + ++ mutex_init(&dev_priv->cs_mutex); ++ r600_cs_legacy_init(); + /* if we require new memory map but we don't have it fail */ + if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { + DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); +@@ -1905,7 +1896,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, + /* Enable vblank on CRTC1 for older X servers + */ + dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; +- ++ dev_priv->do_boxes = 0; + dev_priv->cp_mode = init->cp_mode; + + /* We don't support anything other than bus-mastering ring mode, +@@ -1991,11 +1982,11 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, + } else + #endif + { +- dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; ++ dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; + dev_priv->ring_rptr->handle = +- (void *)dev_priv->ring_rptr->offset; ++ (void *)(unsigned long)dev_priv->ring_rptr->offset; + dev->agp_buffer_map->handle = +- (void *)dev->agp_buffer_map->offset; ++ (void *)(unsigned long)dev->agp_buffer_map->offset; + + DRM_DEBUG("dev_priv->cp_ring->handle %p\n", + dev_priv->cp_ring->handle); +@@ -2147,6 +2138,14 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, + r600_vm_init(dev); + } + ++ if (!dev_priv->me_fw || !dev_priv->pfp_fw) { ++ int err = r600_cp_init_microcode(dev_priv); ++ if (err) { ++ DRM_ERROR("Failed to load firmware!\n"); ++ r600_do_cleanup_cp(dev); ++ return err; ++ } ++ } + if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) + r700_cp_load_microcode(dev_priv); + else +@@ -2291,3 +2290,239 @@ int r600_cp_dispatch_indirect(struct drm_device *dev, + + return 0; + } ++ ++void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ struct drm_master *master = file_priv->master; ++ struct drm_radeon_master_private *master_priv = master->driver_priv; ++ drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; ++ int nbox = sarea_priv->nbox; ++ struct drm_clip_rect *pbox = sarea_priv->boxes; ++ int i, cpp, src_pitch, dst_pitch; ++ uint64_t src, dst; ++ RING_LOCALS; ++ DRM_DEBUG("\n"); ++ ++ if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) ++ cpp = 4; ++ else ++ cpp = 2; ++ ++ if (sarea_priv->pfCurrentPage == 0) { ++ src_pitch = dev_priv->back_pitch; ++ dst_pitch = dev_priv->front_pitch; ++ src = dev_priv->back_offset + dev_priv->fb_location; ++ dst = dev_priv->front_offset + dev_priv->fb_location; ++ } else { ++ src_pitch = dev_priv->front_pitch; ++ dst_pitch = dev_priv->back_pitch; ++ src = dev_priv->front_offset + dev_priv->fb_location; ++ dst = dev_priv->back_offset + dev_priv->fb_location; ++ } ++ ++ if (r600_prepare_blit_copy(dev, file_priv)) { ++ DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); ++ return; ++ } ++ for (i = 0; i < nbox; i++) { ++ int x = pbox[i].x1; ++ int y = pbox[i].y1; ++ int w = pbox[i].x2 - x; ++ int h = pbox[i].y2 - y; ++ ++ DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); ++ ++ r600_blit_swap(dev, ++ src, dst, ++ x, y, x, y, w, h, ++ src_pitch, dst_pitch, cpp); ++ } ++ r600_done_blit_copy(dev); ++ ++ /* Increment the frame counter. The client-side 3D driver must ++ * throttle the framerate by waiting for this value before ++ * performing the swapbuffer ioctl. ++ */ ++ sarea_priv->last_frame++; ++ ++ BEGIN_RING(3); ++ R600_FRAME_AGE(sarea_priv->last_frame); ++ ADVANCE_RING(); ++} ++ ++int r600_cp_dispatch_texture(struct drm_device *dev, ++ struct drm_file *file_priv, ++ drm_radeon_texture_t *tex, ++ drm_radeon_tex_image_t *image) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ struct drm_buf *buf; ++ u32 *buffer; ++ const u8 __user *data; ++ int size, pass_size; ++ u64 src_offset, dst_offset; ++ ++ if (!radeon_check_offset(dev_priv, tex->offset)) { ++ DRM_ERROR("Invalid destination offset\n"); ++ return -EINVAL; ++ } ++ ++ /* this might fail for zero-sized uploads - are those illegal? */ ++ if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { ++ DRM_ERROR("Invalid final destination offset\n"); ++ return -EINVAL; ++ } ++ ++ size = tex->height * tex->pitch; ++ ++ if (size == 0) ++ return 0; ++ ++ dst_offset = tex->offset; ++ ++ if (r600_prepare_blit_copy(dev, file_priv)) { ++ DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); ++ return -EAGAIN; ++ } ++ do { ++ data = (const u8 __user *)image->data; ++ pass_size = size; ++ ++ buf = radeon_freelist_get(dev); ++ if (!buf) { ++ DRM_DEBUG("EAGAIN\n"); ++ if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) ++ return -EFAULT; ++ return -EAGAIN; ++ } ++ ++ if (pass_size > buf->total) ++ pass_size = buf->total; ++ ++ /* Dispatch the indirect buffer. ++ */ ++ buffer = ++ (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); ++ ++ if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { ++ DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); ++ return -EFAULT; ++ } ++ ++ buf->file_priv = file_priv; ++ buf->used = pass_size; ++ src_offset = dev_priv->gart_buffers_offset + buf->offset; ++ ++ r600_blit_copy(dev, src_offset, dst_offset, pass_size); ++ ++ radeon_cp_discard_buffer(dev, file_priv->master, buf); ++ ++ /* Update the input parameters for next time */ ++ image->data = (const u8 __user *)image->data + pass_size; ++ dst_offset += pass_size; ++ size -= pass_size; ++ } while (size > 0); ++ r600_done_blit_copy(dev); ++ ++ return 0; ++} ++ ++/* ++ * Legacy cs ioctl ++ */ ++static u32 radeon_cs_id_get(struct drm_radeon_private *radeon) ++{ ++ /* FIXME: check if wrap affect last reported wrap & sequence */ ++ radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; ++ if (!radeon->cs_id_scnt) { ++ /* increment wrap counter */ ++ radeon->cs_id_wcnt += 0x01000000; ++ /* valid sequence counter start at 1 */ ++ radeon->cs_id_scnt = 1; ++ } ++ return (radeon->cs_id_scnt | radeon->cs_id_wcnt); ++} ++ ++static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) ++{ ++ RING_LOCALS; ++ ++ *id = radeon_cs_id_get(dev_priv); ++ ++ /* SCRATCH 2 */ ++ BEGIN_RING(3); ++ R600_CLEAR_AGE(*id); ++ ADVANCE_RING(); ++ COMMIT_RING(); ++} ++ ++static int r600_ib_get(struct drm_device *dev, ++ struct drm_file *fpriv, ++ struct drm_buf **buffer) ++{ ++ struct drm_buf *buf; ++ ++ *buffer = NULL; ++ buf = radeon_freelist_get(dev); ++ if (!buf) { ++ return -EBUSY; ++ } ++ buf->file_priv = fpriv; ++ *buffer = buf; ++ return 0; ++} ++ ++static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, ++ struct drm_file *fpriv, int l, int r) ++{ ++ drm_radeon_private_t *dev_priv = dev->dev_private; ++ ++ if (buf) { ++ if (!r) ++ r600_cp_dispatch_indirect(dev, buf, 0, l * 4); ++ radeon_cp_discard_buffer(dev, fpriv->master, buf); ++ COMMIT_RING(); ++ } ++} ++ ++int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) ++{ ++ struct drm_radeon_private *dev_priv = dev->dev_private; ++ struct drm_radeon_cs *cs = data; ++ struct drm_buf *buf; ++ unsigned family; ++ int l, r = 0; ++ u32 *ib, cs_id = 0; ++ ++ if (dev_priv == NULL) { ++ DRM_ERROR("called with no initialization\n"); ++ return -EINVAL; ++ } ++ family = dev_priv->flags & RADEON_FAMILY_MASK; ++ if (family < CHIP_R600) { ++ DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); ++ return -EINVAL; ++ } ++ mutex_lock(&dev_priv->cs_mutex); ++ /* get ib */ ++ r = r600_ib_get(dev, fpriv, &buf); ++ if (r) { ++ DRM_ERROR("ib_get failed\n"); ++ goto out; ++ } ++ ib = dev->agp_buffer_map->handle + buf->offset; ++ /* now parse command stream */ ++ r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); ++ if (r) { ++ goto out; ++ } ++ ++out: ++ r600_ib_free(dev, buf, fpriv, l, r); ++ /* emit cs id sequence */ ++ r600_cs_id_emit(dev_priv, &cs_id); ++ cs->cs_id = cs_id; ++ mutex_unlock(&dev_priv->cs_mutex); ++ return r; ++} +diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c +new file mode 100644 +index 0000000..d28970d +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r600_cs.c +@@ -0,0 +1,783 @@ ++/* ++ * Copyright 2008 Advanced Micro Devices, Inc. ++ * Copyright 2008 Red Hat Inc. ++ * Copyright 2009 Jerome Glisse. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#include "drmP.h" ++#include "radeon.h" ++#include "r600d.h" ++ ++static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, ++ struct radeon_cs_reloc **cs_reloc); ++static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, ++ struct radeon_cs_reloc **cs_reloc); ++typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); ++static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; ++ ++/** ++ * r600_cs_packet_parse() - parse cp packet and point ib index to next packet ++ * @parser: parser structure holding parsing context. ++ * @pkt: where to store packet informations ++ * ++ * Assume that chunk_ib_index is properly set. Will return -EINVAL ++ * if packet is bigger than remaining ib size. or if packets is unknown. ++ **/ ++int r600_cs_packet_parse(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt, ++ unsigned idx) ++{ ++ struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; ++ uint32_t header; ++ ++ if (idx >= ib_chunk->length_dw) { ++ DRM_ERROR("Can not parse packet at %d after CS end %d !\n", ++ idx, ib_chunk->length_dw); ++ return -EINVAL; ++ } ++ header = radeon_get_ib_value(p, idx); ++ pkt->idx = idx; ++ pkt->type = CP_PACKET_GET_TYPE(header); ++ pkt->count = CP_PACKET_GET_COUNT(header); ++ pkt->one_reg_wr = 0; ++ switch (pkt->type) { ++ case PACKET_TYPE0: ++ pkt->reg = CP_PACKET0_GET_REG(header); ++ break; ++ case PACKET_TYPE3: ++ pkt->opcode = CP_PACKET3_GET_OPCODE(header); ++ break; ++ case PACKET_TYPE2: ++ pkt->count = -1; ++ break; ++ default: ++ DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); ++ return -EINVAL; ++ } ++ if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { ++ DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", ++ pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++/** ++ * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3 ++ * @parser: parser structure holding parsing context. ++ * @data: pointer to relocation data ++ * @offset_start: starting offset ++ * @offset_mask: offset mask (to align start offset on) ++ * @reloc: reloc informations ++ * ++ * Check next packet is relocation packet3, do bo validation and compute ++ * GPU offset using the provided start. ++ **/ ++static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, ++ struct radeon_cs_reloc **cs_reloc) ++{ ++ struct radeon_cs_chunk *relocs_chunk; ++ struct radeon_cs_packet p3reloc; ++ unsigned idx; ++ int r; ++ ++ if (p->chunk_relocs_idx == -1) { ++ DRM_ERROR("No relocation chunk !\n"); ++ return -EINVAL; ++ } ++ *cs_reloc = NULL; ++ relocs_chunk = &p->chunks[p->chunk_relocs_idx]; ++ r = r600_cs_packet_parse(p, &p3reloc, p->idx); ++ if (r) { ++ return r; ++ } ++ p->idx += p3reloc.count + 2; ++ if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { ++ DRM_ERROR("No packet3 for relocation for packet at %d.\n", ++ p3reloc.idx); ++ return -EINVAL; ++ } ++ idx = radeon_get_ib_value(p, p3reloc.idx + 1); ++ if (idx >= relocs_chunk->length_dw) { ++ DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", ++ idx, relocs_chunk->length_dw); ++ return -EINVAL; ++ } ++ /* FIXME: we assume reloc size is 4 dwords */ ++ *cs_reloc = p->relocs_ptr[(idx / 4)]; ++ return 0; ++} ++ ++/** ++ * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3 ++ * @parser: parser structure holding parsing context. ++ * @data: pointer to relocation data ++ * @offset_start: starting offset ++ * @offset_mask: offset mask (to align start offset on) ++ * @reloc: reloc informations ++ * ++ * Check next packet is relocation packet3, do bo validation and compute ++ * GPU offset using the provided start. ++ **/ ++static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, ++ struct radeon_cs_reloc **cs_reloc) ++{ ++ struct radeon_cs_chunk *relocs_chunk; ++ struct radeon_cs_packet p3reloc; ++ unsigned idx; ++ int r; ++ ++ if (p->chunk_relocs_idx == -1) { ++ DRM_ERROR("No relocation chunk !\n"); ++ return -EINVAL; ++ } ++ *cs_reloc = NULL; ++ relocs_chunk = &p->chunks[p->chunk_relocs_idx]; ++ r = r600_cs_packet_parse(p, &p3reloc, p->idx); ++ if (r) { ++ return r; ++ } ++ p->idx += p3reloc.count + 2; ++ if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { ++ DRM_ERROR("No packet3 for relocation for packet at %d.\n", ++ p3reloc.idx); ++ return -EINVAL; ++ } ++ idx = radeon_get_ib_value(p, p3reloc.idx + 1); ++ if (idx >= relocs_chunk->length_dw) { ++ DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", ++ idx, relocs_chunk->length_dw); ++ return -EINVAL; ++ } ++ *cs_reloc = &p->relocs[0]; ++ (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; ++ (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; ++ return 0; ++} ++ ++/** ++ * r600_cs_packet_next_vline() - parse userspace VLINE packet ++ * @parser: parser structure holding parsing context. ++ * ++ * Userspace sends a special sequence for VLINE waits. ++ * PACKET0 - VLINE_START_END + value ++ * PACKET3 - WAIT_REG_MEM poll vline status reg ++ * RELOC (P3) - crtc_id in reloc. ++ * ++ * This function parses this and relocates the VLINE START END ++ * and WAIT_REG_MEM packets to the correct crtc. ++ * It also detects a switched off crtc and nulls out the ++ * wait in that case. ++ */ ++static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) ++{ ++ struct drm_mode_object *obj; ++ struct drm_crtc *crtc; ++ struct radeon_crtc *radeon_crtc; ++ struct radeon_cs_packet p3reloc, wait_reg_mem; ++ int crtc_id; ++ int r; ++ uint32_t header, h_idx, reg, wait_reg_mem_info; ++ volatile uint32_t *ib; ++ ++ ib = p->ib->ptr; ++ ++ /* parse the WAIT_REG_MEM */ ++ r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx); ++ if (r) ++ return r; ++ ++ /* check its a WAIT_REG_MEM */ ++ if (wait_reg_mem.type != PACKET_TYPE3 || ++ wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { ++ DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); ++ r = -EINVAL; ++ return r; ++ } ++ ++ wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); ++ /* bit 4 is reg (0) or mem (1) */ ++ if (wait_reg_mem_info & 0x10) { ++ DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); ++ r = -EINVAL; ++ return r; ++ } ++ /* waiting for value to be equal */ ++ if ((wait_reg_mem_info & 0x7) != 0x3) { ++ DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); ++ r = -EINVAL; ++ return r; ++ } ++ if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { ++ DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); ++ r = -EINVAL; ++ return r; ++ } ++ ++ if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { ++ DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); ++ r = -EINVAL; ++ return r; ++ } ++ ++ /* jump over the NOP */ ++ r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); ++ if (r) ++ return r; ++ ++ h_idx = p->idx - 2; ++ p->idx += wait_reg_mem.count + 2; ++ p->idx += p3reloc.count + 2; ++ ++ header = radeon_get_ib_value(p, h_idx); ++ crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); ++ reg = header >> 2; ++ mutex_lock(&p->rdev->ddev->mode_config.mutex); ++ obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); ++ if (!obj) { ++ DRM_ERROR("cannot find crtc %d\n", crtc_id); ++ r = -EINVAL; ++ goto out; ++ } ++ crtc = obj_to_crtc(obj); ++ radeon_crtc = to_radeon_crtc(crtc); ++ crtc_id = radeon_crtc->crtc_id; ++ ++ if (!crtc->enabled) { ++ /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ ++ ib[h_idx + 2] = PACKET2(0); ++ ib[h_idx + 3] = PACKET2(0); ++ ib[h_idx + 4] = PACKET2(0); ++ ib[h_idx + 5] = PACKET2(0); ++ ib[h_idx + 6] = PACKET2(0); ++ ib[h_idx + 7] = PACKET2(0); ++ ib[h_idx + 8] = PACKET2(0); ++ } else if (crtc_id == 1) { ++ switch (reg) { ++ case AVIVO_D1MODE_VLINE_START_END: ++ header &= ~R600_CP_PACKET0_REG_MASK; ++ header |= AVIVO_D2MODE_VLINE_START_END >> 2; ++ break; ++ default: ++ DRM_ERROR("unknown crtc reloc\n"); ++ r = -EINVAL; ++ goto out; ++ } ++ ib[h_idx] = header; ++ ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2; ++ } ++out: ++ mutex_unlock(&p->rdev->ddev->mode_config.mutex); ++ return r; ++} ++ ++static int r600_packet0_check(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt, ++ unsigned idx, unsigned reg) ++{ ++ int r; ++ ++ switch (reg) { ++ case AVIVO_D1MODE_VLINE_START_END: ++ r = r600_cs_packet_parse_vline(p); ++ if (r) { ++ DRM_ERROR("No reloc for ib[%d]=0x%04X\n", ++ idx, reg); ++ return r; ++ } ++ break; ++ default: ++ printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", ++ reg, idx); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int r600_cs_parse_packet0(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt) ++{ ++ unsigned reg, i; ++ unsigned idx; ++ int r; ++ ++ idx = pkt->idx + 1; ++ reg = pkt->reg; ++ for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { ++ r = r600_packet0_check(p, pkt, idx, reg); ++ if (r) { ++ return r; ++ } ++ } ++ return 0; ++} ++ ++static int r600_packet3_check(struct radeon_cs_parser *p, ++ struct radeon_cs_packet *pkt) ++{ ++ struct radeon_cs_reloc *reloc; ++ volatile u32 *ib; ++ unsigned idx; ++ unsigned i; ++ unsigned start_reg, end_reg, reg; ++ int r; ++ u32 idx_value; ++ ++ ib = p->ib->ptr; ++ idx = pkt->idx + 1; ++ idx_value = radeon_get_ib_value(p, idx); ++ ++ switch (pkt->opcode) { ++ case PACKET3_START_3D_CMDBUF: ++ if (p->family >= CHIP_RV770 || pkt->count) { ++ DRM_ERROR("bad START_3D\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_CONTEXT_CONTROL: ++ if (pkt->count != 1) { ++ DRM_ERROR("bad CONTEXT_CONTROL\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_INDEX_TYPE: ++ case PACKET3_NUM_INSTANCES: ++ if (pkt->count) { ++ DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_DRAW_INDEX: ++ if (pkt->count != 3) { ++ DRM_ERROR("bad DRAW_INDEX\n"); ++ return -EINVAL; ++ } ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad DRAW_INDEX\n"); ++ return -EINVAL; ++ } ++ ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); ++ ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; ++ break; ++ case PACKET3_DRAW_INDEX_AUTO: ++ if (pkt->count != 1) { ++ DRM_ERROR("bad DRAW_INDEX_AUTO\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_DRAW_INDEX_IMMD_BE: ++ case PACKET3_DRAW_INDEX_IMMD: ++ if (pkt->count < 2) { ++ DRM_ERROR("bad DRAW_INDEX_IMMD\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_WAIT_REG_MEM: ++ if (pkt->count != 5) { ++ DRM_ERROR("bad WAIT_REG_MEM\n"); ++ return -EINVAL; ++ } ++ /* bit 4 is reg (0) or mem (1) */ ++ if (idx_value & 0x10) { ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad WAIT_REG_MEM\n"); ++ return -EINVAL; ++ } ++ ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); ++ ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; ++ } ++ break; ++ case PACKET3_SURFACE_SYNC: ++ if (pkt->count != 3) { ++ DRM_ERROR("bad SURFACE_SYNC\n"); ++ return -EINVAL; ++ } ++ /* 0xffffffff/0x0 is flush all cache flag */ ++ if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || ++ radeon_get_ib_value(p, idx + 2) != 0) { ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad SURFACE_SYNC\n"); ++ return -EINVAL; ++ } ++ ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); ++ } ++ break; ++ case PACKET3_EVENT_WRITE: ++ if (pkt->count != 2 && pkt->count != 0) { ++ DRM_ERROR("bad EVENT_WRITE\n"); ++ return -EINVAL; ++ } ++ if (pkt->count) { ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad EVENT_WRITE\n"); ++ return -EINVAL; ++ } ++ ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); ++ ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; ++ } ++ break; ++ case PACKET3_EVENT_WRITE_EOP: ++ if (pkt->count != 4) { ++ DRM_ERROR("bad EVENT_WRITE_EOP\n"); ++ return -EINVAL; ++ } ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad EVENT_WRITE\n"); ++ return -EINVAL; ++ } ++ ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); ++ ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; ++ break; ++ case PACKET3_SET_CONFIG_REG: ++ start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; ++ end_reg = 4 * pkt->count + start_reg - 4; ++ if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || ++ (start_reg >= PACKET3_SET_CONFIG_REG_END) || ++ (end_reg >= PACKET3_SET_CONFIG_REG_END)) { ++ DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); ++ return -EINVAL; ++ } ++ for (i = 0; i < pkt->count; i++) { ++ reg = start_reg + (4 * i); ++ switch (reg) { ++ case CP_COHER_BASE: ++ /* use PACKET3_SURFACE_SYNC */ ++ return -EINVAL; ++ default: ++ break; ++ } ++ } ++ break; ++ case PACKET3_SET_CONTEXT_REG: ++ start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; ++ end_reg = 4 * pkt->count + start_reg - 4; ++ if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || ++ (start_reg >= PACKET3_SET_CONTEXT_REG_END) || ++ (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { ++ DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); ++ return -EINVAL; ++ } ++ for (i = 0; i < pkt->count; i++) { ++ reg = start_reg + (4 * i); ++ switch (reg) { ++ case DB_DEPTH_BASE: ++ case CB_COLOR0_BASE: ++ case CB_COLOR1_BASE: ++ case CB_COLOR2_BASE: ++ case CB_COLOR3_BASE: ++ case CB_COLOR4_BASE: ++ case CB_COLOR5_BASE: ++ case CB_COLOR6_BASE: ++ case CB_COLOR7_BASE: ++ case SQ_PGM_START_FS: ++ case SQ_PGM_START_ES: ++ case SQ_PGM_START_VS: ++ case SQ_PGM_START_GS: ++ case SQ_PGM_START_PS: ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad SET_CONTEXT_REG " ++ "0x%04X\n", reg); ++ return -EINVAL; ++ } ++ ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); ++ break; ++ case VGT_DMA_BASE: ++ case VGT_DMA_BASE_HI: ++ /* These should be handled by DRAW_INDEX packet 3 */ ++ case VGT_STRMOUT_BASE_OFFSET_0: ++ case VGT_STRMOUT_BASE_OFFSET_1: ++ case VGT_STRMOUT_BASE_OFFSET_2: ++ case VGT_STRMOUT_BASE_OFFSET_3: ++ case VGT_STRMOUT_BASE_OFFSET_HI_0: ++ case VGT_STRMOUT_BASE_OFFSET_HI_1: ++ case VGT_STRMOUT_BASE_OFFSET_HI_2: ++ case VGT_STRMOUT_BASE_OFFSET_HI_3: ++ case VGT_STRMOUT_BUFFER_BASE_0: ++ case VGT_STRMOUT_BUFFER_BASE_1: ++ case VGT_STRMOUT_BUFFER_BASE_2: ++ case VGT_STRMOUT_BUFFER_BASE_3: ++ case VGT_STRMOUT_BUFFER_OFFSET_0: ++ case VGT_STRMOUT_BUFFER_OFFSET_1: ++ case VGT_STRMOUT_BUFFER_OFFSET_2: ++ case VGT_STRMOUT_BUFFER_OFFSET_3: ++ /* These should be handled by STRMOUT_BUFFER packet 3 */ ++ DRM_ERROR("bad context reg: 0x%08x\n", reg); ++ return -EINVAL; ++ default: ++ break; ++ } ++ } ++ break; ++ case PACKET3_SET_RESOURCE: ++ if (pkt->count % 7) { ++ DRM_ERROR("bad SET_RESOURCE\n"); ++ return -EINVAL; ++ } ++ start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; ++ end_reg = 4 * pkt->count + start_reg - 4; ++ if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || ++ (start_reg >= PACKET3_SET_RESOURCE_END) || ++ (end_reg >= PACKET3_SET_RESOURCE_END)) { ++ DRM_ERROR("bad SET_RESOURCE\n"); ++ return -EINVAL; ++ } ++ for (i = 0; i < (pkt->count / 7); i++) { ++ switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { ++ case SQ_TEX_VTX_VALID_TEXTURE: ++ /* tex base */ ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad SET_RESOURCE\n"); ++ return -EINVAL; ++ } ++ ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); ++ /* tex mip base */ ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad SET_RESOURCE\n"); ++ return -EINVAL; ++ } ++ ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); ++ break; ++ case SQ_TEX_VTX_VALID_BUFFER: ++ /* vtx base */ ++ r = r600_cs_packet_next_reloc(p, &reloc); ++ if (r) { ++ DRM_ERROR("bad SET_RESOURCE\n"); ++ return -EINVAL; ++ } ++ ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); ++ ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; ++ break; ++ case SQ_TEX_VTX_INVALID_TEXTURE: ++ case SQ_TEX_VTX_INVALID_BUFFER: ++ default: ++ DRM_ERROR("bad SET_RESOURCE\n"); ++ return -EINVAL; ++ } ++ } ++ break; ++ case PACKET3_SET_ALU_CONST: ++ start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; ++ end_reg = 4 * pkt->count + start_reg - 4; ++ if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || ++ (start_reg >= PACKET3_SET_ALU_CONST_END) || ++ (end_reg >= PACKET3_SET_ALU_CONST_END)) { ++ DRM_ERROR("bad SET_ALU_CONST\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_SET_BOOL_CONST: ++ start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; ++ end_reg = 4 * pkt->count + start_reg - 4; ++ if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || ++ (start_reg >= PACKET3_SET_BOOL_CONST_END) || ++ (end_reg >= PACKET3_SET_BOOL_CONST_END)) { ++ DRM_ERROR("bad SET_BOOL_CONST\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_SET_LOOP_CONST: ++ start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET; ++ end_reg = 4 * pkt->count + start_reg - 4; ++ if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || ++ (start_reg >= PACKET3_SET_LOOP_CONST_END) || ++ (end_reg >= PACKET3_SET_LOOP_CONST_END)) { ++ DRM_ERROR("bad SET_LOOP_CONST\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_SET_CTL_CONST: ++ start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET; ++ end_reg = 4 * pkt->count + start_reg - 4; ++ if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || ++ (start_reg >= PACKET3_SET_CTL_CONST_END) || ++ (end_reg >= PACKET3_SET_CTL_CONST_END)) { ++ DRM_ERROR("bad SET_CTL_CONST\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_SET_SAMPLER: ++ if (pkt->count % 3) { ++ DRM_ERROR("bad SET_SAMPLER\n"); ++ return -EINVAL; ++ } ++ start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; ++ end_reg = 4 * pkt->count + start_reg - 4; ++ if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || ++ (start_reg >= PACKET3_SET_SAMPLER_END) || ++ (end_reg >= PACKET3_SET_SAMPLER_END)) { ++ DRM_ERROR("bad SET_SAMPLER\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_SURFACE_BASE_UPDATE: ++ if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { ++ DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); ++ return -EINVAL; ++ } ++ if (pkt->count) { ++ DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); ++ return -EINVAL; ++ } ++ break; ++ case PACKET3_NOP: ++ break; ++ default: ++ DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++int r600_cs_parse(struct radeon_cs_parser *p) ++{ ++ struct radeon_cs_packet pkt; ++ int r; ++ ++ do { ++ r = r600_cs_packet_parse(p, &pkt, p->idx); ++ if (r) { ++ return r; ++ } ++ p->idx += pkt.count + 2; ++ switch (pkt.type) { ++ case PACKET_TYPE0: ++ r = r600_cs_parse_packet0(p, &pkt); ++ break; ++ case PACKET_TYPE2: ++ break; ++ case PACKET_TYPE3: ++ r = r600_packet3_check(p, &pkt); ++ break; ++ default: ++ DRM_ERROR("Unknown packet type %d !\n", pkt.type); ++ return -EINVAL; ++ } ++ if (r) { ++ return r; ++ } ++ } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); ++#if 0 ++ for (r = 0; r < p->ib->length_dw; r++) { ++ printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]); ++ mdelay(1); ++ } ++#endif ++ return 0; ++} ++ ++static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p) ++{ ++ if (p->chunk_relocs_idx == -1) { ++ return 0; ++ } ++ p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL); ++ if (p->relocs == NULL) { ++ return -ENOMEM; ++ } ++ return 0; ++} ++ ++/** ++ * cs_parser_fini() - clean parser states ++ * @parser: parser structure holding parsing context. ++ * @error: error number ++ * ++ * If error is set than unvalidate buffer, otherwise just free memory ++ * used by parsing context. ++ **/ ++static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error) ++{ ++ unsigned i; ++ ++ kfree(parser->relocs); ++ for (i = 0; i < parser->nchunks; i++) { ++ kfree(parser->chunks[i].kdata); ++ kfree(parser->chunks[i].kpage[0]); ++ kfree(parser->chunks[i].kpage[1]); ++ } ++ kfree(parser->chunks); ++ kfree(parser->chunks_array); ++} ++ ++int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, ++ unsigned family, u32 *ib, int *l) ++{ ++ struct radeon_cs_parser parser; ++ struct radeon_cs_chunk *ib_chunk; ++ struct radeon_ib fake_ib; ++ int r; ++ ++ /* initialize parser */ ++ memset(&parser, 0, sizeof(struct radeon_cs_parser)); ++ parser.filp = filp; ++ parser.rdev = NULL; ++ parser.family = family; ++ parser.ib = &fake_ib; ++ fake_ib.ptr = ib; ++ r = radeon_cs_parser_init(&parser, data); ++ if (r) { ++ DRM_ERROR("Failed to initialize parser !\n"); ++ r600_cs_parser_fini(&parser, r); ++ return r; ++ } ++ r = r600_cs_parser_relocs_legacy(&parser); ++ if (r) { ++ DRM_ERROR("Failed to parse relocation !\n"); ++ r600_cs_parser_fini(&parser, r); ++ return r; ++ } ++ /* Copy the packet into the IB, the parser will read from the ++ * input memory (cached) and write to the IB (which can be ++ * uncached). */ ++ ib_chunk = &parser.chunks[parser.chunk_ib_idx]; ++ parser.ib->length_dw = ib_chunk->length_dw; ++ *l = parser.ib->length_dw; ++ r = r600_cs_parse(&parser); ++ if (r) { ++ DRM_ERROR("Invalid command stream !\n"); ++ r600_cs_parser_fini(&parser, r); ++ return r; ++ } ++ r = radeon_cs_finish_pages(&parser); ++ if (r) { ++ DRM_ERROR("Invalid command stream !\n"); ++ r600_cs_parser_fini(&parser, r); ++ return r; ++ } ++ r600_cs_parser_fini(&parser, r); ++ return r; ++} ++ ++void r600_cs_legacy_init(void) ++{ ++ r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm; ++} +diff --git a/drivers/gpu/drm/radeon/r600_microcode.h b/drivers/gpu/drm/radeon/r600_microcode.h +deleted file mode 100644 +index 778c8b4..0000000 +--- a/drivers/gpu/drm/radeon/r600_microcode.h ++++ /dev/null +@@ -1,23297 +0,0 @@ +-/* +- * Copyright 2008-2009 Advanced Micro Devices, Inc. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef R600_MICROCODE_H +-#define R600_MICROCODE_H +- +-static const int ME_JUMP_TABLE_START = 1764; +-static const int ME_JUMP_TABLE_END = 1792; +- +-#define PFP_UCODE_SIZE 576 +-#define PM4_UCODE_SIZE 1792 +-#define R700_PFP_UCODE_SIZE 848 +-#define R700_PM4_UCODE_SIZE 1360 +- +-static const u32 R600_cp_microcode[][3] = { +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x0000ffff, 0x00284621, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00000000, 0x00e00000, 0x000 }, +- { 0x00010000, 0xc0294620, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x614 }, +- { 0x00000000, 0x00600000, 0x5b2 }, +- { 0x00000000, 0x00600000, 0x5c5 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000f00, 0x00281622, 0x000 }, +- { 0x00000008, 0x00211625, 0x000 }, +- { 0x00000020, 0x00203625, 0x000 }, +- { 0x8d000000, 0x00204411, 0x000 }, +- { 0x00000004, 0x002f0225, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x018 }, +- { 0x00412000, 0x00404811, 0x019 }, +- { 0x00422000, 0x00204811, 0x000 }, +- { 0x8e000000, 0x00204411, 0x000 }, +- { 0x00000031, 0x00204a2d, 0x000 }, +- { 0x90000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x0000000c, 0x00211622, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000019, 0x00211a22, 0x000 }, +- { 0x00000004, 0x00281a26, 0x000 }, +- { 0x00000000, 0x002914c5, 0x000 }, +- { 0x00000021, 0x00203625, 0x000 }, +- { 0x00000000, 0x003a1402, 0x000 }, +- { 0x00000016, 0x00211625, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x0000001d, 0x00200e2d, 0x000 }, +- { 0xfffffffc, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002914a3, 0x000 }, +- { 0x0000001d, 0x00203625, 0x000 }, +- { 0x00008000, 0x00280e22, 0x000 }, +- { 0x00000007, 0x00220e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x20000000, 0x00280e22, 0x000 }, +- { 0x00000006, 0x00210e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x00000000, 0x00220222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x038 }, +- { 0x00000000, 0x2ee00000, 0x035 }, +- { 0x00000000, 0x2ce00000, 0x037 }, +- { 0x00000000, 0x00400e2d, 0x039 }, +- { 0x00000008, 0x00200e2d, 0x000 }, +- { 0x00000009, 0x0040122d, 0x046 }, +- { 0x00000001, 0x00400e2d, 0x039 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x03e }, +- { 0x00000008, 0x00401c11, 0x041 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x0000000f, 0x00281e27, 0x000 }, +- { 0x00000003, 0x00221e27, 0x000 }, +- { 0x7fc00000, 0x00281a23, 0x000 }, +- { 0x00000014, 0x00211a26, 0x000 }, +- { 0x00000001, 0x00331a26, 0x000 }, +- { 0x00000008, 0x00221a26, 0x000 }, +- { 0x00000000, 0x00290cc7, 0x000 }, +- { 0x00000030, 0x00203624, 0x000 }, +- { 0x00007f00, 0x00281221, 0x000 }, +- { 0x00001400, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04b }, +- { 0x00000001, 0x00290e23, 0x000 }, +- { 0x00000010, 0x00203623, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfff80000, 0x00294a23, 0x000 }, +- { 0x00000000, 0x003a2c02, 0x000 }, +- { 0x00000002, 0x00220e2b, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x00000011, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00294a23, 0x000 }, +- { 0x00000030, 0x00204a2d, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000032, 0x00200e2d, 0x000 }, +- { 0x060a0200, 0x00294a23, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x061 }, +- { 0x00000000, 0x2ee00000, 0x05f }, +- { 0x00000000, 0x2ce00000, 0x05e }, +- { 0x00000000, 0x00400e2d, 0x062 }, +- { 0x00000001, 0x00400e2d, 0x062 }, +- { 0x0000000a, 0x00200e2d, 0x000 }, +- { 0x0000000b, 0x0040122d, 0x06a }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x7fc00000, 0x00281623, 0x000 }, +- { 0x00000014, 0x00211625, 0x000 }, +- { 0x00000001, 0x00331625, 0x000 }, +- { 0x80000000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00290ca3, 0x000 }, +- { 0x3ffffc00, 0x00290e23, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x06d }, +- { 0x00000100, 0x00401c11, 0x070 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x000000f0, 0x00281e27, 0x000 }, +- { 0x00000004, 0x00221e27, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0xfffff0ff, 0x00281a30, 0x000 }, +- { 0x0000a028, 0x00204411, 0x000 }, +- { 0x00000000, 0x002948e6, 0x000 }, +- { 0x0000a018, 0x00204411, 0x000 }, +- { 0x3fffffff, 0x00284a23, 0x000 }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x0000002d, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a3, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x080 }, +- { 0x0000002e, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a4, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x081 }, +- { 0x00000000, 0x00400000, 0x087 }, +- { 0x0000002d, 0x00203623, 0x000 }, +- { 0x0000002e, 0x00203624, 0x000 }, +- { 0x0000001d, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x087 }, +- { 0x00000000, 0x00600000, 0x5ed }, +- { 0x00000000, 0x00600000, 0x5e1 }, +- { 0x00000002, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x08a }, +- { 0x00000018, 0xc0403620, 0x090 }, +- { 0x00000000, 0x2ee00000, 0x08e }, +- { 0x00000000, 0x2ce00000, 0x08d }, +- { 0x00000002, 0x00400e2d, 0x08f }, +- { 0x00000003, 0x00400e2d, 0x08f }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000018, 0x00203623, 0x000 }, +- { 0x00000003, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x095 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x09d }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x2ee00000, 0x09b }, +- { 0x00000000, 0x2ce00000, 0x09a }, +- { 0x00000002, 0x00400e2d, 0x09c }, +- { 0x00000003, 0x00400e2d, 0x09c }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x003f0000, 0x00280e23, 0x000 }, +- { 0x00000010, 0x00210e23, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x0000001e, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0a4 }, +- { 0x0000001c, 0xc0203620, 0x000 }, +- { 0x0000001f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0a7 }, +- { 0x0000001b, 0xc0203620, 0x000 }, +- { 0x00000008, 0x00210e2b, 0x000 }, +- { 0x0000007f, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0db }, +- { 0x00000000, 0x27000000, 0x000 }, +- { 0x00000000, 0x00600000, 0x28c }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000000c, 0x00221e30, 0x000 }, +- { 0x99800000, 0x00204411, 0x000 }, +- { 0x00000004, 0x0020122d, 0x000 }, +- { 0x00000008, 0x00221224, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00291ce4, 0x000 }, +- { 0x00000000, 0x00604807, 0x128 }, +- { 0x9b000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x9c000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x0033146f, 0x000 }, +- { 0x00000001, 0x00333e23, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0x00203c05, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e007, 0x00204411, 0x000 }, +- { 0x0000000f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0c5 }, +- { 0x00f8ff08, 0x00204811, 0x000 }, +- { 0x98000000, 0x00404811, 0x0d6 }, +- { 0x000000f0, 0x00280e22, 0x000 }, +- { 0x000000a0, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x0d4 }, +- { 0x00000013, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0cf }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0ce }, +- { 0x00003f00, 0x00400c11, 0x0d0 }, +- { 0x00001f00, 0x00400c11, 0x0d0 }, +- { 0x00000f00, 0x00200c11, 0x000 }, +- { 0x00380009, 0x00294a23, 0x000 }, +- { 0x3f000000, 0x00280e2b, 0x000 }, +- { 0x00000002, 0x00220e23, 0x000 }, +- { 0x00000007, 0x00494a23, 0x0d6 }, +- { 0x00380f09, 0x00204811, 0x000 }, +- { 0x68000007, 0x00204811, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000a202, 0x00204411, 0x000 }, +- { 0x00ff0000, 0x00284a22, 0x000 }, +- { 0x00000030, 0x00200e2d, 0x000 }, +- { 0x0000002e, 0x0020122d, 0x000 }, +- { 0x00000000, 0x002f0083, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0e3 }, +- { 0x00000000, 0x00600000, 0x5e7 }, +- { 0x00000000, 0x00400000, 0x0e4 }, +- { 0x00000000, 0x00600000, 0x5ea }, +- { 0x00000007, 0x0020222d, 0x000 }, +- { 0x00000005, 0x00220e22, 0x000 }, +- { 0x00100000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x000000ef, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x0000001d, 0x00200e2d, 0x000 }, +- { 0x00000003, 0x00210223, 0x000 }, +- { 0x00000000, 0x14e00000, 0x0f1 }, +- { 0x0000000b, 0x00210228, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0f1 }, +- { 0x00000400, 0x00292228, 0x000 }, +- { 0x0000001a, 0x00203628, 0x000 }, +- { 0x0000001c, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0f6 }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000001e, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x104 }, +- { 0x0000a30f, 0x00204411, 0x000 }, +- { 0x00000013, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x0fd }, +- { 0xffffffff, 0x00404811, 0x104 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x100 }, +- { 0x0000ffff, 0x00404811, 0x104 }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x103 }, +- { 0x000000ff, 0x00404811, 0x104 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0002c400, 0x00204411, 0x000 }, +- { 0x0000001f, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x10b }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x00000019, 0x00203623, 0x000 }, +- { 0x00000018, 0x40224a20, 0x000 }, +- { 0x00000010, 0xc0424a20, 0x10d }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x00000019, 0x00203623, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000000a, 0x00201011, 0x000 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x114 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00531224, 0x110 }, +- { 0xffbfffff, 0x00283a2e, 0x000 }, +- { 0x0000001b, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x127 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0x00000018, 0x00220e30, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e00e, 0x00204411, 0x000 }, +- { 0x07f8ff08, 0x00204811, 0x000 }, +- { 0x00000000, 0x00294a23, 0x000 }, +- { 0x00000024, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x00800000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204806, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x614 }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x613 }, +- { 0x00000004, 0x00404c11, 0x12e }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x2fe }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x19f }, +- { 0x00000000, 0x00600000, 0x151 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40280620, 0x000 }, +- { 0x00000010, 0xc0210a20, 0x000 }, +- { 0x00000000, 0x00341461, 0x000 }, +- { 0x00000000, 0x00741882, 0x2a4 }, +- { 0x0001a1fd, 0x00604411, 0x2c9 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x138 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x2fe }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x19f }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x151 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0681a20, 0x2a4 }, +- { 0x0001a1fd, 0x00604411, 0x2c9 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x149 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000001, 0x00300a2f, 0x000 }, +- { 0x00000001, 0x00210a22, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600000, 0x17c }, +- { 0x00000000, 0x00600000, 0x18d }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00202c08, 0x000 }, +- { 0x00000000, 0x00202411, 0x000 }, +- { 0x00000000, 0x00202811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00221e29, 0x000 }, +- { 0x00000000, 0x007048eb, 0x189 }, +- { 0x00000000, 0x00600000, 0x2a4 }, +- { 0x00000001, 0x40330620, 0x000 }, +- { 0x00000000, 0xc0302409, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x28c }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x173 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000001, 0x00530621, 0x16f }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0604800, 0x184 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000013, 0x0020062d, 0x000 }, +- { 0x00000000, 0x0078042a, 0x2e4 }, +- { 0x00000000, 0x00202809, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x165 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000210, 0x00600411, 0x2fe }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x181 }, +- { 0x0000001b, 0xc0203620, 0x000 }, +- { 0x0000001c, 0xc0203620, 0x000 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x46000000, 0x00600811, 0x19f }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x188 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00804811, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40281620, 0x000 }, +- { 0x00000010, 0xc0811a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000008, 0x00221e30, 0x000 }, +- { 0x00000032, 0x00201a2d, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfffbff09, 0x00204811, 0x000 }, +- { 0x00000011, 0x0020222d, 0x000 }, +- { 0x00001fff, 0x00294a28, 0x000 }, +- { 0x00000006, 0x0020222d, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000100, 0x00201811, 0x000 }, +- { 0x00000008, 0x00621e28, 0x128 }, +- { 0x00000008, 0x00822228, 0x000 }, +- { 0x0002c000, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00600e2d, 0x1aa }, +- { 0x0000001c, 0x00600e2d, 0x1aa }, +- { 0x0000c008, 0x00204411, 0x000 }, +- { 0x0000001d, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1a6 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x39000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00804802, 0x000 }, +- { 0x00000020, 0x00202e2d, 0x000 }, +- { 0x00000000, 0x003b0d63, 0x000 }, +- { 0x00000008, 0x00224a23, 0x000 }, +- { 0x00000010, 0x00224a23, 0x000 }, +- { 0x00000018, 0x00224a23, 0x000 }, +- { 0x00000000, 0x00804803, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x2fe }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x19f }, +- { 0x00000007, 0x0021062f, 0x000 }, +- { 0x00000019, 0x00200a2d, 0x000 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000ffff, 0x40282220, 0x000 }, +- { 0x0000000f, 0x00262228, 0x000 }, +- { 0x00000010, 0x40212620, 0x000 }, +- { 0x0000000f, 0x00262629, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1cd }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000081, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000080, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1c9 }, +- { 0x00000000, 0x00600000, 0x1d6 }, +- { 0x00000001, 0x00531e27, 0x1c5 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000001f, 0x00280a22, 0x000 }, +- { 0x0000001f, 0x00282a2a, 0x000 }, +- { 0x00000001, 0x00530621, 0x1be }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000002, 0x00304a2f, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000001, 0x00301e2f, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x1d6 }, +- { 0x00000001, 0x00531e27, 0x1d2 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x0000000f, 0x00260e23, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000000f, 0x00261224, 0x000 }, +- { 0x00000000, 0x00201411, 0x000 }, +- { 0x00000000, 0x00601811, 0x2a4 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022b, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1e5 }, +- { 0x00000010, 0x00221628, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a29, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x0020480a, 0x000 }, +- { 0x00000000, 0x00202c11, 0x000 }, +- { 0x00000010, 0x00221623, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a24, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x00731503, 0x1f2 }, +- { 0x00000000, 0x00201805, 0x000 }, +- { 0x00000000, 0x00731524, 0x1f2 }, +- { 0x00000000, 0x002d14c5, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00000000, 0x00202003, 0x000 }, +- { 0x00000000, 0x00802404, 0x000 }, +- { 0x0000000f, 0x00210225, 0x000 }, +- { 0x00000000, 0x14c00000, 0x613 }, +- { 0x00000000, 0x002b1405, 0x000 }, +- { 0x00000001, 0x00901625, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x2fe }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x19f }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00294a22, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a21, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000ffff, 0x40281220, 0x000 }, +- { 0x00000010, 0xc0211a20, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211620, 0x000 }, +- { 0x00000000, 0x00741465, 0x2a4 }, +- { 0x0001a1fd, 0x00604411, 0x2c9 }, +- { 0x00000001, 0x00330621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x206 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x1ff }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x5c5 }, +- { 0x00000000, 0x0040040f, 0x200 }, +- { 0x00000000, 0x00600000, 0x5b2 }, +- { 0x00000000, 0x00600000, 0x5c5 }, +- { 0x00000210, 0x00600411, 0x2fe }, +- { 0x00000000, 0x00600000, 0x18d }, +- { 0x00000000, 0x00600000, 0x189 }, +- { 0x00000000, 0x00600000, 0x2a4 }, +- { 0x00000000, 0x00600000, 0x28c }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x21f }, +- { 0x00000000, 0xc0404800, 0x21c }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x00600411, 0x2e4 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x5b2 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000018, 0x40210a20, 0x000 }, +- { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x235 }, +- { 0x0000001a, 0x0020222d, 0x000 }, +- { 0x00080101, 0x00292228, 0x000 }, +- { 0x0000001a, 0x00203628, 0x000 }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x23a }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000010, 0x00600411, 0x2fe }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x19f }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00000000, 0x00600000, 0x265 }, +- { 0x0000001d, 0x00201e2d, 0x000 }, +- { 0x00000001, 0x00211e27, 0x000 }, +- { 0x00000000, 0x14e00000, 0x253 }, +- { 0x00000018, 0x00201e2d, 0x000 }, +- { 0x0000ffff, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00341c27, 0x000 }, +- { 0x00000000, 0x12c00000, 0x248 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e5, 0x000 }, +- { 0x00000000, 0x08c00000, 0x24b }, +- { 0x00000000, 0x00201407, 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{ 0x00000001, 0x00204811, 0x000 }, +- { 0x00002258, 0x00300a24, 0x000 }, +- { 0x00040000, 0x00694622, 0x614 }, +- { 0x00000000, 0xc0201c10, 0x000 }, +- { 0x00000000, 0xc0400000, 0x55b }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x54d }, +- { 0x00000000, 0xc0201c00, 0x000 }, +- { 0x00000000, 0xc0400000, 0x55b }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x559 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000216d, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x554 }, +- { 0x9e000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x557 }, +- { 0x00000000, 0x00401c10, 0x55b }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00000000, 0xc0400000, 0x000 }, +- { 0x00000000, 0x0ee00000, 0x55d }, +- { 0x00000000, 0x00600000, 0x5a4 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x56d }, +- { 0x0000a2b7, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2b6, 0x00604411, 0x614 }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x0000a2c4, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x56b }, +- { 0x0000a2d1, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d1, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x00000001, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x57d }, +- { 0x0000a2bb, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2ba, 0x00604411, 0x614 }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x0000a2c5, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x57b }, +- { 0x0000a2d2, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d2, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x00000002, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x58d }, +- { 0x0000a2bf, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2be, 0x00604411, 0x614 }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x0000a2c6, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x58b }, +- { 0x0000a2d3, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d3, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x0000a2c3, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2c2, 0x00604411, 0x614 }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x0000a2c7, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x599 }, +- { 0x0000a2d4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d4, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x85000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x0000304a, 0x00204411, 0x000 }, +- { 0x01000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00400000, 0x59f }, +- { 0xa4000000, 0xc0204411, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0xc0600000, 0x5a4 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000005, 0x00204811, 0x000 }, +- { 0x0000a1f4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x88000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0xff000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000002, 0x00804811, 0x000 }, +- { 0x00000000, 0x0ee00000, 0x5b7 }, +- { 0x00001000, 0x00200811, 0x000 }, +- { 0x00000034, 0x00203622, 0x000 }, +- { 0x00000000, 0x00600000, 0x5bb }, +- { 0x00000000, 0x00600000, 0x5a4 }, +- { 0x98000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00804811, 0x000 }, +- { 0x00000000, 0xc0600000, 0x5bb }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000022, 0x00204811, 0x000 }, +- { 0x89000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0xff000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000002, 0x00804811, 0x000 }, +- { 0x0000217a, 0xc0204411, 0x000 }, +- { 0x00000000, 0x00404811, 0x000 }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0xff000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000002, 0x00804811, 0x000 }, +- { 0x00000000, 0x00600000, 0x5e1 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0xc0204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000016, 0x00604811, 0x35e }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x09800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x614 }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x00000004, 0x00404c11, 0x5dc }, +- { 0x0000001d, 0x00201e2d, 0x000 }, +- { 0x00000004, 0x00291e27, 0x000 }, +- { 0x0000001d, 0x00803627, 0x000 }, +- { 0x0000001d, 0x00201e2d, 0x000 }, +- { 0xfffffffb, 0x00281e27, 0x000 }, +- { 0x0000001d, 0x00803627, 0x000 }, +- { 0x0000001d, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00291e27, 0x000 }, +- { 0x0000001d, 0x00803627, 0x000 }, +- { 0x0000001d, 0x00201e2d, 0x000 }, +- { 0xfffffff7, 0x00281e27, 0x000 }, +- { 0x0000001d, 0x00803627, 0x000 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000016, 0x00604811, 0x35e }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x01800000, 0x00204811, 0x000 }, +- { 0x00ffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004217f, 0x00604411, 0x614 }, +- { 0x00000000, 0x00200010, 0x000 }, +- { 0x00000000, 0x14c00000, 0x613 }, +- { 0x00000010, 0x00404c11, 0x5f9 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x38c00000, 0x000 }, +- { 0x00000025, 0x00200a2d, 0x000 }, +- { 0x00000026, 0x00200e2d, 0x000 }, +- { 0x00000027, 0x0020122d, 0x000 }, +- { 0x00000028, 0x0020162d, 0x000 }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000004, 0x00301224, 0x000 }, +- { 0x00000000, 0x002f0064, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x612 }, +- { 0x00000003, 0x00281a22, 0x000 }, +- { 0x00000008, 0x00221222, 0x000 }, +- { 0xfffff000, 0x00281224, 0x000 }, +- { 0x00000000, 0x002910c4, 0x000 }, +- { 0x00000027, 0x00403624, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x614 }, +- { 0x9f000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x617 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x2fe }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x19f }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0xc0204411, 0x000 }, +- { 0x00000029, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x0000002c, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000002a, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000002b, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00404811, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x013304ef, 0x059b0239, 0x000 }, +- { 0x01b00159, 0x0425059b, 0x000 }, +- { 0x021201f6, 0x02390142, 0x000 }, +- { 0x0210022e, 0x0289022a, 0x000 }, +- { 0x03c2059b, 0x059b059b, 0x000 }, +- { 0x05cd05ce, 0x0308059b, 0x000 }, +- { 0x059b05a0, 0x03090329, 0x000 }, +- { 0x0313026b, 0x032b031d, 0x000 }, +- { 0x059b059b, 0x059b059b, 0x000 }, +- { 0x059b052c, 0x059b059b, 0x000 }, +- { 0x03a5059b, 0x04a2032d, 0x000 }, +- { 0x04810433, 0x0423059b, 0x000 }, +- { 0x04bb04ed, 0x042704c8, 0x000 }, +- { 0x043304f4, 0x033a0365, 0x000 }, +- { 0x059b059b, 0x059b059b, 0x000 }, +- { 0x059b059b, 0x059b059b, 0x000 }, +- { 0x059b059b, 0x05b905a2, 0x000 }, +- { 0x059b059b, 0x0007059b, 0x000 }, +- { 0x059b059b, 0x059b059b, 0x000 }, +- { 0x059b059b, 0x059b059b, 0x000 }, +- { 0x03e303d8, 0x03f303f1, 0x000 }, +- { 0x03f903f5, 0x03f703fb, 0x000 }, +- { 0x04070403, 0x040f040b, 0x000 }, +- { 0x04170413, 0x041f041b, 0x000 }, +- { 0x059b059b, 0x059b059b, 0x000 }, +- { 0x059b059b, 0x059b059b, 0x000 }, +- { 0x059b059b, 0x059b059b, 0x000 }, +- { 0x00020600, 0x06190006, 0x000 }, +-}; +- +-static const u32 R600_pfp_microcode[] = { +-0xd40071, +-0xd40072, +-0xca0400, +-0xa00000, +-0x7e828b, +-0x800003, +-0xca0400, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xc41838, +-0xca2400, +-0xca2800, +-0x9581a8, +-0xc41c3a, +-0xc3c000, +-0xca0800, +-0xca0c00, +-0x7c744b, +-0xc20005, +-0x99c000, +-0xc41c3a, +-0x7c744c, +-0xc0fff0, +-0x042c04, +-0x309002, +-0x7d2500, +-0x351402, +-0x7d350b, +-0x255403, +-0x7cd580, +-0x259c03, +-0x95c004, +-0xd5001b, +-0x7eddc1, +-0x7d9d80, +-0xd6801b, +-0xd5801b, +-0xd4401e, +-0xd5401e, +-0xd6401e, +-0xd6801e, +-0xd4801e, +-0xd4c01e, +-0x9783d4, +-0xd5c01e, +-0xca0800, +-0x80001b, +-0xca0c00, +-0xe4011e, +-0xd4001e, +-0x80000d, +-0xc41838, +-0xe4013e, +-0xd4001e, +-0x80000d, +-0xc41838, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca1800, +-0xd4401e, +-0xd5801e, +-0x800054, +-0xd40073, +-0xd4401e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd48019, +-0xd4c018, +-0xd50017, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xe2001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0xd48060, +-0xd4401e, +-0x800002, +-0xd4801e, +-0xca0800, +-0xd48061, +-0xd4401e, +-0x800002, +-0xd4801e, +-0xca0800, +-0xca0c00, +-0xd4401e, +-0xd48016, +-0xd4c016, +-0xd4801e, +-0x8001b9, +-0xd4c01e, +-0xc6083e, +-0xca0c00, +-0xca1000, +-0x948004, +-0xca1400, +-0xe420f3, +-0xd42013, +-0xd56065, +-0xd4e01c, +-0xd5201c, +-0xd5601c, +-0x800002, +-0x062001, +-0xc6083e, +-0xca0c00, +-0xca1000, +-0x9483f7, +-0xca1400, +-0xe420f3, +-0x80007a, +-0xd42013, +-0xc6083e, +-0xca0c00, +-0xca1000, +-0x9883ef, +-0xca1400, +-0xd40064, +-0x80008e, +-0x000000, +-0xc41432, +-0xc6183e, +-0xc4082f, +-0x954005, +-0xc40c30, +-0xd4401e, +-0x800002, +-0xee001e, +-0x9583f5, +-0xc41031, +-0xd44033, +-0xd52065, +-0xd4a01c, +-0xd4e01c, +-0xd5201c, +-0xd40073, +-0xe4015e, +-0xd4001e, +-0x8001b9, +-0x062001, +-0x0a2001, +-0xd60074, +-0xc40836, +-0xc61040, +-0x988007, +-0xcc3835, +-0x95010f, +-0xd4001f, +-0xd46062, +-0x800002, +-0xd42062, +-0xcc1433, +-0x8401bc, +-0xd40070, +-0xd5401e, +-0x800002, +-0xee001e, +-0xca0c00, +-0xca1000, +-0xd4c01a, +-0x8401bc, +-0xd5001a, +-0xcc0443, +-0x35101f, +-0x2c9401, +-0x7d098b, +-0x984005, +-0x7d15cb, +-0xd4001a, +-0x8001b9, +-0xd4006d, +-0x344401, +-0xcc0c44, +-0x98403a, +-0xcc2c46, +-0x958004, +-0xcc0445, +-0x8001b9, +-0xd4001a, +-0xd4c01a, +-0x282801, +-0x8400f3, +-0xcc1003, +-0x98801b, +-0x04380c, +-0x8400f3, +-0xcc1003, +-0x988017, +-0x043808, +-0x8400f3, +-0xcc1003, +-0x988013, +-0x043804, +-0x8400f3, +-0xcc1003, +-0x988014, +-0xcc1047, +-0x9a8009, +-0xcc1448, +-0x9840da, +-0xd4006d, +-0xcc1844, +-0xd5001a, +-0xd5401a, +-0x8000cc, +-0xd5801a, +-0x96c0d3, +-0xd4006d, +-0x8001b9, +-0xd4006e, +-0x9ac003, +-0xd4006d, +-0xd4006e, +-0x800002, +-0xec007f, +-0x9ac0ca, +-0xd4006d, +-0x8001b9, +-0xd4006e, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0x7d9103, +-0x7dd583, +-0x7d190c, +-0x35cc1f, +-0x35701f, +-0x7cf0cb, +-0x7cd08b, +-0x880000, +-0x7e8e8b, +-0x95c004, +-0xd4006e, +-0x8001b9, +-0xd4001a, +-0xd4c01a, +-0xcc0803, +-0xcc0c03, +-0xcc1003, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0xcc2403, +-0xcc2803, +-0x35c41f, +-0x36b01f, +-0x7c704b, +-0x34f01f, +-0x7c704b, +-0x35701f, +-0x7c704b, +-0x7d8881, +-0x7dccc1, +-0x7e5101, +-0x7e9541, +-0x7c9082, +-0x7cd4c2, +-0x7c848b, +-0x9ac003, +-0x7c8c8b, +-0x2c8801, +-0x98809c, +-0xd4006d, +-0x98409a, +-0xd4006e, +-0xcc0847, +-0xcc0c48, +-0xcc1044, +-0xd4801a, +-0xd4c01a, +-0x800104, +-0xd5001a, +-0xcc0832, +-0xd40032, +-0x9482d8, +-0xca0c00, +-0xd4401e, +-0x800002, +-0xd4001e, +-0xe4011e, +-0xd4001e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd4401e, +-0xca1400, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xd5401e, +-0xd54034, +-0x800002, +-0xee001e, +-0x280404, +-0xe2001a, +-0xe2001a, +-0xd4401a, +-0xca3800, +-0xcc0803, +-0xcc0c03, +-0xcc0c03, +-0xcc0c03, +-0x9882bc, +-0x000000, +-0x8401bc, +-0xd7806f, +-0x800002, +-0xee001f, +-0xca0400, +-0xc2ff00, +-0xcc0834, +-0xc13fff, +-0x7c74cb, +-0x7cc90b, +-0x7d010f, +-0x9902af, +-0x7c738b, +-0x8401bc, +-0xd7806f, +-0x800002, +-0xee001f, +-0xca0800, +-0x281900, +-0x7d898b, +-0x958014, +-0x281404, +-0xca0c00, +-0xca1000, +-0xca1c00, +-0xca2400, +-0xe2001f, +-0xd4c01a, +-0xd5001a, +-0xd5401a, +-0xcc1803, +-0xcc2c03, +-0xcc2c03, +-0xcc2c03, +-0x7da58b, +-0x7d9c47, +-0x984296, +-0x000000, +-0x800164, +-0xd4c01a, +-0xd4401e, +-0xd4801e, +-0x800002, +-0xee001e, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0x248c06, +-0x0ccc06, +-0x98c006, +-0xcc1049, +-0x990004, +-0xd40071, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xd4801e, +-0x800002, +-0xee001e, +-0xca0800, +-0xca0c00, +-0x34d018, +-0x251001, +-0x95001f, +-0xc17fff, +-0xca1000, +-0xca1400, +-0xca1800, +-0xd4801d, +-0xd4c01d, +-0x7db18b, +-0xc14202, +-0xc2c001, +-0xd5801d, +-0x34dc0e, +-0x7d5d4c, +-0x7f734c, +-0xd7401e, +-0xd5001e, +-0xd5401e, +-0xc14200, +-0xc2c000, +-0x099c01, +-0x31dc10, +-0x7f5f4c, +-0x7f734c, +-0x7d8380, +-0xd5806f, +-0xd58066, +-0xd7401e, +-0xec005e, +-0xc82402, +-0x8001b9, +-0xd60074, +-0xd4401e, +-0xd4801e, +-0xd4c01e, +-0x800002, +-0xee001e, +-0x800002, +-0xee001f, +-0xd4001f, +-0x800002, +-0xd4001f, +-0xd4001f, +-0x880000, +-0xd4001f, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x010174, +-0x02017b, +-0x030090, +-0x040080, +-0x050005, +-0x060040, +-0x070033, +-0x08012f, +-0x090047, +-0x0a0037, +-0x1001b7, +-0x1700a4, +-0x22013d, +-0x23014c, +-0x2000b5, +-0x240128, +-0x27004e, +-0x28006b, +-0x2a0061, +-0x2b0053, +-0x2f0066, +-0x320088, +-0x340182, +-0x3c0159, +-0x3f0073, +-0x41018f, +-0x440131, +-0x550176, +-0x56017d, +-0x60000c, +-0x610035, +-0x620039, +-0x630039, +-0x640039, +-0x650039, +-0x660039, +-0x670039, +-0x68003b, +-0x690042, +-0x6a0049, +-0x6b0049, +-0x6c0049, +-0x6d0049, +-0x6e0049, +-0x6f0049, +-0x7301b7, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-0x000007, +-}; +- +-static const u32 RV610_cp_microcode[][3] = { +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x0000ffff, 0x00284621, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00000000, 0x00e00000, 0x000 }, +- { 0x00010000, 0xc0294620, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x00000000, 0x00600000, 0x631 }, +- { 0x00000000, 0x00600000, 0x645 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000f00, 0x00281622, 0x000 }, +- { 0x00000008, 0x00211625, 0x000 }, +- { 0x00000018, 0x00203625, 0x000 }, +- { 0x8d000000, 0x00204411, 0x000 }, +- { 0x00000004, 0x002f0225, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x018 }, +- { 0x00412000, 0x00404811, 0x019 }, +- { 0x00422000, 0x00204811, 0x000 }, +- { 0x8e000000, 0x00204411, 0x000 }, +- { 0x00000028, 0x00204a2d, 0x000 }, +- { 0x90000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x0000000c, 0x00211622, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000019, 0x00211a22, 0x000 }, +- { 0x00000004, 0x00281a26, 0x000 }, +- { 0x00000000, 0x002914c5, 0x000 }, +- { 0x00000019, 0x00203625, 0x000 }, +- { 0x00000000, 0x003a1402, 0x000 }, +- { 0x00000016, 0x00211625, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0xfffffffc, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002914a3, 0x000 }, +- { 0x00000017, 0x00203625, 0x000 }, +- { 0x00008000, 0x00280e22, 0x000 }, +- { 0x00000007, 0x00220e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x20000000, 0x00280e22, 0x000 }, +- { 0x00000006, 0x00210e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x00000000, 0x00220222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x038 }, +- { 0x00000000, 0x2ee00000, 0x035 }, +- { 0x00000000, 0x2ce00000, 0x037 }, +- { 0x00000000, 0x00400e2d, 0x039 }, +- { 0x00000008, 0x00200e2d, 0x000 }, +- { 0x00000009, 0x0040122d, 0x046 }, +- { 0x00000001, 0x00400e2d, 0x039 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x03e }, +- { 0x00000008, 0x00401c11, 0x041 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x0000000f, 0x00281e27, 0x000 }, +- { 0x00000003, 0x00221e27, 0x000 }, +- { 0x7fc00000, 0x00281a23, 0x000 }, +- { 0x00000014, 0x00211a26, 0x000 }, +- { 0x00000001, 0x00331a26, 0x000 }, +- { 0x00000008, 0x00221a26, 0x000 }, +- { 0x00000000, 0x00290cc7, 0x000 }, +- { 0x00000027, 0x00203624, 0x000 }, +- { 0x00007f00, 0x00281221, 0x000 }, +- { 0x00001400, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04b }, +- { 0x00000001, 0x00290e23, 0x000 }, +- { 0x0000000e, 0x00203623, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfff80000, 0x00294a23, 0x000 }, +- { 0x00000000, 0x003a2c02, 0x000 }, +- { 0x00000002, 0x00220e2b, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x0000000f, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00204a2d, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000029, 0x00200e2d, 0x000 }, +- { 0x060a0200, 0x00294a23, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x061 }, +- { 0x00000000, 0x2ee00000, 0x05f }, +- { 0x00000000, 0x2ce00000, 0x05e }, +- { 0x00000000, 0x00400e2d, 0x062 }, +- { 0x00000001, 0x00400e2d, 0x062 }, +- { 0x0000000a, 0x00200e2d, 0x000 }, +- { 0x0000000b, 0x0040122d, 0x06a }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x7fc00000, 0x00281623, 0x000 }, +- { 0x00000014, 0x00211625, 0x000 }, +- { 0x00000001, 0x00331625, 0x000 }, +- { 0x80000000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00290ca3, 0x000 }, +- { 0x3ffffc00, 0x00290e23, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x06d }, +- { 0x00000100, 0x00401c11, 0x070 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x000000f0, 0x00281e27, 0x000 }, +- { 0x00000004, 0x00221e27, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0xfffff0ff, 0x00281a30, 0x000 }, +- { 0x0000a028, 0x00204411, 0x000 }, +- { 0x00000000, 0x002948e6, 0x000 }, +- { 0x0000a018, 0x00204411, 0x000 }, +- { 0x3fffffff, 0x00284a23, 0x000 }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000030, 0x0020162d, 0x000 }, +- { 0x00000002, 0x00291625, 0x000 }, +- { 0x00000030, 0x00203625, 0x000 }, +- { 0x00000025, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a3, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x083 }, +- { 0x00000026, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a4, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x084 }, +- { 0x00000000, 0x00400000, 0x08a }, +- { 0x00000025, 0x00203623, 0x000 }, +- { 0x00000026, 0x00203624, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x08a }, +- { 0x00000000, 0x00600000, 0x668 }, +- { 0x00000000, 0x00600000, 0x65c }, +- { 0x00000002, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x08d }, +- { 0x00000012, 0xc0403620, 0x093 }, +- { 0x00000000, 0x2ee00000, 0x091 }, +- { 0x00000000, 0x2ce00000, 0x090 }, +- { 0x00000002, 0x00400e2d, 0x092 }, +- { 0x00000003, 0x00400e2d, 0x092 }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000012, 0x00203623, 0x000 }, +- { 0x00000003, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x098 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x0a0 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x2ee00000, 0x09e }, +- { 0x00000000, 0x2ce00000, 0x09d }, +- { 0x00000002, 0x00400e2d, 0x09f }, +- { 0x00000003, 0x00400e2d, 0x09f }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x003f0000, 0x00280e23, 0x000 }, +- { 0x00000010, 0x00210e23, 0x000 }, +- { 0x00000011, 0x00203623, 0x000 }, +- { 0x0000001e, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0a7 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x0000001f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0aa }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000008, 0x00210e2b, 0x000 }, +- { 0x0000007f, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0e1 }, +- { 0x00000000, 0x27000000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0b3 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000000c, 0x00221e30, 0x000 }, +- { 0x99800000, 0x00204411, 0x000 }, +- { 0x00000004, 0x0020122d, 0x000 }, +- { 0x00000008, 0x00221224, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00291ce4, 0x000 }, +- { 0x00000000, 0x00604807, 0x12f }, +- { 0x9b000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x9c000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x0033146f, 0x000 }, +- { 0x00000001, 0x00333e23, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0x00203c05, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e007, 0x00204411, 0x000 }, +- { 0x0000000f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0cb }, +- { 0x00f8ff08, 0x00204811, 0x000 }, +- { 0x98000000, 0x00404811, 0x0dc }, +- { 0x000000f0, 0x00280e22, 0x000 }, +- { 0x000000a0, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x0da }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d5 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d4 }, +- { 0x00003f00, 0x00400c11, 0x0d6 }, +- { 0x00001f00, 0x00400c11, 0x0d6 }, +- { 0x00000f00, 0x00200c11, 0x000 }, +- { 0x00380009, 0x00294a23, 0x000 }, +- { 0x3f000000, 0x00280e2b, 0x000 }, +- { 0x00000002, 0x00220e23, 0x000 }, +- { 0x00000007, 0x00494a23, 0x0dc }, +- { 0x00380f09, 0x00204811, 0x000 }, +- { 0x68000007, 0x00204811, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000a202, 0x00204411, 0x000 }, +- { 0x00ff0000, 0x00280e22, 0x000 }, +- { 0x00000080, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00200e2d, 0x000 }, +- { 0x00000026, 0x0020122d, 0x000 }, +- { 0x00000000, 0x002f0083, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0ea }, +- { 0x00000000, 0x00600000, 0x662 }, +- { 0x00000000, 0x00400000, 0x0eb }, +- { 0x00000000, 0x00600000, 0x665 }, +- { 0x00000007, 0x0020222d, 0x000 }, +- { 0x00000005, 0x00220e22, 0x000 }, +- { 0x00100000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x000000ef, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000003, 0x00210223, 0x000 }, +- { 0x00000000, 0x14e00000, 0x0f8 }, +- { 0x0000000b, 0x00210228, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0f8 }, +- { 0x00000400, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000001c, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0fd }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000001e, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x10b }, +- { 0x0000a30f, 0x00204411, 0x000 }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x104 }, +- { 0xffffffff, 0x00404811, 0x10b }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x107 }, +- { 0x0000ffff, 0x00404811, 0x10b }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x10a }, +- { 0x000000ff, 0x00404811, 0x10b }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0002c400, 0x00204411, 0x000 }, +- { 0x0000001f, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x112 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000018, 0x40224a20, 0x000 }, +- { 0x00000010, 0xc0424a20, 0x114 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000000a, 0x00201011, 0x000 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x11b }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00531224, 0x117 }, +- { 0xffbfffff, 0x00283a2e, 0x000 }, +- { 0x0000001b, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x12e }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0x00000018, 0x00220e30, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e00e, 0x00204411, 0x000 }, +- { 0x07f8ff08, 0x00204811, 0x000 }, +- { 0x00000000, 0x00294a23, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x00800000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204806, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68d }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x68c }, +- { 0x00000004, 0x00404c11, 0x135 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x000021f8, 0x00204411, 0x000 }, +- { 0x0000001c, 0x00204811, 0x000 }, +- { 0x000421f9, 0x00604411, 0x68d }, +- { 0x00000011, 0x00210230, 0x000 }, +- { 0x00000000, 0x14e00000, 0x13c }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40280620, 0x000 }, +- { 0x00000010, 0xc0210a20, 0x000 }, +- { 0x00000000, 0x00341461, 0x000 }, +- { 0x00000000, 0x00741882, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x147 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0681a20, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x158 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000001, 0x00300a2f, 0x000 }, +- { 0x00000001, 0x00210a22, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600000, 0x18f }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00202c08, 0x000 }, +- { 0x00000000, 0x00202411, 0x000 }, +- { 0x00000000, 0x00202811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00221e29, 0x000 }, +- { 0x00000000, 0x007048eb, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000001, 0x40330620, 0x000 }, +- { 0x00000000, 0xc0302409, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x181 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x186 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x186 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000001, 0x00530621, 0x182 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0604800, 0x197 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000011, 0x0020062d, 0x000 }, +- { 0x00000000, 0x0078042a, 0x2fb }, +- { 0x00000000, 0x00202809, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x174 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x194 }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x46000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x19b }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00804811, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40281620, 0x000 }, +- { 0x00000010, 0xc0811a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000008, 0x00221e30, 0x000 }, +- { 0x00000029, 0x00201a2d, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfffbff09, 0x00204811, 0x000 }, +- { 0x0000000f, 0x0020222d, 0x000 }, +- { 0x00001fff, 0x00294a28, 0x000 }, +- { 0x00000006, 0x0020222d, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000100, 0x00201811, 0x000 }, +- { 0x00000008, 0x00621e28, 0x12f }, +- { 0x00000008, 0x00822228, 0x000 }, +- { 0x0002c000, 0x00204411, 0x000 }, +- { 0x00000015, 0x00600e2d, 0x1bd }, +- { 0x00000016, 0x00600e2d, 0x1bd }, +- { 0x0000c008, 0x00204411, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1b9 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x39000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00804802, 0x000 }, +- { 0x00000018, 0x00202e2d, 0x000 }, +- { 0x00000000, 0x003b0d63, 0x000 }, +- { 0x00000008, 0x00224a23, 0x000 }, +- { 0x00000010, 0x00224a23, 0x000 }, +- { 0x00000018, 0x00224a23, 0x000 }, +- { 0x00000000, 0x00804803, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000007, 0x0021062f, 0x000 }, +- { 0x00000013, 0x00200a2d, 0x000 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000ffff, 0x40282220, 0x000 }, +- { 0x0000000f, 0x00262228, 0x000 }, +- { 0x00000010, 0x40212620, 0x000 }, +- { 0x0000000f, 0x00262629, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1e0 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000081, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000080, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1dc }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1d8 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000001f, 0x00280a22, 0x000 }, +- { 0x0000001f, 0x00282a2a, 0x000 }, +- { 0x00000001, 0x00530621, 0x1d1 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000002, 0x00304a2f, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000001, 0x00301e2f, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1e5 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x0000000f, 0x00260e23, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000000f, 0x00261224, 0x000 }, +- { 0x00000000, 0x00201411, 0x000 }, +- { 0x00000000, 0x00601811, 0x2bb }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022b, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1f8 }, +- { 0x00000010, 0x00221628, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a29, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x0020480a, 0x000 }, +- { 0x00000000, 0x00202c11, 0x000 }, +- { 0x00000010, 0x00221623, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a24, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x00731503, 0x205 }, +- { 0x00000000, 0x00201805, 0x000 }, +- { 0x00000000, 0x00731524, 0x205 }, +- { 0x00000000, 0x002d14c5, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00000000, 0x00202003, 0x000 }, +- { 0x00000000, 0x00802404, 0x000 }, +- { 0x0000000f, 0x00210225, 0x000 }, +- { 0x00000000, 0x14c00000, 0x68c }, +- { 0x00000000, 0x002b1405, 0x000 }, +- { 0x00000001, 0x00901625, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00294a22, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a21, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000ffff, 0x40281220, 0x000 }, +- { 0x00000010, 0xc0211a20, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211620, 0x000 }, +- { 0x00000000, 0x00741465, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00000001, 0x00330621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x219 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x212 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x645 }, +- { 0x00000000, 0x0040040f, 0x213 }, +- { 0x00000000, 0x00600000, 0x631 }, +- { 0x00000000, 0x00600000, 0x645 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00000000, 0x00600000, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x232 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x236 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x236 }, +- { 0x00000000, 0xc0404800, 0x233 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x00600411, 0x2fb }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x631 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000018, 0x40210a20, 0x000 }, +- { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x24c }, +- { 0x00000014, 0x0020222d, 0x000 }, +- { 0x00080101, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x251 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000010, 0x00600411, 0x315 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00000000, 0x00600000, 0x27c }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000001, 0x00211e27, 0x000 }, +- { 0x00000000, 0x14e00000, 0x26a }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x0000ffff, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00341c27, 0x000 }, +- { 0x00000000, 0x12c00000, 0x25f }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e5, 0x000 }, +- { 0x00000000, 0x08c00000, 0x262 }, +- { 0x00000000, 0x00201407, 0x000 }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00211e27, 0x000 }, +- { 0x00000000, 0x00341c47, 0x000 }, +- { 0x00000000, 0x12c00000, 0x267 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e6, 0x000 }, +- { 0x00000000, 0x08c00000, 0x26a }, +- { 0x00000000, 0x00201807, 0x000 }, +- { 0x00000000, 0x00600000, 0x2c1 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000000, 0x00342023, 0x000 }, +- { 0x00000000, 0x12c00000, 0x272 }, +- { 0x00000000, 0x00342044, 0x000 }, +- { 0x00000000, 0x12c00000, 0x271 }, +- { 0x00000016, 0x00404811, 0x276 }, +- { 0x00000018, 0x00404811, 0x276 }, +- { 0x00000000, 0x00342044, 0x000 }, +- { 0x00000000, 0x12c00000, 0x275 }, +- { 0x00000017, 0x00404811, 0x276 }, +- { 0x00000019, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00604411, 0x2e9 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x256 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000010, 0x40210620, 0x000 }, +- { 0x0000ffff, 0xc0280a20, 0x000 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0881a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x00000000, 0x00600000, 0x631 }, +- { 0x00000000, 0xc0600000, 0x2a3 }, +- { 0x00000005, 0x00200a2d, 0x000 }, +- { 0x00000008, 0x00220a22, 0x000 }, +- { 0x0000002b, 0x00201a2d, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00007000, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00311ce6, 0x000 }, +- { 0x0000002a, 0x00201a2d, 0x000 }, +- { 0x0000000c, 0x00221a26, 0x000 }, +- { 0x00000000, 0x002f00e6, 0x000 }, +- { 0x00000000, 0x06e00000, 0x292 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x0000002b, 0x00203623, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00691ce2, 0x12f }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x29d }, +- { 0x00000001, 0x00333e2f, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000001c, 0x00403627, 0x000 }, +- { 0x0000000c, 0xc0220a20, 0x000 }, +- { 0x00000029, 0x00203622, 0x000 }, +- { 0x00000028, 0xc0403620, 0x000 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000009, 0x00204811, 0x000 }, +- { 0xa1000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002c1ce3, 0x000 }, +- { 0x00000021, 0x00203627, 0x000 }, +- { 0x00000022, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002c1ce4, 0x000 }, +- { 0x00000022, 0x00203627, 0x000 }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120a3, 0x000 }, +- { 0x00000000, 0x002d1d07, 0x000 }, +- { 0x00000023, 0x00203627, 0x000 }, +- { 0x00000024, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x00000000, 0x002d1d07, 0x000 }, +- { 0x00000024, 0x00803627, 0x000 }, +- { 0x00000021, 0x00203623, 0x000 }, +- { 0x00000022, 0x00203624, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000023, 0x00203627, 0x000 }, +- { 0x00000000, 0x00311cc4, 0x000 }, +- { 0x00000024, 0x00803627, 0x000 }, +- { 0x0000001a, 0x00203627, 0x000 }, +- { 0x0000001b, 0x00203628, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14c00000, 0x2dc }, +- { 0x00000000, 0x00400000, 0x2d9 }, +- { 0x0000001a, 0x00203627, 0x000 }, +- { 0x0000001b, 0x00203628, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x2d9 }, +- { 0x00000003, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x2dc }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002e00e1, 0x000 }, +- { 0x00000000, 0x02c00000, 0x2dc }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120a1, 0x000 }, +- { 0x00000000, 0x002e00e8, 0x000 }, +- { 0x00000000, 0x06c00000, 0x2dc }, +- { 0x00000024, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002e00e2, 0x000 }, +- { 0x00000000, 0x02c00000, 0x2dc }, +- { 0x00000022, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120c2, 0x000 }, +- { 0x00000000, 0x002e00e8, 0x000 }, +- { 0x00000000, 0x06c00000, 0x2dc }, +- { 0x00000000, 0x00600000, 0x668 }, +- { 0x00000000, 0x00600000, 0x2b5 }, +- { 0x00000000, 0x00400000, 0x2de }, +- { 0x00000000, 0x00600000, 0x2b5 }, +- { 0x00000000, 0x00600000, 0x65f }, +- { 0x00000000, 0x00400000, 0x2de }, +- { 0x00000000, 0x00600000, 0x2a7 }, +- { 0x00000000, 0x00400000, 0x2de }, +- { 0x0000001a, 0x00201e2d, 0x000 }, +- { 0x0000001b, 0x0080222d, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00894907, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000010, 0x00221e21, 0x000 }, +- { 0x00000000, 0x00294847, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000000, 0x00311ca1, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294847, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000010, 0x00221e21, 0x000 }, +- { 0x00000000, 0x003120c2, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00894907, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000001, 0x00220a21, 0x000 }, +- { 0x00000000, 0x003308a2, 0x000 }, +- { 0x00000010, 0x00221e22, 0x000 }, +- { 0x00000010, 0x00212222, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000001, 0x00220a21, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000010, 0x00221e22, 0x000 }, +- { 0x00000010, 0x00212222, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x003808c5, 0x000 }, +- { 0x00000000, 0x00300841, 0x000 }, +- { 0x00000001, 0x00220a22, 0x000 }, +- { 0x00000000, 0x003308a2, 0x000 }, +- { 0x00000010, 0x00221e22, 0x000 }, +- { 0x00000010, 0x00212222, 0x000 }, +- { 0x00000000, 0x00894907, 0x000 }, +- { 0x00000017, 0x0020222d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x318 }, +- { 0xffffffef, 0x00280621, 0x000 }, +- { 0x00000014, 0x0020222d, 0x000 }, +- { 0x0000f8e0, 0x00204411, 0x000 }, +- { 0x00000000, 0x00294901, 0x000 }, +- { 0x00000000, 0x00894901, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00804811, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x97000000, 0xc0204411, 0x000 }, +- { 0x00000000, 0xc0204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00002257, 0x00204411, 0x000 }, +- { 0x00000003, 0xc0484a20, 0x000 }, +- { 0x0000225d, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0x00600000, 0x645 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x40204800, 0x000 }, +- { 0x00000001, 0x40304a20, 0x000 }, +- { 0x00000002, 0xc0304a20, 0x000 }, +- { 0x00000001, 0x00530a22, 0x34b }, +- { 0x0000003f, 0xc0280a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x000021f8, 0x00204411, 0x000 }, +- { 0x00000018, 0x00204811, 0x000 }, +- { 0x000421f9, 0x00604411, 0x68d }, +- { 0x00000011, 0x00210230, 0x000 }, +- { 0x00000000, 0x14e00000, 0x354 }, +- { 0x00000014, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x364 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00604802, 0x36e }, +- { 0x00002100, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 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0x00204411, 0x000 }, +- { 0x00002000, 0x00204811, 0x000 }, +- { 0xb6000000, 0x00204411, 0x000 }, +- { 0x0000a000, 0x00204811, 0x000 }, +- { 0xb7000000, 0x00204411, 0x000 }, +- { 0x0000c000, 0x00204811, 0x000 }, +- { 0xb8000000, 0x00204411, 0x000 }, +- { 0x0000f8e0, 0x00204811, 0x000 }, +- { 0xb9000000, 0x00204411, 0x000 }, +- { 0x0000f880, 0x00204811, 0x000 }, +- { 0xba000000, 0x00204411, 0x000 }, +- { 0x0000e000, 0x00204811, 0x000 }, +- { 0xbb000000, 0x00204411, 0x000 }, +- { 0x0000f000, 0x00204811, 0x000 }, +- { 0xbc000000, 0x00204411, 0x000 }, +- { 0x0000f3fc, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00204811, 0x000 }, +- { 0x000000ff, 0x00280e30, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x519 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000000, 0x14c00000, 0x52e }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x0000001c, 0x00203623, 0x000 }, +- { 0x0000002b, 0x00203623, 0x000 }, +- { 0x00000029, 0x00203623, 0x000 }, +- { 0x00000028, 0x00203623, 0x000 }, +- { 0x00000017, 0x00203623, 0x000 }, +- { 0x00000025, 0x00203623, 0x000 }, +- { 0x00000026, 0x00203623, 0x000 }, +- { 0x00000015, 0x00203623, 0x000 }, +- { 0x00000016, 0x00203623, 0x000 }, +- { 0xffffe000, 0x00200c11, 0x000 }, +- { 0x00000021, 0x00203623, 0x000 }, +- { 0x00000022, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00200c11, 0x000 }, +- { 0x00000023, 0x00203623, 0x000 }, +- { 0x00000024, 0x00203623, 0x000 }, +- { 0xf1ffffff, 0x00283a2e, 0x000 }, +- { 0x0000001a, 0xc0220e20, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000002a, 0x40203620, 0x000 }, +- { 0x87000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000a1f4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x00000030, 0x00203623, 0x000 }, +- { 0x9d000000, 0x00204411, 0x000 }, +- { 0x0000001f, 0x40214a20, 0x000 }, +- { 0x96000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x00000000, 0xc0201000, 0x000 }, +- { 0x0000001f, 0x00211624, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x0000001d, 0x00203623, 0x000 }, +- { 0x00000003, 0x00281e23, 0x000 }, +- { 0x00000008, 0x00222223, 0x000 }, +- { 0xfffff000, 0x00282228, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x0000001f, 0x00203628, 0x000 }, +- { 0x00000018, 0x00211e23, 0x000 }, +- { 0x00000020, 0x00203627, 0x000 }, +- { 0x00000002, 0x00221624, 0x000 }, +- { 0x00000000, 0x003014a8, 0x000 }, +- { 0x0000001e, 0x00203625, 0x000 }, +- { 0x00000003, 0x00211a24, 0x000 }, +- { 0x10000000, 0x00281a26, 0x000 }, +- { 0xefffffff, 0x00283a2e, 0x000 }, +- { 0x00000000, 0x004938ce, 0x67b }, +- { 0x00000001, 0x40280a20, 0x000 }, +- { 0x00000006, 0x40280e20, 0x000 }, +- { 0x00000300, 0xc0281220, 0x000 }, +- { 0x00000008, 0x00211224, 0x000 }, +- { 0x00000000, 0xc0201620, 0x000 }, +- { 0x00000000, 0xc0201a20, 0x000 }, +- { 0x00000000, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x566 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00002258, 0x00300a24, 0x000 }, +- { 0x00040000, 0x00694622, 0x68d }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x00020000, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x56e }, +- { 0x00000000, 0xc0201c10, 0x000 }, +- { 0x00000000, 0xc0400000, 0x57c }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x56e }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00002258, 0x00300a24, 0x000 }, +- { 0x00040000, 0x00694622, 0x68d }, +- { 0x00000000, 0xc0201c10, 0x000 }, +- { 0x00000000, 0xc0400000, 0x57c }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x572 }, +- { 0x00000000, 0xc0201c00, 0x000 }, +- { 0x00000000, 0xc0400000, 0x57c }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x57a }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000216d, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0604800, 0x692 }, +- { 0x00000000, 0x00401c10, 0x57c }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00000000, 0xc0400000, 0x000 }, +- { 0x00000000, 0x0ee00000, 0x57e }, +- { 0x00000000, 0x00600000, 0x5c9 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x58f }, +- { 0x0000a2b7, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2b6, 0x00604411, 0x68d }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x0000a2c4, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x58d }, +- { 0x0000a2d1, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d1, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x00000001, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x5a0 }, +- { 0x0000a2bb, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2ba, 0x00604411, 0x68d }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x0000a2c5, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x59e }, +- { 0x0000a2d2, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d2, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x00000002, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x5b1 }, +- { 0x0000a2bf, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2be, 0x00604411, 0x68d }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x0000a2c6, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x5af }, +- { 0x0000a2d3, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d3, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x0000a2c3, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2c2, 0x00604411, 0x68d }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x0000a2c7, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x5be }, +- { 0x0000a2d4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d4, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x85000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x0000304a, 0x00204411, 0x000 }, +- { 0x01000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00400000, 0x5c4 }, +- { 0xa4000000, 0xc0204411, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0xc0600000, 0x5c9 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000002c, 0x00203621, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0230, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x5d0 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000030, 0x00403621, 0x5e3 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00007e00, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x5e3 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a092, 0x00604411, 0x68d }, +- { 0x00000031, 0x00203630, 0x000 }, +- { 0x0004a093, 0x00604411, 0x68d }, +- { 0x00000032, 0x00203630, 0x000 }, +- { 0x0004a2b6, 0x00604411, 0x68d }, +- { 0x00000033, 0x00203630, 0x000 }, +- { 0x0004a2ba, 0x00604411, 0x68d }, +- { 0x00000034, 0x00203630, 0x000 }, +- { 0x0004a2be, 0x00604411, 0x68d }, +- { 0x00000035, 0x00203630, 0x000 }, +- { 0x0004a2c2, 0x00604411, 0x68d }, +- { 0x00000036, 0x00203630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x00000005, 0x00204811, 0x000 }, +- { 0x0000a1f4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x88000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000001, 0x002f0230, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62c }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62c }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00007e00, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x605 }, +- { 0x0000a092, 0x00204411, 0x000 }, +- { 0x00000031, 0x00204a2d, 0x000 }, +- { 0x0000a093, 0x00204411, 0x000 }, +- { 0x00000032, 0x00204a2d, 0x000 }, +- { 0x0000a2b6, 0x00204411, 0x000 }, +- { 0x00000033, 0x00204a2d, 0x000 }, +- { 0x0000a2ba, 0x00204411, 0x000 }, +- { 0x00000034, 0x00204a2d, 0x000 }, +- { 0x0000a2be, 0x00204411, 0x000 }, +- { 0x00000035, 0x00204a2d, 0x000 }, +- { 0x0000a2c2, 0x00204411, 0x000 }, +- { 0x00000036, 0x00204a2d, 0x000 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x000001ff, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62b }, +- { 0x00000000, 0x00210221, 0x000 }, +- { 0x00000000, 0x14c00000, 0x60e }, +- { 0x0004a003, 0x00604411, 0x68d }, +- { 0x0000a003, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000001, 0x00210621, 0x000 }, +- { 0x00000000, 0x14c00000, 0x613 }, +- { 0x0004a010, 0x00604411, 0x68d }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000001, 0x00210621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62b }, +- { 0x0004a011, 0x00604411, 0x68d }, +- { 0x0000a011, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a012, 0x00604411, 0x68d }, +- { 0x0000a012, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a013, 0x00604411, 0x68d }, +- { 0x0000a013, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a014, 0x00604411, 0x68d }, +- { 0x0000a014, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a015, 0x00604411, 0x68d }, +- { 0x0000a015, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a016, 0x00604411, 0x68d }, +- { 0x0000a016, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a017, 0x00604411, 0x68d }, +- { 0x0000a017, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x0000002c, 0x0080062d, 0x000 }, +- { 0xff000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000002, 0x00804811, 0x000 }, +- { 0x00000000, 0x0ee00000, 0x63d }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00000002, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x63b }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x00001000, 0x00200811, 0x000 }, +- { 0x0000002b, 0x00203622, 0x000 }, +- { 0x00000000, 0x00600000, 0x641 }, +- { 0x00000000, 0x00600000, 0x5c9 }, +- { 0x98000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00804811, 0x000 }, +- { 0x00000000, 0xc0600000, 0x641 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000022, 0x00204811, 0x000 }, +- { 0x89000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00404811, 0x62d }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404811, 0x62d }, +- { 0x00000000, 0x00600000, 0x65c }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0xc0204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36e }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x09800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68d }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x00000004, 0x00404c11, 0x656 }, +- { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000004, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffffb, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffff7, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36e }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x01800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68d }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x68c }, +- { 0x00000010, 0x00404c11, 0x672 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x38c00000, 0x000 }, +- { 0x0000001d, 0x00200a2d, 0x000 }, +- { 0x0000001e, 0x00200e2d, 0x000 }, +- { 0x0000001f, 0x0020122d, 0x000 }, +- { 0x00000020, 0x0020162d, 0x000 }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000004, 0x00301224, 0x000 }, +- { 0x00000000, 0x002f0064, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x68b }, +- { 0x00000003, 0x00281a22, 0x000 }, +- { 0x00000008, 0x00221222, 0x000 }, +- { 0xfffff000, 0x00281224, 0x000 }, +- { 0x00000000, 0x002910c4, 0x000 }, +- { 0x0000001f, 0x00403624, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x68d }, +- { 0x9f000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x690 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x692 }, +- { 0x9e000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x695 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0xc0204411, 0x000 }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000024, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000022, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00404811, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x01420502, 0x05c00250, 0x000 }, +- { 0x01c30168, 0x043f05c0, 0x000 }, +- { 0x02250209, 0x02500151, 0x000 }, +- { 0x02230245, 0x02a00241, 0x000 }, +- { 0x03d705c0, 0x05c005c0, 0x000 }, +- { 0x0649064a, 0x031f05c0, 0x000 }, +- { 0x05c005c5, 0x03200340, 0x000 }, +- { 0x032a0282, 0x03420334, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c00551, 0x05c005c0, 0x000 }, +- { 0x03ba05c0, 0x04bb0344, 0x000 }, +- { 0x049a0450, 0x043d05c0, 0x000 }, +- { 0x04d005c0, 0x044104dd, 0x000 }, +- { 0x04500507, 0x03510375, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c005c0, 0x063f05c7, 0x000 }, +- { 0x05c005c0, 0x000705c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x03f803ed, 0x04080406, 0x000 }, +- { 0x040e040a, 0x040c0410, 0x000 }, +- { 0x041c0418, 0x04240420, 0x000 }, +- { 0x042c0428, 0x04340430, 0x000 }, +- { 0x05c005c0, 0x043805c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x00020679, 0x06970006, 0x000 }, +-}; +- +-static const u32 RV610_pfp_microcode[] = { +-0xca0400, +-0xa00000, +-0x7e828b, +-0x7c038b, +-0x8001b8, +-0x7c038b, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xc41838, +-0xca2400, +-0xca2800, +-0x9581a8, +-0xc41c3a, +-0xc3c000, +-0xca0800, +-0xca0c00, +-0x7c744b, +-0xc20005, +-0x99c000, +-0xc41c3a, +-0x7c744c, +-0xc0fff0, +-0x042c04, +-0x309002, +-0x7d2500, +-0x351402, +-0x7d350b, +-0x255403, +-0x7cd580, +-0x259c03, +-0x95c004, +-0xd5001b, +-0x7eddc1, +-0x7d9d80, +-0xd6801b, +-0xd5801b, +-0xd4401e, +-0xd5401e, +-0xd6401e, +-0xd6801e, +-0xd4801e, +-0xd4c01e, +-0x9783d3, +-0xd5c01e, +-0xca0800, +-0x80001a, +-0xca0c00, +-0xe4011e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xe4013e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca1800, +-0xd4401e, +-0xd5801e, +-0x800053, +-0xd40075, +-0xd4401e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd48019, +-0xd4c018, +-0xd50017, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xe2001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0xd48060, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xd48061, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xca0c00, +-0xd4401e, +-0xd48016, +-0xd4c016, +-0xd4801e, +-0x8001b8, +-0xd4c01e, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x948004, +-0xca1400, +-0xe420f3, +-0xd42013, +-0xd56065, +-0xd4e01c, +-0xd5201c, +-0xd5601c, +-0x800000, +-0x062001, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9483f7, +-0xca1400, +-0xe420f3, +-0x800079, +-0xd42013, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9883ef, +-0xca1400, +-0xd40064, +-0x80008d, +-0x000000, +-0xc41432, +-0xc61843, +-0xc4082f, +-0x954005, +-0xc40c30, +-0xd4401e, +-0x800000, +-0xee001e, +-0x9583f5, +-0xc41031, +-0xd44033, +-0xd52065, +-0xd4a01c, +-0xd4e01c, +-0xd5201c, +-0xe4015e, +-0xd4001e, +-0x800000, +-0x062001, +-0xca1800, +-0x0a2001, +-0xd60076, +-0xc40836, +-0x988007, +-0xc61045, +-0x950110, +-0xd4001f, +-0xd46062, +-0x800000, +-0xd42062, +-0xcc3835, +-0xcc1433, +-0x8401bb, +-0xd40072, +-0xd5401e, +-0x800000, +-0xee001e, +-0xe2001a, +-0x8401bb, +-0xe2001a, +-0xcc104b, +-0xcc0447, +-0x2c9401, +-0x7d098b, +-0x984005, +-0x7d15cb, +-0xd4001a, +-0x8001b8, +-0xd4006d, +-0x344401, +-0xcc0c48, +-0x98403a, +-0xcc2c4a, +-0x958004, +-0xcc0449, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0x282801, +-0x8400f0, +-0xcc1003, +-0x98801b, +-0x04380c, +-0x8400f0, +-0xcc1003, +-0x988017, +-0x043808, +-0x8400f0, +-0xcc1003, +-0x988013, +-0x043804, +-0x8400f0, +-0xcc1003, +-0x988014, +-0xcc104c, +-0x9a8009, +-0xcc144d, +-0x9840dc, +-0xd4006d, +-0xcc1848, +-0xd5001a, +-0xd5401a, +-0x8000c9, +-0xd5801a, +-0x96c0d5, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0x9ac003, +-0xd4006d, +-0xd4006e, +-0x800000, +-0xec007f, +-0x9ac0cc, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0x7d9103, +-0x7dd583, +-0x7d190c, +-0x35cc1f, +-0x35701f, +-0x7cf0cb, +-0x7cd08b, +-0x880000, +-0x7e8e8b, +-0x95c004, +-0xd4006e, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0xcc0803, +-0xcc0c03, +-0xcc1003, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0xcc2403, +-0xcc2803, +-0x35c41f, +-0x36b01f, +-0x7c704b, +-0x34f01f, +-0x7c704b, +-0x35701f, +-0x7c704b, +-0x7d8881, +-0x7dccc1, +-0x7e5101, +-0x7e9541, +-0x7c9082, +-0x7cd4c2, +-0x7c848b, +-0x9ac003, +-0x7c8c8b, +-0x2c8801, +-0x98809e, +-0xd4006d, +-0x98409c, +-0xd4006e, +-0xcc084c, +-0xcc0c4d, +-0xcc1048, +-0xd4801a, +-0xd4c01a, +-0x800101, +-0xd5001a, +-0xcc0832, +-0xd40032, +-0x9482d9, +-0xca0c00, +-0xd4401e, +-0x800000, +-0xd4001e, +-0xe4011e, +-0xd4001e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd4401e, +-0xca1400, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xd5401e, +-0xd54034, +-0x800000, +-0xee001e, +-0x280404, +-0xe2001a, +-0xe2001a, +-0xd4401a, +-0xca3800, +-0xcc0803, +-0xcc0c03, +-0xcc0c03, +-0xcc0c03, +-0x9882bd, +-0x000000, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0400, +-0xc2ff00, +-0xcc0834, +-0xc13fff, +-0x7c74cb, +-0x7cc90b, +-0x7d010f, +-0x9902b0, +-0x7c738b, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0800, +-0x281900, +-0x7d898b, +-0x958014, +-0x281404, +-0xca0c00, +-0xca1000, +-0xca1c00, +-0xca2400, +-0xe2001f, +-0xd4c01a, +-0xd5001a, +-0xd5401a, +-0xcc1803, +-0xcc2c03, +-0xcc2c03, +-0xcc2c03, +-0x7da58b, +-0x7d9c47, +-0x984297, +-0x000000, +-0x800161, +-0xd4c01a, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0x248c06, +-0x0ccc06, +-0x98c006, +-0xcc104e, +-0x990004, +-0xd40073, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xca0800, +-0xca0c00, +-0x34d018, +-0x251001, +-0x950021, +-0xc17fff, +-0xca1000, +-0xca1400, +-0xca1800, +-0xd4801d, +-0xd4c01d, +-0x7db18b, +-0xc14202, +-0xc2c001, +-0xd5801d, +-0x34dc0e, +-0x7d5d4c, +-0x7f734c, +-0xd7401e, +-0xd5001e, +-0xd5401e, +-0xc14200, +-0xc2c000, +-0x099c01, +-0x31dc10, +-0x7f5f4c, +-0x7f734c, +-0x042802, +-0x7d8380, +-0xd5a86f, +-0xd58066, +-0xd7401e, +-0xec005e, +-0xc82402, +-0xc82402, +-0x8001b8, +-0xd60076, +-0xd4401e, +-0xd4801e, +-0xd4c01e, +-0x800000, +-0xee001e, +-0x800000, +-0xee001f, +-0xd4001f, +-0x800000, +-0xd4001f, +-0xd4001f, +-0x880000, +-0xd4001f, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x010171, +-0x020178, +-0x03008f, +-0x04007f, +-0x050003, +-0x06003f, +-0x070032, +-0x08012c, +-0x090046, +-0x0a0036, +-0x1001b6, +-0x1700a2, +-0x22013a, +-0x230149, +-0x2000b4, +-0x240125, +-0x27004d, +-0x28006a, +-0x2a0060, +-0x2b0052, +-0x2f0065, +-0x320087, +-0x34017f, +-0x3c0156, +-0x3f0072, +-0x41018c, +-0x44012e, +-0x550173, +-0x56017a, +-0x60000b, +-0x610034, +-0x620038, +-0x630038, +-0x640038, +-0x650038, +-0x660038, +-0x670038, +-0x68003a, +-0x690041, +-0x6a0048, +-0x6b0048, +-0x6c0048, +-0x6d0048, +-0x6e0048, +-0x6f0048, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-}; +- +-static const u32 RV620_cp_microcode[][3] = { +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x0000ffff, 0x00284621, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00000000, 0x00e00000, 0x000 }, +- { 0x00010000, 0xc0294620, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x00000000, 0x00600000, 0x631 }, +- { 0x00000000, 0x00600000, 0x645 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000f00, 0x00281622, 0x000 }, +- { 0x00000008, 0x00211625, 0x000 }, +- { 0x00000018, 0x00203625, 0x000 }, +- { 0x8d000000, 0x00204411, 0x000 }, +- { 0x00000004, 0x002f0225, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x018 }, +- { 0x00412000, 0x00404811, 0x019 }, +- { 0x00422000, 0x00204811, 0x000 }, +- { 0x8e000000, 0x00204411, 0x000 }, +- { 0x00000028, 0x00204a2d, 0x000 }, +- { 0x90000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x0000000c, 0x00211622, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000019, 0x00211a22, 0x000 }, +- { 0x00000004, 0x00281a26, 0x000 }, +- { 0x00000000, 0x002914c5, 0x000 }, +- { 0x00000019, 0x00203625, 0x000 }, +- { 0x00000000, 0x003a1402, 0x000 }, +- { 0x00000016, 0x00211625, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0xfffffffc, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002914a3, 0x000 }, +- { 0x00000017, 0x00203625, 0x000 }, +- { 0x00008000, 0x00280e22, 0x000 }, +- { 0x00000007, 0x00220e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x20000000, 0x00280e22, 0x000 }, +- { 0x00000006, 0x00210e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x00000000, 0x00220222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x038 }, +- { 0x00000000, 0x2ee00000, 0x035 }, +- { 0x00000000, 0x2ce00000, 0x037 }, +- { 0x00000000, 0x00400e2d, 0x039 }, +- { 0x00000008, 0x00200e2d, 0x000 }, +- { 0x00000009, 0x0040122d, 0x046 }, +- { 0x00000001, 0x00400e2d, 0x039 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x03e }, +- { 0x00000008, 0x00401c11, 0x041 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x0000000f, 0x00281e27, 0x000 }, +- { 0x00000003, 0x00221e27, 0x000 }, +- { 0x7fc00000, 0x00281a23, 0x000 }, +- { 0x00000014, 0x00211a26, 0x000 }, +- { 0x00000001, 0x00331a26, 0x000 }, +- { 0x00000008, 0x00221a26, 0x000 }, +- { 0x00000000, 0x00290cc7, 0x000 }, +- { 0x00000027, 0x00203624, 0x000 }, +- { 0x00007f00, 0x00281221, 0x000 }, +- { 0x00001400, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04b }, +- { 0x00000001, 0x00290e23, 0x000 }, +- { 0x0000000e, 0x00203623, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfff80000, 0x00294a23, 0x000 }, +- { 0x00000000, 0x003a2c02, 0x000 }, +- { 0x00000002, 0x00220e2b, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x0000000f, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00204a2d, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000029, 0x00200e2d, 0x000 }, +- { 0x060a0200, 0x00294a23, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x061 }, +- { 0x00000000, 0x2ee00000, 0x05f }, +- { 0x00000000, 0x2ce00000, 0x05e }, +- { 0x00000000, 0x00400e2d, 0x062 }, +- { 0x00000001, 0x00400e2d, 0x062 }, +- { 0x0000000a, 0x00200e2d, 0x000 }, +- { 0x0000000b, 0x0040122d, 0x06a }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x7fc00000, 0x00281623, 0x000 }, +- { 0x00000014, 0x00211625, 0x000 }, +- { 0x00000001, 0x00331625, 0x000 }, +- { 0x80000000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00290ca3, 0x000 }, +- { 0x3ffffc00, 0x00290e23, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x06d }, +- { 0x00000100, 0x00401c11, 0x070 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x000000f0, 0x00281e27, 0x000 }, +- { 0x00000004, 0x00221e27, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0xfffff0ff, 0x00281a30, 0x000 }, +- { 0x0000a028, 0x00204411, 0x000 }, +- { 0x00000000, 0x002948e6, 0x000 }, +- { 0x0000a018, 0x00204411, 0x000 }, +- { 0x3fffffff, 0x00284a23, 0x000 }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000030, 0x0020162d, 0x000 }, +- { 0x00000002, 0x00291625, 0x000 }, +- { 0x00000030, 0x00203625, 0x000 }, +- { 0x00000025, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a3, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x083 }, +- { 0x00000026, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a4, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x084 }, +- { 0x00000000, 0x00400000, 0x08a }, +- { 0x00000025, 0x00203623, 0x000 }, +- { 0x00000026, 0x00203624, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x08a }, +- { 0x00000000, 0x00600000, 0x668 }, +- { 0x00000000, 0x00600000, 0x65c }, +- { 0x00000002, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x08d }, +- { 0x00000012, 0xc0403620, 0x093 }, +- { 0x00000000, 0x2ee00000, 0x091 }, +- { 0x00000000, 0x2ce00000, 0x090 }, +- { 0x00000002, 0x00400e2d, 0x092 }, +- { 0x00000003, 0x00400e2d, 0x092 }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000012, 0x00203623, 0x000 }, +- { 0x00000003, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x098 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x0a0 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x2ee00000, 0x09e }, +- { 0x00000000, 0x2ce00000, 0x09d }, +- { 0x00000002, 0x00400e2d, 0x09f }, +- { 0x00000003, 0x00400e2d, 0x09f }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x003f0000, 0x00280e23, 0x000 }, +- { 0x00000010, 0x00210e23, 0x000 }, +- { 0x00000011, 0x00203623, 0x000 }, +- { 0x0000001e, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0a7 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x0000001f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0aa }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000008, 0x00210e2b, 0x000 }, +- { 0x0000007f, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0e1 }, +- { 0x00000000, 0x27000000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0b3 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000000c, 0x00221e30, 0x000 }, +- { 0x99800000, 0x00204411, 0x000 }, +- { 0x00000004, 0x0020122d, 0x000 }, +- { 0x00000008, 0x00221224, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00291ce4, 0x000 }, +- { 0x00000000, 0x00604807, 0x12f }, +- { 0x9b000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x9c000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x0033146f, 0x000 }, +- { 0x00000001, 0x00333e23, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0x00203c05, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e007, 0x00204411, 0x000 }, +- { 0x0000000f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0cb }, +- { 0x00f8ff08, 0x00204811, 0x000 }, +- { 0x98000000, 0x00404811, 0x0dc }, +- { 0x000000f0, 0x00280e22, 0x000 }, +- { 0x000000a0, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x0da }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d5 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d4 }, +- { 0x00003f00, 0x00400c11, 0x0d6 }, +- { 0x00001f00, 0x00400c11, 0x0d6 }, +- { 0x00000f00, 0x00200c11, 0x000 }, +- { 0x00380009, 0x00294a23, 0x000 }, +- { 0x3f000000, 0x00280e2b, 0x000 }, +- { 0x00000002, 0x00220e23, 0x000 }, +- { 0x00000007, 0x00494a23, 0x0dc }, +- { 0x00380f09, 0x00204811, 0x000 }, +- { 0x68000007, 0x00204811, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000a202, 0x00204411, 0x000 }, +- { 0x00ff0000, 0x00280e22, 0x000 }, +- { 0x00000080, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00200e2d, 0x000 }, +- { 0x00000026, 0x0020122d, 0x000 }, +- { 0x00000000, 0x002f0083, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0ea }, +- { 0x00000000, 0x00600000, 0x662 }, +- { 0x00000000, 0x00400000, 0x0eb }, +- { 0x00000000, 0x00600000, 0x665 }, +- { 0x00000007, 0x0020222d, 0x000 }, +- { 0x00000005, 0x00220e22, 0x000 }, +- { 0x00100000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x000000ef, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000003, 0x00210223, 0x000 }, +- { 0x00000000, 0x14e00000, 0x0f8 }, +- { 0x0000000b, 0x00210228, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0f8 }, +- { 0x00000400, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000001c, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0fd }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000001e, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x10b }, +- { 0x0000a30f, 0x00204411, 0x000 }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x104 }, +- { 0xffffffff, 0x00404811, 0x10b }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x107 }, +- { 0x0000ffff, 0x00404811, 0x10b }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x10a }, +- { 0x000000ff, 0x00404811, 0x10b }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0002c400, 0x00204411, 0x000 }, +- { 0x0000001f, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x112 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000018, 0x40224a20, 0x000 }, +- { 0x00000010, 0xc0424a20, 0x114 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000000a, 0x00201011, 0x000 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x11b }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00531224, 0x117 }, +- { 0xffbfffff, 0x00283a2e, 0x000 }, +- { 0x0000001b, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x12e }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0x00000018, 0x00220e30, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e00e, 0x00204411, 0x000 }, +- { 0x07f8ff08, 0x00204811, 0x000 }, +- { 0x00000000, 0x00294a23, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x00800000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204806, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68d }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x68c }, +- { 0x00000004, 0x00404c11, 0x135 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x000021f8, 0x00204411, 0x000 }, +- { 0x0000001c, 0x00204811, 0x000 }, +- { 0x000421f9, 0x00604411, 0x68d }, +- { 0x00000011, 0x00210230, 0x000 }, +- { 0x00000000, 0x14e00000, 0x13c }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40280620, 0x000 }, +- { 0x00000010, 0xc0210a20, 0x000 }, +- { 0x00000000, 0x00341461, 0x000 }, +- { 0x00000000, 0x00741882, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x147 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0681a20, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x158 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000001, 0x00300a2f, 0x000 }, +- { 0x00000001, 0x00210a22, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600000, 0x18f }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00202c08, 0x000 }, +- { 0x00000000, 0x00202411, 0x000 }, +- { 0x00000000, 0x00202811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00221e29, 0x000 }, +- { 0x00000000, 0x007048eb, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000001, 0x40330620, 0x000 }, +- { 0x00000000, 0xc0302409, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x181 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x186 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x186 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000001, 0x00530621, 0x182 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0604800, 0x197 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000011, 0x0020062d, 0x000 }, +- { 0x00000000, 0x0078042a, 0x2fb }, +- { 0x00000000, 0x00202809, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x174 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x194 }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x46000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x19b }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00804811, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40281620, 0x000 }, +- { 0x00000010, 0xc0811a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000008, 0x00221e30, 0x000 }, +- { 0x00000029, 0x00201a2d, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfffbff09, 0x00204811, 0x000 }, +- { 0x0000000f, 0x0020222d, 0x000 }, +- { 0x00001fff, 0x00294a28, 0x000 }, +- { 0x00000006, 0x0020222d, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000100, 0x00201811, 0x000 }, +- { 0x00000008, 0x00621e28, 0x12f }, +- { 0x00000008, 0x00822228, 0x000 }, +- { 0x0002c000, 0x00204411, 0x000 }, +- { 0x00000015, 0x00600e2d, 0x1bd }, +- { 0x00000016, 0x00600e2d, 0x1bd }, +- { 0x0000c008, 0x00204411, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1b9 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x39000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00804802, 0x000 }, +- { 0x00000018, 0x00202e2d, 0x000 }, +- { 0x00000000, 0x003b0d63, 0x000 }, +- { 0x00000008, 0x00224a23, 0x000 }, +- { 0x00000010, 0x00224a23, 0x000 }, +- { 0x00000018, 0x00224a23, 0x000 }, +- { 0x00000000, 0x00804803, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000007, 0x0021062f, 0x000 }, +- { 0x00000013, 0x00200a2d, 0x000 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000ffff, 0x40282220, 0x000 }, +- { 0x0000000f, 0x00262228, 0x000 }, +- { 0x00000010, 0x40212620, 0x000 }, +- { 0x0000000f, 0x00262629, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1e0 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000081, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000080, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1dc }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1d8 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000001f, 0x00280a22, 0x000 }, +- { 0x0000001f, 0x00282a2a, 0x000 }, +- { 0x00000001, 0x00530621, 0x1d1 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000002, 0x00304a2f, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000001, 0x00301e2f, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1e5 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x0000000f, 0x00260e23, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000000f, 0x00261224, 0x000 }, +- { 0x00000000, 0x00201411, 0x000 }, +- { 0x00000000, 0x00601811, 0x2bb }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022b, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1f8 }, +- { 0x00000010, 0x00221628, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a29, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x0020480a, 0x000 }, +- { 0x00000000, 0x00202c11, 0x000 }, +- { 0x00000010, 0x00221623, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a24, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x00731503, 0x205 }, +- { 0x00000000, 0x00201805, 0x000 }, +- { 0x00000000, 0x00731524, 0x205 }, +- { 0x00000000, 0x002d14c5, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00000000, 0x00202003, 0x000 }, +- { 0x00000000, 0x00802404, 0x000 }, +- { 0x0000000f, 0x00210225, 0x000 }, +- { 0x00000000, 0x14c00000, 0x68c }, +- { 0x00000000, 0x002b1405, 0x000 }, +- { 0x00000001, 0x00901625, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00294a22, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a21, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000ffff, 0x40281220, 0x000 }, +- { 0x00000010, 0xc0211a20, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211620, 0x000 }, +- { 0x00000000, 0x00741465, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00000001, 0x00330621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x219 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x212 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x645 }, +- { 0x00000000, 0x0040040f, 0x213 }, +- { 0x00000000, 0x00600000, 0x631 }, +- { 0x00000000, 0x00600000, 0x645 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00000000, 0x00600000, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x232 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x236 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x236 }, +- { 0x00000000, 0xc0404800, 0x233 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x00600411, 0x2fb }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x631 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000018, 0x40210a20, 0x000 }, +- { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x24c }, +- { 0x00000014, 0x0020222d, 0x000 }, +- { 0x00080101, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x251 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000010, 0x00600411, 0x315 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00000000, 0x00600000, 0x27c }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000001, 0x00211e27, 0x000 }, +- { 0x00000000, 0x14e00000, 0x26a }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x0000ffff, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00341c27, 0x000 }, +- { 0x00000000, 0x12c00000, 0x25f }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e5, 0x000 }, +- { 0x00000000, 0x08c00000, 0x262 }, +- { 0x00000000, 0x00201407, 0x000 }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00211e27, 0x000 }, +- { 0x00000000, 0x00341c47, 0x000 }, +- { 0x00000000, 0x12c00000, 0x267 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e6, 0x000 }, +- { 0x00000000, 0x08c00000, 0x26a }, +- { 0x00000000, 0x00201807, 0x000 }, +- { 0x00000000, 0x00600000, 0x2c1 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000000, 0x00342023, 0x000 }, +- { 0x00000000, 0x12c00000, 0x272 }, +- { 0x00000000, 0x00342044, 0x000 }, +- { 0x00000000, 0x12c00000, 0x271 }, +- { 0x00000016, 0x00404811, 0x276 }, +- { 0x00000018, 0x00404811, 0x276 }, +- { 0x00000000, 0x00342044, 0x000 }, +- { 0x00000000, 0x12c00000, 0x275 }, +- { 0x00000017, 0x00404811, 0x276 }, +- { 0x00000019, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00604411, 0x2e9 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x256 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000010, 0x40210620, 0x000 }, +- { 0x0000ffff, 0xc0280a20, 0x000 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0881a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x00000000, 0x00600000, 0x631 }, +- { 0x00000000, 0xc0600000, 0x2a3 }, +- { 0x00000005, 0x00200a2d, 0x000 }, +- { 0x00000008, 0x00220a22, 0x000 }, +- { 0x0000002b, 0x00201a2d, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00007000, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00311ce6, 0x000 }, +- { 0x0000002a, 0x00201a2d, 0x000 }, +- { 0x0000000c, 0x00221a26, 0x000 }, +- { 0x00000000, 0x002f00e6, 0x000 }, +- { 0x00000000, 0x06e00000, 0x292 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x0000002b, 0x00203623, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00691ce2, 0x12f }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x29d }, +- { 0x00000001, 0x00333e2f, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000001c, 0x00403627, 0x000 }, +- { 0x0000000c, 0xc0220a20, 0x000 }, +- { 0x00000029, 0x00203622, 0x000 }, +- { 0x00000028, 0xc0403620, 0x000 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000009, 0x00204811, 0x000 }, +- { 0xa1000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002c1ce3, 0x000 }, +- { 0x00000021, 0x00203627, 0x000 }, +- { 0x00000022, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002c1ce4, 0x000 }, +- { 0x00000022, 0x00203627, 0x000 }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120a3, 0x000 }, +- { 0x00000000, 0x002d1d07, 0x000 }, +- { 0x00000023, 0x00203627, 0x000 }, +- { 0x00000024, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x00000000, 0x002d1d07, 0x000 }, +- { 0x00000024, 0x00803627, 0x000 }, +- { 0x00000021, 0x00203623, 0x000 }, +- { 0x00000022, 0x00203624, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000023, 0x00203627, 0x000 }, +- { 0x00000000, 0x00311cc4, 0x000 }, +- { 0x00000024, 0x00803627, 0x000 }, +- { 0x0000001a, 0x00203627, 0x000 }, +- { 0x0000001b, 0x00203628, 0x000 }, +- { 0x00000017, 0x00201e2d, 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0x00007e00, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x5e3 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a092, 0x00604411, 0x68d }, +- { 0x00000031, 0x00203630, 0x000 }, +- { 0x0004a093, 0x00604411, 0x68d }, +- { 0x00000032, 0x00203630, 0x000 }, +- { 0x0004a2b6, 0x00604411, 0x68d }, +- { 0x00000033, 0x00203630, 0x000 }, +- { 0x0004a2ba, 0x00604411, 0x68d }, +- { 0x00000034, 0x00203630, 0x000 }, +- { 0x0004a2be, 0x00604411, 0x68d }, +- { 0x00000035, 0x00203630, 0x000 }, +- { 0x0004a2c2, 0x00604411, 0x68d }, +- { 0x00000036, 0x00203630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x00000005, 0x00204811, 0x000 }, +- { 0x0000a1f4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x88000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000001, 0x002f0230, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62c }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62c }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00007e00, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x605 }, +- { 0x0000a092, 0x00204411, 0x000 }, +- { 0x00000031, 0x00204a2d, 0x000 }, +- { 0x0000a093, 0x00204411, 0x000 }, +- { 0x00000032, 0x00204a2d, 0x000 }, +- { 0x0000a2b6, 0x00204411, 0x000 }, +- { 0x00000033, 0x00204a2d, 0x000 }, +- { 0x0000a2ba, 0x00204411, 0x000 }, +- { 0x00000034, 0x00204a2d, 0x000 }, +- { 0x0000a2be, 0x00204411, 0x000 }, +- { 0x00000035, 0x00204a2d, 0x000 }, +- { 0x0000a2c2, 0x00204411, 0x000 }, +- { 0x00000036, 0x00204a2d, 0x000 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x000001ff, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62b }, +- { 0x00000000, 0x00210221, 0x000 }, +- { 0x00000000, 0x14c00000, 0x60e }, +- { 0x0004a003, 0x00604411, 0x68d }, +- { 0x0000a003, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000001, 0x00210621, 0x000 }, +- { 0x00000000, 0x14c00000, 0x613 }, +- { 0x0004a010, 0x00604411, 0x68d }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000001, 0x00210621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62b }, +- { 0x0004a011, 0x00604411, 0x68d }, +- { 0x0000a011, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a012, 0x00604411, 0x68d }, +- { 0x0000a012, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a013, 0x00604411, 0x68d }, +- { 0x0000a013, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a014, 0x00604411, 0x68d }, +- { 0x0000a014, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a015, 0x00604411, 0x68d }, +- { 0x0000a015, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a016, 0x00604411, 0x68d }, +- { 0x0000a016, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a017, 0x00604411, 0x68d }, +- { 0x0000a017, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x0000002c, 0x0080062d, 0x000 }, +- { 0xff000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000002, 0x00804811, 0x000 }, +- { 0x00000000, 0x0ee00000, 0x63d }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00000002, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x63b }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68d }, +- { 0x00001000, 0x00200811, 0x000 }, +- { 0x0000002b, 0x00203622, 0x000 }, +- { 0x00000000, 0x00600000, 0x641 }, +- { 0x00000000, 0x00600000, 0x5c9 }, +- { 0x98000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00804811, 0x000 }, +- { 0x00000000, 0xc0600000, 0x641 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000022, 0x00204811, 0x000 }, +- { 0x89000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00404811, 0x62d }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404811, 0x62d }, +- { 0x00000000, 0x00600000, 0x65c }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0xc0204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36e }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x09800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68d }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x00000004, 0x00404c11, 0x656 }, +- { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000004, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffffb, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffff7, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36e }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x01800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68d }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x68c }, +- { 0x00000010, 0x00404c11, 0x672 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x38c00000, 0x000 }, +- { 0x0000001d, 0x00200a2d, 0x000 }, +- { 0x0000001e, 0x00200e2d, 0x000 }, +- { 0x0000001f, 0x0020122d, 0x000 }, +- { 0x00000020, 0x0020162d, 0x000 }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000004, 0x00301224, 0x000 }, +- { 0x00000000, 0x002f0064, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x68b }, +- { 0x00000003, 0x00281a22, 0x000 }, +- { 0x00000008, 0x00221222, 0x000 }, +- { 0xfffff000, 0x00281224, 0x000 }, +- { 0x00000000, 0x002910c4, 0x000 }, +- { 0x0000001f, 0x00403624, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x68d }, +- { 0x9f000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x690 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x692 }, +- { 0x9e000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x695 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0xc0204411, 0x000 }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000024, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000022, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00404811, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x01420502, 0x05c00250, 0x000 }, +- { 0x01c30168, 0x043f05c0, 0x000 }, +- { 0x02250209, 0x02500151, 0x000 }, +- { 0x02230245, 0x02a00241, 0x000 }, +- { 0x03d705c0, 0x05c005c0, 0x000 }, +- { 0x0649064a, 0x031f05c0, 0x000 }, +- { 0x05c005c5, 0x03200340, 0x000 }, +- { 0x032a0282, 0x03420334, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c00551, 0x05c005c0, 0x000 }, +- { 0x03ba05c0, 0x04bb0344, 0x000 }, +- { 0x049a0450, 0x043d05c0, 0x000 }, +- { 0x04d005c0, 0x044104dd, 0x000 }, +- { 0x04500507, 0x03510375, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c005c0, 0x063f05c7, 0x000 }, +- { 0x05c005c0, 0x000705c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x03f803ed, 0x04080406, 0x000 }, +- { 0x040e040a, 0x040c0410, 0x000 }, +- { 0x041c0418, 0x04240420, 0x000 }, +- { 0x042c0428, 0x04340430, 0x000 }, +- { 0x05c005c0, 0x043805c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x05c005c0, 0x05c005c0, 0x000 }, +- { 0x00020679, 0x06970006, 0x000 }, +-}; +- +-static const u32 RV620_pfp_microcode[] = { +-0xca0400, +-0xa00000, +-0x7e828b, +-0x7c038b, +-0x8001b8, +-0x7c038b, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xc41838, +-0xca2400, +-0xca2800, +-0x9581a8, +-0xc41c3a, +-0xc3c000, +-0xca0800, +-0xca0c00, +-0x7c744b, +-0xc20005, +-0x99c000, +-0xc41c3a, +-0x7c744c, +-0xc0fff0, +-0x042c04, +-0x309002, +-0x7d2500, +-0x351402, +-0x7d350b, +-0x255403, +-0x7cd580, +-0x259c03, +-0x95c004, +-0xd5001b, +-0x7eddc1, +-0x7d9d80, +-0xd6801b, +-0xd5801b, +-0xd4401e, +-0xd5401e, +-0xd6401e, +-0xd6801e, +-0xd4801e, +-0xd4c01e, +-0x9783d3, +-0xd5c01e, +-0xca0800, +-0x80001a, +-0xca0c00, +-0xe4011e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xe4013e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca1800, +-0xd4401e, +-0xd5801e, +-0x800053, +-0xd40075, +-0xd4401e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd48019, +-0xd4c018, +-0xd50017, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xe2001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0xd48060, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xd48061, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xca0c00, +-0xd4401e, +-0xd48016, +-0xd4c016, +-0xd4801e, +-0x8001b8, +-0xd4c01e, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x948004, +-0xca1400, +-0xe420f3, +-0xd42013, +-0xd56065, +-0xd4e01c, +-0xd5201c, +-0xd5601c, +-0x800000, +-0x062001, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9483f7, +-0xca1400, +-0xe420f3, +-0x800079, +-0xd42013, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9883ef, +-0xca1400, +-0xd40064, +-0x80008d, +-0x000000, +-0xc41432, +-0xc61843, +-0xc4082f, +-0x954005, +-0xc40c30, +-0xd4401e, +-0x800000, +-0xee001e, +-0x9583f5, +-0xc41031, +-0xd44033, +-0xd52065, +-0xd4a01c, +-0xd4e01c, +-0xd5201c, +-0xe4015e, +-0xd4001e, +-0x800000, +-0x062001, +-0xca1800, +-0x0a2001, +-0xd60076, +-0xc40836, +-0x988007, +-0xc61045, +-0x950110, +-0xd4001f, +-0xd46062, +-0x800000, +-0xd42062, +-0xcc3835, +-0xcc1433, +-0x8401bb, +-0xd40072, +-0xd5401e, +-0x800000, +-0xee001e, +-0xe2001a, +-0x8401bb, +-0xe2001a, +-0xcc104b, +-0xcc0447, +-0x2c9401, +-0x7d098b, +-0x984005, +-0x7d15cb, +-0xd4001a, +-0x8001b8, +-0xd4006d, +-0x344401, +-0xcc0c48, +-0x98403a, +-0xcc2c4a, +-0x958004, +-0xcc0449, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0x282801, +-0x8400f0, +-0xcc1003, +-0x98801b, +-0x04380c, +-0x8400f0, +-0xcc1003, +-0x988017, +-0x043808, +-0x8400f0, +-0xcc1003, +-0x988013, +-0x043804, +-0x8400f0, +-0xcc1003, +-0x988014, +-0xcc104c, +-0x9a8009, +-0xcc144d, +-0x9840dc, +-0xd4006d, +-0xcc1848, +-0xd5001a, +-0xd5401a, +-0x8000c9, +-0xd5801a, +-0x96c0d5, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0x9ac003, +-0xd4006d, +-0xd4006e, +-0x800000, +-0xec007f, +-0x9ac0cc, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0x7d9103, +-0x7dd583, +-0x7d190c, +-0x35cc1f, +-0x35701f, +-0x7cf0cb, +-0x7cd08b, +-0x880000, +-0x7e8e8b, +-0x95c004, +-0xd4006e, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0xcc0803, +-0xcc0c03, +-0xcc1003, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0xcc2403, +-0xcc2803, +-0x35c41f, +-0x36b01f, +-0x7c704b, +-0x34f01f, +-0x7c704b, +-0x35701f, +-0x7c704b, +-0x7d8881, +-0x7dccc1, +-0x7e5101, +-0x7e9541, +-0x7c9082, +-0x7cd4c2, +-0x7c848b, +-0x9ac003, +-0x7c8c8b, +-0x2c8801, +-0x98809e, +-0xd4006d, +-0x98409c, +-0xd4006e, +-0xcc084c, +-0xcc0c4d, +-0xcc1048, +-0xd4801a, +-0xd4c01a, +-0x800101, +-0xd5001a, +-0xcc0832, +-0xd40032, +-0x9482d9, +-0xca0c00, +-0xd4401e, +-0x800000, +-0xd4001e, +-0xe4011e, +-0xd4001e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd4401e, +-0xca1400, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xd5401e, +-0xd54034, +-0x800000, +-0xee001e, +-0x280404, +-0xe2001a, +-0xe2001a, +-0xd4401a, +-0xca3800, +-0xcc0803, +-0xcc0c03, +-0xcc0c03, +-0xcc0c03, +-0x9882bd, +-0x000000, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0400, +-0xc2ff00, +-0xcc0834, +-0xc13fff, +-0x7c74cb, +-0x7cc90b, +-0x7d010f, +-0x9902b0, +-0x7c738b, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0800, +-0x281900, +-0x7d898b, +-0x958014, +-0x281404, +-0xca0c00, +-0xca1000, +-0xca1c00, +-0xca2400, +-0xe2001f, +-0xd4c01a, +-0xd5001a, +-0xd5401a, +-0xcc1803, +-0xcc2c03, +-0xcc2c03, +-0xcc2c03, +-0x7da58b, +-0x7d9c47, +-0x984297, +-0x000000, +-0x800161, +-0xd4c01a, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0x248c06, +-0x0ccc06, +-0x98c006, +-0xcc104e, +-0x990004, +-0xd40073, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xca0800, +-0xca0c00, +-0x34d018, +-0x251001, +-0x950021, +-0xc17fff, +-0xca1000, +-0xca1400, +-0xca1800, +-0xd4801d, +-0xd4c01d, +-0x7db18b, +-0xc14202, +-0xc2c001, +-0xd5801d, +-0x34dc0e, +-0x7d5d4c, +-0x7f734c, +-0xd7401e, +-0xd5001e, +-0xd5401e, +-0xc14200, +-0xc2c000, +-0x099c01, +-0x31dc10, +-0x7f5f4c, +-0x7f734c, +-0x042802, +-0x7d8380, +-0xd5a86f, +-0xd58066, +-0xd7401e, +-0xec005e, +-0xc82402, +-0xc82402, +-0x8001b8, +-0xd60076, +-0xd4401e, +-0xd4801e, +-0xd4c01e, +-0x800000, +-0xee001e, +-0x800000, +-0xee001f, +-0xd4001f, +-0x800000, +-0xd4001f, +-0xd4001f, +-0x880000, +-0xd4001f, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x010171, +-0x020178, +-0x03008f, +-0x04007f, +-0x050003, +-0x06003f, +-0x070032, +-0x08012c, +-0x090046, +-0x0a0036, +-0x1001b6, +-0x1700a2, +-0x22013a, +-0x230149, +-0x2000b4, +-0x240125, +-0x27004d, +-0x28006a, +-0x2a0060, +-0x2b0052, +-0x2f0065, +-0x320087, +-0x34017f, +-0x3c0156, +-0x3f0072, +-0x41018c, +-0x44012e, +-0x550173, +-0x56017a, +-0x60000b, +-0x610034, +-0x620038, +-0x630038, +-0x640038, +-0x650038, +-0x660038, +-0x670038, +-0x68003a, +-0x690041, +-0x6a0048, +-0x6b0048, +-0x6c0048, +-0x6d0048, +-0x6e0048, +-0x6f0048, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-}; +- +-static const u32 RV630_cp_microcode[][3] = { +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x0000ffff, 0x00284621, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00000000, 0x00e00000, 0x000 }, +- { 0x00010000, 0xc0294620, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x00000000, 0x00600000, 0x62e }, +- { 0x00000000, 0x00600000, 0x642 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000f00, 0x00281622, 0x000 }, +- { 0x00000008, 0x00211625, 0x000 }, +- { 0x00000018, 0x00203625, 0x000 }, +- { 0x8d000000, 0x00204411, 0x000 }, +- { 0x00000004, 0x002f0225, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x018 }, +- { 0x00412000, 0x00404811, 0x019 }, +- { 0x00422000, 0x00204811, 0x000 }, +- { 0x8e000000, 0x00204411, 0x000 }, +- { 0x00000028, 0x00204a2d, 0x000 }, +- { 0x90000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x0000000c, 0x00211622, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000019, 0x00211a22, 0x000 }, +- { 0x00000004, 0x00281a26, 0x000 }, +- { 0x00000000, 0x002914c5, 0x000 }, +- { 0x00000019, 0x00203625, 0x000 }, +- { 0x00000000, 0x003a1402, 0x000 }, +- { 0x00000016, 0x00211625, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0xfffffffc, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002914a3, 0x000 }, +- { 0x00000017, 0x00203625, 0x000 }, +- { 0x00008000, 0x00280e22, 0x000 }, +- { 0x00000007, 0x00220e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x20000000, 0x00280e22, 0x000 }, +- { 0x00000006, 0x00210e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x00000000, 0x00220222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x038 }, +- { 0x00000000, 0x2ee00000, 0x035 }, +- { 0x00000000, 0x2ce00000, 0x037 }, +- { 0x00000000, 0x00400e2d, 0x039 }, +- { 0x00000008, 0x00200e2d, 0x000 }, +- { 0x00000009, 0x0040122d, 0x046 }, +- { 0x00000001, 0x00400e2d, 0x039 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x03e }, +- { 0x00000008, 0x00401c11, 0x041 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x0000000f, 0x00281e27, 0x000 }, +- { 0x00000003, 0x00221e27, 0x000 }, +- { 0x7fc00000, 0x00281a23, 0x000 }, +- { 0x00000014, 0x00211a26, 0x000 }, +- { 0x00000001, 0x00331a26, 0x000 }, +- { 0x00000008, 0x00221a26, 0x000 }, +- { 0x00000000, 0x00290cc7, 0x000 }, +- { 0x00000027, 0x00203624, 0x000 }, +- { 0x00007f00, 0x00281221, 0x000 }, +- { 0x00001400, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04b }, +- { 0x00000001, 0x00290e23, 0x000 }, +- { 0x0000000e, 0x00203623, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfff80000, 0x00294a23, 0x000 }, +- { 0x00000000, 0x003a2c02, 0x000 }, +- { 0x00000002, 0x00220e2b, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x0000000f, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00204a2d, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000029, 0x00200e2d, 0x000 }, +- { 0x060a0200, 0x00294a23, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x061 }, +- { 0x00000000, 0x2ee00000, 0x05f }, +- { 0x00000000, 0x2ce00000, 0x05e }, +- { 0x00000000, 0x00400e2d, 0x062 }, +- { 0x00000001, 0x00400e2d, 0x062 }, +- { 0x0000000a, 0x00200e2d, 0x000 }, +- { 0x0000000b, 0x0040122d, 0x06a }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x7fc00000, 0x00281623, 0x000 }, +- { 0x00000014, 0x00211625, 0x000 }, +- { 0x00000001, 0x00331625, 0x000 }, +- { 0x80000000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00290ca3, 0x000 }, +- { 0x3ffffc00, 0x00290e23, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x06d }, +- { 0x00000100, 0x00401c11, 0x070 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x000000f0, 0x00281e27, 0x000 }, +- { 0x00000004, 0x00221e27, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0xfffff0ff, 0x00281a30, 0x000 }, +- { 0x0000a028, 0x00204411, 0x000 }, +- { 0x00000000, 0x002948e6, 0x000 }, +- { 0x0000a018, 0x00204411, 0x000 }, +- { 0x3fffffff, 0x00284a23, 0x000 }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000030, 0x0020162d, 0x000 }, +- { 0x00000002, 0x00291625, 0x000 }, +- { 0x00000030, 0x00203625, 0x000 }, +- { 0x00000025, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a3, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x083 }, +- { 0x00000026, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a4, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x084 }, +- { 0x00000000, 0x00400000, 0x08a }, +- { 0x00000025, 0x00203623, 0x000 }, +- { 0x00000026, 0x00203624, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x08a }, +- { 0x00000000, 0x00600000, 0x665 }, +- { 0x00000000, 0x00600000, 0x659 }, +- { 0x00000002, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x08d }, +- { 0x00000012, 0xc0403620, 0x093 }, +- { 0x00000000, 0x2ee00000, 0x091 }, +- { 0x00000000, 0x2ce00000, 0x090 }, +- { 0x00000002, 0x00400e2d, 0x092 }, +- { 0x00000003, 0x00400e2d, 0x092 }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000012, 0x00203623, 0x000 }, +- { 0x00000003, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x098 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x0a0 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x2ee00000, 0x09e }, +- { 0x00000000, 0x2ce00000, 0x09d }, +- { 0x00000002, 0x00400e2d, 0x09f }, +- { 0x00000003, 0x00400e2d, 0x09f }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x003f0000, 0x00280e23, 0x000 }, +- { 0x00000010, 0x00210e23, 0x000 }, +- { 0x00000011, 0x00203623, 0x000 }, +- { 0x0000001e, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0a7 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x0000001f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0aa }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000008, 0x00210e2b, 0x000 }, +- { 0x0000007f, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0e1 }, +- { 0x00000000, 0x27000000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0b3 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000000c, 0x00221e30, 0x000 }, +- { 0x99800000, 0x00204411, 0x000 }, +- { 0x00000004, 0x0020122d, 0x000 }, +- { 0x00000008, 0x00221224, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00291ce4, 0x000 }, +- { 0x00000000, 0x00604807, 0x12f }, +- { 0x9b000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x9c000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x0033146f, 0x000 }, +- { 0x00000001, 0x00333e23, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0x00203c05, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e007, 0x00204411, 0x000 }, +- { 0x0000000f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0cb }, +- { 0x00f8ff08, 0x00204811, 0x000 }, +- { 0x98000000, 0x00404811, 0x0dc }, +- { 0x000000f0, 0x00280e22, 0x000 }, +- { 0x000000a0, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x0da }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d5 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d4 }, +- { 0x00003f00, 0x00400c11, 0x0d6 }, +- { 0x00001f00, 0x00400c11, 0x0d6 }, +- { 0x00000f00, 0x00200c11, 0x000 }, +- { 0x00380009, 0x00294a23, 0x000 }, +- { 0x3f000000, 0x00280e2b, 0x000 }, +- { 0x00000002, 0x00220e23, 0x000 }, +- { 0x00000007, 0x00494a23, 0x0dc }, +- { 0x00380f09, 0x00204811, 0x000 }, +- { 0x68000007, 0x00204811, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000a202, 0x00204411, 0x000 }, +- { 0x00ff0000, 0x00280e22, 0x000 }, +- { 0x00000080, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00200e2d, 0x000 }, +- { 0x00000026, 0x0020122d, 0x000 }, +- { 0x00000000, 0x002f0083, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0ea }, +- { 0x00000000, 0x00600000, 0x65f }, +- { 0x00000000, 0x00400000, 0x0eb }, +- { 0x00000000, 0x00600000, 0x662 }, +- { 0x00000007, 0x0020222d, 0x000 }, +- { 0x00000005, 0x00220e22, 0x000 }, +- { 0x00100000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x000000ef, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000003, 0x00210223, 0x000 }, +- { 0x00000000, 0x14e00000, 0x0f8 }, +- { 0x0000000b, 0x00210228, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0f8 }, +- { 0x00000400, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000001c, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0fd }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000001e, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x10b }, +- { 0x0000a30f, 0x00204411, 0x000 }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x104 }, +- { 0xffffffff, 0x00404811, 0x10b }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x107 }, +- { 0x0000ffff, 0x00404811, 0x10b }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x10a }, +- { 0x000000ff, 0x00404811, 0x10b }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0002c400, 0x00204411, 0x000 }, +- { 0x0000001f, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x112 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000018, 0x40224a20, 0x000 }, +- { 0x00000010, 0xc0424a20, 0x114 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000000a, 0x00201011, 0x000 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x11b }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00531224, 0x117 }, +- { 0xffbfffff, 0x00283a2e, 0x000 }, +- { 0x0000001b, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x12e }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0x00000018, 0x00220e30, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e00e, 0x00204411, 0x000 }, +- { 0x07f8ff08, 0x00204811, 0x000 }, +- { 0x00000000, 0x00294a23, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x00800000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204806, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68a }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x689 }, +- { 0x00000004, 0x00404c11, 0x135 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x000021f8, 0x00204411, 0x000 }, +- { 0x0000001c, 0x00204811, 0x000 }, +- { 0x000421f9, 0x00604411, 0x68a }, +- { 0x00000011, 0x00210230, 0x000 }, +- { 0x00000000, 0x14e00000, 0x13c }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40280620, 0x000 }, +- { 0x00000010, 0xc0210a20, 0x000 }, +- { 0x00000000, 0x00341461, 0x000 }, +- { 0x00000000, 0x00741882, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x147 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0681a20, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x158 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000001, 0x00300a2f, 0x000 }, +- { 0x00000001, 0x00210a22, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600000, 0x18f }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00202c08, 0x000 }, +- { 0x00000000, 0x00202411, 0x000 }, +- { 0x00000000, 0x00202811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00221e29, 0x000 }, +- { 0x00000000, 0x007048eb, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000001, 0x40330620, 0x000 }, +- { 0x00000000, 0xc0302409, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x181 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x186 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x186 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000001, 0x00530621, 0x182 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0604800, 0x197 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000011, 0x0020062d, 0x000 }, +- { 0x00000000, 0x0078042a, 0x2fb }, +- { 0x00000000, 0x00202809, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x174 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x194 }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x46000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x19b }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00804811, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40281620, 0x000 }, +- { 0x00000010, 0xc0811a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000008, 0x00221e30, 0x000 }, +- { 0x00000029, 0x00201a2d, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfffbff09, 0x00204811, 0x000 }, +- { 0x0000000f, 0x0020222d, 0x000 }, +- { 0x00001fff, 0x00294a28, 0x000 }, +- { 0x00000006, 0x0020222d, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000100, 0x00201811, 0x000 }, +- { 0x00000008, 0x00621e28, 0x12f }, +- { 0x00000008, 0x00822228, 0x000 }, +- { 0x0002c000, 0x00204411, 0x000 }, +- { 0x00000015, 0x00600e2d, 0x1bd }, +- { 0x00000016, 0x00600e2d, 0x1bd }, +- { 0x0000c008, 0x00204411, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1b9 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x39000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00804802, 0x000 }, +- { 0x00000018, 0x00202e2d, 0x000 }, +- { 0x00000000, 0x003b0d63, 0x000 }, +- { 0x00000008, 0x00224a23, 0x000 }, +- { 0x00000010, 0x00224a23, 0x000 }, +- { 0x00000018, 0x00224a23, 0x000 }, +- { 0x00000000, 0x00804803, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000007, 0x0021062f, 0x000 }, +- { 0x00000013, 0x00200a2d, 0x000 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000ffff, 0x40282220, 0x000 }, +- { 0x0000000f, 0x00262228, 0x000 }, +- { 0x00000010, 0x40212620, 0x000 }, +- { 0x0000000f, 0x00262629, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1e0 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000081, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000080, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1dc }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1d8 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000001f, 0x00280a22, 0x000 }, +- { 0x0000001f, 0x00282a2a, 0x000 }, +- { 0x00000001, 0x00530621, 0x1d1 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000002, 0x00304a2f, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000001, 0x00301e2f, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1e5 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x0000000f, 0x00260e23, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000000f, 0x00261224, 0x000 }, +- { 0x00000000, 0x00201411, 0x000 }, +- { 0x00000000, 0x00601811, 0x2bb }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022b, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1f8 }, +- { 0x00000010, 0x00221628, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a29, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x0020480a, 0x000 }, +- { 0x00000000, 0x00202c11, 0x000 }, +- { 0x00000010, 0x00221623, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a24, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x00731503, 0x205 }, +- { 0x00000000, 0x00201805, 0x000 }, +- { 0x00000000, 0x00731524, 0x205 }, +- { 0x00000000, 0x002d14c5, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00000000, 0x00202003, 0x000 }, +- { 0x00000000, 0x00802404, 0x000 }, +- { 0x0000000f, 0x00210225, 0x000 }, +- { 0x00000000, 0x14c00000, 0x689 }, +- { 0x00000000, 0x002b1405, 0x000 }, +- { 0x00000001, 0x00901625, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00294a22, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a21, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000ffff, 0x40281220, 0x000 }, +- { 0x00000010, 0xc0211a20, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211620, 0x000 }, +- { 0x00000000, 0x00741465, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00000001, 0x00330621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x219 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x212 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x642 }, +- { 0x00000000, 0x0040040f, 0x213 }, +- { 0x00000000, 0x00600000, 0x62e }, +- { 0x00000000, 0x00600000, 0x642 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00000000, 0x00600000, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x232 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x236 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x236 }, +- { 0x00000000, 0xc0404800, 0x233 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x00600411, 0x2fb }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x62e }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000018, 0x40210a20, 0x000 }, +- { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x24c }, +- { 0x00000014, 0x0020222d, 0x000 }, +- { 0x00080101, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x251 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000010, 0x00600411, 0x315 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00000000, 0x00600000, 0x27c }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000001, 0x00211e27, 0x000 }, +- { 0x00000000, 0x14e00000, 0x26a }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x0000ffff, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00341c27, 0x000 }, +- { 0x00000000, 0x12c00000, 0x25f }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e5, 0x000 }, +- { 0x00000000, 0x08c00000, 0x262 }, +- { 0x00000000, 0x00201407, 0x000 }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00211e27, 0x000 }, +- { 0x00000000, 0x00341c47, 0x000 }, +- { 0x00000000, 0x12c00000, 0x267 }, +- { 0x00000000, 0x00201c11, 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0x00000000, 0x00600000, 0x5c6 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x58c }, +- { 0x0000a2b7, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2b6, 0x00604411, 0x68a }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x0000a2c4, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x58a }, +- { 0x0000a2d1, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d1, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x00000001, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x59d }, +- { 0x0000a2bb, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2ba, 0x00604411, 0x68a }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 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{ 0x00000000, 0x0ce00000, 0x638 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x00001000, 0x00200811, 0x000 }, +- { 0x0000002b, 0x00203622, 0x000 }, +- { 0x00000000, 0x00600000, 0x63e }, +- { 0x00000000, 0x00600000, 0x5c6 }, +- { 0x98000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00804811, 0x000 }, +- { 0x00000000, 0xc0600000, 0x63e }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000022, 0x00204811, 0x000 }, +- { 0x89000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00404811, 0x62a }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404811, 0x62a }, +- { 0x00000000, 0x00600000, 0x659 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0xc0204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36e }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x09800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68a }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x00000004, 0x00404c11, 0x653 }, +- { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000004, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffffb, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffff7, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 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0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x014204ff, 0x05bd0250, 0x000 }, +- { 0x01c30168, 0x043f05bd, 0x000 }, +- { 0x02250209, 0x02500151, 0x000 }, +- { 0x02230245, 0x02a00241, 0x000 }, +- { 0x03d705bd, 0x05bd05bd, 0x000 }, +- { 0x06460647, 0x031f05bd, 0x000 }, +- { 0x05bd05c2, 0x03200340, 0x000 }, +- { 0x032a0282, 0x03420334, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd054e, 0x05bd05bd, 0x000 }, +- { 0x03ba05bd, 0x04b80344, 0x000 }, +- { 0x0497044d, 0x043d05bd, 0x000 }, +- { 0x04cd05bd, 0x044104da, 0x000 }, +- { 0x044d0504, 0x03510375, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd05bd, 0x063c05c4, 0x000 }, +- { 0x05bd05bd, 0x000705bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x03f803ed, 0x04080406, 0x000 }, +- { 0x040e040a, 0x040c0410, 0x000 }, +- { 0x041c0418, 0x04240420, 0x000 }, +- { 0x042c0428, 0x04340430, 0x000 }, +- { 0x05bd05bd, 0x043805bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x00020676, 0x06940006, 0x000 }, +-}; +- +-static const u32 RV630_pfp_microcode[] = { +-0xca0400, +-0xa00000, +-0x7e828b, +-0x7c038b, +-0x8001b8, +-0x7c038b, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xc41838, +-0xca2400, +-0xca2800, +-0x9581a8, +-0xc41c3a, +-0xc3c000, +-0xca0800, +-0xca0c00, +-0x7c744b, +-0xc20005, +-0x99c000, +-0xc41c3a, +-0x7c744c, +-0xc0fff0, +-0x042c04, +-0x309002, +-0x7d2500, +-0x351402, +-0x7d350b, +-0x255403, +-0x7cd580, +-0x259c03, +-0x95c004, +-0xd5001b, +-0x7eddc1, +-0x7d9d80, +-0xd6801b, +-0xd5801b, +-0xd4401e, +-0xd5401e, +-0xd6401e, +-0xd6801e, +-0xd4801e, +-0xd4c01e, +-0x9783d3, +-0xd5c01e, +-0xca0800, +-0x80001a, +-0xca0c00, +-0xe4011e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xe4013e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca1800, +-0xd4401e, +-0xd5801e, +-0x800053, +-0xd40075, +-0xd4401e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd48019, +-0xd4c018, +-0xd50017, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xe2001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0xd48060, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xd48061, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xca0c00, +-0xd4401e, +-0xd48016, +-0xd4c016, +-0xd4801e, +-0x8001b8, +-0xd4c01e, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x948004, +-0xca1400, +-0xe420f3, +-0xd42013, +-0xd56065, +-0xd4e01c, +-0xd5201c, +-0xd5601c, +-0x800000, +-0x062001, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9483f7, +-0xca1400, +-0xe420f3, +-0x800079, +-0xd42013, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9883ef, +-0xca1400, +-0xd40064, +-0x80008d, +-0x000000, +-0xc41432, +-0xc61843, +-0xc4082f, +-0x954005, +-0xc40c30, +-0xd4401e, +-0x800000, +-0xee001e, +-0x9583f5, +-0xc41031, +-0xd44033, +-0xd52065, +-0xd4a01c, +-0xd4e01c, +-0xd5201c, +-0xe4015e, +-0xd4001e, +-0x800000, +-0x062001, +-0xca1800, +-0x0a2001, +-0xd60076, +-0xc40836, +-0x988007, +-0xc61045, +-0x950110, +-0xd4001f, +-0xd46062, +-0x800000, +-0xd42062, +-0xcc3835, +-0xcc1433, +-0x8401bb, +-0xd40072, +-0xd5401e, +-0x800000, +-0xee001e, +-0xe2001a, +-0x8401bb, +-0xe2001a, +-0xcc104b, +-0xcc0447, +-0x2c9401, +-0x7d098b, +-0x984005, +-0x7d15cb, +-0xd4001a, +-0x8001b8, +-0xd4006d, +-0x344401, +-0xcc0c48, +-0x98403a, +-0xcc2c4a, +-0x958004, +-0xcc0449, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0x282801, +-0x8400f0, +-0xcc1003, +-0x98801b, +-0x04380c, +-0x8400f0, +-0xcc1003, +-0x988017, +-0x043808, +-0x8400f0, +-0xcc1003, +-0x988013, +-0x043804, +-0x8400f0, +-0xcc1003, +-0x988014, +-0xcc104c, +-0x9a8009, +-0xcc144d, +-0x9840dc, +-0xd4006d, +-0xcc1848, +-0xd5001a, +-0xd5401a, +-0x8000c9, +-0xd5801a, +-0x96c0d5, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0x9ac003, +-0xd4006d, +-0xd4006e, +-0x800000, +-0xec007f, +-0x9ac0cc, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0x7d9103, +-0x7dd583, +-0x7d190c, +-0x35cc1f, +-0x35701f, +-0x7cf0cb, +-0x7cd08b, +-0x880000, +-0x7e8e8b, +-0x95c004, +-0xd4006e, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0xcc0803, +-0xcc0c03, +-0xcc1003, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0xcc2403, +-0xcc2803, +-0x35c41f, +-0x36b01f, +-0x7c704b, +-0x34f01f, +-0x7c704b, +-0x35701f, +-0x7c704b, +-0x7d8881, +-0x7dccc1, +-0x7e5101, +-0x7e9541, +-0x7c9082, +-0x7cd4c2, +-0x7c848b, +-0x9ac003, +-0x7c8c8b, +-0x2c8801, +-0x98809e, +-0xd4006d, +-0x98409c, +-0xd4006e, +-0xcc084c, +-0xcc0c4d, +-0xcc1048, +-0xd4801a, +-0xd4c01a, +-0x800101, +-0xd5001a, +-0xcc0832, +-0xd40032, +-0x9482d9, +-0xca0c00, +-0xd4401e, +-0x800000, +-0xd4001e, +-0xe4011e, +-0xd4001e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd4401e, +-0xca1400, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xd5401e, +-0xd54034, +-0x800000, +-0xee001e, +-0x280404, +-0xe2001a, +-0xe2001a, +-0xd4401a, +-0xca3800, +-0xcc0803, +-0xcc0c03, +-0xcc0c03, +-0xcc0c03, +-0x9882bd, +-0x000000, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0400, +-0xc2ff00, +-0xcc0834, +-0xc13fff, +-0x7c74cb, +-0x7cc90b, +-0x7d010f, +-0x9902b0, +-0x7c738b, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0800, +-0x281900, +-0x7d898b, +-0x958014, +-0x281404, +-0xca0c00, +-0xca1000, +-0xca1c00, +-0xca2400, +-0xe2001f, +-0xd4c01a, +-0xd5001a, +-0xd5401a, +-0xcc1803, +-0xcc2c03, +-0xcc2c03, +-0xcc2c03, +-0x7da58b, +-0x7d9c47, +-0x984297, +-0x000000, +-0x800161, +-0xd4c01a, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0x248c06, +-0x0ccc06, +-0x98c006, +-0xcc104e, +-0x990004, +-0xd40073, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xca0800, +-0xca0c00, +-0x34d018, +-0x251001, +-0x950021, +-0xc17fff, +-0xca1000, +-0xca1400, +-0xca1800, +-0xd4801d, +-0xd4c01d, +-0x7db18b, +-0xc14202, +-0xc2c001, +-0xd5801d, +-0x34dc0e, +-0x7d5d4c, +-0x7f734c, +-0xd7401e, +-0xd5001e, +-0xd5401e, +-0xc14200, +-0xc2c000, +-0x099c01, +-0x31dc10, +-0x7f5f4c, +-0x7f734c, +-0x042802, +-0x7d8380, +-0xd5a86f, +-0xd58066, +-0xd7401e, +-0xec005e, +-0xc82402, +-0xc82402, +-0x8001b8, +-0xd60076, +-0xd4401e, +-0xd4801e, +-0xd4c01e, +-0x800000, +-0xee001e, +-0x800000, +-0xee001f, +-0xd4001f, +-0x800000, +-0xd4001f, +-0xd4001f, +-0x880000, +-0xd4001f, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x010171, +-0x020178, +-0x03008f, +-0x04007f, +-0x050003, +-0x06003f, +-0x070032, +-0x08012c, +-0x090046, +-0x0a0036, +-0x1001b6, +-0x1700a2, +-0x22013a, +-0x230149, +-0x2000b4, +-0x240125, +-0x27004d, +-0x28006a, +-0x2a0060, +-0x2b0052, +-0x2f0065, +-0x320087, +-0x34017f, +-0x3c0156, +-0x3f0072, +-0x41018c, +-0x44012e, +-0x550173, +-0x56017a, +-0x60000b, +-0x610034, +-0x620038, +-0x630038, +-0x640038, +-0x650038, +-0x660038, +-0x670038, +-0x68003a, +-0x690041, +-0x6a0048, +-0x6b0048, +-0x6c0048, +-0x6d0048, +-0x6e0048, +-0x6f0048, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-}; +- +-static const u32 RV635_cp_microcode[][3] = { +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x0000ffff, 0x00284621, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00000000, 0x00e00000, 0x000 }, +- { 0x00010000, 0xc0294620, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x00000000, 0x00600000, 0x62e }, +- { 0x00000000, 0x00600000, 0x642 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000f00, 0x00281622, 0x000 }, +- { 0x00000008, 0x00211625, 0x000 }, +- { 0x00000018, 0x00203625, 0x000 }, +- { 0x8d000000, 0x00204411, 0x000 }, +- { 0x00000004, 0x002f0225, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x018 }, +- { 0x00412000, 0x00404811, 0x019 }, +- { 0x00422000, 0x00204811, 0x000 }, +- { 0x8e000000, 0x00204411, 0x000 }, +- { 0x00000028, 0x00204a2d, 0x000 }, +- { 0x90000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x0000000c, 0x00211622, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000019, 0x00211a22, 0x000 }, +- { 0x00000004, 0x00281a26, 0x000 }, +- { 0x00000000, 0x002914c5, 0x000 }, +- { 0x00000019, 0x00203625, 0x000 }, +- { 0x00000000, 0x003a1402, 0x000 }, +- { 0x00000016, 0x00211625, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0xfffffffc, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002914a3, 0x000 }, +- { 0x00000017, 0x00203625, 0x000 }, +- { 0x00008000, 0x00280e22, 0x000 }, +- { 0x00000007, 0x00220e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x20000000, 0x00280e22, 0x000 }, +- { 0x00000006, 0x00210e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x00000000, 0x00220222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x038 }, +- { 0x00000000, 0x2ee00000, 0x035 }, +- { 0x00000000, 0x2ce00000, 0x037 }, +- { 0x00000000, 0x00400e2d, 0x039 }, +- { 0x00000008, 0x00200e2d, 0x000 }, +- { 0x00000009, 0x0040122d, 0x046 }, +- { 0x00000001, 0x00400e2d, 0x039 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x03e }, +- { 0x00000008, 0x00401c11, 0x041 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x0000000f, 0x00281e27, 0x000 }, +- { 0x00000003, 0x00221e27, 0x000 }, +- { 0x7fc00000, 0x00281a23, 0x000 }, +- { 0x00000014, 0x00211a26, 0x000 }, +- { 0x00000001, 0x00331a26, 0x000 }, +- { 0x00000008, 0x00221a26, 0x000 }, +- { 0x00000000, 0x00290cc7, 0x000 }, +- { 0x00000027, 0x00203624, 0x000 }, +- { 0x00007f00, 0x00281221, 0x000 }, +- { 0x00001400, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04b }, +- { 0x00000001, 0x00290e23, 0x000 }, +- { 0x0000000e, 0x00203623, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfff80000, 0x00294a23, 0x000 }, +- { 0x00000000, 0x003a2c02, 0x000 }, +- { 0x00000002, 0x00220e2b, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x0000000f, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00204a2d, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000029, 0x00200e2d, 0x000 }, +- { 0x060a0200, 0x00294a23, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x061 }, +- { 0x00000000, 0x2ee00000, 0x05f }, +- { 0x00000000, 0x2ce00000, 0x05e }, +- { 0x00000000, 0x00400e2d, 0x062 }, +- { 0x00000001, 0x00400e2d, 0x062 }, +- { 0x0000000a, 0x00200e2d, 0x000 }, +- { 0x0000000b, 0x0040122d, 0x06a }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x7fc00000, 0x00281623, 0x000 }, +- { 0x00000014, 0x00211625, 0x000 }, +- { 0x00000001, 0x00331625, 0x000 }, +- { 0x80000000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00290ca3, 0x000 }, +- { 0x3ffffc00, 0x00290e23, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x06d }, +- { 0x00000100, 0x00401c11, 0x070 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x000000f0, 0x00281e27, 0x000 }, +- { 0x00000004, 0x00221e27, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0xfffff0ff, 0x00281a30, 0x000 }, +- { 0x0000a028, 0x00204411, 0x000 }, +- { 0x00000000, 0x002948e6, 0x000 }, +- { 0x0000a018, 0x00204411, 0x000 }, +- { 0x3fffffff, 0x00284a23, 0x000 }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000030, 0x0020162d, 0x000 }, +- { 0x00000002, 0x00291625, 0x000 }, +- { 0x00000030, 0x00203625, 0x000 }, +- { 0x00000025, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a3, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x083 }, +- { 0x00000026, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a4, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x084 }, +- { 0x00000000, 0x00400000, 0x08a }, +- { 0x00000025, 0x00203623, 0x000 }, +- { 0x00000026, 0x00203624, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x08a }, +- { 0x00000000, 0x00600000, 0x665 }, +- { 0x00000000, 0x00600000, 0x659 }, +- { 0x00000002, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x08d }, +- { 0x00000012, 0xc0403620, 0x093 }, +- { 0x00000000, 0x2ee00000, 0x091 }, +- { 0x00000000, 0x2ce00000, 0x090 }, +- { 0x00000002, 0x00400e2d, 0x092 }, +- { 0x00000003, 0x00400e2d, 0x092 }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000012, 0x00203623, 0x000 }, +- { 0x00000003, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x098 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x0a0 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x2ee00000, 0x09e }, +- { 0x00000000, 0x2ce00000, 0x09d }, +- { 0x00000002, 0x00400e2d, 0x09f }, +- { 0x00000003, 0x00400e2d, 0x09f }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x003f0000, 0x00280e23, 0x000 }, +- { 0x00000010, 0x00210e23, 0x000 }, +- { 0x00000011, 0x00203623, 0x000 }, +- { 0x0000001e, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0a7 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x0000001f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0aa }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000008, 0x00210e2b, 0x000 }, +- { 0x0000007f, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0e1 }, +- { 0x00000000, 0x27000000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0b3 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000000c, 0x00221e30, 0x000 }, +- { 0x99800000, 0x00204411, 0x000 }, +- { 0x00000004, 0x0020122d, 0x000 }, +- { 0x00000008, 0x00221224, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00291ce4, 0x000 }, +- { 0x00000000, 0x00604807, 0x12f }, +- { 0x9b000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x9c000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x0033146f, 0x000 }, +- { 0x00000001, 0x00333e23, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0x00203c05, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e007, 0x00204411, 0x000 }, +- { 0x0000000f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0cb }, +- { 0x00f8ff08, 0x00204811, 0x000 }, +- { 0x98000000, 0x00404811, 0x0dc }, +- { 0x000000f0, 0x00280e22, 0x000 }, +- { 0x000000a0, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x0da }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d5 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d4 }, +- { 0x00003f00, 0x00400c11, 0x0d6 }, +- { 0x00001f00, 0x00400c11, 0x0d6 }, +- { 0x00000f00, 0x00200c11, 0x000 }, +- { 0x00380009, 0x00294a23, 0x000 }, +- { 0x3f000000, 0x00280e2b, 0x000 }, +- { 0x00000002, 0x00220e23, 0x000 }, +- { 0x00000007, 0x00494a23, 0x0dc }, +- { 0x00380f09, 0x00204811, 0x000 }, +- { 0x68000007, 0x00204811, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000a202, 0x00204411, 0x000 }, +- { 0x00ff0000, 0x00280e22, 0x000 }, +- { 0x00000080, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00200e2d, 0x000 }, +- { 0x00000026, 0x0020122d, 0x000 }, +- { 0x00000000, 0x002f0083, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0ea }, +- { 0x00000000, 0x00600000, 0x65f }, +- { 0x00000000, 0x00400000, 0x0eb }, +- { 0x00000000, 0x00600000, 0x662 }, +- { 0x00000007, 0x0020222d, 0x000 }, +- { 0x00000005, 0x00220e22, 0x000 }, +- { 0x00100000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x000000ef, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000003, 0x00210223, 0x000 }, +- { 0x00000000, 0x14e00000, 0x0f8 }, +- { 0x0000000b, 0x00210228, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0f8 }, +- { 0x00000400, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000001c, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0fd }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000001e, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x10b }, +- { 0x0000a30f, 0x00204411, 0x000 }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x104 }, +- { 0xffffffff, 0x00404811, 0x10b }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x107 }, +- { 0x0000ffff, 0x00404811, 0x10b }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x10a }, +- { 0x000000ff, 0x00404811, 0x10b }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0002c400, 0x00204411, 0x000 }, +- { 0x0000001f, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x112 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000018, 0x40224a20, 0x000 }, +- { 0x00000010, 0xc0424a20, 0x114 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000000a, 0x00201011, 0x000 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x11b }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00531224, 0x117 }, +- { 0xffbfffff, 0x00283a2e, 0x000 }, +- { 0x0000001b, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x12e }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0x00000018, 0x00220e30, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e00e, 0x00204411, 0x000 }, +- { 0x07f8ff08, 0x00204811, 0x000 }, +- { 0x00000000, 0x00294a23, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x00800000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204806, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68a }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x689 }, +- { 0x00000004, 0x00404c11, 0x135 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x000021f8, 0x00204411, 0x000 }, +- { 0x0000001c, 0x00204811, 0x000 }, +- { 0x000421f9, 0x00604411, 0x68a }, +- { 0x00000011, 0x00210230, 0x000 }, +- { 0x00000000, 0x14e00000, 0x13c }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40280620, 0x000 }, +- { 0x00000010, 0xc0210a20, 0x000 }, +- { 0x00000000, 0x00341461, 0x000 }, +- { 0x00000000, 0x00741882, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x147 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0681a20, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x158 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000001, 0x00300a2f, 0x000 }, +- { 0x00000001, 0x00210a22, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600000, 0x18f }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00202c08, 0x000 }, +- { 0x00000000, 0x00202411, 0x000 }, +- { 0x00000000, 0x00202811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00221e29, 0x000 }, +- { 0x00000000, 0x007048eb, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000001, 0x40330620, 0x000 }, +- { 0x00000000, 0xc0302409, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x181 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x186 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x186 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000001, 0x00530621, 0x182 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0604800, 0x197 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000011, 0x0020062d, 0x000 }, +- { 0x00000000, 0x0078042a, 0x2fb }, +- { 0x00000000, 0x00202809, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x174 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x194 }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x46000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x19b }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00804811, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40281620, 0x000 }, +- { 0x00000010, 0xc0811a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000008, 0x00221e30, 0x000 }, +- { 0x00000029, 0x00201a2d, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfffbff09, 0x00204811, 0x000 }, +- { 0x0000000f, 0x0020222d, 0x000 }, +- { 0x00001fff, 0x00294a28, 0x000 }, +- { 0x00000006, 0x0020222d, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000100, 0x00201811, 0x000 }, +- { 0x00000008, 0x00621e28, 0x12f }, +- { 0x00000008, 0x00822228, 0x000 }, +- { 0x0002c000, 0x00204411, 0x000 }, +- { 0x00000015, 0x00600e2d, 0x1bd }, +- { 0x00000016, 0x00600e2d, 0x1bd }, +- { 0x0000c008, 0x00204411, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1b9 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x39000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00804802, 0x000 }, +- { 0x00000018, 0x00202e2d, 0x000 }, +- { 0x00000000, 0x003b0d63, 0x000 }, +- { 0x00000008, 0x00224a23, 0x000 }, +- { 0x00000010, 0x00224a23, 0x000 }, +- { 0x00000018, 0x00224a23, 0x000 }, +- { 0x00000000, 0x00804803, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000007, 0x0021062f, 0x000 }, +- { 0x00000013, 0x00200a2d, 0x000 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000ffff, 0x40282220, 0x000 }, +- { 0x0000000f, 0x00262228, 0x000 }, +- { 0x00000010, 0x40212620, 0x000 }, +- { 0x0000000f, 0x00262629, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1e0 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000081, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000080, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1dc }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1d8 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000001f, 0x00280a22, 0x000 }, +- { 0x0000001f, 0x00282a2a, 0x000 }, +- { 0x00000001, 0x00530621, 0x1d1 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000002, 0x00304a2f, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000001, 0x00301e2f, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1e5 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x0000000f, 0x00260e23, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000000f, 0x00261224, 0x000 }, +- { 0x00000000, 0x00201411, 0x000 }, +- { 0x00000000, 0x00601811, 0x2bb }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022b, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1f8 }, +- { 0x00000010, 0x00221628, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a29, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x0020480a, 0x000 }, +- { 0x00000000, 0x00202c11, 0x000 }, +- { 0x00000010, 0x00221623, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a24, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x00731503, 0x205 }, +- { 0x00000000, 0x00201805, 0x000 }, +- { 0x00000000, 0x00731524, 0x205 }, +- { 0x00000000, 0x002d14c5, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00000000, 0x00202003, 0x000 }, +- { 0x00000000, 0x00802404, 0x000 }, +- { 0x0000000f, 0x00210225, 0x000 }, +- { 0x00000000, 0x14c00000, 0x689 }, +- { 0x00000000, 0x002b1405, 0x000 }, +- { 0x00000001, 0x00901625, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00294a22, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a21, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000ffff, 0x40281220, 0x000 }, +- { 0x00000010, 0xc0211a20, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211620, 0x000 }, +- { 0x00000000, 0x00741465, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00000001, 0x00330621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x219 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x212 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x642 }, +- { 0x00000000, 0x0040040f, 0x213 }, +- { 0x00000000, 0x00600000, 0x62e }, +- { 0x00000000, 0x00600000, 0x642 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00000000, 0x00600000, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x232 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x236 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x236 }, +- { 0x00000000, 0xc0404800, 0x233 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x00600411, 0x2fb }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x62e }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000018, 0x40210a20, 0x000 }, +- { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x24c }, +- { 0x00000014, 0x0020222d, 0x000 }, +- { 0x00080101, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x251 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000010, 0x00600411, 0x315 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00000000, 0x00600000, 0x27c }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000001, 0x00211e27, 0x000 }, +- { 0x00000000, 0x14e00000, 0x26a }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x0000ffff, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00341c27, 0x000 }, +- { 0x00000000, 0x12c00000, 0x25f }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e5, 0x000 }, +- { 0x00000000, 0x08c00000, 0x262 }, +- { 0x00000000, 0x00201407, 0x000 }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00211e27, 0x000 }, +- { 0x00000000, 0x00341c47, 0x000 }, +- { 0x00000000, 0x12c00000, 0x267 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e6, 0x000 }, +- { 0x00000000, 0x08c00000, 0x26a }, +- { 0x00000000, 0x00201807, 0x000 }, +- { 0x00000000, 0x00600000, 0x2c1 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000000, 0x00342023, 0x000 }, +- { 0x00000000, 0x12c00000, 0x272 }, +- { 0x00000000, 0x00342044, 0x000 }, +- { 0x00000000, 0x12c00000, 0x271 }, +- { 0x00000016, 0x00404811, 0x276 }, +- { 0x00000018, 0x00404811, 0x276 }, +- { 0x00000000, 0x00342044, 0x000 }, +- { 0x00000000, 0x12c00000, 0x275 }, +- { 0x00000017, 0x00404811, 0x276 }, +- { 0x00000019, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00604411, 0x2e9 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x256 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000010, 0x40210620, 0x000 }, +- { 0x0000ffff, 0xc0280a20, 0x000 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0881a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x00000000, 0x00600000, 0x62e }, +- { 0x00000000, 0xc0600000, 0x2a3 }, +- { 0x00000005, 0x00200a2d, 0x000 }, +- { 0x00000008, 0x00220a22, 0x000 }, +- { 0x0000002b, 0x00201a2d, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00007000, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00311ce6, 0x000 }, +- { 0x0000002a, 0x00201a2d, 0x000 }, +- { 0x0000000c, 0x00221a26, 0x000 }, +- { 0x00000000, 0x002f00e6, 0x000 }, +- { 0x00000000, 0x06e00000, 0x292 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x0000002b, 0x00203623, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00691ce2, 0x12f }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x29d }, +- { 0x00000001, 0x00333e2f, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000001c, 0x00403627, 0x000 }, +- { 0x0000000c, 0xc0220a20, 0x000 }, +- { 0x00000029, 0x00203622, 0x000 }, +- { 0x00000028, 0xc0403620, 0x000 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000009, 0x00204811, 0x000 }, +- { 0xa1000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002c1ce3, 0x000 }, +- { 0x00000021, 0x00203627, 0x000 }, +- { 0x00000022, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002c1ce4, 0x000 }, +- { 0x00000022, 0x00203627, 0x000 }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120a3, 0x000 }, +- { 0x00000000, 0x002d1d07, 0x000 }, +- { 0x00000023, 0x00203627, 0x000 }, +- { 0x00000024, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x00000000, 0x002d1d07, 0x000 }, +- { 0x00000024, 0x00803627, 0x000 }, +- { 0x00000021, 0x00203623, 0x000 }, +- { 0x00000022, 0x00203624, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000023, 0x00203627, 0x000 }, +- { 0x00000000, 0x00311cc4, 0x000 }, +- { 0x00000024, 0x00803627, 0x000 }, +- { 0x0000001a, 0x00203627, 0x000 }, +- { 0x0000001b, 0x00203628, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14c00000, 0x2dc }, +- { 0x00000000, 0x00400000, 0x2d9 }, +- { 0x0000001a, 0x00203627, 0x000 }, +- { 0x0000001b, 0x00203628, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x2d9 }, +- { 0x00000003, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x2dc }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002e00e1, 0x000 }, +- { 0x00000000, 0x02c00000, 0x2dc }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120a1, 0x000 }, +- { 0x00000000, 0x002e00e8, 0x000 }, +- { 0x00000000, 0x06c00000, 0x2dc }, +- { 0x00000024, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002e00e2, 0x000 }, +- { 0x00000000, 0x02c00000, 0x2dc }, +- { 0x00000022, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120c2, 0x000 }, +- { 0x00000000, 0x002e00e8, 0x000 }, +- { 0x00000000, 0x06c00000, 0x2dc }, +- { 0x00000000, 0x00600000, 0x665 }, +- { 0x00000000, 0x00600000, 0x2b5 }, +- { 0x00000000, 0x00400000, 0x2de }, +- { 0x00000000, 0x00600000, 0x2b5 }, +- { 0x00000000, 0x00600000, 0x65c }, +- { 0x00000000, 0x00400000, 0x2de }, +- { 0x00000000, 0x00600000, 0x2a7 }, +- { 0x00000000, 0x00400000, 0x2de }, +- { 0x0000001a, 0x00201e2d, 0x000 }, +- { 0x0000001b, 0x0080222d, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00894907, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000010, 0x00221e21, 0x000 }, +- { 0x00000000, 0x00294847, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000000, 0x00311ca1, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294847, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000010, 0x00221e21, 0x000 }, +- { 0x00000000, 0x003120c2, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00894907, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000001, 0x00220a21, 0x000 }, +- { 0x00000000, 0x003308a2, 0x000 }, +- { 0x00000010, 0x00221e22, 0x000 }, +- { 0x00000010, 0x00212222, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294887, 0x000 }, +- { 0x00000001, 0x00220a21, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000010, 0x00221e22, 0x000 }, +- { 0x00000010, 0x00212222, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000010, 0x00221e23, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x003808c5, 0x000 }, +- { 0x00000000, 0x00300841, 0x000 }, +- { 0x00000001, 0x00220a22, 0x000 }, +- { 0x00000000, 0x003308a2, 0x000 }, +- { 0x00000010, 0x00221e22, 0x000 }, +- { 0x00000010, 0x00212222, 0x000 }, +- { 0x00000000, 0x00894907, 0x000 }, +- { 0x00000017, 0x0020222d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x318 }, +- { 0xffffffef, 0x00280621, 0x000 }, +- { 0x00000014, 0x0020222d, 0x000 }, +- { 0x0000f8e0, 0x00204411, 0x000 }, +- { 0x00000000, 0x00294901, 0x000 }, +- { 0x00000000, 0x00894901, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00804811, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x97000000, 0xc0204411, 0x000 }, +- { 0x00000000, 0xc0204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00002257, 0x00204411, 0x000 }, +- { 0x00000003, 0xc0484a20, 0x000 }, +- { 0x0000225d, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0x00600000, 0x642 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0001a1fd, 0x00204411, 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0x81000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000216d, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0604800, 0x68f }, +- { 0x00000000, 0x00400000, 0x4c4 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00040000, 0xc0294620, 0x000 }, +- { 0x00000000, 0xc0600000, 0x68a }, +- { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x4cb }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0xcafebabe, 0x00404811, 0x000 }, +- { 0x00000000, 0xc0204400, 0x000 }, +- { 0x00000000, 0xc0404810, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x000021f8, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x000421f9, 0x00604411, 0x68a }, +- { 0x00000000, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x4cd }, +- { 0x00002180, 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0x000 }, +- { 0x00000008, 0x00300a22, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000002d, 0x0020122d, 0x000 }, +- { 0x00000000, 0x00290c83, 0x000 }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000008, 0x00300a22, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000011, 0x00210224, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x00000000, 0x00400000, 0x4a7 }, +- { 0x0000002c, 0xc0203620, 0x000 }, +- { 0x0000002d, 0xc0403620, 0x000 }, +- { 0x0000000f, 0x00210221, 0x000 }, +- { 0x00000000, 0x14c00000, 0x502 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0xd9000000, 0x000 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0xb5000000, 0x00204411, 0x000 }, +- { 0x00002000, 0x00204811, 0x000 }, +- { 0xb6000000, 0x00204411, 0x000 }, +- { 0x0000a000, 0x00204811, 0x000 }, +- { 0xb7000000, 0x00204411, 0x000 }, +- { 0x0000c000, 0x00204811, 0x000 }, +- { 0xb8000000, 0x00204411, 0x000 }, +- { 0x0000f8e0, 0x00204811, 0x000 }, +- { 0xb9000000, 0x00204411, 0x000 }, +- { 0x0000f880, 0x00204811, 0x000 }, +- { 0xba000000, 0x00204411, 0x000 }, +- { 0x0000e000, 0x00204811, 0x000 }, +- { 0xbb000000, 0x00204411, 0x000 }, +- { 0x0000f000, 0x00204811, 0x000 }, +- { 0xbc000000, 0x00204411, 0x000 }, +- { 0x0000f3fc, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00204811, 0x000 }, +- { 0x000000ff, 0x00280e30, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x516 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000000, 0x14c00000, 0x52b }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x0000001c, 0x00203623, 0x000 }, +- { 0x0000002b, 0x00203623, 0x000 }, +- { 0x00000029, 0x00203623, 0x000 }, +- { 0x00000028, 0x00203623, 0x000 }, +- { 0x00000017, 0x00203623, 0x000 }, +- { 0x00000025, 0x00203623, 0x000 }, +- { 0x00000026, 0x00203623, 0x000 }, +- { 0x00000015, 0x00203623, 0x000 }, +- { 0x00000016, 0x00203623, 0x000 }, +- { 0xffffe000, 0x00200c11, 0x000 }, +- { 0x00000021, 0x00203623, 0x000 }, +- { 0x00000022, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00200c11, 0x000 }, +- { 0x00000023, 0x00203623, 0x000 }, +- { 0x00000024, 0x00203623, 0x000 }, +- { 0xf1ffffff, 0x00283a2e, 0x000 }, +- { 0x0000001a, 0xc0220e20, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000002a, 0x40203620, 0x000 }, +- { 0x87000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000a1f4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x00000030, 0x00203623, 0x000 }, +- { 0x9d000000, 0x00204411, 0x000 }, +- { 0x0000001f, 0x40214a20, 0x000 }, +- { 0x96000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x00000000, 0xc0201000, 0x000 }, +- { 0x0000001f, 0x00211624, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x0000001d, 0x00203623, 0x000 }, +- { 0x00000003, 0x00281e23, 0x000 }, +- { 0x00000008, 0x00222223, 0x000 }, +- { 0xfffff000, 0x00282228, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x0000001f, 0x00203628, 0x000 }, +- { 0x00000018, 0x00211e23, 0x000 }, +- { 0x00000020, 0x00203627, 0x000 }, +- { 0x00000002, 0x00221624, 0x000 }, +- { 0x00000000, 0x003014a8, 0x000 }, +- { 0x0000001e, 0x00203625, 0x000 }, +- { 0x00000003, 0x00211a24, 0x000 }, +- { 0x10000000, 0x00281a26, 0x000 }, +- { 0xefffffff, 0x00283a2e, 0x000 }, +- { 0x00000000, 0x004938ce, 0x678 }, +- { 0x00000001, 0x40280a20, 0x000 }, +- { 0x00000006, 0x40280e20, 0x000 }, +- { 0x00000300, 0xc0281220, 0x000 }, +- { 0x00000008, 0x00211224, 0x000 }, +- { 0x00000000, 0xc0201620, 0x000 }, +- { 0x00000000, 0xc0201a20, 0x000 }, +- { 0x00000000, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x563 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00002258, 0x00300a24, 0x000 }, +- { 0x00040000, 0x00694622, 0x68a }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x00020000, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x56b }, +- { 0x00000000, 0xc0201c10, 0x000 }, +- { 0x00000000, 0xc0400000, 0x579 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x56b }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00002258, 0x00300a24, 0x000 }, +- { 0x00040000, 0x00694622, 0x68a }, +- { 0x00000000, 0xc0201c10, 0x000 }, +- { 0x00000000, 0xc0400000, 0x579 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x56f }, +- { 0x00000000, 0xc0201c00, 0x000 }, +- { 0x00000000, 0xc0400000, 0x579 }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x577 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000216d, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0604800, 0x68f }, +- { 0x00000000, 0x00401c10, 0x579 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00000000, 0xc0400000, 0x000 }, +- { 0x00000000, 0x0ee00000, 0x57b }, +- { 0x00000000, 0x00600000, 0x5c6 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x58c }, +- { 0x0000a2b7, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2b6, 0x00604411, 0x68a }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x0000a2c4, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x58a }, +- { 0x0000a2d1, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d1, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x00000001, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x59d }, +- { 0x0000a2bb, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2ba, 0x00604411, 0x68a }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x0000a2c5, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x59b }, +- { 0x0000a2d2, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d2, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x00000002, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x5ae }, +- { 0x0000a2bf, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2be, 0x00604411, 0x68a }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x0000a2c6, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x5ac }, +- { 0x0000a2d3, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d3, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x0000a2c3, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2c2, 0x00604411, 0x68a }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x0000a2c7, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x5bb }, +- { 0x0000a2d4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d4, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x85000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x0000304a, 0x00204411, 0x000 }, +- { 0x01000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00400000, 0x5c1 }, +- { 0xa4000000, 0xc0204411, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0xc0600000, 0x5c6 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000002c, 0x00203621, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0230, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x5cd }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000030, 0x00403621, 0x5e0 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00007e00, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x5e0 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a092, 0x00604411, 0x68a }, +- { 0x00000031, 0x00203630, 0x000 }, +- { 0x0004a093, 0x00604411, 0x68a }, +- { 0x00000032, 0x00203630, 0x000 }, +- { 0x0004a2b6, 0x00604411, 0x68a }, +- { 0x00000033, 0x00203630, 0x000 }, +- { 0x0004a2ba, 0x00604411, 0x68a }, +- { 0x00000034, 0x00203630, 0x000 }, +- { 0x0004a2be, 0x00604411, 0x68a }, +- { 0x00000035, 0x00203630, 0x000 }, +- { 0x0004a2c2, 0x00604411, 0x68a }, +- { 0x00000036, 0x00203630, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x00000005, 0x00204811, 0x000 }, +- { 0x0000a1f4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x88000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000001, 0x002f0230, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x629 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x629 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00007e00, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x602 }, +- { 0x0000a092, 0x00204411, 0x000 }, +- { 0x00000031, 0x00204a2d, 0x000 }, +- { 0x0000a093, 0x00204411, 0x000 }, +- { 0x00000032, 0x00204a2d, 0x000 }, +- { 0x0000a2b6, 0x00204411, 0x000 }, +- { 0x00000033, 0x00204a2d, 0x000 }, +- { 0x0000a2ba, 0x00204411, 0x000 }, +- { 0x00000034, 0x00204a2d, 0x000 }, +- { 0x0000a2be, 0x00204411, 0x000 }, +- { 0x00000035, 0x00204a2d, 0x000 }, +- { 0x0000a2c2, 0x00204411, 0x000 }, +- { 0x00000036, 0x00204a2d, 0x000 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x000001ff, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x628 }, +- { 0x00000000, 0x00210221, 0x000 }, +- { 0x00000000, 0x14c00000, 0x60b }, +- { 0x0004a003, 0x00604411, 0x68a }, +- { 0x0000a003, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000001, 0x00210621, 0x000 }, +- { 0x00000000, 0x14c00000, 0x610 }, +- { 0x0004a010, 0x00604411, 0x68a }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000001, 0x00210621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x628 }, +- { 0x0004a011, 0x00604411, 0x68a }, +- { 0x0000a011, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a012, 0x00604411, 0x68a }, +- { 0x0000a012, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a013, 0x00604411, 0x68a }, +- { 0x0000a013, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a014, 0x00604411, 0x68a }, +- { 0x0000a014, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a015, 0x00604411, 0x68a }, +- { 0x0000a015, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a016, 0x00604411, 0x68a }, +- { 0x0000a016, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a017, 0x00604411, 0x68a }, +- { 0x0000a017, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x0000002c, 0x0080062d, 0x000 }, +- { 0xff000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000002, 0x00804811, 0x000 }, +- { 0x00000000, 0x0ee00000, 0x63a }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00000002, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x638 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x68a }, +- { 0x00001000, 0x00200811, 0x000 }, +- { 0x0000002b, 0x00203622, 0x000 }, +- { 0x00000000, 0x00600000, 0x63e }, +- { 0x00000000, 0x00600000, 0x5c6 }, +- { 0x98000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00804811, 0x000 }, +- { 0x00000000, 0xc0600000, 0x63e }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000022, 0x00204811, 0x000 }, +- { 0x89000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00404811, 0x62a }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404811, 0x62a }, +- { 0x00000000, 0x00600000, 0x659 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0xc0204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36e }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x09800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68a }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x00000004, 0x00404c11, 0x653 }, +- { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000004, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffffb, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffff7, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00008000, 0x00204811, 0x000 }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36e }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x01800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004217f, 0x00604411, 0x68a }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x689 }, +- { 0x00000010, 0x00404c11, 0x66f }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x38c00000, 0x000 }, +- { 0x0000001d, 0x00200a2d, 0x000 }, +- { 0x0000001e, 0x00200e2d, 0x000 }, +- { 0x0000001f, 0x0020122d, 0x000 }, +- { 0x00000020, 0x0020162d, 0x000 }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000004, 0x00301224, 0x000 }, +- { 0x00000000, 0x002f0064, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x688 }, +- { 0x00000003, 0x00281a22, 0x000 }, +- { 0x00000008, 0x00221222, 0x000 }, +- { 0xfffff000, 0x00281224, 0x000 }, +- { 0x00000000, 0x002910c4, 0x000 }, +- { 0x0000001f, 0x00403624, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x68a }, +- { 0x9f000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x68d }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x68f }, +- { 0x9e000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x692 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0xc0204411, 0x000 }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000024, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000022, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00404811, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x014204ff, 0x05bd0250, 0x000 }, +- { 0x01c30168, 0x043f05bd, 0x000 }, +- { 0x02250209, 0x02500151, 0x000 }, +- { 0x02230245, 0x02a00241, 0x000 }, +- { 0x03d705bd, 0x05bd05bd, 0x000 }, +- { 0x06460647, 0x031f05bd, 0x000 }, +- { 0x05bd05c2, 0x03200340, 0x000 }, +- { 0x032a0282, 0x03420334, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd054e, 0x05bd05bd, 0x000 }, +- { 0x03ba05bd, 0x04b80344, 0x000 }, +- { 0x0497044d, 0x043d05bd, 0x000 }, +- { 0x04cd05bd, 0x044104da, 0x000 }, +- { 0x044d0504, 0x03510375, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd05bd, 0x063c05c4, 0x000 }, +- { 0x05bd05bd, 0x000705bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x03f803ed, 0x04080406, 0x000 }, +- { 0x040e040a, 0x040c0410, 0x000 }, +- { 0x041c0418, 0x04240420, 0x000 }, +- { 0x042c0428, 0x04340430, 0x000 }, +- { 0x05bd05bd, 0x043805bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x05bd05bd, 0x05bd05bd, 0x000 }, +- { 0x00020676, 0x06940006, 0x000 }, +-}; +- +-static const u32 RV635_pfp_microcode[] = { +-0xca0400, +-0xa00000, +-0x7e828b, +-0x7c038b, +-0x8001b8, +-0x7c038b, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xc41838, +-0xca2400, +-0xca2800, +-0x9581a8, +-0xc41c3a, +-0xc3c000, +-0xca0800, +-0xca0c00, +-0x7c744b, +-0xc20005, +-0x99c000, +-0xc41c3a, +-0x7c744c, +-0xc0fff0, +-0x042c04, +-0x309002, +-0x7d2500, +-0x351402, +-0x7d350b, +-0x255403, +-0x7cd580, +-0x259c03, +-0x95c004, +-0xd5001b, +-0x7eddc1, +-0x7d9d80, +-0xd6801b, +-0xd5801b, +-0xd4401e, +-0xd5401e, +-0xd6401e, +-0xd6801e, +-0xd4801e, +-0xd4c01e, +-0x9783d3, +-0xd5c01e, +-0xca0800, +-0x80001a, +-0xca0c00, +-0xe4011e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xe4013e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca1800, +-0xd4401e, +-0xd5801e, +-0x800053, +-0xd40075, +-0xd4401e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd48019, +-0xd4c018, +-0xd50017, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xe2001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0xd48060, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xd48061, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xca0c00, +-0xd4401e, +-0xd48016, +-0xd4c016, +-0xd4801e, +-0x8001b8, +-0xd4c01e, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x948004, +-0xca1400, +-0xe420f3, +-0xd42013, +-0xd56065, +-0xd4e01c, +-0xd5201c, +-0xd5601c, +-0x800000, +-0x062001, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9483f7, +-0xca1400, +-0xe420f3, +-0x800079, +-0xd42013, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9883ef, +-0xca1400, +-0xd40064, +-0x80008d, +-0x000000, +-0xc41432, +-0xc61843, +-0xc4082f, +-0x954005, +-0xc40c30, +-0xd4401e, +-0x800000, +-0xee001e, +-0x9583f5, +-0xc41031, +-0xd44033, +-0xd52065, +-0xd4a01c, +-0xd4e01c, +-0xd5201c, +-0xe4015e, +-0xd4001e, +-0x800000, +-0x062001, +-0xca1800, +-0x0a2001, +-0xd60076, +-0xc40836, +-0x988007, +-0xc61045, +-0x950110, +-0xd4001f, +-0xd46062, +-0x800000, +-0xd42062, +-0xcc3835, +-0xcc1433, +-0x8401bb, +-0xd40072, +-0xd5401e, +-0x800000, +-0xee001e, +-0xe2001a, +-0x8401bb, +-0xe2001a, +-0xcc104b, +-0xcc0447, +-0x2c9401, +-0x7d098b, +-0x984005, +-0x7d15cb, +-0xd4001a, +-0x8001b8, +-0xd4006d, +-0x344401, +-0xcc0c48, +-0x98403a, +-0xcc2c4a, +-0x958004, +-0xcc0449, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0x282801, +-0x8400f0, +-0xcc1003, +-0x98801b, +-0x04380c, +-0x8400f0, +-0xcc1003, +-0x988017, +-0x043808, +-0x8400f0, +-0xcc1003, +-0x988013, +-0x043804, +-0x8400f0, +-0xcc1003, +-0x988014, +-0xcc104c, +-0x9a8009, +-0xcc144d, +-0x9840dc, +-0xd4006d, +-0xcc1848, +-0xd5001a, +-0xd5401a, +-0x8000c9, +-0xd5801a, +-0x96c0d5, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0x9ac003, +-0xd4006d, +-0xd4006e, +-0x800000, +-0xec007f, +-0x9ac0cc, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0x7d9103, +-0x7dd583, +-0x7d190c, +-0x35cc1f, +-0x35701f, +-0x7cf0cb, +-0x7cd08b, +-0x880000, +-0x7e8e8b, +-0x95c004, +-0xd4006e, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0xcc0803, +-0xcc0c03, +-0xcc1003, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0xcc2403, +-0xcc2803, +-0x35c41f, +-0x36b01f, +-0x7c704b, +-0x34f01f, +-0x7c704b, +-0x35701f, +-0x7c704b, +-0x7d8881, +-0x7dccc1, +-0x7e5101, +-0x7e9541, +-0x7c9082, +-0x7cd4c2, +-0x7c848b, +-0x9ac003, +-0x7c8c8b, +-0x2c8801, +-0x98809e, +-0xd4006d, +-0x98409c, +-0xd4006e, +-0xcc084c, +-0xcc0c4d, +-0xcc1048, +-0xd4801a, +-0xd4c01a, +-0x800101, +-0xd5001a, +-0xcc0832, +-0xd40032, +-0x9482d9, +-0xca0c00, +-0xd4401e, +-0x800000, +-0xd4001e, +-0xe4011e, +-0xd4001e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd4401e, +-0xca1400, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xd5401e, +-0xd54034, +-0x800000, +-0xee001e, +-0x280404, +-0xe2001a, +-0xe2001a, +-0xd4401a, +-0xca3800, +-0xcc0803, +-0xcc0c03, +-0xcc0c03, +-0xcc0c03, +-0x9882bd, +-0x000000, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0400, +-0xc2ff00, +-0xcc0834, +-0xc13fff, +-0x7c74cb, +-0x7cc90b, +-0x7d010f, +-0x9902b0, +-0x7c738b, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0800, +-0x281900, +-0x7d898b, +-0x958014, +-0x281404, +-0xca0c00, +-0xca1000, +-0xca1c00, +-0xca2400, +-0xe2001f, +-0xd4c01a, +-0xd5001a, +-0xd5401a, +-0xcc1803, +-0xcc2c03, +-0xcc2c03, +-0xcc2c03, +-0x7da58b, +-0x7d9c47, +-0x984297, +-0x000000, +-0x800161, +-0xd4c01a, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0x248c06, +-0x0ccc06, +-0x98c006, +-0xcc104e, +-0x990004, +-0xd40073, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xca0800, +-0xca0c00, +-0x34d018, +-0x251001, +-0x950021, +-0xc17fff, +-0xca1000, +-0xca1400, +-0xca1800, +-0xd4801d, +-0xd4c01d, +-0x7db18b, +-0xc14202, +-0xc2c001, +-0xd5801d, +-0x34dc0e, +-0x7d5d4c, +-0x7f734c, +-0xd7401e, +-0xd5001e, +-0xd5401e, +-0xc14200, +-0xc2c000, +-0x099c01, +-0x31dc10, +-0x7f5f4c, +-0x7f734c, +-0x042802, +-0x7d8380, +-0xd5a86f, +-0xd58066, +-0xd7401e, +-0xec005e, +-0xc82402, +-0xc82402, +-0x8001b8, +-0xd60076, +-0xd4401e, +-0xd4801e, +-0xd4c01e, +-0x800000, +-0xee001e, +-0x800000, +-0xee001f, +-0xd4001f, +-0x800000, +-0xd4001f, +-0xd4001f, +-0x880000, +-0xd4001f, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x010171, +-0x020178, +-0x03008f, +-0x04007f, +-0x050003, +-0x06003f, +-0x070032, +-0x08012c, +-0x090046, +-0x0a0036, +-0x1001b6, +-0x1700a2, +-0x22013a, +-0x230149, +-0x2000b4, +-0x240125, +-0x27004d, +-0x28006a, +-0x2a0060, +-0x2b0052, +-0x2f0065, +-0x320087, +-0x34017f, +-0x3c0156, +-0x3f0072, +-0x41018c, +-0x44012e, +-0x550173, +-0x56017a, +-0x60000b, +-0x610034, +-0x620038, +-0x630038, +-0x640038, +-0x650038, +-0x660038, +-0x670038, +-0x68003a, +-0x690041, +-0x6a0048, +-0x6b0048, +-0x6c0048, +-0x6d0048, +-0x6e0048, +-0x6f0048, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-}; +- +-static const u32 RV670_cp_microcode[][3] = { +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x0000ffff, 0x00284621, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00000000, 0x00e00000, 0x000 }, +- { 0x00010000, 0xc0294620, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x67c }, +- { 0x00000000, 0x00600000, 0x624 }, +- { 0x00000000, 0x00600000, 0x638 }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000f00, 0x00281622, 0x000 }, +- { 0x00000008, 0x00211625, 0x000 }, +- { 0x00000018, 0x00203625, 0x000 }, +- { 0x8d000000, 0x00204411, 0x000 }, +- { 0x00000004, 0x002f0225, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x018 }, +- { 0x00412000, 0x00404811, 0x019 }, +- { 0x00422000, 0x00204811, 0x000 }, +- { 0x8e000000, 0x00204411, 0x000 }, +- { 0x00000028, 0x00204a2d, 0x000 }, +- { 0x90000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x0000000c, 0x00211622, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000019, 0x00211a22, 0x000 }, +- { 0x00000004, 0x00281a26, 0x000 }, +- { 0x00000000, 0x002914c5, 0x000 }, +- { 0x00000019, 0x00203625, 0x000 }, +- { 0x00000000, 0x003a1402, 0x000 }, +- { 0x00000016, 0x00211625, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0xfffffffc, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002914a3, 0x000 }, +- { 0x00000017, 0x00203625, 0x000 }, +- { 0x00008000, 0x00280e22, 0x000 }, +- { 0x00000007, 0x00220e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x20000000, 0x00280e22, 0x000 }, +- { 0x00000006, 0x00210e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x00000000, 0x00220222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x038 }, +- { 0x00000000, 0x2ee00000, 0x035 }, +- { 0x00000000, 0x2ce00000, 0x037 }, +- { 0x00000000, 0x00400e2d, 0x039 }, +- { 0x00000008, 0x00200e2d, 0x000 }, +- { 0x00000009, 0x0040122d, 0x046 }, +- { 0x00000001, 0x00400e2d, 0x039 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x03e }, +- { 0x00000008, 0x00401c11, 0x041 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x0000000f, 0x00281e27, 0x000 }, +- { 0x00000003, 0x00221e27, 0x000 }, +- { 0x7fc00000, 0x00281a23, 0x000 }, +- { 0x00000014, 0x00211a26, 0x000 }, +- { 0x00000001, 0x00331a26, 0x000 }, +- { 0x00000008, 0x00221a26, 0x000 }, +- { 0x00000000, 0x00290cc7, 0x000 }, +- { 0x00000027, 0x00203624, 0x000 }, +- { 0x00007f00, 0x00281221, 0x000 }, +- { 0x00001400, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04b }, +- { 0x00000001, 0x00290e23, 0x000 }, +- { 0x0000000e, 0x00203623, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfff80000, 0x00294a23, 0x000 }, +- { 0x00000000, 0x003a2c02, 0x000 }, +- { 0x00000002, 0x00220e2b, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x0000000f, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00204a2d, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000029, 0x00200e2d, 0x000 }, +- { 0x060a0200, 0x00294a23, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x061 }, +- { 0x00000000, 0x2ee00000, 0x05f }, +- { 0x00000000, 0x2ce00000, 0x05e }, +- { 0x00000000, 0x00400e2d, 0x062 }, +- { 0x00000001, 0x00400e2d, 0x062 }, +- { 0x0000000a, 0x00200e2d, 0x000 }, +- { 0x0000000b, 0x0040122d, 0x06a }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x7fc00000, 0x00281623, 0x000 }, +- { 0x00000014, 0x00211625, 0x000 }, +- { 0x00000001, 0x00331625, 0x000 }, +- { 0x80000000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00290ca3, 0x000 }, +- { 0x3ffffc00, 0x00290e23, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x06d }, +- { 0x00000100, 0x00401c11, 0x070 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x000000f0, 0x00281e27, 0x000 }, +- { 0x00000004, 0x00221e27, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0xfffff0ff, 0x00281a30, 0x000 }, +- { 0x0000a028, 0x00204411, 0x000 }, +- { 0x00000000, 0x002948e6, 0x000 }, +- { 0x0000a018, 0x00204411, 0x000 }, +- { 0x3fffffff, 0x00284a23, 0x000 }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000030, 0x0020162d, 0x000 }, +- { 0x00000002, 0x00291625, 0x000 }, +- { 0x00000030, 0x00203625, 0x000 }, +- { 0x00000025, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a3, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x083 }, +- { 0x00000026, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a4, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x084 }, +- { 0x00000000, 0x00400000, 0x08a }, +- { 0x00000025, 0x00203623, 0x000 }, +- { 0x00000026, 0x00203624, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x08a }, +- { 0x00000000, 0x00600000, 0x659 }, +- { 0x00000000, 0x00600000, 0x64d }, +- { 0x00000002, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x08d }, +- { 0x00000012, 0xc0403620, 0x093 }, +- { 0x00000000, 0x2ee00000, 0x091 }, +- { 0x00000000, 0x2ce00000, 0x090 }, +- { 0x00000002, 0x00400e2d, 0x092 }, +- { 0x00000003, 0x00400e2d, 0x092 }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000012, 0x00203623, 0x000 }, +- { 0x00000003, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x098 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x0a0 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x2ee00000, 0x09e }, +- { 0x00000000, 0x2ce00000, 0x09d }, +- { 0x00000002, 0x00400e2d, 0x09f }, +- { 0x00000003, 0x00400e2d, 0x09f }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x003f0000, 0x00280e23, 0x000 }, +- { 0x00000010, 0x00210e23, 0x000 }, +- { 0x00000011, 0x00203623, 0x000 }, +- { 0x0000001e, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0a7 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x0000001f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0aa }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000008, 0x00210e2b, 0x000 }, +- { 0x0000007f, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0e1 }, +- { 0x00000000, 0x27000000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0b3 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000000c, 0x00221e30, 0x000 }, +- { 0x99800000, 0x00204411, 0x000 }, +- { 0x00000004, 0x0020122d, 0x000 }, +- { 0x00000008, 0x00221224, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00291ce4, 0x000 }, +- { 0x00000000, 0x00604807, 0x12f }, +- { 0x9b000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x9c000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x0033146f, 0x000 }, +- { 0x00000001, 0x00333e23, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0x00203c05, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e007, 0x00204411, 0x000 }, +- { 0x0000000f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0cb }, +- { 0x00f8ff08, 0x00204811, 0x000 }, +- { 0x98000000, 0x00404811, 0x0dc }, +- { 0x000000f0, 0x00280e22, 0x000 }, +- { 0x000000a0, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x0da }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d5 }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0d4 }, +- { 0x00003f00, 0x00400c11, 0x0d6 }, +- { 0x00001f00, 0x00400c11, 0x0d6 }, +- { 0x00000f00, 0x00200c11, 0x000 }, +- { 0x00380009, 0x00294a23, 0x000 }, +- { 0x3f000000, 0x00280e2b, 0x000 }, +- { 0x00000002, 0x00220e23, 0x000 }, +- { 0x00000007, 0x00494a23, 0x0dc }, +- { 0x00380f09, 0x00204811, 0x000 }, +- { 0x68000007, 0x00204811, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000a202, 0x00204411, 0x000 }, +- { 0x00ff0000, 0x00280e22, 0x000 }, +- { 0x00000080, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00200e2d, 0x000 }, +- { 0x00000026, 0x0020122d, 0x000 }, +- { 0x00000000, 0x002f0083, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0ea }, +- { 0x00000000, 0x00600000, 0x653 }, +- { 0x00000000, 0x00400000, 0x0eb }, +- { 0x00000000, 0x00600000, 0x656 }, +- { 0x00000007, 0x0020222d, 0x000 }, +- { 0x00000005, 0x00220e22, 0x000 }, +- { 0x00100000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x000000ef, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00292068, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000003, 0x00210223, 0x000 }, +- { 0x00000000, 0x14e00000, 0x0f8 }, +- { 0x0000000b, 0x00210228, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0f8 }, +- { 0x00000400, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000001c, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0fd }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000001e, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x10b }, +- { 0x0000a30f, 0x00204411, 0x000 }, +- { 0x00000011, 0x00200e2d, 0x000 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x104 }, +- { 0xffffffff, 0x00404811, 0x10b }, +- { 0x00000002, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x107 }, +- { 0x0000ffff, 0x00404811, 0x10b }, +- { 0x00000004, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x10a }, +- { 0x000000ff, 0x00404811, 0x10b }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0002c400, 0x00204411, 0x000 }, +- { 0x0000001f, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x112 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000018, 0x40224a20, 0x000 }, +- { 0x00000010, 0xc0424a20, 0x114 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x00000013, 0x00203623, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x0000000a, 0x00201011, 0x000 }, +- { 0x00000000, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x11b }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00531224, 0x117 }, +- { 0xffbfffff, 0x00283a2e, 0x000 }, +- { 0x0000001b, 0x00210222, 0x000 }, +- { 0x00000000, 0x14c00000, 0x12e }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0x00000018, 0x00220e30, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000e, 0x00204811, 0x000 }, +- { 0x00000000, 0x00201010, 0x000 }, +- { 0x0000e00e, 0x00204411, 0x000 }, +- { 0x07f8ff08, 0x00204811, 0x000 }, +- { 0x00000000, 0x00294a23, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a24, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x00800000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204806, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x67c }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x67b }, +- { 0x00000004, 0x00404c11, 0x135 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x000021f8, 0x00204411, 0x000 }, +- { 0x0000001c, 0x00204811, 0x000 }, +- { 0x000421f9, 0x00604411, 0x67c }, +- { 0x00000011, 0x00210230, 0x000 }, +- { 0x00000000, 0x14e00000, 0x13c }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40280620, 0x000 }, +- { 0x00000010, 0xc0210a20, 0x000 }, +- { 0x00000000, 0x00341461, 0x000 }, +- { 0x00000000, 0x00741882, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x147 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0681a20, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x158 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000001, 0x00300a2f, 0x000 }, +- { 0x00000001, 0x00210a22, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600000, 0x18f }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00202c08, 0x000 }, +- { 0x00000000, 0x00202411, 0x000 }, +- { 0x00000000, 0x00202811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00221e29, 0x000 }, +- { 0x00000000, 0x007048eb, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000001, 0x40330620, 0x000 }, +- { 0x00000000, 0xc0302409, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x181 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x186 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x186 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000001, 0x00530621, 0x182 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0604800, 0x197 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000011, 0x0020062d, 0x000 }, +- { 0x00000000, 0x0078042a, 0x2fb }, +- { 0x00000000, 0x00202809, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x174 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x194 }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x46000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x19b }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00804811, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40281620, 0x000 }, +- { 0x00000010, 0xc0811a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000008, 0x00221e30, 0x000 }, +- { 0x00000029, 0x00201a2d, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfffbff09, 0x00204811, 0x000 }, +- { 0x0000000f, 0x0020222d, 0x000 }, +- { 0x00001fff, 0x00294a28, 0x000 }, +- { 0x00000006, 0x0020222d, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000100, 0x00201811, 0x000 }, +- { 0x00000008, 0x00621e28, 0x12f }, +- { 0x00000008, 0x00822228, 0x000 }, +- { 0x0002c000, 0x00204411, 0x000 }, +- { 0x00000015, 0x00600e2d, 0x1bd }, +- { 0x00000016, 0x00600e2d, 0x1bd }, +- { 0x0000c008, 0x00204411, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1b9 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x39000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00804802, 0x000 }, +- { 0x00000018, 0x00202e2d, 0x000 }, +- { 0x00000000, 0x003b0d63, 0x000 }, +- { 0x00000008, 0x00224a23, 0x000 }, +- { 0x00000010, 0x00224a23, 0x000 }, +- { 0x00000018, 0x00224a23, 0x000 }, +- { 0x00000000, 0x00804803, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000007, 0x0021062f, 0x000 }, +- { 0x00000013, 0x00200a2d, 0x000 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000ffff, 0x40282220, 0x000 }, +- { 0x0000000f, 0x00262228, 0x000 }, +- { 0x00000010, 0x40212620, 0x000 }, +- { 0x0000000f, 0x00262629, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1e0 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000081, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000080, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1dc }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1d8 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000001f, 0x00280a22, 0x000 }, +- { 0x0000001f, 0x00282a2a, 0x000 }, +- { 0x00000001, 0x00530621, 0x1d1 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000002, 0x00304a2f, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000001, 0x00301e2f, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1e5 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x0000000f, 0x00260e23, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000000f, 0x00261224, 0x000 }, +- { 0x00000000, 0x00201411, 0x000 }, +- { 0x00000000, 0x00601811, 0x2bb }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022b, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1f8 }, +- { 0x00000010, 0x00221628, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a29, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x0020480a, 0x000 }, +- { 0x00000000, 0x00202c11, 0x000 }, +- { 0x00000010, 0x00221623, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a24, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x00731503, 0x205 }, +- { 0x00000000, 0x00201805, 0x000 }, +- { 0x00000000, 0x00731524, 0x205 }, +- { 0x00000000, 0x002d14c5, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00000000, 0x00202003, 0x000 }, +- { 0x00000000, 0x00802404, 0x000 }, +- { 0x0000000f, 0x00210225, 0x000 }, +- { 0x00000000, 0x14c00000, 0x67b }, +- { 0x00000000, 0x002b1405, 0x000 }, +- { 0x00000001, 0x00901625, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00294a22, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a21, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000ffff, 0x40281220, 0x000 }, +- { 0x00000010, 0xc0211a20, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211620, 0x000 }, +- { 0x00000000, 0x00741465, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00000001, 0x00330621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x219 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x212 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x638 }, +- { 0x00000000, 0x0040040f, 0x213 }, +- { 0x00000000, 0x00600000, 0x624 }, +- { 0x00000000, 0x00600000, 0x638 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00000000, 0x00600000, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x232 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x236 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x236 }, +- { 0x00000000, 0xc0404800, 0x233 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x00600411, 0x2fb }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x624 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000018, 0x40210a20, 0x000 }, +- { 0x00000003, 0x002f0222, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x24c }, +- { 0x00000014, 0x0020222d, 0x000 }, +- { 0x00080101, 0x00292228, 0x000 }, +- { 0x00000014, 0x00203628, 0x000 }, +- { 0x0000a30c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x251 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000010, 0x00600411, 0x315 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00000000, 0x00600000, 0x27c }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000001, 0x00211e27, 0x000 }, +- { 0x00000000, 0x14e00000, 0x26a }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x0000ffff, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00341c27, 0x000 }, +- { 0x00000000, 0x12c00000, 0x25f }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e5, 0x000 }, +- { 0x00000000, 0x08c00000, 0x262 }, +- { 0x00000000, 0x00201407, 0x000 }, +- { 0x00000012, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00211e27, 0x000 }, +- { 0x00000000, 0x00341c47, 0x000 }, +- { 0x00000000, 0x12c00000, 0x267 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f00e6, 0x000 }, +- { 0x00000000, 0x08c00000, 0x26a }, +- { 0x00000000, 0x00201807, 0x000 }, +- { 0x00000000, 0x00600000, 0x2c1 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000000, 0x00342023, 0x000 }, +- { 0x00000000, 0x12c00000, 0x272 }, +- { 0x00000000, 0x00342044, 0x000 }, +- { 0x00000000, 0x12c00000, 0x271 }, +- { 0x00000016, 0x00404811, 0x276 }, +- { 0x00000018, 0x00404811, 0x276 }, +- { 0x00000000, 0x00342044, 0x000 }, +- { 0x00000000, 0x12c00000, 0x275 }, +- { 0x00000017, 0x00404811, 0x276 }, +- { 0x00000019, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0x00604411, 0x2e9 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x256 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000010, 0x40210620, 0x000 }, +- { 0x0000ffff, 0xc0280a20, 0x000 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0881a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x67c }, +- { 0x00000000, 0x00600000, 0x624 }, +- { 0x00000000, 0xc0600000, 0x2a3 }, +- { 0x00000005, 0x00200a2d, 0x000 }, +- { 0x00000008, 0x00220a22, 0x000 }, +- { 0x0000002b, 0x00201a2d, 0x000 }, +- { 0x0000001c, 0x00201e2d, 0x000 }, +- { 0x00007000, 0x00281e27, 0x000 }, +- { 0x00000000, 0x00311ce6, 0x000 }, +- { 0x0000002a, 0x00201a2d, 0x000 }, +- { 0x0000000c, 0x00221a26, 0x000 }, +- { 0x00000000, 0x002f00e6, 0x000 }, +- { 0x00000000, 0x06e00000, 0x292 }, +- { 0x00000000, 0x00201c11, 0x000 }, +- { 0x00000000, 0x00200c11, 0x000 }, +- { 0x0000002b, 0x00203623, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00691ce2, 0x12f }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x29d }, +- { 0x00000001, 0x00333e2f, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x0000001c, 0x00403627, 0x000 }, +- { 0x0000000c, 0xc0220a20, 0x000 }, +- { 0x00000029, 0x00203622, 0x000 }, +- { 0x00000028, 0xc0403620, 0x000 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000009, 0x00204811, 0x000 }, +- { 0xa1000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002c1ce3, 0x000 }, +- { 0x00000021, 0x00203627, 0x000 }, +- { 0x00000022, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x002c1ce4, 0x000 }, +- { 0x00000022, 0x00203627, 0x000 }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120a3, 0x000 }, +- { 0x00000000, 0x002d1d07, 0x000 }, +- { 0x00000023, 0x00203627, 0x000 }, +- { 0x00000024, 0x00201e2d, 0x000 }, +- { 0x00000000, 0x003120c4, 0x000 }, +- { 0x00000000, 0x002d1d07, 0x000 }, +- { 0x00000024, 0x00803627, 0x000 }, +- { 0x00000021, 0x00203623, 0x000 }, +- { 0x00000022, 0x00203624, 0x000 }, +- { 0x00000000, 0x00311ca3, 0x000 }, +- { 0x00000023, 0x00203627, 0x000 }, +- { 0x00000000, 0x00311cc4, 0x000 }, +- { 0x00000024, 0x00803627, 0x000 }, +- { 0x0000001a, 0x00203627, 0x000 }, +- { 0x0000001b, 0x00203628, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 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0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x5a2 }, +- { 0x0000a2d3, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d3, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x0000a2c3, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204807, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a2c2, 0x00604411, 0x67c }, +- { 0x0000001a, 0x00212230, 0x000 }, +- { 0x00000006, 0x00222630, 0x000 }, +- { 0x00042004, 0x00604411, 0x67c }, +- { 0x0000a2c7, 0x00204411, 0x000 }, +- { 0x00000000, 0x003048e9, 0x000 }, +- { 0x00000000, 0x00e00000, 0x5b1 }, +- { 0x0000a2d4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404808, 0x000 }, +- { 0x0000a2d4, 0x00204411, 0x000 }, +- { 0x00000001, 0x00504a28, 0x000 }, +- { 0x85000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x0000304a, 0x00204411, 0x000 }, +- { 0x01000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00400000, 0x5b7 }, +- { 0xa4000000, 0xc0204411, 0x000 }, +- { 0x00000000, 0xc0404800, 0x000 }, +- { 0x00000000, 0xc0600000, 0x5bc }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000002c, 0x00203621, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0230, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x5c3 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000030, 0x00403621, 0x5d6 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00007e00, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x5d6 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004a092, 0x00604411, 0x67c }, +- { 0x00000031, 0x00203630, 0x000 }, +- { 0x0004a093, 0x00604411, 0x67c }, +- { 0x00000032, 0x00203630, 0x000 }, +- { 0x0004a2b6, 0x00604411, 0x67c }, +- { 0x00000033, 0x00203630, 0x000 }, +- { 0x0004a2ba, 0x00604411, 0x67c }, +- { 0x00000034, 0x00203630, 0x000 }, +- { 0x0004a2be, 0x00604411, 0x67c }, +- { 0x00000035, 0x00203630, 0x000 }, +- { 0x0004a2c2, 0x00604411, 0x67c }, +- { 0x00000036, 0x00203630, 0x000 }, +- { 0x00042004, 0x00604411, 0x67c }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x0000003f, 0x00204811, 0x000 }, +- { 0x00000005, 0x00204811, 0x000 }, +- { 0x0000a1f4, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x88000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000001, 0x002f0230, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x61f }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x61f }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00007e00, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x5f8 }, +- { 0x0000a092, 0x00204411, 0x000 }, +- { 0x00000031, 0x00204a2d, 0x000 }, +- { 0x0000a093, 0x00204411, 0x000 }, +- { 0x00000032, 0x00204a2d, 0x000 }, +- { 0x0000a2b6, 0x00204411, 0x000 }, +- { 0x00000033, 0x00204a2d, 0x000 }, +- { 0x0000a2ba, 0x00204411, 0x000 }, +- { 0x00000034, 0x00204a2d, 0x000 }, +- { 0x0000a2be, 0x00204411, 0x000 }, +- { 0x00000035, 0x00204a2d, 0x000 }, +- { 0x0000a2c2, 0x00204411, 0x000 }, +- { 0x00000036, 0x00204a2d, 0x000 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x000001ff, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x61e }, +- { 0x00000000, 0x00210221, 0x000 }, +- { 0x00000000, 0x14c00000, 0x601 }, +- { 0x0004a003, 0x00604411, 0x67c }, +- { 0x0000a003, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000001, 0x00210621, 0x000 }, +- { 0x00000000, 0x14c00000, 0x606 }, +- { 0x0004a010, 0x00604411, 0x67c }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00000001, 0x00210621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x61e }, +- { 0x0004a011, 0x00604411, 0x67c }, +- { 0x0000a011, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a012, 0x00604411, 0x67c }, +- { 0x0000a012, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a013, 0x00604411, 0x67c }, +- { 0x0000a013, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a014, 0x00604411, 0x67c }, +- { 0x0000a014, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a015, 0x00604411, 0x67c }, +- { 0x0000a015, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a016, 0x00604411, 0x67c }, +- { 0x0000a016, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x0004a017, 0x00604411, 0x67c }, +- { 0x0000a017, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204810, 0x000 }, +- { 0x00042004, 0x00604411, 0x67c }, +- { 0x0000002c, 0x0080062d, 0x000 }, +- { 0xff000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000002, 0x00804811, 0x000 }, +- { 0x00000000, 0x0ee00000, 0x630 }, +- { 0x00000030, 0x0020062d, 0x000 }, +- { 0x00000002, 0x00280621, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x62e }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x67c }, +- { 0x00001000, 0x00200811, 0x000 }, +- { 0x0000002b, 0x00203622, 0x000 }, +- { 0x00000000, 0x00600000, 0x634 }, +- { 0x00000000, 0x00600000, 0x5bc }, +- { 0x98000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00804811, 0x000 }, +- { 0x00000000, 0xc0600000, 0x634 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000a2a4, 0x00204411, 0x000 }, +- { 0x00000022, 0x00204811, 0x000 }, +- { 0x89000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00404811, 0x620 }, +- { 0x97000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x8a000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00404811, 0x620 }, +- { 0x00000000, 0x00600000, 0x64d }, +- { 0x0001a2a4, 0xc0204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36a }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x09800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x67c }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x000 }, +- { 0x00000004, 0x00404c11, 0x647 }, +- { 0x00000000, 0x00400000, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000004, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffffb, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000008, 0x00291e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0xfffffff7, 0x00281e27, 0x000 }, +- { 0x00000017, 0x00803627, 0x000 }, +- { 0x0001a2a4, 0x00204411, 0x000 }, +- { 0x00000016, 0x00604811, 0x36a }, +- { 0x00002010, 0x00204411, 0x000 }, +- { 0x00010000, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x01800000, 0x00204811, 0x000 }, +- { 0xffffffff, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0004217f, 0x00604411, 0x67c }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x67b }, +- { 0x00000010, 0x00404c11, 0x661 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x38c00000, 0x000 }, +- { 0x0000001d, 0x00200a2d, 0x000 }, +- { 0x0000001e, 0x00200e2d, 0x000 }, +- { 0x0000001f, 0x0020122d, 0x000 }, +- { 0x00000020, 0x0020162d, 0x000 }, +- { 0x00002169, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000004, 0x00301224, 0x000 }, +- { 0x00000000, 0x002f0064, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x67a }, +- { 0x00000003, 0x00281a22, 0x000 }, +- { 0x00000008, 0x00221222, 0x000 }, +- { 0xfffff000, 0x00281224, 0x000 }, +- { 0x00000000, 0x002910c4, 0x000 }, +- { 0x0000001f, 0x00403624, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x67c }, +- { 0x9f000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x67f }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x1ac00000, 0x681 }, +- { 0x9e000000, 0x00204411, 0x000 }, +- { 0xcafebabe, 0x00204811, 0x000 }, +- { 0x00000000, 0x1ae00000, 0x684 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0001a1fd, 0xc0204411, 0x000 }, +- { 0x00000021, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000024, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000022, 0x0020222d, 0x000 }, +- { 0x0000ffff, 0x00282228, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000023, 0x00201e2d, 0x000 }, +- { 0x00000010, 0x00221e27, 0x000 }, +- { 0x00000000, 0x00294907, 0x000 }, +- { 0x00000000, 0x00404811, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x014204f5, 0x05b30250, 0x000 }, +- { 0x01c30168, 0x043505b3, 0x000 }, +- { 0x02250209, 0x02500151, 0x000 }, +- { 0x02230245, 0x02a00241, 0x000 }, +- { 0x03cd05b3, 0x05b305b3, 0x000 }, +- { 0x063c063d, 0x031f05b3, 0x000 }, +- { 0x05b305b8, 0x03200340, 0x000 }, +- { 0x032a0282, 0x03420334, 0x000 }, +- { 0x05b305b3, 0x05b305b3, 0x000 }, +- { 0x05b30544, 0x05b305b3, 0x000 }, +- { 0x03b205b3, 0x04ae0344, 0x000 }, +- { 0x048d0443, 0x043305b3, 0x000 }, +- { 0x04c305b3, 0x043704d0, 0x000 }, +- { 0x044304fa, 0x03510371, 0x000 }, +- { 0x05b305b3, 0x05b305b3, 0x000 }, +- { 0x05b305b3, 0x05b305b3, 0x000 }, +- { 0x05b305b3, 0x063205ba, 0x000 }, +- { 0x05b305b3, 0x000705b3, 0x000 }, +- { 0x05b305b3, 0x05b305b3, 0x000 }, +- { 0x05b305b3, 0x05b305b3, 0x000 }, +- { 0x03ee03e3, 0x03fe03fc, 0x000 }, +- { 0x04040400, 0x04020406, 0x000 }, +- { 0x0412040e, 0x041a0416, 0x000 }, +- { 0x0422041e, 0x042a0426, 0x000 }, +- { 0x05b305b3, 0x042e05b3, 0x000 }, +- { 0x05b305b3, 0x05b305b3, 0x000 }, +- { 0x05b305b3, 0x05b305b3, 0x000 }, +- { 0x00020668, 0x06860006, 0x000 }, +-}; +- +-static const u32 RV670_pfp_microcode[] = { +-0xca0400, +-0xa00000, +-0x7e828b, +-0x7c038b, +-0x8001b8, +-0x7c038b, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xc41838, +-0xca2400, +-0xca2800, +-0x9581a8, +-0xc41c3a, +-0xc3c000, +-0xca0800, +-0xca0c00, +-0x7c744b, +-0xc20005, +-0x99c000, +-0xc41c3a, +-0x7c744c, +-0xc0fff0, +-0x042c04, +-0x309002, +-0x7d2500, +-0x351402, +-0x7d350b, +-0x255403, +-0x7cd580, +-0x259c03, +-0x95c004, +-0xd5001b, +-0x7eddc1, +-0x7d9d80, +-0xd6801b, +-0xd5801b, +-0xd4401e, +-0xd5401e, +-0xd6401e, +-0xd6801e, +-0xd4801e, +-0xd4c01e, +-0x9783d3, +-0xd5c01e, +-0xca0800, +-0x80001a, +-0xca0c00, +-0xe4011e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xe4013e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca1800, +-0xd4401e, +-0xd5801e, +-0x800053, +-0xd40075, +-0xd4401e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd48019, +-0xd4c018, +-0xd50017, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xe2001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0xd48060, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xd48061, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xca0c00, +-0xd4401e, +-0xd48016, +-0xd4c016, +-0xd4801e, +-0x8001b8, +-0xd4c01e, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x948004, +-0xca1400, +-0xe420f3, +-0xd42013, +-0xd56065, +-0xd4e01c, +-0xd5201c, +-0xd5601c, +-0x800000, +-0x062001, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9483f7, +-0xca1400, +-0xe420f3, +-0x800079, +-0xd42013, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9883ef, +-0xca1400, +-0xd40064, +-0x80008d, +-0x000000, +-0xc41432, +-0xc61843, +-0xc4082f, +-0x954005, +-0xc40c30, +-0xd4401e, +-0x800000, +-0xee001e, +-0x9583f5, +-0xc41031, +-0xd44033, +-0xd52065, +-0xd4a01c, +-0xd4e01c, +-0xd5201c, +-0xe4015e, +-0xd4001e, +-0x800000, +-0x062001, +-0xca1800, +-0x0a2001, +-0xd60076, +-0xc40836, +-0x988007, +-0xc61045, +-0x950110, +-0xd4001f, +-0xd46062, +-0x800000, +-0xd42062, +-0xcc3835, +-0xcc1433, +-0x8401bb, +-0xd40072, +-0xd5401e, +-0x800000, +-0xee001e, +-0xe2001a, +-0x8401bb, +-0xe2001a, +-0xcc104b, +-0xcc0447, +-0x2c9401, +-0x7d098b, +-0x984005, +-0x7d15cb, +-0xd4001a, +-0x8001b8, +-0xd4006d, +-0x344401, +-0xcc0c48, +-0x98403a, +-0xcc2c4a, +-0x958004, +-0xcc0449, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0x282801, +-0x8400f0, +-0xcc1003, +-0x98801b, +-0x04380c, +-0x8400f0, +-0xcc1003, +-0x988017, +-0x043808, +-0x8400f0, +-0xcc1003, +-0x988013, +-0x043804, +-0x8400f0, +-0xcc1003, +-0x988014, +-0xcc104c, +-0x9a8009, +-0xcc144d, +-0x9840dc, +-0xd4006d, +-0xcc1848, +-0xd5001a, +-0xd5401a, +-0x8000c9, +-0xd5801a, +-0x96c0d5, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0x9ac003, +-0xd4006d, +-0xd4006e, +-0x800000, +-0xec007f, +-0x9ac0cc, +-0xd4006d, +-0x8001b8, +-0xd4006e, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0x7d9103, +-0x7dd583, +-0x7d190c, +-0x35cc1f, +-0x35701f, +-0x7cf0cb, +-0x7cd08b, +-0x880000, +-0x7e8e8b, +-0x95c004, +-0xd4006e, +-0x8001b8, +-0xd4001a, +-0xd4c01a, +-0xcc0803, +-0xcc0c03, +-0xcc1003, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0xcc2403, +-0xcc2803, +-0x35c41f, +-0x36b01f, +-0x7c704b, +-0x34f01f, +-0x7c704b, +-0x35701f, +-0x7c704b, +-0x7d8881, +-0x7dccc1, +-0x7e5101, +-0x7e9541, +-0x7c9082, +-0x7cd4c2, +-0x7c848b, +-0x9ac003, +-0x7c8c8b, +-0x2c8801, +-0x98809e, +-0xd4006d, +-0x98409c, +-0xd4006e, +-0xcc084c, +-0xcc0c4d, +-0xcc1048, +-0xd4801a, +-0xd4c01a, +-0x800101, +-0xd5001a, +-0xcc0832, +-0xd40032, +-0x9482d9, +-0xca0c00, +-0xd4401e, +-0x800000, +-0xd4001e, +-0xe4011e, +-0xd4001e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd4401e, +-0xca1400, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xd5401e, +-0xd54034, +-0x800000, +-0xee001e, +-0x280404, +-0xe2001a, +-0xe2001a, +-0xd4401a, +-0xca3800, +-0xcc0803, +-0xcc0c03, +-0xcc0c03, +-0xcc0c03, +-0x9882bd, +-0x000000, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0400, +-0xc2ff00, +-0xcc0834, +-0xc13fff, +-0x7c74cb, +-0x7cc90b, +-0x7d010f, +-0x9902b0, +-0x7c738b, +-0x8401bb, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0800, +-0x281900, +-0x7d898b, +-0x958014, +-0x281404, +-0xca0c00, +-0xca1000, +-0xca1c00, +-0xca2400, +-0xe2001f, +-0xd4c01a, +-0xd5001a, +-0xd5401a, +-0xcc1803, +-0xcc2c03, +-0xcc2c03, +-0xcc2c03, +-0x7da58b, +-0x7d9c47, +-0x984297, +-0x000000, +-0x800161, +-0xd4c01a, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0x248c06, +-0x0ccc06, +-0x98c006, +-0xcc104e, +-0x990004, +-0xd40073, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xca0800, +-0xca0c00, +-0x34d018, +-0x251001, +-0x950021, +-0xc17fff, +-0xca1000, +-0xca1400, +-0xca1800, +-0xd4801d, +-0xd4c01d, +-0x7db18b, +-0xc14202, +-0xc2c001, +-0xd5801d, +-0x34dc0e, +-0x7d5d4c, +-0x7f734c, +-0xd7401e, +-0xd5001e, +-0xd5401e, +-0xc14200, +-0xc2c000, +-0x099c01, +-0x31dc10, +-0x7f5f4c, +-0x7f734c, +-0x042802, +-0x7d8380, +-0xd5a86f, +-0xd58066, +-0xd7401e, +-0xec005e, +-0xc82402, +-0xc82402, +-0x8001b8, +-0xd60076, +-0xd4401e, +-0xd4801e, +-0xd4c01e, +-0x800000, +-0xee001e, +-0x800000, +-0xee001f, +-0xd4001f, +-0x800000, +-0xd4001f, +-0xd4001f, +-0x880000, +-0xd4001f, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x010171, +-0x020178, +-0x03008f, +-0x04007f, +-0x050003, +-0x06003f, +-0x070032, +-0x08012c, +-0x090046, +-0x0a0036, +-0x1001b6, +-0x1700a2, +-0x22013a, +-0x230149, +-0x2000b4, +-0x240125, +-0x27004d, +-0x28006a, +-0x2a0060, +-0x2b0052, +-0x2f0065, +-0x320087, +-0x34017f, +-0x3c0156, +-0x3f0072, +-0x41018c, +-0x44012e, +-0x550173, +-0x56017a, +-0x60000b, +-0x610034, +-0x620038, +-0x630038, +-0x640038, +-0x650038, +-0x660038, +-0x670038, +-0x68003a, +-0x690041, +-0x6a0048, +-0x6b0048, +-0x6c0048, +-0x6d0048, +-0x6e0048, +-0x6f0048, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-}; +- +-static const u32 RS780_cp_microcode[][3] = { +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x0000ffff, 0x00284621, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x00000000, 0x00e00000, 0x000 }, +- { 0x00010000, 0xc0294620, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x00000000, 0x00a0000a, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00042004, 0x00604411, 0x622 }, +- { 0x00000000, 0x00600000, 0x5d1 }, +- { 0x00000000, 0x00600000, 0x5de }, +- { 0x00000000, 0xc0200800, 0x000 }, +- { 0x00000f00, 0x00281622, 0x000 }, +- { 0x00000008, 0x00211625, 0x000 }, +- { 0x00000018, 0x00203625, 0x000 }, +- { 0x8d000000, 0x00204411, 0x000 }, +- { 0x00000004, 0x002f0225, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x018 }, +- { 0x00412000, 0x00404811, 0x019 }, +- { 0x00422000, 0x00204811, 0x000 }, +- { 0x8e000000, 0x00204411, 0x000 }, +- { 0x00000028, 0x00204a2d, 0x000 }, +- { 0x90000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204805, 0x000 }, +- { 0x0000000c, 0x00211622, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000019, 0x00211a22, 0x000 }, +- { 0x00000004, 0x00281a26, 0x000 }, +- { 0x00000000, 0x002914c5, 0x000 }, +- { 0x00000019, 0x00203625, 0x000 }, +- { 0x00000000, 0x003a1402, 0x000 }, +- { 0x00000016, 0x00211625, 0x000 }, +- { 0x00000003, 0x00281625, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0xfffffffc, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002914a3, 0x000 }, +- { 0x00000017, 0x00203625, 0x000 }, +- { 0x00008000, 0x00280e22, 0x000 }, +- { 0x00000007, 0x00220e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x20000000, 0x00280e22, 0x000 }, +- { 0x00000006, 0x00210e23, 0x000 }, +- { 0x00000000, 0x0029386e, 0x000 }, +- { 0x00000000, 0x00220222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x038 }, +- { 0x00000000, 0x2ee00000, 0x035 }, +- { 0x00000000, 0x2ce00000, 0x037 }, +- { 0x00000000, 0x00400e2d, 0x039 }, +- { 0x00000008, 0x00200e2d, 0x000 }, +- { 0x00000009, 0x0040122d, 0x046 }, +- { 0x00000001, 0x00400e2d, 0x039 }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x03e }, +- { 0x00000008, 0x00401c11, 0x041 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x0000000f, 0x00281e27, 0x000 }, +- { 0x00000003, 0x00221e27, 0x000 }, +- { 0x7fc00000, 0x00281a23, 0x000 }, +- { 0x00000014, 0x00211a26, 0x000 }, +- { 0x00000001, 0x00331a26, 0x000 }, +- { 0x00000008, 0x00221a26, 0x000 }, +- { 0x00000000, 0x00290cc7, 0x000 }, +- { 0x00000027, 0x00203624, 0x000 }, +- { 0x00007f00, 0x00281221, 0x000 }, +- { 0x00001400, 0x002f0224, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x04b }, +- { 0x00000001, 0x00290e23, 0x000 }, +- { 0x0000000e, 0x00203623, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfff80000, 0x00294a23, 0x000 }, +- { 0x00000000, 0x003a2c02, 0x000 }, +- { 0x00000002, 0x00220e2b, 0x000 }, +- { 0xfc000000, 0x00280e23, 0x000 }, +- { 0x0000000f, 0x00203623, 0x000 }, +- { 0x00001fff, 0x00294a23, 0x000 }, +- { 0x00000027, 0x00204a2d, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000029, 0x00200e2d, 0x000 }, +- { 0x060a0200, 0x00294a23, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000001, 0x00210222, 0x000 }, +- { 0x00000000, 0x14e00000, 0x061 }, +- { 0x00000000, 0x2ee00000, 0x05f }, +- { 0x00000000, 0x2ce00000, 0x05e }, +- { 0x00000000, 0x00400e2d, 0x062 }, +- { 0x00000001, 0x00400e2d, 0x062 }, +- { 0x0000000a, 0x00200e2d, 0x000 }, +- { 0x0000000b, 0x0040122d, 0x06a }, +- { 0x00000000, 0xc0200c00, 0x000 }, +- { 0x003ffffc, 0x00281223, 0x000 }, +- { 0x00000002, 0x00221224, 0x000 }, +- { 0x7fc00000, 0x00281623, 0x000 }, +- { 0x00000014, 0x00211625, 0x000 }, +- { 0x00000001, 0x00331625, 0x000 }, +- { 0x80000000, 0x00280e23, 0x000 }, +- { 0x00000000, 0x00290ca3, 0x000 }, +- { 0x3ffffc00, 0x00290e23, 0x000 }, +- { 0x0000001f, 0x00211e23, 0x000 }, +- { 0x00000000, 0x14e00000, 0x06d }, +- { 0x00000100, 0x00401c11, 0x070 }, +- { 0x0000000d, 0x00201e2d, 0x000 }, +- { 0x000000f0, 0x00281e27, 0x000 }, +- { 0x00000004, 0x00221e27, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x0000000d, 0x00204811, 0x000 }, +- { 0xfffff0ff, 0x00281a30, 0x000 }, +- { 0x0000a028, 0x00204411, 0x000 }, +- { 0x00000000, 0x002948e6, 0x000 }, +- { 0x0000a018, 0x00204411, 0x000 }, +- { 0x3fffffff, 0x00284a23, 0x000 }, +- { 0x0000a010, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204804, 0x000 }, +- { 0x00000030, 0x0020162d, 0x000 }, +- { 0x00000002, 0x00291625, 0x000 }, +- { 0x00000030, 0x00203625, 0x000 }, +- { 0x00000025, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a3, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x083 }, +- { 0x00000026, 0x0020162d, 0x000 }, +- { 0x00000000, 0x002f00a4, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x084 }, +- { 0x00000000, 0x00400000, 0x08a }, +- { 0x00000025, 0x00203623, 0x000 }, +- { 0x00000026, 0x00203624, 0x000 }, +- { 0x00000017, 0x00201e2d, 0x000 }, +- { 0x00000002, 0x00210227, 0x000 }, +- { 0x00000000, 0x14e00000, 0x08a }, +- { 0x00000000, 0x00600000, 0x5ff }, +- { 0x00000000, 0x00600000, 0x5f3 }, +- { 0x00000002, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x08d }, +- { 0x00000012, 0xc0403620, 0x093 }, +- { 0x00000000, 0x2ee00000, 0x091 }, +- { 0x00000000, 0x2ce00000, 0x090 }, +- { 0x00000002, 0x00400e2d, 0x092 }, +- { 0x00000003, 0x00400e2d, 0x092 }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000012, 0x00203623, 0x000 }, +- { 0x00000003, 0x00210e22, 0x000 }, +- { 0x00000000, 0x14c00000, 0x098 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000000, 0xc0404800, 0x0a0 }, +- { 0x0000a00c, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x2ee00000, 0x09e }, +- { 0x00000000, 0x2ce00000, 0x09d }, +- { 0x00000002, 0x00400e2d, 0x09f }, +- { 0x00000003, 0x00400e2d, 0x09f }, +- { 0x0000000c, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x00204803, 0x000 }, +- { 0x00000000, 0x003a0c02, 0x000 }, +- { 0x003f0000, 0x00280e23, 0x000 }, +- { 0x00000010, 0x00210e23, 0x000 }, +- { 0x00000011, 0x00203623, 0x000 }, +- { 0x0000001e, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0a7 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x0000001f, 0x0021022b, 0x000 }, +- { 0x00000000, 0x14c00000, 0x0aa }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000008, 0x00210e2b, 0x000 }, +- { 0x0000007f, 0x00280e23, 0x000 }, +- { 0x00000000, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x0e1 }, +- { 0x00000000, 0x27000000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000001, 0x002f0223, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x0b3 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x0000000c, 0x00221e30, 0x000 }, +- { 0x99800000, 0x00204411, 0x000 }, +- { 0x00000004, 0x0020122d, 0x000 }, +- { 0x00000008, 0x00221224, 0x000 }, +- { 0x00000010, 0x00201811, 0x000 }, +- { 0x00000000, 0x00291ce4, 0x000 }, +- { 0x00000000, 0x00604807, 0x12f }, +- { 0x9b000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x9c000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x0033146f, 0x000 }, +- { 0x00000001, 0x00333e23, 0x000 }, +- { 0x00000000, 0xd9004800, 0x000 }, +- { 0x00000000, 0x00203c05, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 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0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000217c, 0x00204411, 0x000 }, +- { 0x00800000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204806, 0x000 }, +- { 0x00000008, 0x00214a27, 0x000 }, +- { 0x00000000, 0x17000000, 0x000 }, +- { 0x0004217f, 0x00604411, 0x622 }, +- { 0x0000001f, 0x00210230, 0x000 }, +- { 0x00000000, 0x14c00000, 0x621 }, +- { 0x00000004, 0x00404c11, 0x135 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x000021f8, 0x00204411, 0x000 }, +- { 0x0000001c, 0x00204811, 0x000 }, +- { 0x000421f9, 0x00604411, 0x622 }, +- { 0x00000011, 0x00210230, 0x000 }, +- { 0x00000000, 0x14e00000, 0x13c }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40280620, 0x000 }, +- { 0x00000010, 0xc0210a20, 0x000 }, +- { 0x00000000, 0x00341461, 0x000 }, +- { 0x00000000, 0x00741882, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x147 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x160 }, +- { 0x00000010, 0x40210e20, 0x000 }, +- { 0x0000ffff, 0xc0281220, 0x000 }, +- { 0x00000010, 0x40211620, 0x000 }, +- { 0x0000ffff, 0xc0681a20, 0x2bb }, +- { 0x0001a1fd, 0x00604411, 0x2e0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x158 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000001, 0x00300a2f, 0x000 }, +- { 0x00000001, 0x00210a22, 0x000 }, +- { 0x00000003, 0x00384a22, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600000, 0x18f }, +- { 0x00000000, 0x00600000, 0x1a0 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00202c08, 0x000 }, +- { 0x00000000, 0x00202411, 0x000 }, +- { 0x00000000, 0x00202811, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x00000016, 0x00204811, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00204811, 0x000 }, +- { 0x93800000, 0x00204411, 0x000 }, +- { 0x00000002, 0x00221e29, 0x000 }, +- { 0x00000000, 0x007048eb, 0x19c }, +- { 0x00000000, 0x00600000, 0x2bb }, +- { 0x00000001, 0x40330620, 0x000 }, +- { 0x00000000, 0xc0302409, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x2a3 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ae00000, 0x181 }, +- { 0x00000000, 0x00600000, 0x13a }, +- { 0x00000000, 0x00400000, 0x186 }, +- { 0x95000000, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x186 }, +- { 0x00000000, 0xc0204800, 0x000 }, +- { 0x00000001, 0x00530621, 0x182 }, +- { 0x92000000, 0x00204411, 0x000 }, +- { 0x00000000, 0xc0604800, 0x197 }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000011, 0x0020062d, 0x000 }, +- { 0x00000000, 0x0078042a, 0x2fb }, +- { 0x00000000, 0x00202809, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x174 }, +- { 0x00000000, 0xc0400400, 0x001 }, +- { 0x00000210, 0x00600411, 0x315 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x194 }, +- { 0x00000015, 0xc0203620, 0x000 }, +- { 0x00000016, 0xc0203620, 0x000 }, +- { 0x3f800000, 0x00200411, 0x000 }, +- { 0x46000000, 0x00600811, 0x1b2 }, +- { 0x00000000, 0x00800000, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0cc00000, 0x19b }, +- { 0x00000001, 0x00804811, 0x000 }, +- { 0x00000021, 0x00804811, 0x000 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000ffff, 0x40281620, 0x000 }, +- { 0x00000010, 0xc0811a20, 0x000 }, +- { 0x81000000, 0x00204411, 0x000 }, +- { 0x00000006, 0x00204811, 0x000 }, +- { 0x00000008, 0x00221e30, 0x000 }, +- { 0x00000029, 0x00201a2d, 0x000 }, +- { 0x0000e000, 0x00204411, 0x000 }, +- { 0xfffbff09, 0x00204811, 0x000 }, +- { 0x0000000f, 0x0020222d, 0x000 }, +- { 0x00001fff, 0x00294a28, 0x000 }, +- { 0x00000006, 0x0020222d, 0x000 }, +- { 0x00000000, 0x002920e8, 0x000 }, +- { 0x00000000, 0x00204808, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x060a0200, 0x00294a26, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000100, 0x00201811, 0x000 }, +- { 0x00000008, 0x00621e28, 0x12f }, +- { 0x00000008, 0x00822228, 0x000 }, +- { 0x0002c000, 0x00204411, 0x000 }, +- { 0x00000015, 0x00600e2d, 0x1bd }, +- { 0x00000016, 0x00600e2d, 0x1bd }, +- { 0x0000c008, 0x00204411, 0x000 }, +- { 0x00000017, 0x00200e2d, 0x000 }, +- { 0x00000000, 0x14c00000, 0x1b9 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00204801, 0x000 }, +- { 0x39000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00204811, 0x000 }, +- { 0x00000000, 0x00804802, 0x000 }, +- { 0x00000018, 0x00202e2d, 0x000 }, +- { 0x00000000, 0x003b0d63, 0x000 }, +- { 0x00000008, 0x00224a23, 0x000 }, +- { 0x00000010, 0x00224a23, 0x000 }, +- { 0x00000018, 0x00224a23, 0x000 }, +- { 0x00000000, 0x00804803, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00001000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00000007, 0x0021062f, 0x000 }, +- { 0x00000013, 0x00200a2d, 0x000 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000ffff, 0x40282220, 0x000 }, +- { 0x0000000f, 0x00262228, 0x000 }, +- { 0x00000010, 0x40212620, 0x000 }, +- { 0x0000000f, 0x00262629, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001b, 0x00204811, 0x000 }, +- { 0x00000000, 0x002f0221, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1e0 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000081, 0x00204811, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000080, 0x00201c11, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1dc }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1d8 }, +- { 0x00000001, 0x00202c11, 0x000 }, +- { 0x0000001f, 0x00280a22, 0x000 }, +- { 0x0000001f, 0x00282a2a, 0x000 }, +- { 0x00000001, 0x00530621, 0x1d1 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000002, 0x00304a2f, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x00000001, 0x00301e2f, 0x000 }, +- { 0x00000000, 0x002f0227, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0x00600000, 0x1e9 }, +- { 0x00000001, 0x00531e27, 0x1e5 }, +- { 0x0000ffff, 0x40280e20, 0x000 }, +- { 0x0000000f, 0x00260e23, 0x000 }, +- { 0x00000010, 0xc0211220, 0x000 }, +- { 0x0000000f, 0x00261224, 0x000 }, +- { 0x00000000, 0x00201411, 0x000 }, +- { 0x00000000, 0x00601811, 0x2bb }, +- { 0x0001a1fd, 0x00204411, 0x000 }, +- { 0x00000000, 0x002f022b, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x1f8 }, +- { 0x00000010, 0x00221628, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a29, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x0020480a, 0x000 }, +- { 0x00000000, 0x00202c11, 0x000 }, +- { 0x00000010, 0x00221623, 0x000 }, +- { 0xffff0000, 0x00281625, 0x000 }, +- { 0x0000ffff, 0x00281a24, 0x000 }, +- { 0x00000000, 0x002948c5, 0x000 }, +- { 0x00000000, 0x00731503, 0x205 }, +- { 0x00000000, 0x00201805, 0x000 }, +- { 0x00000000, 0x00731524, 0x205 }, +- { 0x00000000, 0x002d14c5, 0x000 }, +- { 0x00000000, 0x003008a2, 0x000 }, +- { 0x00000000, 0x00204802, 0x000 }, +- { 0x00000000, 0x00202802, 0x000 }, +- { 0x00000000, 0x00202003, 0x000 }, +- { 0x00000000, 0x00802404, 0x000 }, +- { 0x0000000f, 0x00210225, 0x000 }, +- { 0x00000000, 0x14c00000, 0x621 }, +- { 0x00000000, 0x002b1405, 0x000 }, +- { 0x00000001, 0x00901625, 0x000 }, +- { 0x00000000, 0x00600000, 0x00b }, +- { 0x00000000, 0x00600411, 0x315 }, +- { 0x00000000, 0x00200411, 0x000 }, +- { 0x00000000, 0x00600811, 0x1b2 }, +- { 0x00002256, 0x00204411, 0x000 }, +- { 0x0000001a, 0x00294a22, 0x000 }, +- { 0x00000000, 0xc0200000, 0x000 }, +- { 0x00003fff, 0x002f022f, 0x000 }, +- { 0x00000000, 0x0ce00000, 0x000 }, +- { 0x00000000, 0xc0200400, 0x000 }, +- { 0x0000225c, 0x00204411, 0x000 }, +- { 0x00000003, 0x00384a21, 0x000 }, +- { 0x0000a1fc, 0x00204411, 0x000 }, +- { 0x00000001, 0x00204811, 0x000 }, +- { 0x0000ffff, 0x40281220, 0x000 }, +- { 0x00000010, 0xc0211a20, 0x000 }, +- { 0x0000ffff, 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0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x00000000, 0x00000000, 0x000 }, +- { 0x0142050a, 0x05ba0250, 0x000 }, +- { 0x01c30168, 0x044105ba, 0x000 }, +- { 0x02250209, 0x02500151, 0x000 }, +- { 0x02230245, 0x02a00241, 0x000 }, +- { 0x03d705ba, 0x05ba05ba, 0x000 }, +- { 0x05e205e3, 0x031f05ba, 0x000 }, +- { 0x032005bf, 0x0320034a, 0x000 }, +- { 0x03340282, 0x034c033e, 0x000 }, +- { 0x05ba05ba, 0x05ba05ba, 0x000 }, +- { 0x05ba0557, 0x05ba032a, 0x000 }, +- { 0x03bc05ba, 0x04c3034e, 0x000 }, +- { 0x04a20455, 0x043f05ba, 0x000 }, +- { 0x04d805ba, 0x044304e5, 0x000 }, +- { 0x0455050f, 0x035b037b, 0x000 }, +- { 0x05ba05ba, 0x05ba05ba, 0x000 }, +- { 0x05ba05ba, 0x05ba05ba, 0x000 }, +- { 0x05ba05ba, 0x05d805c1, 0x000 }, +- { 0x05ba05ba, 0x000705ba, 0x000 }, +- { 0x05ba05ba, 0x05ba05ba, 0x000 }, +- { 0x05ba05ba, 0x05ba05ba, 0x000 }, +- { 0x03f803ed, 0x04080406, 0x000 }, +- { 0x040e040a, 0x040c0410, 0x000 }, +- { 0x041c0418, 0x04240420, 0x000 }, +- { 0x042c0428, 0x04340430, 0x000 }, +- { 0x05ba05ba, 0x043a0438, 0x000 }, +- { 0x05ba05ba, 0x05ba05ba, 0x000 }, +- { 0x05ba05ba, 0x05ba05ba, 0x000 }, +- { 0x0002060e, 0x062c0006, 0x000 }, +-}; +- +-static const u32 RS780_pfp_microcode[] = { +-0xca0400, +-0xa00000, +-0x7e828b, +-0x7c038b, +-0x8001db, +-0x7c038b, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xc41838, +-0xca2400, +-0xca2800, +-0x9581cb, +-0xc41c3a, +-0xc3c000, +-0xca0800, +-0xca0c00, +-0x7c744b, +-0xc20005, +-0x99c000, +-0xc41c3a, +-0x7c744c, +-0xc0ffe0, +-0x042c08, +-0x309002, +-0x7d2500, +-0x351402, +-0x7d350b, +-0x255407, +-0x7cd580, +-0x259c07, +-0x95c004, +-0xd5001b, +-0x7eddc1, +-0x7d9d80, +-0xd6801b, +-0xd5801b, +-0xd4401e, +-0xd5401e, +-0xd6401e, +-0xd6801e, +-0xd4801e, +-0xd4c01e, +-0x9783d3, +-0xd5c01e, +-0xca0800, +-0x80001a, +-0xca0c00, +-0xe4011e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xe4013e, +-0xd4001e, +-0x80000c, +-0xc41838, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0xca0c00, +-0x8001db, +-0xd48024, +-0xca0800, +-0x7c00c0, +-0xc81425, +-0xc81824, +-0x7c9488, +-0x7c9880, +-0xc20003, +-0xd40075, +-0x7c744c, +-0x800064, +-0xd4401e, +-0xca1800, +-0xd4401e, +-0xd5801e, +-0x800062, +-0xd40075, +-0xd4401e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd48019, +-0xd4c018, +-0xd50017, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xe2001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xd40075, +-0xd4401e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd48019, +-0xd4c018, +-0xd50017, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0x248c01, +-0xd48060, +-0x94c003, +-0x041001, +-0x041002, +-0xd50025, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xd48061, +-0xd4401e, +-0x800000, +-0xd4801e, +-0xca0800, +-0xca0c00, +-0xd4401e, +-0xd48016, +-0xd4c016, +-0xd4801e, +-0x8001db, +-0xd4c01e, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x948004, +-0xca1400, +-0xe420f3, +-0xd42013, +-0xd56065, +-0xd4e01c, +-0xd5201c, +-0xd5601c, +-0x800000, +-0x062001, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9483f7, +-0xca1400, +-0xe420f3, +-0x80009c, +-0xd42013, +-0xc60843, +-0xca0c00, +-0xca1000, +-0x9883ef, +-0xca1400, +-0xd40064, +-0x8000b0, +-0x000000, +-0xc41432, +-0xc61843, +-0xc4082f, +-0x954005, +-0xc40c30, +-0xd4401e, +-0x800000, +-0xee001e, +-0x9583f5, +-0xc41031, +-0xd44033, +-0xd52065, +-0xd4a01c, +-0xd4e01c, +-0xd5201c, +-0xe4015e, +-0xd4001e, +-0x800000, +-0x062001, +-0xca1800, +-0x0a2001, +-0xd60076, +-0xc40836, +-0x988007, +-0xc61045, +-0x950110, +-0xd4001f, +-0xd46062, +-0x800000, +-0xd42062, +-0xcc3835, +-0xcc1433, +-0x8401de, +-0xd40072, +-0xd5401e, +-0x800000, +-0xee001e, +-0xe2001a, +-0x8401de, +-0xe2001a, +-0xcc104b, +-0xcc0447, +-0x2c9401, +-0x7d098b, +-0x984005, +-0x7d15cb, +-0xd4001a, +-0x8001db, +-0xd4006d, +-0x344401, +-0xcc0c48, +-0x98403a, +-0xcc2c4a, +-0x958004, +-0xcc0449, +-0x8001db, +-0xd4001a, +-0xd4c01a, +-0x282801, +-0x840113, +-0xcc1003, +-0x98801b, +-0x04380c, +-0x840113, +-0xcc1003, +-0x988017, +-0x043808, +-0x840113, +-0xcc1003, +-0x988013, +-0x043804, +-0x840113, +-0xcc1003, +-0x988014, +-0xcc104c, +-0x9a8009, +-0xcc144d, +-0x9840dc, +-0xd4006d, +-0xcc1848, +-0xd5001a, +-0xd5401a, +-0x8000ec, +-0xd5801a, +-0x96c0d5, +-0xd4006d, +-0x8001db, +-0xd4006e, +-0x9ac003, +-0xd4006d, +-0xd4006e, +-0x800000, +-0xec007f, +-0x9ac0cc, +-0xd4006d, +-0x8001db, +-0xd4006e, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0x7d9103, +-0x7dd583, +-0x7d190c, +-0x35cc1f, +-0x35701f, +-0x7cf0cb, +-0x7cd08b, +-0x880000, +-0x7e8e8b, +-0x95c004, +-0xd4006e, +-0x8001db, +-0xd4001a, +-0xd4c01a, +-0xcc0803, +-0xcc0c03, +-0xcc1003, +-0xcc1403, +-0xcc1803, +-0xcc1c03, +-0xcc2403, +-0xcc2803, +-0x35c41f, +-0x36b01f, +-0x7c704b, +-0x34f01f, +-0x7c704b, +-0x35701f, +-0x7c704b, +-0x7d8881, +-0x7dccc1, +-0x7e5101, +-0x7e9541, +-0x7c9082, +-0x7cd4c2, +-0x7c848b, +-0x9ac003, +-0x7c8c8b, +-0x2c8801, +-0x98809e, +-0xd4006d, +-0x98409c, +-0xd4006e, +-0xcc084c, +-0xcc0c4d, +-0xcc1048, +-0xd4801a, +-0xd4c01a, +-0x800124, +-0xd5001a, +-0xcc0832, +-0xd40032, +-0x9482b6, +-0xca0c00, +-0xd4401e, +-0x800000, +-0xd4001e, +-0xe4011e, +-0xd4001e, +-0xca0800, +-0xca0c00, +-0xca1000, +-0xd4401e, +-0xca1400, +-0xd4801e, +-0xd4c01e, +-0xd5001e, +-0xd5401e, +-0xd54034, +-0x800000, +-0xee001e, +-0x280404, +-0xe2001a, +-0xe2001a, +-0xd4401a, +-0xca3800, +-0xcc0803, +-0xcc0c03, +-0xcc0c03, +-0xcc0c03, +-0x98829a, +-0x000000, +-0x8401de, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0400, +-0xc2ff00, +-0xcc0834, +-0xc13fff, +-0x7c74cb, +-0x7cc90b, +-0x7d010f, +-0x99028d, +-0x7c738b, +-0x8401de, +-0xd7a06f, +-0x800000, +-0xee001f, +-0xca0800, +-0x281900, +-0x7d898b, +-0x958014, +-0x281404, +-0xca0c00, +-0xca1000, +-0xca1c00, +-0xca2400, +-0xe2001f, +-0xd4c01a, +-0xd5001a, +-0xd5401a, +-0xcc1803, +-0xcc2c03, +-0xcc2c03, +-0xcc2c03, +-0x7da58b, +-0x7d9c47, +-0x984274, +-0x000000, +-0x800184, +-0xd4c01a, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xe4013e, +-0xd4001e, +-0xd4401e, +-0xee001e, +-0xca0400, +-0xa00000, +-0x7e828b, +-0xca0800, +-0x248c06, +-0x0ccc06, +-0x98c006, +-0xcc104e, +-0x990004, +-0xd40073, +-0xe4011e, +-0xd4001e, +-0xd4401e, +-0xd4801e, +-0x800000, +-0xee001e, +-0xca0800, +-0xca0c00, +-0x34d018, +-0x251001, +-0x950021, +-0xc17fff, +-0xca1000, +-0xca1400, +-0xca1800, +-0xd4801d, +-0xd4c01d, +-0x7db18b, +-0xc14202, +-0xc2c001, +-0xd5801d, +-0x34dc0e, +-0x7d5d4c, +-0x7f734c, +-0xd7401e, +-0xd5001e, +-0xd5401e, +-0xc14200, +-0xc2c000, +-0x099c01, +-0x31dc10, +-0x7f5f4c, +-0x7f734c, +-0x042802, +-0x7d8380, +-0xd5a86f, +-0xd58066, +-0xd7401e, +-0xec005e, +-0xc82402, +-0xc82402, +-0x8001db, +-0xd60076, +-0xd4401e, +-0xd4801e, +-0xd4c01e, +-0x800000, +-0xee001e, +-0x800000, +-0xee001f, +-0xd4001f, +-0x800000, +-0xd4001f, +-0xd4001f, +-0x880000, +-0xd4001f, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x000000, +-0x010194, +-0x02019b, +-0x0300b2, +-0x0400a2, +-0x050003, +-0x06003f, +-0x070032, +-0x08014f, +-0x090046, +-0x0a0036, +-0x1001d9, +-0x1700c5, +-0x22015d, +-0x23016c, +-0x2000d7, +-0x240148, +-0x26004d, +-0x27005c, +-0x28008d, +-0x290051, +-0x2a007e, +-0x2b0061, +-0x2f0088, +-0x3200aa, +-0x3401a2, +-0x36006f, +-0x3c0179, +-0x3f0095, +-0x4101af, +-0x440151, +-0x550196, +-0x56019d, +-0x60000b, +-0x610034, +-0x620038, +-0x630038, +-0x640038, +-0x650038, +-0x660038, +-0x670038, +-0x68003a, +-0x690041, +-0x6a0048, +-0x6b0048, +-0x6c0048, +-0x6d0048, +-0x6e0048, +-0x6f0048, +-0x7301d9, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-0x000006, +-}; +- +-static const u32 RV770_cp_microcode[] = { +-0xcc0003ea, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x80000001, +-0xd040007f, +-0x80000001, +-0xcc400041, +-0x7c40c000, +-0xc0160004, +-0x30d03fff, +-0x7d15000c, +-0xcc110000, +-0x28d8001e, +-0x31980001, +-0x28dc001f, +-0xc8200004, +-0x95c00006, +-0x7c424000, +-0xcc000062, +-0x7e56800c, +-0xcc290000, +-0xc8240004, +-0x7e26000b, +-0x95800006, +-0x7c42c000, +-0xcc000062, +-0x7ed7000c, +-0xcc310000, +-0xc82c0004, +-0x7e2e000c, +-0xcc000062, +-0x31103fff, +-0x80000001, +-0xce110000, +-0x7c40c000, +-0x80000001, +-0xcc400040, +-0x80000001, +-0xcc412257, +-0x7c418000, +-0xcc400045, +-0xcc400048, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xcc400045, +-0xcc400048, +-0x7c40c000, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xcc000045, +-0xcc000048, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x040ca1fd, +-0xc0120001, +-0xcc000045, +-0xcc000048, +-0x7cd0c00c, +-0xcc41225c, +-0xcc41a1fc, +-0xd04d0000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x80000001, +-0xcc41225d, +-0x7c408000, +-0x7c40c000, +-0xc02a0002, +-0x7c410000, +-0x7d29000c, +-0x30940001, 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+-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00010333, +-0x00100004, +-0x00170006, +-0x00210008, +-0x00270028, +-0x00280023, +-0x00290029, +-0x002a0026, +-0x002b0029, +-0x002d0038, +-0x002e003f, +-0x002f004a, +-0x0034004c, +-0x00360030, +-0x003900af, +-0x003a00d0, +-0x003b00e5, +-0x003c00fd, +-0x003d016c, +-0x003f00ad, +-0x00410338, +-0x0043036c, +-0x0044018f, +-0x004500fd, +-0x004601ad, +-0x004701ad, +-0x00480200, +-0x0049020e, +-0x004a0257, +-0x004b0284, +-0x00520261, +-0x00530273, +-0x00540289, +-0x0057029b, +-0x0060029f, +-0x006102ae, +-0x006202b8, +-0x006302c2, +-0x006402cc, +-0x006502d6, +-0x006602e0, +-0x006702ea, +-0x006802f4, +-0x006902f8, +-0x006a02fc, +-0x006b0300, +-0x006c0304, +-0x006d0308, +-0x006e030c, +-0x006f0310, +-0x00700314, +-0x00720386, +-0x0074038c, +-0x0079038a, +-0x007c031e, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-0x000f039b, +-}; +- +-static const u32 RV770_pfp_microcode[] = { +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x80000000, +-0xdc030000, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xc818000e, +-0x31980001, +-0x7c424000, +-0x95800252, +-0x7c428000, +-0xc81c001c, +-0xc037c000, +-0x7c40c000, +-0x7c410000, +-0x7cb4800b, +-0xc0360003, +-0x99c00000, +-0xc81c001c, +-0x7cb4800c, +-0x24d40002, +-0x7d654000, +-0xcd400043, +-0xce800043, +-0xcd000043, +-0xcc800040, +-0xce400040, +-0xce800040, +-0xccc00040, +-0xdc3a0000, +-0x9780ffde, +-0xcd000040, +-0x7c40c000, +-0x80000018, +-0x7c410000, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xc818000e, +-0x8000000c, +-0x31980002, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xc818000e, +-0x288c0008, +-0x30cc000f, +-0x34100001, +-0x7d0d0008, +-0x8000000c, +-0x7d91800b, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xcc4003f9, +-0x80000261, +-0xcc4003f8, +-0xc82003f8, +-0xc81c03f9, +-0xc81803fb, +-0xc037ffff, +-0x7c414000, +-0xcf41a29e, +-0x66200020, +-0x7de1c02c, +-0x7d58c008, +-0x7cdcc020, +-0x68d00020, +-0xc0360003, +-0xcc000054, +-0x7cb4800c, +-0x8000006a, +-0xcc800040, +-0x7c418000, +-0xcd81a29e, +-0xcc800040, +-0xcd800040, +-0x80000068, +-0xcc000054, +-0xc019ffff, +-0xcc800040, +-0xcd81a29e, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0xccc1a1fa, +-0xcd01a1f9, +-0xcd41a29d, +-0xccc00040, +-0xcd000040, +-0xcd400040, +-0xcc400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xcc000054, +-0xcc800040, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0xccc1a1fa, +-0xcd01a1f9, +-0xcd41a29d, +-0xccc00040, +-0xcd000040, +-0xcd400040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x7c40c000, +-0x30d00001, +-0xccc1a29f, +-0x95000003, +-0x04140001, +-0x04140002, +-0xcd4003fb, +-0xcc800040, +-0x80000000, +-0xccc00040, +-0x7c40c000, +-0xcc800040, +-0xccc1a2a2, +-0x80000000, +-0xccc00040, +-0x7c40c000, +-0x28d4001f, +-0xcc800040, +-0x95400003, +-0x7c410000, +-0xccc00057, +-0x2918001f, +-0xccc00040, +-0x95800003, +-0xcd000040, +-0xcd000058, +-0x80000261, +-0xcc00007f, +-0xc8200017, +-0xc8300022, +-0x9a000006, +-0x0e280001, +-0xc824001e, +-0x0a640001, +-0xd4001240, +-0xce400040, +-0xc036c000, +-0x96800007, +-0x37747900, +-0x041c0001, +-0xcf400040, +-0xcdc00040, +-0xcf0003fa, +-0x7c030000, +-0xca0c0010, +-0x7c410000, +-0x94c00004, +-0x7c414000, +-0xd42002c4, +-0xcde00044, +-0x9b00000b, +-0x7c418000, +-0xcc00004b, +-0xcda00049, +-0xcd200041, +-0xcd600041, +-0xcda00041, +-0x06200001, +-0xce000056, +-0x80000261, +-0xcc00007f, +-0xc8280020, +-0xc82c0021, +-0xcc000063, +-0x7eea4001, +-0x65740020, +-0x7f53402c, +-0x269c0002, +-0x7df5c020, +-0x69f80020, +-0xce80004b, +-0xce600049, +-0xcde00041, +-0xcfa00041, +-0xce600041, +-0x271c0002, +-0x7df5c020, +-0x69f80020, +-0x7db24001, +-0xcf00004b, +-0xce600049, +-0xcde00041, +-0xcfa00041, +-0x800000bd, +-0xce600041, +-0xc8200017, +-0xc8300022, +-0x9a000006, +-0x0e280001, +-0xc824001e, +-0x0a640001, +-0xd4001240, +-0xce400040, +-0xca0c0010, +-0x7c410000, +-0x94c0000b, +-0xc036c000, +-0x96800007, +-0x37747900, +-0x041c0001, +-0xcf400040, +-0xcdc00040, +-0xcf0003fa, +-0x7c030000, +-0x800000b6, +-0x7c414000, +-0xcc000048, +-0x800000ef, +-0x00000000, +-0xc8200017, +-0xc81c0023, +-0x0e240002, +-0x99c00015, +-0x7c418000, +-0x0a200001, +-0xce000056, +-0xd4000440, +-0xcc000040, +-0xc036c000, +-0xca140013, +-0x96400007, +-0x37747900, +-0xcf400040, +-0xcc000040, +-0xc83003fa, +-0x80000104, +-0xcf000022, +-0xcc000022, +-0x9540015d, +-0xcc00007f, +-0xcca00046, +-0x80000000, +-0xcc200046, +-0x80000261, +-0xcc000064, +-0xc8200017, +-0xc810001f, +-0x96000005, +-0x09100001, +-0xd4000440, +-0xcd000040, +-0xcd000022, +-0xcc800040, +-0xd0400040, +-0xc80c0025, +-0x94c0feeb, +-0xc8100008, +-0xcd000040, +-0xd4000fc0, +-0x80000000, +-0xd4000fa2, +-0x7c40c000, +-0x7c410000, +-0xccc003fd, +-0xcd0003fc, +-0xccc00042, +-0xcd000042, +-0x2914001f, +-0x29180010, +-0x31980007, +-0x3b5c0001, +-0x7d76000b, +-0x99800005, +-0x7d5e400b, +-0xcc000042, +-0x80000261, +-0xcc00004d, +-0x29980001, +-0x292c0008, +-0x9980003d, +-0x32ec0001, +-0x96000004, +-0x2930000c, +-0x80000261, +-0xcc000042, +-0x04140010, +-0xcd400042, +-0x33300001, +-0x34280001, +-0x8400015e, +-0xc8140003, +-0x9b40001b, +-0x0438000c, +-0x8400015e, +-0xc8140003, +-0x9b400017, +-0x04380008, +-0x8400015e, +-0xc8140003, +-0x9b400013, +-0x04380004, +-0x8400015e, +-0xc8140003, +-0x9b400015, +-0xc80c03fd, +-0x9a800009, +-0xc81003fc, +-0x9b000118, +-0xcc00004d, +-0x04140010, +-0xccc00042, +-0xcd000042, +-0x80000136, +-0xcd400042, +-0x96c00111, +-0xcc00004d, +-0x80000261, +-0xcc00004e, +-0x9ac00003, +-0xcc00004d, +-0xcc00004e, +-0xdf830000, +-0x80000000, +-0xd80301ff, +-0x9ac00107, +-0xcc00004d, +-0x80000261, +-0xcc00004e, +-0xc8180003, +-0xc81c0003, +-0xc8200003, +-0x7d5d4003, +-0x7da1c003, +-0x7d5d400c, +-0x2a10001f, +-0x299c001f, +-0x7d1d000b, +-0x7d17400b, +-0x88000000, +-0x7e92800b, +-0x96400004, +-0xcc00004e, +-0x80000261, +-0xcc000042, +-0x04380008, +-0xcf800042, +-0xc8080003, +-0xc80c0003, +-0xc8100003, +-0xc8140003, +-0xc8180003, +-0xc81c0003, +-0xc8240003, +-0xc8280003, +-0x29fc001f, +-0x2ab0001f, +-0x7ff3c00b, +-0x28f0001f, +-0x7ff3c00b, +-0x2970001f, +-0x7ff3c00b, +-0x7d888001, +-0x7dccc001, +-0x7e510001, +-0x7e954001, +-0x7c908002, +-0x7cd4c002, +-0x7cbc800b, +-0x9ac00003, +-0x7c8f400b, +-0x38b40001, +-0x9b4000d8, +-0xcc00004d, +-0x9bc000d6, +-0xcc00004e, +-0xc80c03fd, +-0xc81003fc, +-0xccc00042, +-0x8000016f, +-0xcd000042, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xcc400040, +-0xcc400040, +-0xcc400040, +-0x7c40c000, +-0xccc00040, +-0xccc0000d, +-0x80000000, +-0xd0400040, +-0x7c40c000, +-0x7c410000, +-0x65140020, +-0x7d4d402c, +-0x24580002, +-0x7d598020, +-0x7c41c000, +-0xcd800042, +-0x69980020, +-0xcd800042, +-0xcdc00042, +-0xc023c000, +-0x05e40002, +-0x7ca0800b, +-0x26640010, +-0x7ca4800c, +-0xcc800040, +-0xcdc00040, +-0xccc00040, +-0x95c0000e, +-0xcd000040, +-0x09dc0001, +-0xc8280003, +-0x96800008, +-0xce800040, +-0xc834001d, +-0x97400000, +-0xc834001d, +-0x26a80008, +-0x84000264, +-0xcc2b0000, +-0x99c0fff7, +-0x09dc0001, +-0xdc3a0000, +-0x97800004, +-0x7c418000, +-0x800001a3, +-0x25980002, +-0xa0000000, +-0x7d808000, +-0xc818001d, +-0x7c40c000, +-0x64d00008, +-0x95800000, +-0xc818001d, +-0xcc130000, +-0xcc800040, +-0xccc00040, +-0x80000000, +-0xcc400040, +-0xc810001f, +-0x7c40c000, +-0xcc800040, +-0x7cd1400c, +-0xcd400040, +-0x05180001, +-0x80000000, +-0xcd800022, +-0x7c40c000, +-0x64500020, +-0x84000264, +-0xcc000061, +-0x7cd0c02c, +-0xc8200017, +-0xc8d60000, +-0x99400008, +-0x7c438000, +-0xdf830000, +-0xcfa0004f, +-0x84000264, +-0xcc000062, +-0x80000000, +-0xd040007f, +-0x80000261, +-0xcc000062, +-0x84000264, +-0xcc000061, +-0xc8200017, +-0x7c40c000, +-0xc036ff00, +-0xc810000d, +-0xc0303fff, +-0x7cf5400b, +-0x7d51800b, +-0x7d81800f, +-0x99800008, +-0x7cf3800b, +-0xdf830000, +-0xcfa0004f, +-0x84000264, +-0xcc000062, +-0x80000000, +-0xd040007f, +-0x80000261, +-0xcc000062, +-0x84000264, +-0x7c40c000, +-0x28dc0008, +-0x95c00019, +-0x30dc0010, +-0x7c410000, +-0x99c00004, +-0x64540020, +-0x80000209, +-0xc91d0000, +-0x7d15002c, +-0xc91e0000, +-0x7c420000, +-0x7c424000, +-0x7c418000, +-0x7de5c00b, +-0x7de28007, +-0x9a80000e, +-0x41ac0005, +-0x9ac00000, +-0x0aec0001, +-0x30dc0010, +-0x99c00004, +-0x00000000, +-0x8000020c, +-0xc91d0000, +-0x8000020c, +-0xc91e0000, +-0xcc800040, +-0xccc00040, +-0xd0400040, +-0xc80c0025, +-0x94c0fde3, +-0xc8100008, +-0xcd000040, +-0xd4000fc0, +-0x80000000, +-0xd4000fa2, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x7c40c000, +-0x30d00006, +-0x0d100006, +-0x99000007, +-0xc8140015, +-0x99400005, +-0xcc000052, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xccc00040, +-0x80000000, +-0xd0400040, +-0x7c40c000, +-0xcc4d0000, +-0xdc3a0000, +-0x9780fdbc, +-0x04cc0001, +-0x80000243, +-0xcc4d0000, +-0x7c40c000, +-0x7c410000, +-0x29240018, +-0x32640001, +-0x9640000f, +-0xcc800040, +-0x7c414000, +-0x7c418000, +-0x7c41c000, +-0xccc00043, +-0xcd000043, +-0x31dc7fff, +-0xcdc00043, +-0xccc00040, +-0xcd000040, +-0xcd400040, +-0xcd800040, +-0x80000000, +-0xcdc00040, +-0xccc00040, +-0xcd000040, +-0x80000000, +-0xd0400040, +-0x80000000, +-0xd040007f, +-0xcc00007f, +-0x80000000, +-0xcc00007f, +-0xcc00007f, +-0x88000000, +-0xcc00007f, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00030223, +-0x0004022b, +-0x000500a0, +-0x00020003, +-0x0006003c, +-0x00070027, +-0x00080192, +-0x00090044, +-0x000a002d, +-0x0010025f, +-0x001700f1, +-0x002201d8, +-0x002301e9, +-0x0026004c, +-0x0027005f, +-0x0020011b, +-0x00280093, +-0x0029004f, +-0x002a0084, +-0x002b0065, +-0x002f008e, +-0x003200d9, +-0x00340233, +-0x00360075, +-0x0039010b, +-0x003c01fd, +-0x003f00a0, +-0x00410248, +-0x00440195, +-0x0048019e, +-0x004901c6, +-0x004a01d0, +-0x00550226, +-0x0056022e, +-0x0060000a, +-0x0061002a, +-0x00620030, +-0x00630030, +-0x00640030, +-0x00650030, +-0x00660030, +-0x00670030, +-0x00680037, +-0x0069003f, +-0x006a0047, +-0x006b0047, +-0x006c0047, +-0x006d0047, +-0x006e0047, +-0x006f0047, +-0x00700047, +-0x0073025f, +-0x007b0241, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-}; +- +-static const u32 RV730_pfp_microcode[] = { +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x80000000, +-0xdc030000, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xc818000e, +-0x31980001, +-0x7c424000, +-0x9580023a, +-0x7c428000, +-0xc81c001c, +-0xc037c000, +-0x7c40c000, +-0x7c410000, +-0x7cb4800b, +-0xc0360003, +-0x99c00000, +-0xc81c001c, +-0x7cb4800c, +-0x24d40002, +-0x7d654000, +-0xcd400043, +-0xce800043, +-0xcd000043, +-0xcc800040, +-0xce400040, +-0xce800040, +-0xccc00040, +-0xdc3a0000, +-0x9780ffde, +-0xcd000040, +-0x7c40c000, +-0x80000018, +-0x7c410000, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xc818000e, +-0x8000000c, +-0x31980002, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xc818000e, +-0x288c0008, +-0x30cc000f, +-0x34100001, +-0x7d0d0008, +-0x8000000c, +-0x7d91800b, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xcc4003f9, +-0x80000249, +-0xcc4003f8, +-0xc037ffff, +-0x7c414000, +-0xcf41a29e, +-0xc82003f8, +-0xc81c03f9, +-0x66200020, +-0xc81803fb, +-0x7de1c02c, +-0x7d58c008, +-0x7cdcc020, +-0x69100020, +-0xc0360003, +-0xcc000054, +-0x7cb4800c, +-0x80000069, +-0xcc800040, +-0x7c418000, +-0xcd81a29e, +-0xcc800040, +-0x80000067, +-0xcd800040, +-0xc019ffff, +-0xcc800040, +-0xcd81a29e, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0xccc1a1fa, +-0xcd01a1f9, +-0xcd41a29d, +-0xccc00040, +-0xcd000040, +-0xcd400040, +-0xcc400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xcc000054, +-0xcc800040, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0xccc1a1fa, +-0xcd01a1f9, +-0xcd41a29d, +-0xccc00040, +-0xcd000040, +-0xcd400040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x7c40c000, +-0x30d00001, +-0xccc1a29f, +-0x95000003, +-0x04140001, +-0x04140002, +-0xcd4003fb, +-0xcc800040, +-0x80000000, +-0xccc00040, +-0x7c40c000, +-0xcc800040, +-0xccc1a2a2, +-0x80000000, +-0xccc00040, +-0x7c40c000, +-0x28d4001f, +-0xcc800040, +-0x95400003, +-0x7c410000, +-0xccc00057, +-0x2918001f, +-0xccc00040, +-0x95800003, +-0xcd000040, +-0xcd000058, +-0x80000249, +-0xcc00007f, +-0xc8200017, +-0xc8300022, +-0x9a000006, +-0x0e280001, +-0xc824001e, +-0x0a640001, +-0xd4001240, +-0xce400040, +-0xc036c000, +-0x96800007, +-0x37747900, +-0x041c0001, +-0xcf400040, +-0xcdc00040, +-0xcf0003fa, +-0x7c030000, +-0xca0c0010, +-0x7c410000, +-0x94c00004, +-0x7c414000, +-0xd42002c4, +-0xcde00044, +-0x9b00000b, +-0x7c418000, +-0xcc00004b, +-0xcda00049, +-0xcd200041, +-0xcd600041, +-0xcda00041, +-0x06200001, +-0xce000056, +-0x80000249, +-0xcc00007f, +-0xc8280020, +-0xc82c0021, +-0xcc000063, +-0x7eea4001, +-0x65740020, +-0x7f53402c, +-0x269c0002, +-0x7df5c020, +-0x69f80020, +-0xce80004b, +-0xce600049, +-0xcde00041, +-0xcfa00041, +-0xce600041, +-0x271c0002, +-0x7df5c020, +-0x69f80020, +-0x7db24001, +-0xcf00004b, +-0xce600049, +-0xcde00041, +-0xcfa00041, +-0x800000bc, +-0xce600041, +-0xc8200017, +-0xc8300022, +-0x9a000006, +-0x0e280001, +-0xc824001e, +-0x0a640001, +-0xd4001240, +-0xce400040, +-0xca0c0010, +-0x7c410000, +-0x94c0000b, +-0xc036c000, +-0x96800007, +-0x37747900, +-0x041c0001, +-0xcf400040, +-0xcdc00040, +-0xcf0003fa, +-0x7c030000, +-0x800000b5, +-0x7c414000, +-0xcc000048, +-0x800000ee, +-0x00000000, +-0xc8200017, +-0xc81c0023, +-0x0e240002, +-0x99c00015, +-0x7c418000, +-0x0a200001, +-0xce000056, +-0xd4000440, +-0xcc000040, +-0xc036c000, +-0xca140013, +-0x96400007, +-0x37747900, +-0xcf400040, +-0xcc000040, +-0xc83003fa, +-0x80000103, +-0xcf000022, +-0xcc000022, +-0x95400146, +-0xcc00007f, +-0xcca00046, +-0x80000000, +-0xcc200046, +-0x80000249, +-0xcc000064, +-0xc8200017, +-0xc810001f, +-0x96000005, +-0x09100001, +-0xd4000440, +-0xcd000040, +-0xcd000022, +-0xcc800040, +-0xd0400040, +-0xc80c0025, +-0x94c0feec, +-0xc8100008, +-0xcd000040, +-0xd4000fc0, +-0x80000000, +-0xd4000fa2, +-0x7c40c000, +-0x7c410000, +-0xccc003fd, +-0xcd0003fc, +-0xccc00042, +-0xcd000042, +-0x2914001f, +-0x29180010, +-0x31980007, +-0x3b5c0001, +-0x7d76000b, +-0x99800005, +-0x7d5e400b, +-0xcc000042, +-0x80000249, +-0xcc00004d, +-0x29980001, +-0x292c0008, +-0x9980003d, +-0x32ec0001, +-0x96000004, +-0x2930000c, +-0x80000249, +-0xcc000042, +-0x04140010, +-0xcd400042, +-0x33300001, +-0x34280001, +-0x8400015d, +-0xc8140003, +-0x9b40001b, +-0x0438000c, +-0x8400015d, +-0xc8140003, +-0x9b400017, +-0x04380008, +-0x8400015d, +-0xc8140003, +-0x9b400013, +-0x04380004, +-0x8400015d, +-0xc8140003, +-0x9b400015, +-0xc80c03fd, +-0x9a800009, +-0xc81003fc, +-0x9b000101, +-0xcc00004d, +-0x04140010, +-0xccc00042, +-0xcd000042, +-0x80000135, +-0xcd400042, +-0x96c000fa, +-0xcc00004d, +-0x80000249, +-0xcc00004e, +-0x9ac00003, +-0xcc00004d, +-0xcc00004e, +-0xdf830000, +-0x80000000, +-0xd80301ff, +-0x9ac000f0, +-0xcc00004d, +-0x80000249, +-0xcc00004e, +-0xc8180003, +-0xc81c0003, +-0xc8200003, +-0x7d5d4003, +-0x7da1c003, +-0x7d5d400c, +-0x2a10001f, +-0x299c001f, +-0x7d1d000b, +-0x7d17400b, +-0x88000000, +-0x7e92800b, +-0x96400004, +-0xcc00004e, +-0x80000249, +-0xcc000042, +-0x04380008, +-0xcf800042, +-0xc8080003, +-0xc80c0003, +-0xc8100003, +-0xc8140003, +-0xc8180003, +-0xc81c0003, +-0xc8240003, +-0xc8280003, +-0x29fc001f, +-0x2ab0001f, +-0x7ff3c00b, +-0x28f0001f, +-0x7ff3c00b, +-0x2970001f, +-0x7ff3c00b, +-0x7d888001, +-0x7dccc001, +-0x7e510001, +-0x7e954001, +-0x7c908002, +-0x7cd4c002, +-0x7cbc800b, +-0x9ac00003, +-0x7c8f400b, +-0x38b40001, +-0x9b4000c1, +-0xcc00004d, +-0x9bc000bf, +-0xcc00004e, +-0xc80c03fd, +-0xc81003fc, +-0xccc00042, +-0x8000016e, +-0xcd000042, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xcc400040, +-0xcc400040, +-0xcc400040, +-0x7c40c000, +-0xccc00040, +-0xccc0000d, +-0x80000000, +-0xd0400040, +-0x7c40c000, +-0x7c410000, +-0x65140020, +-0x7d4d402c, +-0x24580002, +-0x7d598020, +-0x7c41c000, +-0xcd800042, +-0x69980020, +-0xcd800042, +-0xcdc00042, +-0xc023c000, +-0x05e40002, +-0x7ca0800b, +-0x26640010, +-0x7ca4800c, +-0xcc800040, +-0xcdc00040, +-0xccc00040, +-0x95c0000e, +-0xcd000040, +-0x09dc0001, +-0xc8280003, +-0x96800008, +-0xce800040, +-0xc834001d, +-0x97400000, +-0xc834001d, +-0x26a80008, +-0x8400024c, +-0xcc2b0000, +-0x99c0fff7, +-0x09dc0001, +-0xdc3a0000, +-0x97800004, +-0x7c418000, +-0x800001a2, +-0x25980002, +-0xa0000000, +-0x7d808000, +-0xc818001d, +-0x7c40c000, +-0x64d00008, +-0x95800000, +-0xc818001d, +-0xcc130000, +-0xcc800040, +-0xccc00040, +-0x80000000, +-0xcc400040, +-0xc810001f, +-0x7c40c000, +-0xcc800040, +-0x7cd1400c, +-0xcd400040, +-0x05180001, +-0x80000000, +-0xcd800022, +-0x7c40c000, +-0x64500020, +-0x8400024c, +-0xcc000061, +-0x7cd0c02c, +-0xc8200017, +-0xc8d60000, +-0x99400008, +-0x7c438000, +-0xdf830000, +-0xcfa0004f, +-0x8400024c, +-0xcc000062, +-0x80000000, +-0xd040007f, +-0x80000249, +-0xcc000062, +-0x8400024c, +-0xcc000061, +-0xc8200017, +-0x7c40c000, +-0xc036ff00, +-0xc810000d, +-0xc0303fff, +-0x7cf5400b, +-0x7d51800b, +-0x7d81800f, +-0x99800008, +-0x7cf3800b, +-0xdf830000, +-0xcfa0004f, +-0x8400024c, +-0xcc000062, +-0x80000000, +-0xd040007f, +-0x80000249, +-0xcc000062, +-0x8400024c, +-0x7c40c000, +-0x28dc0008, +-0x95c00019, +-0x30dc0010, +-0x7c410000, +-0x99c00004, +-0x64540020, +-0x80000208, +-0xc91d0000, +-0x7d15002c, +-0xc91e0000, +-0x7c420000, +-0x7c424000, +-0x7c418000, +-0x7de5c00b, +-0x7de28007, +-0x9a80000e, +-0x41ac0005, +-0x9ac00000, +-0x0aec0001, +-0x30dc0010, +-0x99c00004, +-0x00000000, +-0x8000020b, +-0xc91d0000, +-0x8000020b, +-0xc91e0000, +-0xcc800040, +-0xccc00040, +-0xd0400040, +-0xc80c0025, +-0x94c0fde4, +-0xc8100008, +-0xcd000040, +-0xd4000fc0, +-0x80000000, +-0xd4000fa2, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x7c40c000, +-0x30d00006, +-0x0d100006, +-0x99000007, +-0xc8140015, +-0x99400005, +-0xcc000052, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xccc00040, +-0x80000000, +-0xd0400040, +-0x7c40c000, +-0xcc4d0000, +-0xdc3a0000, +-0x9780fdbd, +-0x04cc0001, +-0x80000242, +-0xcc4d0000, +-0x80000000, +-0xd040007f, +-0xcc00007f, +-0x80000000, +-0xcc00007f, +-0xcc00007f, +-0x88000000, +-0xcc00007f, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00030222, +-0x0004022a, +-0x0005009f, +-0x00020003, +-0x0006003c, +-0x00070027, +-0x00080191, +-0x00090044, +-0x000a002d, +-0x00100247, +-0x001700f0, +-0x002201d7, +-0x002301e8, +-0x0026004c, +-0x0027005f, +-0x0020011a, +-0x00280092, +-0x0029004f, +-0x002a0083, +-0x002b0064, +-0x002f008d, +-0x003200d8, +-0x00340232, +-0x00360074, +-0x0039010a, +-0x003c01fc, +-0x003f009f, +-0x00410005, +-0x00440194, +-0x0048019d, +-0x004901c5, +-0x004a01cf, +-0x00550225, +-0x0056022d, +-0x0060000a, +-0x0061002a, +-0x00620030, +-0x00630030, +-0x00640030, +-0x00650030, +-0x00660030, +-0x00670030, +-0x00680037, +-0x0069003f, +-0x006a0047, +-0x006b0047, +-0x006c0047, +-0x006d0047, +-0x006e0047, +-0x006f0047, +-0x00700047, +-0x00730247, +-0x007b0240, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-}; +- +-static const u32 RV730_cp_microcode[] = { +-0xcc0003ea, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x80000001, +-0xd040007f, +-0x80000001, +-0xcc400041, +-0x7c40c000, +-0xc0160004, +-0x30d03fff, +-0x7d15000c, +-0xcc110000, +-0x28d8001e, +-0x31980001, +-0x28dc001f, +-0xc8200004, +-0x95c00006, +-0x7c424000, +-0xcc000062, +-0x7e56800c, +-0xcc290000, +-0xc8240004, +-0x7e26000b, +-0x95800006, +-0x7c42c000, +-0xcc000062, +-0x7ed7000c, +-0xcc310000, +-0xc82c0004, +-0x7e2e000c, +-0xcc000062, +-0x31103fff, +-0x80000001, +-0xce110000, +-0x7c40c000, +-0x80000001, +-0xcc400040, +-0x80000001, +-0xcc412257, +-0x7c418000, +-0xcc400045, +-0xcc400048, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xcc400045, +-0xcc400048, +-0x7c40c000, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xcc000045, +-0xcc000048, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x040ca1fd, +-0xc0120001, +-0xcc000045, +-0xcc000048, +-0x7cd0c00c, +-0xcc41225c, +-0xcc41a1fc, +-0xd04d0000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x80000001, +-0xcc41225d, +-0x7c408000, +-0x7c40c000, +-0xc02a0002, +-0x7c410000, +-0x7d29000c, +-0x30940001, +-0x30980006, +-0x309c0300, +-0x29dc0008, +-0x7c420000, +-0x7c424000, +-0x9540000f, +-0xc02e0004, +-0x05f02258, +-0x7f2f000c, +-0xcc310000, +-0xc8280004, +-0xccc12169, +-0xcd01216a, +-0xce81216b, +-0x0db40002, +-0xcc01216c, +-0x9740000e, +-0x0db40000, +-0x8000007b, +-0xc834000a, +-0x0db40002, +-0x97400009, +-0x0db40000, +-0xc02e0004, +-0x05f02258, +-0x7f2f000c, +-0xcc310000, +-0xc8280004, +-0x8000007b, +-0xc834000a, +-0x97400004, +-0x7e028000, +-0x8000007b, +-0xc834000a, +-0x0db40004, +-0x9740ff8c, +-0x00000000, +-0xce01216d, +-0xce41216e, +-0xc8280003, +-0xc834000a, +-0x9b400004, +-0x043c0005, +-0x8400026b, +-0xcc000062, +-0x0df40000, +-0x9740000b, +-0xc82c03e6, +-0xce81a2b7, +-0xc0300006, +-0x7ef34028, +-0xc0300020, +-0x7f6b8020, +-0x7fb3c029, +-0xcf81a2c4, +-0x80000001, +-0xcfc1a2d1, +-0x0df40001, +-0x9740000b, +-0xc82c03e7, +-0xce81a2bb, +-0xc0300006, +-0x7ef34028, +-0xc0300020, +-0x7f6b8020, +-0x7fb3c029, +-0xcf81a2c5, +-0x80000001, +-0xcfc1a2d2, +-0x0df40002, +-0x9740000b, +-0xc82c03e8, +-0xce81a2bf, +-0xc0300006, +-0x7ef34028, +-0xc0300020, +-0x7f6b8020, +-0x7fb3c029, +-0xcf81a2c6, +-0x80000001, +-0xcfc1a2d3, +-0xc82c03e9, +-0xce81a2c3, +-0xc0300006, +-0x7ef34028, +-0xc0300020, +-0x7f6b8020, +-0x7fb3c029, +-0xcf81a2c7, +-0x80000001, +-0xcfc1a2d4, +-0x80000001, +-0xcc400042, +-0x7c40c000, +-0x7c410000, +-0x2914001d, +-0x31540001, +-0x9940000c, +-0x31181000, +-0xc81c0011, +-0x95c00000, +-0xc81c0011, +-0xccc12100, +-0xcd012101, +-0xccc12102, +-0xcd012103, +-0x04180004, +-0x8000037c, +-0xcd81a2a4, +-0xc02a0004, +-0x95800008, +-0x36a821a3, +-0xcc290000, +-0xc8280004, +-0xc81c0011, +-0x0de40040, +-0x9640ffff, +-0xc81c0011, +-0xccc12170, +-0xcd012171, +-0xc8200012, +-0x96000000, +-0xc8200012, +-0x8000037c, +-0xcc000064, +-0x7c40c000, +-0x7c410000, +-0xcc000045, +-0xcc000048, +-0x40d40003, +-0xcd41225c, +-0xcd01a1fc, +-0xc01a0001, +-0x041ca1fd, +-0x7dd9c00c, +-0x7c420000, +-0x08cc0001, +-0x06240001, +-0x06280002, +-0xce1d0000, +-0xce5d0000, +-0x98c0fffa, +-0xce9d0000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x7c40c000, +-0x30d00001, +-0x28cc0001, +-0x7c414000, +-0x95000006, +-0x7c418000, +-0xcd41216d, +-0xcd81216e, +-0x800000f2, +-0xc81c0003, +-0xc0220004, +-0x7e16000c, +-0xcc210000, +-0xc81c0004, +-0x7c424000, +-0x98c00004, +-0x7c428000, +-0x80000001, +-0xcde50000, +-0xce412169, +-0xce81216a, +-0xcdc1216b, +-0x80000001, +-0xcc01216c, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0x7c41c000, +-0x28a40008, +-0x326400ff, +-0x0e68003c, +-0x9680000a, +-0x7c020000, +-0x7c420000, +-0x1e300003, +-0xcc00006a, +-0x9b000003, +-0x42200005, +-0x04200040, +-0x8000010f, +-0x7c024000, +-0x7e024000, +-0x9a400000, +-0x0a640001, +-0x30ec0010, +-0x9ac0000a, +-0xcc000062, +-0xc02a0004, +-0xc82c0021, +-0x7e92800c, +-0xcc000041, +-0xcc290000, +-0xcec00021, +-0x8000011f, +-0xc8300004, +-0xcd01216d, +-0xcd41216e, +-0xc8300003, +-0x7f1f000b, +-0x30f40007, +-0x27780001, +-0x9740002a, +-0x07b80124, +-0x9f800000, +-0x00000000, +-0x80000134, +-0x7f1b8004, +-0x80000138, +-0x7f1b8005, +-0x8000013c, +-0x7f1b8002, +-0x80000140, +-0x7f1b8003, +-0x80000144, +-0x7f1b8007, +-0x80000148, +-0x7f1b8006, +-0x8000014d, +-0x28a40008, +-0x9b800019, +-0x28a40008, +-0x8000015d, +-0x326400ff, +-0x9b800015, +-0x28a40008, +-0x8000015d, +-0x326400ff, +-0x9b800011, +-0x28a40008, +-0x8000015d, +-0x326400ff, +-0x9b80000d, +-0x28a40008, +-0x8000015d, +-0x326400ff, +-0x9b800009, +-0x28a40008, +-0x8000015d, +-0x326400ff, +-0x9b800005, +-0x28a40008, +-0x8000015d, +-0x326400ff, +-0x28a40008, +-0x326400ff, +-0x0e68003c, +-0x9a80feb2, +-0x28ec0008, +-0x7c434000, +-0x7c438000, +-0x7c43c000, +-0x96c00007, +-0xcc000062, +-0xcf412169, +-0xcf81216a, +-0xcfc1216b, +-0x80000001, +-0xcc01216c, +-0x80000001, +-0xcff50000, +-0xcc00006b, +-0x8400037f, +-0x0e68003c, +-0x9a800004, +-0xc8280015, +-0x80000001, +-0xd040007f, +-0x9680ffab, +-0x7e024000, +-0x84000239, +-0xc00e0002, +-0xcc000041, +-0x80000237, +-0xccc1304a, +-0x7c40c000, +-0x7c410000, +-0xc01e0001, +-0x29240012, +-0xc0220002, +-0x96400005, +-0xc0260004, +-0xc027fffb, +-0x7d25000b, +-0xc0260000, +-0x7dd2800b, +-0x7e12c00b, +-0x7d25000c, +-0x7c414000, +-0x7c418000, +-0xccc12169, +-0x9a80000a, +-0xcd01216a, +-0xcd41216b, +-0x96c0fe83, +-0xcd81216c, +-0xc8300018, +-0x97000000, +-0xc8300018, +-0x80000001, +-0xcc000018, +-0x8400037f, +-0xcc00007f, +-0xc8140013, +-0xc8180014, +-0xcd41216b, +-0x96c0fe77, +-0xcd81216c, +-0x80000181, +-0xc8300018, +-0xc80c0008, +-0x98c00000, +-0xc80c0008, +-0x7c410000, +-0x95000002, +-0x00000000, +-0x7c414000, +-0xc8200009, +-0xcc400043, +-0xce01a1f4, +-0xcc400044, +-0xc00e8000, +-0x7c424000, +-0x7c428000, +-0x2aac001f, +-0x96c0fe64, +-0xc035f000, +-0xce4003e2, +-0x32780003, +-0x267c0008, +-0x7ff7c00b, +-0x7ffbc00c, +-0x2a780018, +-0xcfc003e3, +-0xcf8003e4, +-0x26b00002, +-0x7f3f0000, +-0xcf0003e5, +-0x8000031d, +-0x7c80c000, +-0x7c40c000, +-0x28d00008, +-0x3110000f, +-0x9500000f, +-0x25280001, +-0x06a801b2, +-0x9e800000, +-0x00000000, +-0x800001d3, +-0xc0120800, +-0x800001e1, +-0xc814000f, +-0x800001e8, +-0xc8140010, +-0x800001ef, +-0xccc1a2a4, +-0x800001f8, +-0xc8140011, +-0x30d0003f, +-0x0d280015, +-0x9a800012, +-0x0d28001e, +-0x9a80001e, +-0x0d280020, +-0x9a800023, +-0x0d24000f, +-0x0d280010, +-0x7e6a800c, +-0x9a800026, +-0x0d200004, +-0x0d240014, +-0x0d280028, +-0x7e62400c, +-0x7ea6800c, +-0x9a80002a, +-0xc8140011, +-0x80000001, +-0xccc1a2a4, +-0xc0120800, +-0x7c414000, +-0x7d0cc00c, +-0xc0120008, +-0x29580003, +-0x295c000c, +-0x7c420000, +-0x7dd1c00b, +-0x26200014, +-0x7e1e400c, +-0x7e4e800c, +-0xce81a2a4, +-0x80000001, +-0xcd81a1fe, +-0xc814000f, +-0x0410210e, +-0x95400000, +-0xc814000f, +-0xd0510000, +-0x80000001, +-0xccc1a2a4, +-0xc8140010, +-0x04102108, +-0x95400000, +-0xc8140010, +-0xd0510000, +-0x80000001, +-0xccc1a2a4, +-0xccc1a2a4, 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+-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00010331, +-0x00100004, +-0x00170006, +-0x00210008, +-0x00270028, +-0x00280023, +-0x00290029, +-0x002a0026, +-0x002b0029, +-0x002d0038, +-0x002e003f, +-0x002f004a, +-0x0034004c, +-0x00360030, +-0x003900af, +-0x003a00cf, +-0x003b00e4, +-0x003c00fc, +-0x003d016b, +-0x003f00ad, +-0x00410336, +-0x00430349, +-0x0044018e, +-0x004500fc, +-0x004601ac, +-0x004701ac, +-0x004801fe, +-0x0049020c, +-0x004a0255, +-0x004b0282, +-0x0052025f, +-0x00530271, +-0x00540287, +-0x00570299, +-0x0060029d, +-0x006102ac, +-0x006202b6, +-0x006302c0, +-0x006402ca, +-0x006502d4, +-0x006602de, +-0x006702e8, +-0x006802f2, +-0x006902f6, +-0x006a02fa, +-0x006b02fe, +-0x006c0302, +-0x006d0306, +-0x006e030a, +-0x006f030e, +-0x00700312, +-0x00720363, +-0x00740369, +-0x00790367, +-0x007c031c, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-0x000f0378, +-}; +- +-static const u32 RV710_pfp_microcode[] = { +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x80000000, +-0xdc030000, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xc818000e, +-0x31980001, +-0x7c424000, +-0x9580023a, +-0x7c428000, +-0xc81c001c, +-0xc037c000, +-0x7c40c000, +-0x7c410000, +-0x7cb4800b, +-0xc0360003, +-0x99c00000, +-0xc81c001c, +-0x7cb4800c, +-0x24d40002, +-0x7d654000, +-0xcd400043, +-0xce800043, +-0xcd000043, +-0xcc800040, +-0xce400040, +-0xce800040, +-0xccc00040, +-0xdc3a0000, +-0x9780ffde, +-0xcd000040, +-0x7c40c000, +-0x80000018, +-0x7c410000, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xc818000e, +-0x8000000c, +-0x31980002, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xc818000e, +-0x288c0008, +-0x30cc000f, +-0x34100001, +-0x7d0d0008, +-0x8000000c, +-0x7d91800b, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xcc4003f9, +-0x80000249, +-0xcc4003f8, +-0xc037ffff, +-0x7c414000, +-0xcf41a29e, +-0xc82003f8, +-0xc81c03f9, +-0x66200020, +-0xc81803fb, +-0x7de1c02c, +-0x7d58c008, +-0x7cdcc020, +-0x69100020, +-0xc0360003, +-0xcc000054, +-0x7cb4800c, +-0x80000069, +-0xcc800040, +-0x7c418000, +-0xcd81a29e, +-0xcc800040, +-0x80000067, +-0xcd800040, +-0xc019ffff, +-0xcc800040, +-0xcd81a29e, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0xccc1a1fa, +-0xcd01a1f9, +-0xcd41a29d, +-0xccc00040, +-0xcd000040, +-0xcd400040, +-0xcc400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xcc000054, +-0xcc800040, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0xccc1a1fa, +-0xcd01a1f9, +-0xcd41a29d, +-0xccc00040, +-0xcd000040, +-0xcd400040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x7c40c000, +-0x30d00001, +-0xccc1a29f, +-0x95000003, +-0x04140001, +-0x04140002, +-0xcd4003fb, +-0xcc800040, +-0x80000000, +-0xccc00040, +-0x7c40c000, +-0xcc800040, +-0xccc1a2a2, +-0x80000000, +-0xccc00040, +-0x7c40c000, +-0x28d4001f, +-0xcc800040, +-0x95400003, +-0x7c410000, +-0xccc00057, +-0x2918001f, +-0xccc00040, +-0x95800003, +-0xcd000040, +-0xcd000058, +-0x80000249, +-0xcc00007f, +-0xc8200017, +-0xc8300022, +-0x9a000006, +-0x0e280001, +-0xc824001e, +-0x0a640001, +-0xd4001240, +-0xce400040, +-0xc036c000, +-0x96800007, +-0x37747900, +-0x041c0001, +-0xcf400040, +-0xcdc00040, +-0xcf0003fa, +-0x7c030000, +-0xca0c0010, +-0x7c410000, +-0x94c00004, +-0x7c414000, +-0xd42002c4, +-0xcde00044, +-0x9b00000b, +-0x7c418000, +-0xcc00004b, +-0xcda00049, +-0xcd200041, +-0xcd600041, +-0xcda00041, +-0x06200001, +-0xce000056, +-0x80000249, +-0xcc00007f, +-0xc8280020, +-0xc82c0021, +-0xcc000063, +-0x7eea4001, +-0x65740020, +-0x7f53402c, +-0x269c0002, +-0x7df5c020, +-0x69f80020, +-0xce80004b, +-0xce600049, +-0xcde00041, +-0xcfa00041, +-0xce600041, +-0x271c0002, +-0x7df5c020, +-0x69f80020, +-0x7db24001, +-0xcf00004b, +-0xce600049, +-0xcde00041, +-0xcfa00041, +-0x800000bc, +-0xce600041, +-0xc8200017, +-0xc8300022, +-0x9a000006, +-0x0e280001, +-0xc824001e, +-0x0a640001, +-0xd4001240, +-0xce400040, +-0xca0c0010, +-0x7c410000, +-0x94c0000b, +-0xc036c000, +-0x96800007, +-0x37747900, +-0x041c0001, +-0xcf400040, +-0xcdc00040, +-0xcf0003fa, +-0x7c030000, +-0x800000b5, +-0x7c414000, +-0xcc000048, +-0x800000ee, +-0x00000000, +-0xc8200017, +-0xc81c0023, +-0x0e240002, +-0x99c00015, +-0x7c418000, +-0x0a200001, +-0xce000056, +-0xd4000440, +-0xcc000040, +-0xc036c000, +-0xca140013, +-0x96400007, +-0x37747900, +-0xcf400040, +-0xcc000040, +-0xc83003fa, +-0x80000103, +-0xcf000022, +-0xcc000022, +-0x95400146, +-0xcc00007f, +-0xcca00046, +-0x80000000, +-0xcc200046, +-0x80000249, +-0xcc000064, +-0xc8200017, +-0xc810001f, +-0x96000005, +-0x09100001, +-0xd4000440, +-0xcd000040, +-0xcd000022, +-0xcc800040, +-0xd0400040, +-0xc80c0025, +-0x94c0feec, +-0xc8100008, +-0xcd000040, +-0xd4000fc0, +-0x80000000, +-0xd4000fa2, +-0x7c40c000, +-0x7c410000, +-0xccc003fd, +-0xcd0003fc, +-0xccc00042, +-0xcd000042, +-0x2914001f, +-0x29180010, +-0x31980007, +-0x3b5c0001, +-0x7d76000b, +-0x99800005, +-0x7d5e400b, +-0xcc000042, +-0x80000249, +-0xcc00004d, +-0x29980001, +-0x292c0008, +-0x9980003d, +-0x32ec0001, +-0x96000004, +-0x2930000c, +-0x80000249, +-0xcc000042, +-0x04140010, +-0xcd400042, +-0x33300001, +-0x34280001, +-0x8400015d, +-0xc8140003, +-0x9b40001b, +-0x0438000c, +-0x8400015d, +-0xc8140003, +-0x9b400017, +-0x04380008, +-0x8400015d, +-0xc8140003, +-0x9b400013, +-0x04380004, +-0x8400015d, +-0xc8140003, +-0x9b400015, +-0xc80c03fd, +-0x9a800009, +-0xc81003fc, +-0x9b000101, +-0xcc00004d, +-0x04140010, +-0xccc00042, +-0xcd000042, +-0x80000135, +-0xcd400042, +-0x96c000fa, +-0xcc00004d, +-0x80000249, +-0xcc00004e, +-0x9ac00003, +-0xcc00004d, +-0xcc00004e, +-0xdf830000, +-0x80000000, +-0xd80301ff, +-0x9ac000f0, +-0xcc00004d, +-0x80000249, +-0xcc00004e, +-0xc8180003, +-0xc81c0003, +-0xc8200003, +-0x7d5d4003, +-0x7da1c003, +-0x7d5d400c, +-0x2a10001f, +-0x299c001f, +-0x7d1d000b, +-0x7d17400b, +-0x88000000, +-0x7e92800b, +-0x96400004, +-0xcc00004e, +-0x80000249, +-0xcc000042, +-0x04380008, +-0xcf800042, +-0xc8080003, +-0xc80c0003, +-0xc8100003, +-0xc8140003, +-0xc8180003, +-0xc81c0003, +-0xc8240003, +-0xc8280003, +-0x29fc001f, +-0x2ab0001f, +-0x7ff3c00b, +-0x28f0001f, +-0x7ff3c00b, +-0x2970001f, +-0x7ff3c00b, +-0x7d888001, +-0x7dccc001, +-0x7e510001, +-0x7e954001, +-0x7c908002, +-0x7cd4c002, +-0x7cbc800b, +-0x9ac00003, +-0x7c8f400b, +-0x38b40001, +-0x9b4000c1, +-0xcc00004d, +-0x9bc000bf, +-0xcc00004e, +-0xc80c03fd, +-0xc81003fc, +-0xccc00042, +-0x8000016e, +-0xcd000042, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xcc400040, +-0xcc400040, +-0xcc400040, +-0x7c40c000, +-0xccc00040, +-0xccc0000d, +-0x80000000, +-0xd0400040, +-0x7c40c000, +-0x7c410000, +-0x65140020, +-0x7d4d402c, +-0x24580002, +-0x7d598020, +-0x7c41c000, +-0xcd800042, +-0x69980020, +-0xcd800042, +-0xcdc00042, +-0xc023c000, +-0x05e40002, +-0x7ca0800b, +-0x26640010, +-0x7ca4800c, +-0xcc800040, +-0xcdc00040, +-0xccc00040, +-0x95c0000e, +-0xcd000040, +-0x09dc0001, +-0xc8280003, +-0x96800008, +-0xce800040, +-0xc834001d, +-0x97400000, +-0xc834001d, +-0x26a80008, +-0x8400024c, +-0xcc2b0000, +-0x99c0fff7, +-0x09dc0001, +-0xdc3a0000, +-0x97800004, +-0x7c418000, +-0x800001a2, +-0x25980002, +-0xa0000000, +-0x7d808000, +-0xc818001d, +-0x7c40c000, +-0x64d00008, +-0x95800000, +-0xc818001d, +-0xcc130000, +-0xcc800040, +-0xccc00040, +-0x80000000, +-0xcc400040, +-0xc810001f, +-0x7c40c000, +-0xcc800040, +-0x7cd1400c, +-0xcd400040, +-0x05180001, +-0x80000000, +-0xcd800022, +-0x7c40c000, +-0x64500020, +-0x8400024c, +-0xcc000061, +-0x7cd0c02c, +-0xc8200017, +-0xc8d60000, +-0x99400008, +-0x7c438000, +-0xdf830000, +-0xcfa0004f, +-0x8400024c, +-0xcc000062, +-0x80000000, +-0xd040007f, +-0x80000249, +-0xcc000062, +-0x8400024c, +-0xcc000061, +-0xc8200017, +-0x7c40c000, +-0xc036ff00, +-0xc810000d, +-0xc0303fff, +-0x7cf5400b, +-0x7d51800b, +-0x7d81800f, +-0x99800008, +-0x7cf3800b, +-0xdf830000, +-0xcfa0004f, +-0x8400024c, +-0xcc000062, +-0x80000000, +-0xd040007f, +-0x80000249, +-0xcc000062, +-0x8400024c, +-0x7c40c000, +-0x28dc0008, +-0x95c00019, +-0x30dc0010, +-0x7c410000, +-0x99c00004, +-0x64540020, +-0x80000208, +-0xc91d0000, +-0x7d15002c, +-0xc91e0000, +-0x7c420000, +-0x7c424000, +-0x7c418000, +-0x7de5c00b, +-0x7de28007, +-0x9a80000e, +-0x41ac0005, +-0x9ac00000, +-0x0aec0001, +-0x30dc0010, +-0x99c00004, +-0x00000000, +-0x8000020b, +-0xc91d0000, +-0x8000020b, +-0xc91e0000, +-0xcc800040, +-0xccc00040, +-0xd0400040, +-0xc80c0025, +-0x94c0fde4, +-0xc8100008, +-0xcd000040, +-0xd4000fc0, +-0x80000000, +-0xd4000fa2, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0xd40003c0, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xd0400040, +-0x7c408000, +-0xa0000000, +-0x7e82800b, +-0x7c40c000, +-0x30d00006, +-0x0d100006, +-0x99000007, +-0xc8140015, +-0x99400005, +-0xcc000052, +-0xd4000340, +-0xd4000fc0, +-0xd4000fa2, +-0xcc800040, +-0xccc00040, +-0x80000000, +-0xd0400040, +-0x7c40c000, +-0xcc4d0000, +-0xdc3a0000, +-0x9780fdbd, +-0x04cc0001, +-0x80000242, +-0xcc4d0000, +-0x80000000, +-0xd040007f, +-0xcc00007f, +-0x80000000, +-0xcc00007f, +-0xcc00007f, +-0x88000000, +-0xcc00007f, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00030222, +-0x0004022a, +-0x0005009f, +-0x00020003, +-0x0006003c, +-0x00070027, +-0x00080191, +-0x00090044, +-0x000a002d, +-0x00100247, +-0x001700f0, +-0x002201d7, +-0x002301e8, +-0x0026004c, +-0x0027005f, +-0x0020011a, +-0x00280092, +-0x0029004f, +-0x002a0083, +-0x002b0064, +-0x002f008d, +-0x003200d8, +-0x00340232, +-0x00360074, +-0x0039010a, +-0x003c01fc, +-0x003f009f, +-0x00410005, +-0x00440194, +-0x0048019d, +-0x004901c5, +-0x004a01cf, +-0x00550225, +-0x0056022d, +-0x0060000a, +-0x0061002a, +-0x00620030, +-0x00630030, +-0x00640030, +-0x00650030, +-0x00660030, +-0x00670030, +-0x00680037, +-0x0069003f, +-0x006a0047, +-0x006b0047, +-0x006c0047, +-0x006d0047, +-0x006e0047, +-0x006f0047, +-0x00700047, +-0x00730247, +-0x007b0240, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-0x00000005, +-}; +- +-static const u32 RV710_cp_microcode[] = { +-0xcc0003ea, +-0x04080003, +-0xcc800043, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x80000003, +-0xd040007f, +-0x80000003, +-0xcc400041, +-0x7c40c000, +-0xc0160004, +-0x30d03fff, +-0x7d15000c, +-0xcc110000, +-0x28d8001e, +-0x31980001, +-0x28dc001f, +-0xc8200004, +-0x95c00006, +-0x7c424000, +-0xcc000062, +-0x7e56800c, +-0xcc290000, +-0xc8240004, +-0x7e26000b, +-0x95800006, +-0x7c42c000, +-0xcc000062, +-0x7ed7000c, +-0xcc310000, +-0xc82c0004, +-0x7e2e000c, +-0xcc000062, +-0x31103fff, +-0x80000003, +-0xce110000, +-0x7c40c000, +-0x80000003, +-0xcc400040, +-0x80000003, +-0xcc412257, +-0x7c418000, +-0xcc400045, +-0xcc400048, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xcc400045, +-0xcc400048, +-0x7c40c000, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xcc000045, +-0xcc000048, +-0xcc41225c, +-0xcc41a1fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x040ca1fd, +-0xc0120001, +-0xcc000045, +-0xcc000048, +-0x7cd0c00c, +-0xcc41225c, +-0xcc41a1fc, +-0xd04d0000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x80000003, +-0xcc41225d, +-0x7c408000, +-0x7c40c000, +-0xc02a0002, +-0x7c410000, +-0x7d29000c, +-0x30940001, +-0x30980006, +-0x309c0300, +-0x29dc0008, +-0x7c420000, +-0x7c424000, +-0x9540000f, +-0xc02e0004, +-0x05f02258, +-0x7f2f000c, +-0xcc310000, +-0xc8280004, +-0xccc12169, +-0xcd01216a, +-0xce81216b, +-0x0db40002, +-0xcc01216c, +-0x9740000e, +-0x0db40000, +-0x8000007d, +-0xc834000a, +-0x0db40002, +-0x97400009, +-0x0db40000, +-0xc02e0004, +-0x05f02258, +-0x7f2f000c, +-0xcc310000, +-0xc8280004, +-0x8000007d, +-0xc834000a, +-0x97400004, +-0x7e028000, +-0x8000007d, +-0xc834000a, +-0x0db40004, +-0x9740ff8c, +-0x00000000, +-0xce01216d, +-0xce41216e, +-0xc8280003, +-0xc834000a, +-0x9b400004, +-0x043c0005, +-0x8400026d, +-0xcc000062, +-0x0df40000, +-0x9740000b, +-0xc82c03e6, +-0xce81a2b7, +-0xc0300006, +-0x7ef34028, +-0xc0300020, +-0x7f6b8020, +-0x7fb3c029, +-0xcf81a2c4, +-0x80000003, +-0xcfc1a2d1, +-0x0df40001, +-0x9740000b, +-0xc82c03e7, +-0xce81a2bb, +-0xc0300006, +-0x7ef34028, +-0xc0300020, +-0x7f6b8020, +-0x7fb3c029, +-0xcf81a2c5, +-0x80000003, +-0xcfc1a2d2, +-0x0df40002, +-0x9740000b, +-0xc82c03e8, +-0xce81a2bf, +-0xc0300006, +-0x7ef34028, +-0xc0300020, +-0x7f6b8020, +-0x7fb3c029, +-0xcf81a2c6, +-0x80000003, +-0xcfc1a2d3, +-0xc82c03e9, +-0xce81a2c3, +-0xc0300006, +-0x7ef34028, +-0xc0300020, +-0x7f6b8020, +-0x7fb3c029, +-0xcf81a2c7, +-0x80000003, +-0xcfc1a2d4, +-0x80000003, +-0xcc400042, +-0x7c40c000, +-0x7c410000, +-0x2914001d, +-0x31540001, +-0x9940000c, +-0x31181000, +-0xc81c0011, +-0x95c00000, +-0xc81c0011, +-0xccc12100, +-0xcd012101, +-0xccc12102, +-0xcd012103, +-0x04180004, +-0x8000037e, +-0xcd81a2a4, +-0xc02a0004, +-0x95800008, +-0x36a821a3, +-0xcc290000, +-0xc8280004, +-0xc81c0011, +-0x0de40040, +-0x9640ffff, +-0xc81c0011, +-0xccc12170, +-0xcd012171, +-0xc8200012, +-0x96000000, +-0xc8200012, +-0x8000037e, +-0xcc000064, +-0x7c40c000, +-0x7c410000, +-0xcc000045, +-0xcc000048, +-0x40d40003, +-0xcd41225c, +-0xcd01a1fc, +-0xc01a0001, +-0x041ca1fd, +-0x7dd9c00c, +-0x7c420000, +-0x08cc0001, +-0x06240001, +-0x06280002, +-0xce1d0000, +-0xce5d0000, +-0x98c0fffa, +-0xce9d0000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x7c40c000, +-0x30d00001, +-0x28cc0001, +-0x7c414000, +-0x95000006, +-0x7c418000, +-0xcd41216d, +-0xcd81216e, +-0x800000f4, +-0xc81c0003, +-0xc0220004, +-0x7e16000c, +-0xcc210000, +-0xc81c0004, +-0x7c424000, +-0x98c00004, +-0x7c428000, +-0x80000003, +-0xcde50000, +-0xce412169, +-0xce81216a, +-0xcdc1216b, +-0x80000003, +-0xcc01216c, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0x7c41c000, +-0x28a40008, +-0x326400ff, +-0x0e68003c, +-0x9680000a, +-0x7c020000, +-0x7c420000, +-0x1e300003, +-0xcc00006a, +-0x9b000003, +-0x42200005, +-0x04200040, +-0x80000111, +-0x7c024000, +-0x7e024000, +-0x9a400000, +-0x0a640001, +-0x30ec0010, +-0x9ac0000a, +-0xcc000062, +-0xc02a0004, +-0xc82c0021, +-0x7e92800c, +-0xcc000041, +-0xcc290000, +-0xcec00021, +-0x80000121, +-0xc8300004, +-0xcd01216d, +-0xcd41216e, +-0xc8300003, +-0x7f1f000b, +-0x30f40007, +-0x27780001, +-0x9740002a, +-0x07b80126, +-0x9f800000, +-0x00000000, +-0x80000136, +-0x7f1b8004, +-0x8000013a, +-0x7f1b8005, +-0x8000013e, +-0x7f1b8002, +-0x80000142, +-0x7f1b8003, +-0x80000146, +-0x7f1b8007, +-0x8000014a, +-0x7f1b8006, +-0x8000014f, +-0x28a40008, +-0x9b800019, +-0x28a40008, +-0x8000015f, +-0x326400ff, +-0x9b800015, +-0x28a40008, +-0x8000015f, +-0x326400ff, +-0x9b800011, +-0x28a40008, +-0x8000015f, +-0x326400ff, +-0x9b80000d, +-0x28a40008, +-0x8000015f, +-0x326400ff, +-0x9b800009, +-0x28a40008, +-0x8000015f, +-0x326400ff, +-0x9b800005, +-0x28a40008, +-0x8000015f, +-0x326400ff, +-0x28a40008, +-0x326400ff, +-0x0e68003c, +-0x9a80feb2, +-0x28ec0008, +-0x7c434000, +-0x7c438000, +-0x7c43c000, +-0x96c00007, +-0xcc000062, +-0xcf412169, +-0xcf81216a, +-0xcfc1216b, +-0x80000003, +-0xcc01216c, +-0x80000003, +-0xcff50000, +-0xcc00006b, +-0x84000381, +-0x0e68003c, +-0x9a800004, +-0xc8280015, +-0x80000003, +-0xd040007f, +-0x9680ffab, +-0x7e024000, +-0x8400023b, +-0xc00e0002, +-0xcc000041, +-0x80000239, +-0xccc1304a, +-0x7c40c000, +-0x7c410000, +-0xc01e0001, +-0x29240012, +-0xc0220002, +-0x96400005, +-0xc0260004, +-0xc027fffb, +-0x7d25000b, +-0xc0260000, +-0x7dd2800b, +-0x7e12c00b, +-0x7d25000c, +-0x7c414000, +-0x7c418000, +-0xccc12169, +-0x9a80000a, +-0xcd01216a, +-0xcd41216b, +-0x96c0fe83, +-0xcd81216c, +-0xc8300018, +-0x97000000, +-0xc8300018, +-0x80000003, +-0xcc000018, +-0x84000381, +-0xcc00007f, +-0xc8140013, +-0xc8180014, +-0xcd41216b, +-0x96c0fe77, +-0xcd81216c, +-0x80000183, +-0xc8300018, +-0xc80c0008, +-0x98c00000, +-0xc80c0008, +-0x7c410000, +-0x95000002, +-0x00000000, +-0x7c414000, +-0xc8200009, +-0xcc400043, +-0xce01a1f4, +-0xcc400044, +-0xc00e8000, +-0x7c424000, +-0x7c428000, +-0x2aac001f, +-0x96c0fe64, +-0xc035f000, +-0xce4003e2, +-0x32780003, +-0x267c0008, +-0x7ff7c00b, +-0x7ffbc00c, +-0x2a780018, +-0xcfc003e3, +-0xcf8003e4, +-0x26b00002, +-0x7f3f0000, +-0xcf0003e5, +-0x8000031f, +-0x7c80c000, +-0x7c40c000, +-0x28d00008, +-0x3110000f, +-0x9500000f, +-0x25280001, +-0x06a801b4, +-0x9e800000, +-0x00000000, +-0x800001d5, +-0xc0120800, +-0x800001e3, +-0xc814000f, +-0x800001ea, +-0xc8140010, +-0x800001f1, +-0xccc1a2a4, +-0x800001fa, +-0xc8140011, +-0x30d0003f, +-0x0d280015, +-0x9a800012, +-0x0d28001e, +-0x9a80001e, +-0x0d280020, +-0x9a800023, +-0x0d24000f, +-0x0d280010, +-0x7e6a800c, +-0x9a800026, +-0x0d200004, +-0x0d240014, +-0x0d280028, +-0x7e62400c, +-0x7ea6800c, +-0x9a80002a, +-0xc8140011, +-0x80000003, +-0xccc1a2a4, +-0xc0120800, +-0x7c414000, +-0x7d0cc00c, +-0xc0120008, +-0x29580003, +-0x295c000c, +-0x7c420000, +-0x7dd1c00b, +-0x26200014, +-0x7e1e400c, +-0x7e4e800c, +-0xce81a2a4, +-0x80000003, +-0xcd81a1fe, +-0xc814000f, +-0x0410210e, +-0x95400000, +-0xc814000f, +-0xd0510000, +-0x80000003, +-0xccc1a2a4, +-0xc8140010, +-0x04102108, +-0x95400000, +-0xc8140010, +-0xd0510000, +-0x80000003, +-0xccc1a2a4, +-0xccc1a2a4, +-0x04100001, +-0xcd000019, +-0x84000381, +-0xcc00007f, +-0xc8100019, +-0x99000000, +-0xc8100019, +-0x80000004, +-0x7c408000, +-0x04102100, +-0x95400000, +-0xc8140011, +-0xd0510000, +-0x8000037e, +-0xccc1a2a4, +-0x7c40c000, +-0xcc40000d, +-0x94c0fe01, +-0xcc40000e, +-0x7c410000, +-0x95000005, +-0x08cc0001, +-0xc8140005, +-0x99400014, +-0x00000000, +-0x98c0fffb, +-0x7c410000, +-0x80000004, +-0x7d008000, +-0xc8140005, +-0x7c40c000, +-0x9940000c, +-0xc818000c, +-0x7c410000, +-0x9580fdf0, +-0xc820000e, +-0xc81c000d, +-0x66200020, +-0x7e1e002c, +-0x25240002, +-0x7e624020, +-0x80000003, +-0xcce60000, +-0x7c410000, +-0xcc00006c, +-0xcc00006d, +-0xc818001f, +-0xc81c001e, +-0x65980020, +-0x7dd9c02c, +-0x7cd4c00c, +-0xccde0000, +-0x45dc0004, +-0xc8280017, +-0x9680000f, +-0xc00e0001, +-0x28680008, +-0x2aac0016, +-0x32a800ff, +-0x0eb00049, +-0x7f2f000b, +-0x97000006, +-0x00000000, +-0xc8140005, +-0x7c40c000, +-0x80000223, +-0x7c410000, +-0x80000226, +-0xd040007f, +-0x8400023b, +-0xcc000041, +-0xccc1304a, +-0x94000000, +-0xc83c001a, +-0x043c0005, +-0xcfc1a2a4, +-0xc0361f90, +-0xc0387fff, +-0x7c03c010, +-0x7f7b400c, +-0xcf41217c, +-0xcfc1217d, +-0xcc01217e, +-0xc03a0004, +-0x0434217f, +-0x7f7b400c, +-0xcc350000, +-0xc83c0004, +-0x2bfc001f, +-0x04380020, +-0x97c00005, +-0xcc000062, +-0x9b800000, +-0x0bb80001, +-0x80000247, +-0xcc000071, +-0xcc01a1f4, +-0x04380016, +-0xc0360002, +-0xcf81a2a4, +-0x88000000, +-0xcf412010, +-0x7c40c000, +-0x28d0001c, +-0x95000005, +-0x04d40001, +-0xcd400065, +-0x80000003, +-0xcd400068, +-0x09540002, +-0x80000003, +-0xcd400066, +-0x8400026c, +-0xc81803ea, +-0x7c40c000, +-0x9980fd9f, +-0xc8140016, +-0x08d00001, +-0x9940002b, +-0xcd000068, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x043c0005, +-0xcfc1a2a4, +-0xcc01a1f4, +-0x84000381, +-0xcc000046, +-0x88000000, +-0xcc00007f, +-0x8400027e, +-0xc81803ea, +-0x7c40c000, +-0x9980fd8d, +-0xc8140016, +-0x08d00001, +-0x99400019, +-0xcd000068, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x043c0022, +-0xcfc1a2a4, +-0x84000381, +-0xcc000047, +-0x88000000, +-0xcc00007f, +-0xc8100016, +-0x9900000d, +-0xcc400067, +-0x80000004, +-0x7c408000, +-0xc81803ea, +-0x9980fd79, +-0x7c40c000, +-0x94c00003, +-0xc8100016, +-0x99000004, +-0xccc00068, +-0x80000004, +-0x7c408000, +-0x8400023b, +-0xc0148000, +-0xcc000041, +-0xcd41304a, +-0xc0148000, +-0x99000000, +-0xc8100016, +-0x80000004, +-0x7c408000, +-0xc0120001, +-0x7c51400c, +-0x80000003, +-0xd0550000, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0x291c001f, +-0xccc0004a, +-0xcd00004b, +-0x95c00003, +-0xc01c8000, +-0xcdc12010, +-0xdd830000, +-0x055c2000, +-0xcc000062, +-0x80000003, +-0xd81f4100, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0xccc0004c, +-0xcd00004d, +-0xdd830000, +-0x055ca000, +-0x80000003, +-0xd81f4100, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0xccc0004e, +-0xcd00004f, +-0xdd830000, +-0x055cc000, +-0x80000003, +-0xd81f4100, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0xccc00050, +-0xcd000051, +-0xdd830000, +-0x055cf8e0, +-0x80000003, +-0xd81f4100, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0xccc00052, +-0xcd000053, +-0xdd830000, +-0x055cf880, +-0x80000003, +-0xd81f4100, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0xccc00054, +-0xcd000055, +-0xdd830000, +-0x055ce000, +-0x80000003, +-0xd81f4100, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0xccc00056, +-0xcd000057, +-0xdd830000, +-0x055cf000, +-0x80000003, +-0xd81f4100, +-0x7c40c000, +-0x7c410000, +-0x7c414000, +-0x7c418000, +-0xccc00058, +-0xcd000059, +-0xdd830000, +-0x055cf3fc, +-0x80000003, +-0xd81f4100, +-0xd0432000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xd043a000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xd043c000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xd043f8e0, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xd043f880, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xd043e000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xd043f000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xd043f3fc, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xc81403e0, +-0xcc430000, +-0xcc430000, +-0xcc430000, +-0x7d45c000, +-0xcdc30000, +-0xd0430000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0x7c40c000, +-0xc81003e2, +-0xc81403e5, +-0xc81803e3, +-0xc81c03e4, +-0xcd812169, +-0xcdc1216a, +-0xccc1216b, +-0xcc01216c, +-0x04200004, +-0x7da18000, +-0x7d964002, +-0x9640fcd9, +-0xcd8003e3, +-0x31280003, +-0xc02df000, +-0x25180008, +-0x7dad800b, +-0x7da9800c, +-0x80000003, +-0xcd8003e3, +-0x308cffff, +-0xd04d0000, +-0x7c408000, +-0xa0000000, +-0xcc800062, +-0xc8140020, +-0x15580002, +-0x9580ffff, +-0xc8140020, +-0xcc00006e, +-0xcc412180, +-0x7c40c000, +-0xccc1218d, +-0xcc412181, +-0x28d0001f, +-0x34588000, +-0xcd81218c, +-0x9500fcbf, +-0xcc412182, +-0xc8140020, +-0x9940ffff, +-0xc8140020, +-0x80000004, +-0x7c408000, +-0x7c40c000, +-0x28d00018, +-0x31100001, +-0xc0160080, +-0x95000003, +-0xc02a0004, +-0x7cd4c00c, +-0xccc1217c, +-0xcc41217d, +-0xcc41217e, +-0x7c418000, +-0x1db00003, +-0x36a0217f, +-0x9b000003, +-0x419c0005, +-0x041c0040, +-0x99c00000, +-0x09dc0001, +-0xcc210000, +-0xc8240004, +-0x2a6c001f, +-0x419c0005, +-0x9ac0fffa, +-0xcc800062, +-0x80000004, +-0x7c408000, +-0x7c40c000, +-0x04d403e6, +-0x80000003, +-0xcc540000, +-0x8000037e, +-0xcc4003ea, +-0xc01c8000, +-0x044ca000, +-0xcdc12010, +-0x7c410000, +-0xc8140009, +-0x04180000, +-0x041c0008, +-0xcd800071, +-0x09dc0001, +-0x05980001, +-0xcd0d0000, +-0x99c0fffc, +-0xcc800062, +-0x8000037e, +-0xcd400071, +-0xc00e0100, +-0xcc000041, +-0xccc1304a, +-0xc83c007f, +-0xcc00007f, +-0x80000003, +-0xcc00007f, +-0xcc00007f, +-0x88000000, +-0xcc00007f, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00000000, +-0x00010333, +-0x00100006, +-0x00170008, +-0x0021000a, +-0x0027002a, +-0x00280025, +-0x0029002b, +-0x002a0028, +-0x002b002b, +-0x002d003a, +-0x002e0041, +-0x002f004c, +-0x0034004e, +-0x00360032, +-0x003900b1, +-0x003a00d1, +-0x003b00e6, +-0x003c00fe, +-0x003d016d, +-0x003f00af, +-0x00410338, +-0x0043034b, +-0x00440190, +-0x004500fe, +-0x004601ae, +-0x004701ae, +-0x00480200, +-0x0049020e, +-0x004a0257, +-0x004b0284, +-0x00520261, +-0x00530273, +-0x00540289, +-0x0057029b, +-0x0060029f, +-0x006102ae, +-0x006202b8, +-0x006302c2, +-0x006402cc, +-0x006502d6, +-0x006602e0, +-0x006702ea, +-0x006802f4, +-0x006902f8, +-0x006a02fc, +-0x006b0300, +-0x006c0304, +-0x006d0308, +-0x006e030c, +-0x006f0310, +-0x00700314, +-0x00720365, +-0x0074036b, +-0x00790369, +-0x007c031e, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-0x000f037a, +-}; +- +-#endif +diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h +new file mode 100644 +index 0000000..723295f +--- /dev/null ++++ b/drivers/gpu/drm/radeon/r600d.h +@@ -0,0 +1,661 @@ ++/* ++ * Copyright 2009 Advanced Micro Devices, Inc. ++ * Copyright 2009 Red Hat Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#ifndef R600D_H ++#define R600D_H ++ ++#define CP_PACKET2 0x80000000 ++#define PACKET2_PAD_SHIFT 0 ++#define PACKET2_PAD_MASK (0x3fffffff << 0) ++ ++#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) ++ ++#define R6XX_MAX_SH_GPRS 256 ++#define R6XX_MAX_TEMP_GPRS 16 ++#define R6XX_MAX_SH_THREADS 256 ++#define R6XX_MAX_SH_STACK_ENTRIES 4096 ++#define R6XX_MAX_BACKENDS 8 ++#define R6XX_MAX_BACKENDS_MASK 0xff ++#define R6XX_MAX_SIMDS 8 ++#define R6XX_MAX_SIMDS_MASK 0xff ++#define R6XX_MAX_PIPES 8 ++#define R6XX_MAX_PIPES_MASK 0xff ++ ++/* PTE flags */ ++#define PTE_VALID (1 << 0) ++#define PTE_SYSTEM (1 << 1) ++#define PTE_SNOOPED (1 << 2) ++#define PTE_READABLE (1 << 5) ++#define PTE_WRITEABLE (1 << 6) ++ ++/* Registers */ ++#define ARB_POP 0x2418 ++#define ENABLE_TC128 (1 << 30) ++#define ARB_GDEC_RD_CNTL 0x246C ++ ++#define CC_GC_SHADER_PIPE_CONFIG 0x8950 ++#define CC_RB_BACKEND_DISABLE 0x98F4 ++#define BACKEND_DISABLE(x) ((x) << 16) ++ ++#define CB_COLOR0_BASE 0x28040 ++#define CB_COLOR1_BASE 0x28044 ++#define CB_COLOR2_BASE 0x28048 ++#define CB_COLOR3_BASE 0x2804C ++#define CB_COLOR4_BASE 0x28050 ++#define CB_COLOR5_BASE 0x28054 ++#define CB_COLOR6_BASE 0x28058 ++#define CB_COLOR7_BASE 0x2805C ++#define CB_COLOR7_FRAG 0x280FC ++ ++#define CB_COLOR0_SIZE 0x28060 ++#define CB_COLOR0_VIEW 0x28080 ++#define CB_COLOR0_INFO 0x280a0 ++#define CB_COLOR0_TILE 0x280c0 ++#define CB_COLOR0_FRAG 0x280e0 ++#define CB_COLOR0_MASK 0x28100 ++ ++#define CONFIG_MEMSIZE 0x5428 ++#define CP_STAT 0x8680 ++#define CP_COHER_BASE 0x85F8 ++#define CP_DEBUG 0xC1FC ++#define R_0086D8_CP_ME_CNTL 0x86D8 ++#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) ++#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) ++#define CP_ME_RAM_DATA 0xC160 ++#define CP_ME_RAM_RADDR 0xC158 ++#define CP_ME_RAM_WADDR 0xC15C ++#define CP_MEQ_THRESHOLDS 0x8764 ++#define MEQ_END(x) ((x) << 16) ++#define ROQ_END(x) ((x) << 24) ++#define CP_PERFMON_CNTL 0x87FC ++#define CP_PFP_UCODE_ADDR 0xC150 ++#define CP_PFP_UCODE_DATA 0xC154 ++#define CP_QUEUE_THRESHOLDS 0x8760 ++#define ROQ_IB1_START(x) ((x) << 0) ++#define ROQ_IB2_START(x) ((x) << 8) ++#define CP_RB_BASE 0xC100 ++#define CP_RB_CNTL 0xC104 ++#define RB_BUFSZ(x) ((x)<<0) ++#define RB_BLKSZ(x) ((x)<<8) ++#define RB_NO_UPDATE (1<<27) ++#define RB_RPTR_WR_ENA (1<<31) ++#define BUF_SWAP_32BIT (2 << 16) ++#define CP_RB_RPTR 0x8700 ++#define CP_RB_RPTR_ADDR 0xC10C ++#define CP_RB_RPTR_ADDR_HI 0xC110 ++#define CP_RB_RPTR_WR 0xC108 ++#define CP_RB_WPTR 0xC114 ++#define CP_RB_WPTR_ADDR 0xC118 ++#define CP_RB_WPTR_ADDR_HI 0xC11C ++#define CP_RB_WPTR_DELAY 0x8704 ++#define CP_ROQ_IB1_STAT 0x8784 ++#define CP_ROQ_IB2_STAT 0x8788 ++#define CP_SEM_WAIT_TIMER 0x85BC ++ ++#define DB_DEBUG 0x9830 ++#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) ++#define DB_DEPTH_BASE 0x2800C ++#define DB_WATERMARKS 0x9838 ++#define DEPTH_FREE(x) ((x) << 0) ++#define DEPTH_FLUSH(x) ((x) << 5) ++#define DEPTH_PENDING_FREE(x) ((x) << 15) ++#define DEPTH_CACHELINE_FREE(x) ((x) << 20) ++ ++#define DCP_TILING_CONFIG 0x6CA0 ++#define PIPE_TILING(x) ((x) << 1) ++#define BANK_TILING(x) ((x) << 4) ++#define GROUP_SIZE(x) ((x) << 6) ++#define ROW_TILING(x) ((x) << 8) ++#define BANK_SWAPS(x) ((x) << 11) ++#define SAMPLE_SPLIT(x) ((x) << 14) ++#define BACKEND_MAP(x) ((x) << 16) ++ ++#define GB_TILING_CONFIG 0x98F0 ++ ++#define GC_USER_SHADER_PIPE_CONFIG 0x8954 ++#define INACTIVE_QD_PIPES(x) ((x) << 8) ++#define INACTIVE_QD_PIPES_MASK 0x0000FF00 ++#define INACTIVE_SIMDS(x) ((x) << 16) ++#define INACTIVE_SIMDS_MASK 0x00FF0000 ++ ++#define SQ_CONFIG 0x8c00 ++# define VC_ENABLE (1 << 0) ++# define EXPORT_SRC_C (1 << 1) ++# define DX9_CONSTS (1 << 2) ++# define ALU_INST_PREFER_VECTOR (1 << 3) ++# define DX10_CLAMP (1 << 4) ++# define CLAUSE_SEQ_PRIO(x) ((x) << 8) ++# define PS_PRIO(x) ((x) << 24) ++# define VS_PRIO(x) ((x) << 26) ++# define GS_PRIO(x) ((x) << 28) ++# define ES_PRIO(x) ((x) << 30) ++#define SQ_GPR_RESOURCE_MGMT_1 0x8c04 ++# define NUM_PS_GPRS(x) ((x) << 0) ++# define NUM_VS_GPRS(x) ((x) << 16) ++# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) ++#define SQ_GPR_RESOURCE_MGMT_2 0x8c08 ++# define NUM_GS_GPRS(x) ((x) << 0) ++# define NUM_ES_GPRS(x) ((x) << 16) ++#define SQ_THREAD_RESOURCE_MGMT 0x8c0c ++# define NUM_PS_THREADS(x) ((x) << 0) ++# define NUM_VS_THREADS(x) ((x) << 8) ++# define NUM_GS_THREADS(x) ((x) << 16) ++# define NUM_ES_THREADS(x) ((x) << 24) ++#define SQ_STACK_RESOURCE_MGMT_1 0x8c10 ++# define NUM_PS_STACK_ENTRIES(x) ((x) << 0) ++# define NUM_VS_STACK_ENTRIES(x) ((x) << 16) ++#define SQ_STACK_RESOURCE_MGMT_2 0x8c14 ++# define NUM_GS_STACK_ENTRIES(x) ((x) << 0) ++# define NUM_ES_STACK_ENTRIES(x) ((x) << 16) ++ ++#define GRBM_CNTL 0x8000 ++# define GRBM_READ_TIMEOUT(x) ((x) << 0) ++#define GRBM_STATUS 0x8010 ++#define CMDFIFO_AVAIL_MASK 0x0000001F ++#define GUI_ACTIVE (1<<31) ++#define GRBM_STATUS2 0x8014 ++#define GRBM_SOFT_RESET 0x8020 ++#define SOFT_RESET_CP (1<<0) ++ ++#define HDP_HOST_PATH_CNTL 0x2C00 ++#define HDP_NONSURFACE_BASE 0x2C04 ++#define HDP_NONSURFACE_INFO 0x2C08 ++#define HDP_NONSURFACE_SIZE 0x2C0C ++#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 ++#define HDP_TILING_CONFIG 0x2F3C ++ ++#define MC_VM_AGP_TOP 0x2184 ++#define MC_VM_AGP_BOT 0x2188 ++#define MC_VM_AGP_BASE 0x218C ++#define MC_VM_FB_LOCATION 0x2180 ++#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C ++#define ENABLE_L1_TLB (1 << 0) ++#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) ++#define ENABLE_L1_STRICT_ORDERING (1 << 2) ++#define SYSTEM_ACCESS_MODE_MASK 0x000000C0 ++#define SYSTEM_ACCESS_MODE_SHIFT 6 ++#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) ++#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) ++#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) ++#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) ++#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) ++#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) ++#define ENABLE_SEMAPHORE_MODE (1 << 10) ++#define ENABLE_WAIT_L2_QUERY (1 << 11) ++#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) ++#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 ++#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 ++#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) ++#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 ++#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 ++#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 ++#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC ++#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 ++#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 ++#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C ++#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 ++#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 ++#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 ++#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 ++#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 ++#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C ++#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 ++#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 ++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 ++#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF ++#define LOGICAL_PAGE_NUMBER_SHIFT 0 ++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 ++ ++#define PA_CL_ENHANCE 0x8A14 ++#define CLIP_VTX_REORDER_ENA (1 << 0) ++#define NUM_CLIP_SEQ(x) ((x) << 1) ++#define PA_SC_AA_CONFIG 0x28C04 ++#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 ++#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 ++#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 ++#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C ++#define S0_X(x) ((x) << 0) ++#define S0_Y(x) ((x) << 4) ++#define S1_X(x) ((x) << 8) ++#define S1_Y(x) ((x) << 12) ++#define S2_X(x) ((x) << 16) ++#define S2_Y(x) ((x) << 20) ++#define S3_X(x) ((x) << 24) ++#define S3_Y(x) ((x) << 28) ++#define S4_X(x) ((x) << 0) ++#define S4_Y(x) ((x) << 4) ++#define S5_X(x) ((x) << 8) ++#define S5_Y(x) ((x) << 12) ++#define S6_X(x) ((x) << 16) ++#define S6_Y(x) ((x) << 20) ++#define S7_X(x) ((x) << 24) ++#define S7_Y(x) ((x) << 28) ++#define PA_SC_CLIPRECT_RULE 0x2820c ++#define PA_SC_ENHANCE 0x8BF0 ++#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) ++#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) ++#define PA_SC_LINE_STIPPLE 0x28A0C ++#define PA_SC_LINE_STIPPLE_STATE 0x8B10 ++#define PA_SC_MODE_CNTL 0x28A4C ++#define PA_SC_MULTI_CHIP_CNTL 0x8B20 ++ ++#define PA_SC_SCREEN_SCISSOR_TL 0x28030 ++#define PA_SC_GENERIC_SCISSOR_TL 0x28240 ++#define PA_SC_WINDOW_SCISSOR_TL 0x28204 ++ ++#define PCIE_PORT_INDEX 0x0038 ++#define PCIE_PORT_DATA 0x003C ++ ++#define RAMCFG 0x2408 ++#define NOOFBANK_SHIFT 0 ++#define NOOFBANK_MASK 0x00000001 ++#define NOOFRANK_SHIFT 1 ++#define NOOFRANK_MASK 0x00000002 ++#define NOOFROWS_SHIFT 2 ++#define NOOFROWS_MASK 0x0000001C ++#define NOOFCOLS_SHIFT 5 ++#define NOOFCOLS_MASK 0x00000060 ++#define CHANSIZE_SHIFT 7 ++#define CHANSIZE_MASK 0x00000080 ++#define BURSTLENGTH_SHIFT 8 ++#define BURSTLENGTH_MASK 0x00000100 ++#define CHANSIZE_OVERRIDE (1 << 10) ++ ++#define SCRATCH_REG0 0x8500 ++#define SCRATCH_REG1 0x8504 ++#define SCRATCH_REG2 0x8508 ++#define SCRATCH_REG3 0x850C ++#define SCRATCH_REG4 0x8510 ++#define SCRATCH_REG5 0x8514 ++#define SCRATCH_REG6 0x8518 ++#define SCRATCH_REG7 0x851C ++#define SCRATCH_UMSK 0x8540 ++#define SCRATCH_ADDR 0x8544 ++ ++#define SPI_CONFIG_CNTL 0x9100 ++#define GPR_WRITE_PRIORITY(x) ((x) << 0) ++#define DISABLE_INTERP_1 (1 << 5) ++#define SPI_CONFIG_CNTL_1 0x913C ++#define VTX_DONE_DELAY(x) ((x) << 0) ++#define INTERP_ONE_PRIM_PER_ROW (1 << 4) ++#define SPI_INPUT_Z 0x286D8 ++#define SPI_PS_IN_CONTROL_0 0x286CC ++#define NUM_INTERP(x) ((x)<<0) ++#define POSITION_ENA (1<<8) ++#define POSITION_CENTROID (1<<9) ++#define POSITION_ADDR(x) ((x)<<10) ++#define PARAM_GEN(x) ((x)<<15) ++#define PARAM_GEN_ADDR(x) ((x)<<19) ++#define BARYC_SAMPLE_CNTL(x) ((x)<<26) ++#define PERSP_GRADIENT_ENA (1<<28) ++#define LINEAR_GRADIENT_ENA (1<<29) ++#define POSITION_SAMPLE (1<<30) ++#define BARYC_AT_SAMPLE_ENA (1<<31) ++#define SPI_PS_IN_CONTROL_1 0x286D0 ++#define GEN_INDEX_PIX (1<<0) ++#define GEN_INDEX_PIX_ADDR(x) ((x)<<1) ++#define FRONT_FACE_ENA (1<<8) ++#define FRONT_FACE_CHAN(x) ((x)<<9) ++#define FRONT_FACE_ALL_BITS (1<<11) ++#define FRONT_FACE_ADDR(x) ((x)<<12) ++#define FOG_ADDR(x) ((x)<<17) ++#define FIXED_PT_POSITION_ENA (1<<24) ++#define FIXED_PT_POSITION_ADDR(x) ((x)<<25) ++ ++#define SQ_MS_FIFO_SIZES 0x8CF0 ++#define CACHE_FIFO_SIZE(x) ((x) << 0) ++#define FETCH_FIFO_HIWATER(x) ((x) << 8) ++#define DONE_FIFO_HIWATER(x) ((x) << 16) ++#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) ++#define SQ_PGM_START_ES 0x28880 ++#define SQ_PGM_START_FS 0x28894 ++#define SQ_PGM_START_GS 0x2886C ++#define SQ_PGM_START_PS 0x28840 ++#define SQ_PGM_RESOURCES_PS 0x28850 ++#define SQ_PGM_EXPORTS_PS 0x28854 ++#define SQ_PGM_CF_OFFSET_PS 0x288cc ++#define SQ_PGM_START_VS 0x28858 ++#define SQ_PGM_RESOURCES_VS 0x28868 ++#define SQ_PGM_CF_OFFSET_VS 0x288d0 ++#define SQ_VTX_CONSTANT_WORD6_0 0x38018 ++#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) ++#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) ++#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 ++#define SQ_TEX_VTX_INVALID_BUFFER 0x1 ++#define SQ_TEX_VTX_VALID_TEXTURE 0x2 ++#define SQ_TEX_VTX_VALID_BUFFER 0x3 ++ ++ ++#define SX_MISC 0x28350 ++#define SX_DEBUG_1 0x9054 ++#define SMX_EVENT_RELEASE (1 << 0) ++#define ENABLE_NEW_SMX_ADDRESS (1 << 16) ++ ++#define TA_CNTL_AUX 0x9508 ++#define DISABLE_CUBE_WRAP (1 << 0) ++#define DISABLE_CUBE_ANISO (1 << 1) ++#define SYNC_GRADIENT (1 << 24) ++#define SYNC_WALKER (1 << 25) ++#define SYNC_ALIGNER (1 << 26) ++#define BILINEAR_PRECISION_6_BIT (0 << 31) ++#define BILINEAR_PRECISION_8_BIT (1 << 31) ++ ++#define TC_CNTL 0x9608 ++#define TC_L2_SIZE(x) ((x)<<5) ++#define L2_DISABLE_LATE_HIT (1<<9) ++ ++ ++#define VGT_CACHE_INVALIDATION 0x88C4 ++#define CACHE_INVALIDATION(x) ((x)<<0) ++#define VC_ONLY 0 ++#define TC_ONLY 1 ++#define VC_AND_TC 2 ++#define VGT_DMA_BASE 0x287E8 ++#define VGT_DMA_BASE_HI 0x287E4 ++#define VGT_ES_PER_GS 0x88CC ++#define VGT_GS_PER_ES 0x88C8 ++#define VGT_GS_PER_VS 0x88E8 ++#define VGT_GS_VERTEX_REUSE 0x88D4 ++#define VGT_PRIMITIVE_TYPE 0x8958 ++#define VGT_NUM_INSTANCES 0x8974 ++#define VGT_OUT_DEALLOC_CNTL 0x28C5C ++#define DEALLOC_DIST_MASK 0x0000007F ++#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 ++#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 ++#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 ++#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c ++#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 ++#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 ++#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c ++#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 ++#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 ++#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 ++#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 ++#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 ++#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC ++#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC ++#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC ++#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C ++#define VGT_STRMOUT_EN 0x28AB0 ++#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 ++#define VTX_REUSE_DEPTH_MASK 0x000000FF ++#define VGT_EVENT_INITIATOR 0x28a90 ++# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) ++ ++#define VM_CONTEXT0_CNTL 0x1410 ++#define ENABLE_CONTEXT (1 << 0) ++#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) ++#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) ++#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 ++#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 ++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 ++#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 ++#define REQUEST_TYPE(x) (((x) & 0xf) << 0) ++#define RESPONSE_TYPE_MASK 0x000000F0 ++#define RESPONSE_TYPE_SHIFT 4 ++#define VM_L2_CNTL 0x1400 ++#define ENABLE_L2_CACHE (1 << 0) ++#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) ++#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) ++#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) ++#define VM_L2_CNTL2 0x1404 ++#define INVALIDATE_ALL_L1_TLBS (1 << 0) ++#define INVALIDATE_L2_CACHE (1 << 1) ++#define VM_L2_CNTL3 0x1408 ++#define BANK_SELECT_0(x) (((x) & 0x1f) << 0) ++#define BANK_SELECT_1(x) (((x) & 0x1f) << 5) ++#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) ++#define VM_L2_STATUS 0x140C ++#define L2_BUSY (1 << 0) ++ ++#define WAIT_UNTIL 0x8040 ++#define WAIT_2D_IDLE_bit (1 << 14) ++#define WAIT_3D_IDLE_bit (1 << 15) ++#define WAIT_2D_IDLECLEAN_bit (1 << 16) ++#define WAIT_3D_IDLECLEAN_bit (1 << 17) ++ ++ ++ ++/* ++ * PM4 ++ */ ++#define PACKET_TYPE0 0 ++#define PACKET_TYPE1 1 ++#define PACKET_TYPE2 2 ++#define PACKET_TYPE3 3 ++ ++#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) ++#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) ++#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) ++#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) ++#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ ++ (((reg) >> 2) & 0xFFFF) | \ ++ ((n) & 0x3FFF) << 16) ++#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ ++ (((op) & 0xFF) << 8) | \ ++ ((n) & 0x3FFF) << 16) ++ ++/* Packet 3 types */ ++#define PACKET3_NOP 0x10 ++#define PACKET3_INDIRECT_BUFFER_END 0x17 ++#define PACKET3_SET_PREDICATION 0x20 ++#define PACKET3_REG_RMW 0x21 ++#define PACKET3_COND_EXEC 0x22 ++#define PACKET3_PRED_EXEC 0x23 ++#define PACKET3_START_3D_CMDBUF 0x24 ++#define PACKET3_DRAW_INDEX_2 0x27 ++#define PACKET3_CONTEXT_CONTROL 0x28 ++#define PACKET3_DRAW_INDEX_IMMD_BE 0x29 ++#define PACKET3_INDEX_TYPE 0x2A ++#define PACKET3_DRAW_INDEX 0x2B ++#define PACKET3_DRAW_INDEX_AUTO 0x2D ++#define PACKET3_DRAW_INDEX_IMMD 0x2E ++#define PACKET3_NUM_INSTANCES 0x2F ++#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 ++#define PACKET3_INDIRECT_BUFFER_MP 0x38 ++#define PACKET3_MEM_SEMAPHORE 0x39 ++#define PACKET3_MPEG_INDEX 0x3A ++#define PACKET3_WAIT_REG_MEM 0x3C ++#define PACKET3_MEM_WRITE 0x3D ++#define PACKET3_INDIRECT_BUFFER 0x32 ++#define PACKET3_CP_INTERRUPT 0x40 ++#define PACKET3_SURFACE_SYNC 0x43 ++# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) ++# define PACKET3_TC_ACTION_ENA (1 << 23) ++# define PACKET3_VC_ACTION_ENA (1 << 24) ++# define PACKET3_CB_ACTION_ENA (1 << 25) ++# define PACKET3_DB_ACTION_ENA (1 << 26) ++# define PACKET3_SH_ACTION_ENA (1 << 27) ++# define PACKET3_SMX_ACTION_ENA (1 << 28) ++#define PACKET3_ME_INITIALIZE 0x44 ++#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) ++#define PACKET3_COND_WRITE 0x45 ++#define PACKET3_EVENT_WRITE 0x46 ++#define PACKET3_EVENT_WRITE_EOP 0x47 ++#define PACKET3_ONE_REG_WRITE 0x57 ++#define PACKET3_SET_CONFIG_REG 0x68 ++#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 ++#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 ++#define PACKET3_SET_CONTEXT_REG 0x69 ++#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 ++#define PACKET3_SET_CONTEXT_REG_END 0x00029000 ++#define PACKET3_SET_ALU_CONST 0x6A ++#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 ++#define PACKET3_SET_ALU_CONST_END 0x00032000 ++#define PACKET3_SET_BOOL_CONST 0x6B ++#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 ++#define PACKET3_SET_BOOL_CONST_END 0x00040000 ++#define PACKET3_SET_LOOP_CONST 0x6C ++#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 ++#define PACKET3_SET_LOOP_CONST_END 0x0003e380 ++#define PACKET3_SET_RESOURCE 0x6D ++#define PACKET3_SET_RESOURCE_OFFSET 0x00038000 ++#define PACKET3_SET_RESOURCE_END 0x0003c000 ++#define PACKET3_SET_SAMPLER 0x6E ++#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 ++#define PACKET3_SET_SAMPLER_END 0x0003cff0 ++#define PACKET3_SET_CTL_CONST 0x6F ++#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 ++#define PACKET3_SET_CTL_CONST_END 0x0003e200 ++#define PACKET3_SURFACE_BASE_UPDATE 0x73 ++ ++ ++#define R_008020_GRBM_SOFT_RESET 0x8020 ++#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) ++#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) ++#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) ++#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) ++#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) ++#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) ++#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) ++#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) ++#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) ++#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) ++#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) ++#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) ++#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) ++#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) ++#define R_008010_GRBM_STATUS 0x8010 ++#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) ++#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) ++#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) ++#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) ++#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) ++#define S_008010_VC_BUSY(x) (((x) & 1) << 11) ++#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) ++#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) ++#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) ++#define S_008010_VGT_BUSY(x) (((x) & 1) << 17) ++#define S_008010_TA03_BUSY(x) (((x) & 1) << 18) ++#define S_008010_TC_BUSY(x) (((x) & 1) << 19) ++#define S_008010_SX_BUSY(x) (((x) & 1) << 20) ++#define S_008010_SH_BUSY(x) (((x) & 1) << 21) ++#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) ++#define S_008010_SMX_BUSY(x) (((x) & 1) << 23) ++#define S_008010_SC_BUSY(x) (((x) & 1) << 24) ++#define S_008010_PA_BUSY(x) (((x) & 1) << 25) ++#define S_008010_DB03_BUSY(x) (((x) & 1) << 26) ++#define S_008010_CR_BUSY(x) (((x) & 1) << 27) ++#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) ++#define S_008010_CP_BUSY(x) (((x) & 1) << 29) ++#define S_008010_CB03_BUSY(x) (((x) & 1) << 30) ++#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) ++#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) ++#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) ++#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) ++#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) ++#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) ++#define G_008010_VC_BUSY(x) (((x) >> 11) & 1) ++#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) ++#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) ++#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) ++#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) ++#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) ++#define G_008010_TC_BUSY(x) (((x) >> 19) & 1) ++#define G_008010_SX_BUSY(x) (((x) >> 20) & 1) ++#define G_008010_SH_BUSY(x) (((x) >> 21) & 1) ++#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) ++#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) ++#define G_008010_SC_BUSY(x) (((x) >> 24) & 1) ++#define G_008010_PA_BUSY(x) (((x) >> 25) & 1) ++#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) ++#define G_008010_CR_BUSY(x) (((x) >> 27) & 1) ++#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) ++#define G_008010_CP_BUSY(x) (((x) >> 29) & 1) ++#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) ++#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) ++#define R_008014_GRBM_STATUS2 0x8014 ++#define S_008014_CR_CLEAN(x) (((x) & 1) << 0) ++#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) ++#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) ++#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) ++#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) ++#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) ++#define S_008014_TA0_BUSY(x) (((x) & 1) << 12) ++#define S_008014_TA1_BUSY(x) (((x) & 1) << 13) ++#define S_008014_TA2_BUSY(x) (((x) & 1) << 14) ++#define S_008014_TA3_BUSY(x) (((x) & 1) << 15) ++#define S_008014_DB0_BUSY(x) (((x) & 1) << 16) ++#define S_008014_DB1_BUSY(x) (((x) & 1) << 17) ++#define S_008014_DB2_BUSY(x) (((x) & 1) << 18) ++#define S_008014_DB3_BUSY(x) (((x) & 1) << 19) ++#define S_008014_CB0_BUSY(x) (((x) & 1) << 20) ++#define S_008014_CB1_BUSY(x) (((x) & 1) << 21) ++#define S_008014_CB2_BUSY(x) (((x) & 1) << 22) ++#define S_008014_CB3_BUSY(x) (((x) & 1) << 23) ++#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) ++#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) ++#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) ++#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) ++#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) ++#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) ++#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) ++#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) ++#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) ++#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) ++#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) ++#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) ++#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) ++#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) ++#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) ++#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) ++#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) ++#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) ++#define R_000E50_SRBM_STATUS 0x0E50 ++#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) ++#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) ++#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) ++#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) ++#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) ++#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) ++#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) ++#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) ++#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) ++#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) ++#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) ++#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) ++#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) ++#define R_000E60_SRBM_SOFT_RESET 0x0E60 ++#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) ++#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) ++#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) ++#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) ++#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) ++#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) ++#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) ++#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) ++#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) ++#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) ++#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) ++#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) ++#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) ++#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h +index b519fb2..7b0965f 100644 +--- a/drivers/gpu/drm/radeon/radeon.h ++++ b/drivers/gpu/drm/radeon/radeon.h +@@ -44,14 +44,32 @@ + * - TESTING, TESTING, TESTING + */ + ++/* Initialization path: ++ * We expect that acceleration initialization might fail for various ++ * reasons even thought we work hard to make it works on most ++ * configurations. In order to still have a working userspace in such ++ * situation the init path must succeed up to the memory controller ++ * initialization point. Failure before this point are considered as ++ * fatal error. Here is the init callchain : ++ * radeon_device_init perform common structure, mutex initialization ++ * asic_init setup the GPU memory layout and perform all ++ * one time initialization (failure in this ++ * function are considered fatal) ++ * asic_startup setup the GPU acceleration, in order to ++ * follow guideline the first thing this ++ * function should do is setting the GPU ++ * memory controller (only MC setup failure ++ * are considered as fatal) ++ */ ++ + #include <asm/atomic.h> + #include <linux/wait.h> + #include <linux/list.h> + #include <linux/kref.h> + ++#include "radeon_family.h" + #include "radeon_mode.h" + #include "radeon_reg.h" +-#include "r300.h" + + /* + * Modules parameters. +@@ -66,6 +84,7 @@ extern int radeon_gart_size; + extern int radeon_benchmarking; + extern int radeon_testing; + extern int radeon_connector_table; ++extern int radeon_tv; + + /* + * Copy from radeon_drv.h so we don't have to include both and have conflicting +@@ -75,63 +94,7 @@ extern int radeon_connector_table; + #define RADEON_IB_POOL_SIZE 16 + #define RADEON_DEBUGFS_MAX_NUM_FILES 32 + #define RADEONFB_CONN_LIMIT 4 +- +-enum radeon_family { +- CHIP_R100, +- CHIP_RV100, +- CHIP_RS100, +- CHIP_RV200, +- CHIP_RS200, +- CHIP_R200, +- CHIP_RV250, +- CHIP_RS300, +- CHIP_RV280, +- CHIP_R300, +- CHIP_R350, +- CHIP_RV350, +- CHIP_RV380, +- CHIP_R420, +- CHIP_R423, +- CHIP_RV410, +- CHIP_RS400, +- CHIP_RS480, +- CHIP_RS600, +- CHIP_RS690, +- CHIP_RS740, +- CHIP_RV515, +- CHIP_R520, +- CHIP_RV530, +- CHIP_RV560, +- CHIP_RV570, +- CHIP_R580, +- CHIP_R600, +- CHIP_RV610, +- CHIP_RV630, +- CHIP_RV620, +- CHIP_RV635, +- CHIP_RV670, +- CHIP_RS780, +- CHIP_RV770, +- CHIP_RV730, +- CHIP_RV710, +- CHIP_RS880, +- CHIP_LAST, +-}; +- +-enum radeon_chip_flags { +- RADEON_FAMILY_MASK = 0x0000ffffUL, +- RADEON_FLAGS_MASK = 0xffff0000UL, +- RADEON_IS_MOBILITY = 0x00010000UL, +- RADEON_IS_IGP = 0x00020000UL, +- RADEON_SINGLE_CRTC = 0x00040000UL, +- RADEON_IS_AGP = 0x00080000UL, +- RADEON_HAS_HIERZ = 0x00100000UL, +- RADEON_IS_PCIE = 0x00200000UL, +- RADEON_NEW_MEMMAP = 0x00400000UL, +- RADEON_IS_PCI = 0x00800000UL, +- RADEON_IS_IGPGART = 0x01000000UL, +-}; +- ++#define RADEON_BIOS_NUM_SCRATCH 8 + + /* + * Errata workarounds. +@@ -151,10 +114,21 @@ struct radeon_device; + */ + bool radeon_get_bios(struct radeon_device *rdev); + ++ + /* +- * Clocks ++ * Dummy page + */ ++struct radeon_dummy_page { ++ struct page *page; ++ dma_addr_t addr; ++}; ++int radeon_dummy_page_init(struct radeon_device *rdev); ++void radeon_dummy_page_fini(struct radeon_device *rdev); + ++ ++/* ++ * Clocks ++ */ + struct radeon_clock { + struct radeon_pll p1pll; + struct radeon_pll p2pll; +@@ -165,6 +139,7 @@ struct radeon_clock { + uint32_t default_sclk; + }; + ++ + /* + * Fences. + */ +@@ -331,14 +306,18 @@ struct radeon_mc { + resource_size_t aper_size; + resource_size_t aper_base; + resource_size_t agp_base; +- unsigned gtt_location; +- unsigned gtt_size; +- unsigned vram_location; + /* for some chips with <= 32MB we need to lie + * about vram size near mc fb location */ +- unsigned mc_vram_size; ++ u64 mc_vram_size; ++ u64 gtt_location; ++ u64 gtt_size; ++ u64 gtt_start; ++ u64 gtt_end; ++ u64 vram_location; ++ u64 vram_start; ++ u64 vram_end; + unsigned vram_width; +- unsigned real_vram_size; ++ u64 real_vram_size; + int vram_mtrr; + bool vram_is_ddr; + }; +@@ -381,10 +360,14 @@ struct radeon_ib { + unsigned long idx; + uint64_t gpu_addr; + struct radeon_fence *fence; +- volatile uint32_t *ptr; ++ uint32_t *ptr; + uint32_t length_dw; + }; + ++/* ++ * locking - ++ * mutex protects scheduled_ibs, ready, alloc_bm ++ */ + struct radeon_ib_pool { + struct mutex mutex; + struct radeon_object *robj; +@@ -410,6 +393,16 @@ struct radeon_cp { + bool ready; + }; + ++struct r600_blit { ++ struct radeon_object *shader_obj; ++ u64 shader_gpu_addr; ++ u32 vs_offset, ps_offset; ++ u32 state_offset; ++ u32 state_len; ++ u32 vb_used, vb_total; ++ struct radeon_ib *vb_ib; ++}; ++ + int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); + void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); + int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); +@@ -440,7 +433,12 @@ struct radeon_cs_reloc { + struct radeon_cs_chunk { + uint32_t chunk_id; + uint32_t length_dw; ++ int kpage_idx[2]; ++ uint32_t *kpage[2]; + uint32_t *kdata; ++ void __user *user_ptr; ++ int last_copied_page; ++ int last_page_index; + }; + + struct radeon_cs_parser { +@@ -462,8 +460,39 @@ struct radeon_cs_parser { + int chunk_relocs_idx; + struct radeon_ib *ib; + void *track; ++ unsigned family; ++ int parser_error; + }; + ++extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); ++extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); ++ ++ ++static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) ++{ ++ struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; ++ u32 pg_idx, pg_offset; ++ u32 idx_value = 0; ++ int new_page; ++ ++ pg_idx = (idx * 4) / PAGE_SIZE; ++ pg_offset = (idx * 4) % PAGE_SIZE; ++ ++ if (ibc->kpage_idx[0] == pg_idx) ++ return ibc->kpage[0][pg_offset/4]; ++ if (ibc->kpage_idx[1] == pg_idx) ++ return ibc->kpage[1][pg_offset/4]; ++ ++ new_page = radeon_cs_update_pages(p, pg_idx); ++ if (new_page < 0) { ++ p->parser_error = new_page; ++ return 0; ++ } ++ ++ idx_value = ibc->kpage[new_page][pg_offset/4]; ++ return idx_value; ++} ++ + struct radeon_cs_packet { + unsigned idx; + unsigned type; +@@ -558,6 +587,9 @@ int r100_debugfs_cp_init(struct radeon_device *rdev); + */ + struct radeon_asic { + int (*init)(struct radeon_device *rdev); ++ void (*fini)(struct radeon_device *rdev); ++ int (*resume)(struct radeon_device *rdev); ++ int (*suspend)(struct radeon_device *rdev); + void (*errata)(struct radeon_device *rdev); + void (*vram_info)(struct radeon_device *rdev); + int (*gpu_reset)(struct radeon_device *rdev); +@@ -565,6 +597,8 @@ struct radeon_asic { + void (*mc_fini)(struct radeon_device *rdev); + int (*wb_init)(struct radeon_device *rdev); + void (*wb_fini)(struct radeon_device *rdev); ++ int (*gart_init)(struct radeon_device *rdev); ++ void (*gart_fini)(struct radeon_device *rdev); + int (*gart_enable)(struct radeon_device *rdev); + void (*gart_disable)(struct radeon_device *rdev); + void (*gart_tlb_flush)(struct radeon_device *rdev); +@@ -572,7 +606,11 @@ struct radeon_asic { + int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); + void (*cp_fini)(struct radeon_device *rdev); + void (*cp_disable)(struct radeon_device *rdev); ++ void (*cp_commit)(struct radeon_device *rdev); + void (*ring_start)(struct radeon_device *rdev); ++ int (*ring_test)(struct radeon_device *rdev); ++ void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); ++ int (*ib_test)(struct radeon_device *rdev); + int (*irq_set)(struct radeon_device *rdev); + int (*irq_process)(struct radeon_device *rdev); + u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); +@@ -604,8 +642,60 @@ struct radeon_asic { + void (*bandwidth_update)(struct radeon_device *rdev); + }; + ++/* ++ * Asic structures ++ */ ++struct r100_asic { ++ const unsigned *reg_safe_bm; ++ unsigned reg_safe_bm_size; ++}; ++ ++struct r300_asic { ++ const unsigned *reg_safe_bm; ++ unsigned reg_safe_bm_size; ++}; ++ ++struct r600_asic { ++ unsigned max_pipes; ++ unsigned max_tile_pipes; ++ unsigned max_simds; ++ unsigned max_backends; ++ unsigned max_gprs; ++ unsigned max_threads; ++ unsigned max_stack_entries; ++ unsigned max_hw_contexts; ++ unsigned max_gs_threads; ++ unsigned sx_max_export_size; ++ unsigned sx_max_export_pos_size; ++ unsigned sx_max_export_smx_size; ++ unsigned sq_num_cf_insts; ++}; ++ ++struct rv770_asic { ++ unsigned max_pipes; ++ unsigned max_tile_pipes; ++ unsigned max_simds; ++ unsigned max_backends; ++ unsigned max_gprs; ++ unsigned max_threads; ++ unsigned max_stack_entries; ++ unsigned max_hw_contexts; ++ unsigned max_gs_threads; ++ unsigned sx_max_export_size; ++ unsigned sx_max_export_pos_size; ++ unsigned sx_max_export_smx_size; ++ unsigned sq_num_cf_insts; ++ unsigned sx_num_of_sets; ++ unsigned sc_prim_fifo_size; ++ unsigned sc_hiz_tile_fifo_size; ++ unsigned sc_earlyz_tile_fifo_fize; ++}; ++ + union radeon_asic_config { + struct r300_asic r300; ++ struct r100_asic r100; ++ struct r600_asic r600; ++ struct rv770_asic rv770; + }; + + +@@ -646,6 +736,7 @@ typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); + typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); + + struct radeon_device { ++ struct device *dev; + struct drm_device *ddev; + struct pci_dev *pdev; + /* ASIC */ +@@ -689,13 +780,20 @@ struct radeon_device { + struct radeon_asic *asic; + struct radeon_gem gem; + struct radeon_pm pm; ++ uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; + struct mutex cs_mutex; + struct radeon_wb wb; ++ struct radeon_dummy_page dummy_page; + bool gpu_lockup; + bool shutdown; + bool suspend; + bool need_dma32; ++ bool new_init_path; ++ bool accel_working; + struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; ++ const struct firmware *me_fw; /* all family ME firmware */ ++ const struct firmware *pfp_fw; /* r6/700 PFP firmware */ ++ struct r600_blit r600_blit; + }; + + int radeon_device_init(struct radeon_device *rdev, +@@ -705,6 +803,13 @@ int radeon_device_init(struct radeon_device *rdev, + void radeon_device_fini(struct radeon_device *rdev); + int radeon_gpu_wait_for_idle(struct radeon_device *rdev); + ++/* r600 blit */ ++int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); ++void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); ++void r600_kms_blit_copy(struct radeon_device *rdev, ++ u64 src_gpu_addr, u64 dst_gpu_addr, ++ int size_bytes); ++ + static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) + { + if (reg < 0x10000) +@@ -732,6 +837,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32 + #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) + #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) + #define RREG32(reg) r100_mm_rreg(rdev, (reg)) ++#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) + #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) + #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) + #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) +@@ -755,6 +861,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32 + tmp_ |= ((val) & ~(mask)); \ + WREG32_PLL(reg, tmp_); \ + } while (0) ++#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) + + /* + * Indirect registers accessor +@@ -819,51 +926,6 @@ void radeon_atombios_fini(struct radeon_device *rdev); + /* + * RING helpers. + */ +-#define CP_PACKET0 0x00000000 +-#define PACKET0_BASE_INDEX_SHIFT 0 +-#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) +-#define PACKET0_COUNT_SHIFT 16 +-#define PACKET0_COUNT_MASK (0x3fff << 16) +-#define CP_PACKET1 0x40000000 +-#define CP_PACKET2 0x80000000 +-#define PACKET2_PAD_SHIFT 0 +-#define PACKET2_PAD_MASK (0x3fffffff << 0) +-#define CP_PACKET3 0xC0000000 +-#define PACKET3_IT_OPCODE_SHIFT 8 +-#define PACKET3_IT_OPCODE_MASK (0xff << 8) +-#define PACKET3_COUNT_SHIFT 16 +-#define PACKET3_COUNT_MASK (0x3fff << 16) +-/* PACKET3 op code */ +-#define PACKET3_NOP 0x10 +-#define PACKET3_3D_DRAW_VBUF 0x28 +-#define PACKET3_3D_DRAW_IMMD 0x29 +-#define PACKET3_3D_DRAW_INDX 0x2A +-#define PACKET3_3D_LOAD_VBPNTR 0x2F +-#define PACKET3_INDX_BUFFER 0x33 +-#define PACKET3_3D_DRAW_VBUF_2 0x34 +-#define PACKET3_3D_DRAW_IMMD_2 0x35 +-#define PACKET3_3D_DRAW_INDX_2 0x36 +-#define PACKET3_BITBLT_MULTI 0x9B +- +-#define PACKET0(reg, n) (CP_PACKET0 | \ +- REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ +- REG_SET(PACKET0_COUNT, (n))) +-#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +-#define PACKET3(op, n) (CP_PACKET3 | \ +- REG_SET(PACKET3_IT_OPCODE, (op)) | \ +- REG_SET(PACKET3_COUNT, (n))) +- +-#define PACKET_TYPE0 0 +-#define PACKET_TYPE1 1 +-#define PACKET_TYPE2 2 +-#define PACKET_TYPE3 3 +- +-#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +-#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +-#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) +-#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) +-#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +- + static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) + { + #if DRM_DEBUG_CODE +@@ -882,6 +944,9 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) + * ASICs macro. + */ + #define radeon_init(rdev) (rdev)->asic->init((rdev)) ++#define radeon_fini(rdev) (rdev)->asic->fini((rdev)) ++#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) ++#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) + #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) + #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) + #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) +@@ -890,6 +955,8 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) + #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) + #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) + #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) ++#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev)) ++#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev)) + #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) + #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) + #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) +@@ -897,7 +964,11 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) + #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) + #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) + #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) ++#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) + #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) ++#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) ++#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) ++#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev)) + #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) + #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) + #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) +@@ -913,4 +984,109 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) + #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) + #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) + ++/* Common functions */ ++extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); ++extern int radeon_modeset_init(struct radeon_device *rdev); ++extern void radeon_modeset_fini(struct radeon_device *rdev); ++extern bool radeon_card_posted(struct radeon_device *rdev); ++extern int radeon_clocks_init(struct radeon_device *rdev); ++extern void radeon_clocks_fini(struct radeon_device *rdev); ++extern void radeon_scratch_init(struct radeon_device *rdev); ++extern void radeon_surface_init(struct radeon_device *rdev); ++extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); ++extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); ++ ++/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ ++struct r100_mc_save { ++ u32 GENMO_WT; ++ u32 CRTC_EXT_CNTL; ++ u32 CRTC_GEN_CNTL; ++ u32 CRTC2_GEN_CNTL; ++ u32 CUR_OFFSET; ++ u32 CUR2_OFFSET; ++}; ++extern void r100_cp_disable(struct radeon_device *rdev); ++extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); ++extern void r100_cp_fini(struct radeon_device *rdev); ++extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); ++extern int r100_pci_gart_init(struct radeon_device *rdev); ++extern void r100_pci_gart_fini(struct radeon_device *rdev); ++extern int r100_pci_gart_enable(struct radeon_device *rdev); ++extern void r100_pci_gart_disable(struct radeon_device *rdev); ++extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); ++extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); ++extern int r100_gui_wait_for_idle(struct radeon_device *rdev); ++extern void r100_ib_fini(struct radeon_device *rdev); ++extern int r100_ib_init(struct radeon_device *rdev); ++extern void r100_irq_disable(struct radeon_device *rdev); ++extern int r100_irq_set(struct radeon_device *rdev); ++extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); ++extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); ++extern void r100_vram_init_sizes(struct radeon_device *rdev); ++extern void r100_wb_disable(struct radeon_device *rdev); ++extern void r100_wb_fini(struct radeon_device *rdev); ++extern int r100_wb_init(struct radeon_device *rdev); ++extern void r100_hdp_reset(struct radeon_device *rdev); ++extern int r100_rb2d_reset(struct radeon_device *rdev); ++extern int r100_cp_reset(struct radeon_device *rdev); ++ ++/* r300,r350,rv350,rv370,rv380 */ ++extern void r300_set_reg_safe(struct radeon_device *rdev); ++extern void r300_mc_program(struct radeon_device *rdev); ++extern void r300_vram_info(struct radeon_device *rdev); ++extern int rv370_pcie_gart_init(struct radeon_device *rdev); ++extern void rv370_pcie_gart_fini(struct radeon_device *rdev); ++extern int rv370_pcie_gart_enable(struct radeon_device *rdev); ++extern void rv370_pcie_gart_disable(struct radeon_device *rdev); ++ ++/* r420,r423,rv410 */ ++extern int r420_mc_init(struct radeon_device *rdev); ++extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); ++extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); ++extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); ++extern void r420_pipes_init(struct radeon_device *rdev); ++ ++/* rv515 */ ++struct rv515_mc_save { ++ u32 d1vga_control; ++ u32 d2vga_control; ++ u32 vga_render_control; ++ u32 vga_hdp_control; ++ u32 d1crtc_control; ++ u32 d2crtc_control; ++}; ++extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); ++extern void rv515_vga_render_disable(struct radeon_device *rdev); ++extern void rv515_set_safe_registers(struct radeon_device *rdev); ++extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); ++extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); ++extern void rv515_clock_startup(struct radeon_device *rdev); ++extern void rv515_debugfs(struct radeon_device *rdev); ++extern int rv515_suspend(struct radeon_device *rdev); ++ ++/* rs690, rs740 */ ++extern void rs690_line_buffer_adjust(struct radeon_device *rdev, ++ struct drm_display_mode *mode1, ++ struct drm_display_mode *mode2); ++ ++/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ ++extern bool r600_card_posted(struct radeon_device *rdev); ++extern void r600_cp_stop(struct radeon_device *rdev); ++extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); ++extern int r600_cp_resume(struct radeon_device *rdev); ++extern int r600_count_pipe_bits(uint32_t val); ++extern int r600_gart_clear_page(struct radeon_device *rdev, int i); ++extern int r600_mc_wait_for_idle(struct radeon_device *rdev); ++extern int r600_pcie_gart_init(struct radeon_device *rdev); ++extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); ++extern int r600_ib_test(struct radeon_device *rdev); ++extern int r600_ring_test(struct radeon_device *rdev); ++extern int r600_wb_init(struct radeon_device *rdev); ++extern void r600_wb_fini(struct radeon_device *rdev); ++extern void r600_scratch_init(struct radeon_device *rdev); ++extern int r600_blit_init(struct radeon_device *rdev); ++extern void r600_blit_fini(struct radeon_device *rdev); ++extern int r600_cp_init_microcode(struct radeon_device *rdev); ++extern int r600_gpu_reset(struct radeon_device *rdev); ++ + #endif +diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h +index 93d8f88..bce0cb0 100644 +--- a/drivers/gpu/drm/radeon/radeon_asic.h ++++ b/drivers/gpu/drm/radeon/radeon_asic.h +@@ -42,6 +42,7 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); + * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 + */ + int r100_init(struct radeon_device *rdev); ++int r200_init(struct radeon_device *rdev); + uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); + void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); + void r100_errata(struct radeon_device *rdev); +@@ -52,13 +53,16 @@ void r100_mc_fini(struct radeon_device *rdev); + u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); + int r100_wb_init(struct radeon_device *rdev); + void r100_wb_fini(struct radeon_device *rdev); +-int r100_gart_enable(struct radeon_device *rdev); ++int r100_pci_gart_init(struct radeon_device *rdev); ++void r100_pci_gart_fini(struct radeon_device *rdev); ++int r100_pci_gart_enable(struct radeon_device *rdev); + void r100_pci_gart_disable(struct radeon_device *rdev); + void r100_pci_gart_tlb_flush(struct radeon_device *rdev); + int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); + int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); + void r100_cp_fini(struct radeon_device *rdev); + void r100_cp_disable(struct radeon_device *rdev); ++void r100_cp_commit(struct radeon_device *rdev); + void r100_ring_start(struct radeon_device *rdev); + int r100_irq_set(struct radeon_device *rdev); + int r100_irq_process(struct radeon_device *rdev); +@@ -77,6 +81,9 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg, + uint32_t offset, uint32_t obj_size); + int r100_clear_surface_reg(struct radeon_device *rdev, int reg); + void r100_bandwidth_update(struct radeon_device *rdev); ++void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); ++int r100_ib_test(struct radeon_device *rdev); ++int r100_ring_test(struct radeon_device *rdev); + + static struct radeon_asic r100_asic = { + .init = &r100_init, +@@ -87,14 +94,20 @@ static struct radeon_asic r100_asic = { + .mc_fini = &r100_mc_fini, + .wb_init = &r100_wb_init, + .wb_fini = &r100_wb_fini, +- .gart_enable = &r100_gart_enable, ++ .gart_init = &r100_pci_gart_init, ++ .gart_fini = &r100_pci_gart_fini, ++ .gart_enable = &r100_pci_gart_enable, + .gart_disable = &r100_pci_gart_disable, + .gart_tlb_flush = &r100_pci_gart_tlb_flush, + .gart_set_page = &r100_pci_gart_set_page, + .cp_init = &r100_cp_init, + .cp_fini = &r100_cp_fini, + .cp_disable = &r100_cp_disable, ++ .cp_commit = &r100_cp_commit, + .ring_start = &r100_ring_start, ++ .ring_test = &r100_ring_test, ++ .ring_ib_execute = &r100_ring_ib_execute, ++ .ib_test = &r100_ib_test, + .irq_set = &r100_irq_set, + .irq_process = &r100_irq_process, + .get_vblank_counter = &r100_get_vblank_counter, +@@ -126,7 +139,9 @@ void r300_ring_start(struct radeon_device *rdev); + void r300_fence_ring_emit(struct radeon_device *rdev, + struct radeon_fence *fence); + int r300_cs_parse(struct radeon_cs_parser *p); +-int r300_gart_enable(struct radeon_device *rdev); ++int rv370_pcie_gart_init(struct radeon_device *rdev); ++void rv370_pcie_gart_fini(struct radeon_device *rdev); ++int rv370_pcie_gart_enable(struct radeon_device *rdev); + void rv370_pcie_gart_disable(struct radeon_device *rdev); + void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); + int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); +@@ -148,14 +163,20 @@ static struct radeon_asic r300_asic = { + .mc_fini = &r300_mc_fini, + .wb_init = &r100_wb_init, + .wb_fini = &r100_wb_fini, +- .gart_enable = &r300_gart_enable, ++ .gart_init = &r100_pci_gart_init, ++ .gart_fini = &r100_pci_gart_fini, ++ .gart_enable = &r100_pci_gart_enable, + .gart_disable = &r100_pci_gart_disable, + .gart_tlb_flush = &r100_pci_gart_tlb_flush, + .gart_set_page = &r100_pci_gart_set_page, + .cp_init = &r100_cp_init, + .cp_fini = &r100_cp_fini, + .cp_disable = &r100_cp_disable, ++ .cp_commit = &r100_cp_commit, + .ring_start = &r300_ring_start, ++ .ring_test = &r100_ring_test, ++ .ring_ib_execute = &r100_ring_ib_execute, ++ .ib_test = &r100_ib_test, + .irq_set = &r100_irq_set, + .irq_process = &r100_irq_process, + .get_vblank_counter = &r100_get_vblank_counter, +@@ -176,27 +197,34 @@ static struct radeon_asic r300_asic = { + /* + * r420,r423,rv410 + */ +-void r420_errata(struct radeon_device *rdev); +-void r420_vram_info(struct radeon_device *rdev); +-int r420_mc_init(struct radeon_device *rdev); +-void r420_mc_fini(struct radeon_device *rdev); ++extern int r420_init(struct radeon_device *rdev); ++extern void r420_fini(struct radeon_device *rdev); ++extern int r420_suspend(struct radeon_device *rdev); ++extern int r420_resume(struct radeon_device *rdev); + static struct radeon_asic r420_asic = { +- .init = &r300_init, +- .errata = &r420_errata, +- .vram_info = &r420_vram_info, ++ .init = &r420_init, ++ .fini = &r420_fini, ++ .suspend = &r420_suspend, ++ .resume = &r420_resume, ++ .errata = NULL, ++ .vram_info = NULL, + .gpu_reset = &r300_gpu_reset, +- .mc_init = &r420_mc_init, +- .mc_fini = &r420_mc_fini, +- .wb_init = &r100_wb_init, +- .wb_fini = &r100_wb_fini, +- .gart_enable = &r300_gart_enable, +- .gart_disable = &rv370_pcie_gart_disable, ++ .mc_init = NULL, ++ .mc_fini = NULL, ++ .wb_init = NULL, ++ .wb_fini = NULL, ++ .gart_enable = NULL, ++ .gart_disable = NULL, + .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, + .gart_set_page = &rv370_pcie_gart_set_page, +- .cp_init = &r100_cp_init, +- .cp_fini = &r100_cp_fini, +- .cp_disable = &r100_cp_disable, ++ .cp_init = NULL, ++ .cp_fini = NULL, ++ .cp_disable = NULL, ++ .cp_commit = &r100_cp_commit, + .ring_start = &r300_ring_start, ++ .ring_test = &r100_ring_test, ++ .ring_ib_execute = &r100_ring_ib_execute, ++ .ib_test = NULL, + .irq_set = &r100_irq_set, + .irq_process = &r100_irq_process, + .get_vblank_counter = &r100_get_vblank_counter, +@@ -222,6 +250,8 @@ void rs400_errata(struct radeon_device *rdev); + void rs400_vram_info(struct radeon_device *rdev); + int rs400_mc_init(struct radeon_device *rdev); + void rs400_mc_fini(struct radeon_device *rdev); ++int rs400_gart_init(struct radeon_device *rdev); ++void rs400_gart_fini(struct radeon_device *rdev); + int rs400_gart_enable(struct radeon_device *rdev); + void rs400_gart_disable(struct radeon_device *rdev); + void rs400_gart_tlb_flush(struct radeon_device *rdev); +@@ -237,6 +267,8 @@ static struct radeon_asic rs400_asic = { + .mc_fini = &rs400_mc_fini, + .wb_init = &r100_wb_init, + .wb_fini = &r100_wb_fini, ++ .gart_init = &rs400_gart_init, ++ .gart_fini = &rs400_gart_fini, + .gart_enable = &rs400_gart_enable, + .gart_disable = &rs400_gart_disable, + .gart_tlb_flush = &rs400_gart_tlb_flush, +@@ -244,7 +276,11 @@ static struct radeon_asic rs400_asic = { + .cp_init = &r100_cp_init, + .cp_fini = &r100_cp_fini, + .cp_disable = &r100_cp_disable, ++ .cp_commit = &r100_cp_commit, + .ring_start = &r300_ring_start, ++ .ring_test = &r100_ring_test, ++ .ring_ib_execute = &r100_ring_ib_execute, ++ .ib_test = &r100_ib_test, + .irq_set = &r100_irq_set, + .irq_process = &r100_irq_process, + .get_vblank_counter = &r100_get_vblank_counter, +@@ -266,7 +302,7 @@ static struct radeon_asic rs400_asic = { + /* + * rs600. + */ +-int rs600_init(struct radeon_device *dev); ++int rs600_init(struct radeon_device *rdev); + void rs600_errata(struct radeon_device *rdev); + void rs600_vram_info(struct radeon_device *rdev); + int rs600_mc_init(struct radeon_device *rdev); +@@ -274,6 +310,8 @@ void rs600_mc_fini(struct radeon_device *rdev); + int rs600_irq_set(struct radeon_device *rdev); + int rs600_irq_process(struct radeon_device *rdev); + u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); ++int rs600_gart_init(struct radeon_device *rdev); ++void rs600_gart_fini(struct radeon_device *rdev); + int rs600_gart_enable(struct radeon_device *rdev); + void rs600_gart_disable(struct radeon_device *rdev); + void rs600_gart_tlb_flush(struct radeon_device *rdev); +@@ -290,6 +328,8 @@ static struct radeon_asic rs600_asic = { + .mc_fini = &rs600_mc_fini, + .wb_init = &r100_wb_init, + .wb_fini = &r100_wb_fini, ++ .gart_init = &rs600_gart_init, ++ .gart_fini = &rs600_gart_fini, + .gart_enable = &rs600_gart_enable, + .gart_disable = &rs600_gart_disable, + .gart_tlb_flush = &rs600_gart_tlb_flush, +@@ -297,7 +337,11 @@ static struct radeon_asic rs600_asic = { + .cp_init = &r100_cp_init, + .cp_fini = &r100_cp_fini, + .cp_disable = &r100_cp_disable, ++ .cp_commit = &r100_cp_commit, + .ring_start = &r300_ring_start, ++ .ring_test = &r100_ring_test, ++ .ring_ib_execute = &r100_ring_ib_execute, ++ .ib_test = &r100_ib_test, + .irq_set = &rs600_irq_set, + .irq_process = &rs600_irq_process, + .get_vblank_counter = &rs600_get_vblank_counter, +@@ -333,6 +377,8 @@ static struct radeon_asic rs690_asic = { + .mc_fini = &rs690_mc_fini, + .wb_init = &r100_wb_init, + .wb_fini = &r100_wb_fini, ++ .gart_init = &rs400_gart_init, ++ .gart_fini = &rs400_gart_fini, + .gart_enable = &rs400_gart_enable, + .gart_disable = &rs400_gart_disable, + .gart_tlb_flush = &rs400_gart_tlb_flush, +@@ -340,7 +386,11 @@ static struct radeon_asic rs690_asic = { + .cp_init = &r100_cp_init, + .cp_fini = &r100_cp_fini, + .cp_disable = &r100_cp_disable, ++ .cp_commit = &r100_cp_commit, + .ring_start = &r300_ring_start, ++ .ring_test = &r100_ring_test, ++ .ring_ib_execute = &r100_ring_ib_execute, ++ .ib_test = &r100_ib_test, + .irq_set = &rs600_irq_set, + .irq_process = &rs600_irq_process, + .get_vblank_counter = &rs600_get_vblank_counter, +@@ -363,34 +413,42 @@ static struct radeon_asic rs690_asic = { + * rv515 + */ + int rv515_init(struct radeon_device *rdev); +-void rv515_errata(struct radeon_device *rdev); +-void rv515_vram_info(struct radeon_device *rdev); ++void rv515_fini(struct radeon_device *rdev); + int rv515_gpu_reset(struct radeon_device *rdev); +-int rv515_mc_init(struct radeon_device *rdev); +-void rv515_mc_fini(struct radeon_device *rdev); + uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); + void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); + void rv515_ring_start(struct radeon_device *rdev); + uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); + void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); + void rv515_bandwidth_update(struct radeon_device *rdev); ++int rv515_resume(struct radeon_device *rdev); ++int rv515_suspend(struct radeon_device *rdev); + static struct radeon_asic rv515_asic = { + .init = &rv515_init, +- .errata = &rv515_errata, +- .vram_info = &rv515_vram_info, ++ .fini = &rv515_fini, ++ .suspend = &rv515_suspend, ++ .resume = &rv515_resume, ++ .errata = NULL, ++ .vram_info = NULL, + .gpu_reset = &rv515_gpu_reset, +- .mc_init = &rv515_mc_init, +- .mc_fini = &rv515_mc_fini, +- .wb_init = &r100_wb_init, +- .wb_fini = &r100_wb_fini, +- .gart_enable = &r300_gart_enable, +- .gart_disable = &rv370_pcie_gart_disable, ++ .mc_init = NULL, ++ .mc_fini = NULL, ++ .wb_init = NULL, ++ .wb_fini = NULL, ++ .gart_init = &rv370_pcie_gart_init, ++ .gart_fini = &rv370_pcie_gart_fini, ++ .gart_enable = NULL, ++ .gart_disable = NULL, + .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, + .gart_set_page = &rv370_pcie_gart_set_page, +- .cp_init = &r100_cp_init, +- .cp_fini = &r100_cp_fini, +- .cp_disable = &r100_cp_disable, ++ .cp_init = NULL, ++ .cp_fini = NULL, ++ .cp_disable = NULL, ++ .cp_commit = &r100_cp_commit, + .ring_start = &rv515_ring_start, ++ .ring_test = &r100_ring_test, ++ .ring_ib_execute = &r100_ring_ib_execute, ++ .ib_test = NULL, + .irq_set = &rs600_irq_set, + .irq_process = &rs600_irq_process, + .get_vblank_counter = &rs600_get_vblank_counter, +@@ -412,28 +470,34 @@ static struct radeon_asic rv515_asic = { + /* + * r520,rv530,rv560,rv570,r580 + */ +-void r520_errata(struct radeon_device *rdev); +-void r520_vram_info(struct radeon_device *rdev); +-int r520_mc_init(struct radeon_device *rdev); +-void r520_mc_fini(struct radeon_device *rdev); +-void r520_bandwidth_update(struct radeon_device *rdev); ++int r520_init(struct radeon_device *rdev); ++int r520_resume(struct radeon_device *rdev); + static struct radeon_asic r520_asic = { +- .init = &rv515_init, +- .errata = &r520_errata, +- .vram_info = &r520_vram_info, ++ .init = &r520_init, ++ .fini = &rv515_fini, ++ .suspend = &rv515_suspend, ++ .resume = &r520_resume, ++ .errata = NULL, ++ .vram_info = NULL, + .gpu_reset = &rv515_gpu_reset, +- .mc_init = &r520_mc_init, +- .mc_fini = &r520_mc_fini, +- .wb_init = &r100_wb_init, +- .wb_fini = &r100_wb_fini, +- .gart_enable = &r300_gart_enable, +- .gart_disable = &rv370_pcie_gart_disable, ++ .mc_init = NULL, ++ .mc_fini = NULL, ++ .wb_init = NULL, ++ .wb_fini = NULL, ++ .gart_init = NULL, ++ .gart_fini = NULL, ++ .gart_enable = NULL, ++ .gart_disable = NULL, + .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, + .gart_set_page = &rv370_pcie_gart_set_page, +- .cp_init = &r100_cp_init, +- .cp_fini = &r100_cp_fini, +- .cp_disable = &r100_cp_disable, ++ .cp_init = NULL, ++ .cp_fini = NULL, ++ .cp_disable = NULL, ++ .cp_commit = &r100_cp_commit, + .ring_start = &rv515_ring_start, ++ .ring_test = &r100_ring_test, ++ .ring_ib_execute = &r100_ring_ib_execute, ++ .ib_test = NULL, + .irq_set = &rs600_irq_set, + .irq_process = &rs600_irq_process, + .get_vblank_counter = &rs600_get_vblank_counter, +@@ -448,13 +512,131 @@ static struct radeon_asic r520_asic = { + .set_clock_gating = &radeon_atom_set_clock_gating, + .set_surface_reg = r100_set_surface_reg, + .clear_surface_reg = r100_clear_surface_reg, +- .bandwidth_update = &r520_bandwidth_update, ++ .bandwidth_update = &rv515_bandwidth_update, + }; + + /* +- * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710 ++ * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 + */ ++int r600_init(struct radeon_device *rdev); ++void r600_fini(struct radeon_device *rdev); ++int r600_suspend(struct radeon_device *rdev); ++int r600_resume(struct radeon_device *rdev); ++int r600_wb_init(struct radeon_device *rdev); ++void r600_wb_fini(struct radeon_device *rdev); ++void r600_cp_commit(struct radeon_device *rdev); ++void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); + uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); + void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); ++int r600_cs_parse(struct radeon_cs_parser *p); ++void r600_fence_ring_emit(struct radeon_device *rdev, ++ struct radeon_fence *fence); ++int r600_copy_dma(struct radeon_device *rdev, ++ uint64_t src_offset, ++ uint64_t dst_offset, ++ unsigned num_pages, ++ struct radeon_fence *fence); ++int r600_irq_process(struct radeon_device *rdev); ++int r600_irq_set(struct radeon_device *rdev); ++int r600_gpu_reset(struct radeon_device *rdev); ++int r600_set_surface_reg(struct radeon_device *rdev, int reg, ++ uint32_t tiling_flags, uint32_t pitch, ++ uint32_t offset, uint32_t obj_size); ++int r600_clear_surface_reg(struct radeon_device *rdev, int reg); ++void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); ++int r600_ib_test(struct radeon_device *rdev); ++int r600_ring_test(struct radeon_device *rdev); ++int r600_copy_blit(struct radeon_device *rdev, ++ uint64_t src_offset, uint64_t dst_offset, ++ unsigned num_pages, struct radeon_fence *fence); ++ ++static struct radeon_asic r600_asic = { ++ .errata = NULL, ++ .init = &r600_init, ++ .fini = &r600_fini, ++ .suspend = &r600_suspend, ++ .resume = &r600_resume, ++ .cp_commit = &r600_cp_commit, ++ .vram_info = NULL, ++ .gpu_reset = &r600_gpu_reset, ++ .mc_init = NULL, ++ .mc_fini = NULL, ++ .wb_init = &r600_wb_init, ++ .wb_fini = &r600_wb_fini, ++ .gart_enable = NULL, ++ .gart_disable = NULL, ++ .gart_tlb_flush = &r600_pcie_gart_tlb_flush, ++ .gart_set_page = &rs600_gart_set_page, ++ .cp_init = NULL, ++ .cp_fini = NULL, ++ .cp_disable = NULL, ++ .ring_start = NULL, ++ .ring_test = &r600_ring_test, ++ .ring_ib_execute = &r600_ring_ib_execute, ++ .ib_test = &r600_ib_test, ++ .irq_set = &r600_irq_set, ++ .irq_process = &r600_irq_process, ++ .fence_ring_emit = &r600_fence_ring_emit, ++ .cs_parse = &r600_cs_parse, ++ .copy_blit = &r600_copy_blit, ++ .copy_dma = &r600_copy_blit, ++ .copy = &r600_copy_blit, ++ .set_engine_clock = &radeon_atom_set_engine_clock, ++ .set_memory_clock = &radeon_atom_set_memory_clock, ++ .set_pcie_lanes = NULL, ++ .set_clock_gating = &radeon_atom_set_clock_gating, ++ .set_surface_reg = r600_set_surface_reg, ++ .clear_surface_reg = r600_clear_surface_reg, ++ .bandwidth_update = &rv515_bandwidth_update, ++}; ++ ++/* ++ * rv770,rv730,rv710,rv740 ++ */ ++int rv770_init(struct radeon_device *rdev); ++void rv770_fini(struct radeon_device *rdev); ++int rv770_suspend(struct radeon_device *rdev); ++int rv770_resume(struct radeon_device *rdev); ++int rv770_gpu_reset(struct radeon_device *rdev); ++ ++static struct radeon_asic rv770_asic = { ++ .errata = NULL, ++ .init = &rv770_init, ++ .fini = &rv770_fini, ++ .suspend = &rv770_suspend, ++ .resume = &rv770_resume, ++ .cp_commit = &r600_cp_commit, ++ .vram_info = NULL, ++ .gpu_reset = &rv770_gpu_reset, ++ .mc_init = NULL, ++ .mc_fini = NULL, ++ .wb_init = &r600_wb_init, ++ .wb_fini = &r600_wb_fini, ++ .gart_enable = NULL, ++ .gart_disable = NULL, ++ .gart_tlb_flush = &r600_pcie_gart_tlb_flush, ++ .gart_set_page = &rs600_gart_set_page, ++ .cp_init = NULL, ++ .cp_fini = NULL, ++ .cp_disable = NULL, ++ .ring_start = NULL, ++ .ring_test = &r600_ring_test, ++ .ring_ib_execute = &r600_ring_ib_execute, ++ .ib_test = &r600_ib_test, ++ .irq_set = &r600_irq_set, ++ .irq_process = &r600_irq_process, ++ .fence_ring_emit = &r600_fence_ring_emit, ++ .cs_parse = &r600_cs_parse, ++ .copy_blit = &r600_copy_blit, ++ .copy_dma = &r600_copy_blit, ++ .copy = &r600_copy_blit, ++ .set_engine_clock = &radeon_atom_set_engine_clock, ++ .set_memory_clock = &radeon_atom_set_memory_clock, ++ .set_pcie_lanes = NULL, ++ .set_clock_gating = &radeon_atom_set_clock_gating, ++ .set_surface_reg = r600_set_surface_reg, ++ .clear_surface_reg = r600_clear_surface_reg, ++ .bandwidth_update = &rv515_bandwidth_update, ++}; + + #endif +diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c +index fcfe5c0..5b6c08c 100644 +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -104,7 +104,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, + uint32_t supported_device, + int *connector_type, + struct radeon_i2c_bus_rec *i2c_bus, +- uint8_t *line_mux) ++ uint16_t *line_mux) + { + + /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ +@@ -143,20 +143,31 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, + return false; + } + +- /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */ +- if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) || +- (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) { +- if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { +- return false; +- } +- } +- + /* ASUS HD 3600 XT board lists the DVI port as HDMI */ + if ((dev->pdev->device == 0x9598) && + (dev->pdev->subsystem_vendor == 0x1043) && + (dev->pdev->subsystem_device == 0x01da)) { +- if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) { +- *connector_type = DRM_MODE_CONNECTOR_DVID; ++ if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { ++ *connector_type = DRM_MODE_CONNECTOR_DVII; ++ } ++ } ++ ++ /* ASUS HD 3450 board lists the DVI port as HDMI */ ++ if ((dev->pdev->device == 0x95C5) && ++ (dev->pdev->subsystem_vendor == 0x1043) && ++ (dev->pdev->subsystem_device == 0x01e2)) { ++ if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { ++ *connector_type = DRM_MODE_CONNECTOR_DVII; ++ } ++ } ++ ++ /* some BIOSes seem to report DAC on HDMI - usually this is a board with ++ * HDMI + VGA reporting as HDMI ++ */ ++ if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { ++ if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { ++ *connector_type = DRM_MODE_CONNECTOR_VGA; ++ *line_mux = 0; + } + } + +@@ -192,11 +203,11 @@ const int object_connector_convert[] = { + DRM_MODE_CONNECTOR_Composite, + DRM_MODE_CONNECTOR_SVIDEO, + DRM_MODE_CONNECTOR_Unknown, ++ DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_9PinDIN, + DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_HDMIA, + DRM_MODE_CONNECTOR_HDMIB, +- DRM_MODE_CONNECTOR_HDMIB, + DRM_MODE_CONNECTOR_LVDS, + DRM_MODE_CONNECTOR_9PinDIN, + DRM_MODE_CONNECTOR_Unknown, +@@ -218,7 +229,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) + ATOM_OBJECT_HEADER *obj_header; + int i, j, path_size, device_support; + int connector_type; +- uint16_t igp_lane_info; ++ uint16_t igp_lane_info, conn_id; + bool linkb; + struct radeon_i2c_bus_rec ddc_bus; + +@@ -261,12 +272,9 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) + (le16_to_cpu(path->usConnObjectId) & + OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; + +- if ((le16_to_cpu(path->usDeviceTag) == +- ATOM_DEVICE_TV1_SUPPORT) +- || (le16_to_cpu(path->usDeviceTag) == +- ATOM_DEVICE_TV2_SUPPORT) +- || (le16_to_cpu(path->usDeviceTag) == +- ATOM_DEVICE_CV_SUPPORT)) ++ /* TODO CV support */ ++ if (le16_to_cpu(path->usDeviceTag) == ++ ATOM_DEVICE_CV_SUPPORT) + continue; + + if ((rdev->family == CHIP_RS780) && +@@ -370,10 +378,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) + && record-> + ucRecordType <= + ATOM_MAX_OBJECT_RECORD_NUMBER) { +- DRM_ERROR +- ("record type %d\n", +- record-> +- ucRecordType); + switch (record-> + ucRecordType) { + case ATOM_I2C_RECORD_TYPE: +@@ -409,9 +413,15 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) + else + ddc_bus = radeon_lookup_gpio(dev, line_mux); + ++ conn_id = le16_to_cpu(path->usConnObjectId); ++ ++ if (!radeon_atom_apply_quirks ++ (dev, le16_to_cpu(path->usDeviceTag), &connector_type, ++ &ddc_bus, &conn_id)) ++ continue; ++ + radeon_add_atom_connector(dev, +- le16_to_cpu(path-> +- usConnObjectId), ++ conn_id, + le16_to_cpu(path-> + usDeviceTag), + connector_type, &ddc_bus, +@@ -427,7 +437,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) + + struct bios_connector { + bool valid; +- uint8_t line_mux; ++ uint16_t line_mux; + uint16_t devices; + int connector_type; + struct radeon_i2c_bus_rec ddc_bus; +@@ -471,11 +481,6 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct + continue; + } + +- if (i == ATOM_DEVICE_TV1_INDEX) { +- DRM_DEBUG("Skipping TV Out\n"); +- continue; +- } +- + bios_connectors[i].connector_type = + supported_devices_connector_convert[ci.sucConnectorInfo. + sbfAccess. +@@ -711,9 +716,8 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) + return false; + } + +-struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct +- radeon_encoder +- *encoder) ++bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, ++ struct radeon_encoder_int_tmds *tmds) + { + struct drm_device *dev = encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; +@@ -724,7 +728,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct + uint8_t frev, crev; + uint16_t maxfreq; + int i; +- struct radeon_encoder_int_tmds *tmds = NULL; + + atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, + &crev, &data_offset); +@@ -734,12 +737,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct + data_offset); + + if (tmds_info) { +- tmds = +- kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); +- +- if (!tmds) +- return NULL; +- + maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); + for (i = 0; i < 4; i++) { + tmds->tmds_pll[i].freq = +@@ -765,8 +762,9 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct + break; + } + } ++ return true; + } +- return tmds; ++ return false; + } + + union lvds_info { +@@ -858,6 +856,72 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) + return p_dac; + } + ++bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, ++ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, ++ int32_t *pixel_clock) ++{ ++ struct radeon_mode_info *mode_info = &rdev->mode_info; ++ ATOM_ANALOG_TV_INFO *tv_info; ++ ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; ++ ATOM_DTD_FORMAT *dtd_timings; ++ int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); ++ u8 frev, crev; ++ uint16_t data_offset; ++ ++ atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); ++ ++ switch (crev) { ++ case 1: ++ tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); ++ if (index > MAX_SUPPORTED_TV_TIMING) ++ return false; ++ ++ crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); ++ crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); ++ crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); ++ crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); ++ ++ crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); ++ crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); ++ crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); ++ crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); ++ ++ crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; ++ ++ crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); ++ crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); ++ crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); ++ crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); ++ *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; ++ ++ if (index == 1) { ++ /* PAL timings appear to have wrong values for totals */ ++ crtc_timing->usH_Total -= 1; ++ crtc_timing->usV_Total -= 1; ++ } ++ break; ++ case 2: ++ tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); ++ if (index > MAX_SUPPORTED_TV_TIMING_V1_2) ++ return false; ++ ++ dtd_timings = &tv_info_v1_2->aModeTimings[index]; ++ crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time); ++ crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive); ++ crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset); ++ crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth); ++ crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time); ++ crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive); ++ crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset); ++ crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth); ++ ++ crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); ++ *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10; ++ break; ++ } ++ return true; ++} ++ + struct radeon_encoder_tv_dac * + radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) + { +@@ -948,10 +1012,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) + uint32_t bios_2_scratch, bios_6_scratch; + + if (rdev->family >= CHIP_R600) { +- bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); ++ bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); + bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); + } else { +- bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH); ++ bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); + bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); + } + +@@ -971,6 +1035,34 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) + + } + ++void radeon_save_bios_scratch_regs(struct radeon_device *rdev) ++{ ++ uint32_t scratch_reg; ++ int i; ++ ++ if (rdev->family >= CHIP_R600) ++ scratch_reg = R600_BIOS_0_SCRATCH; ++ else ++ scratch_reg = RADEON_BIOS_0_SCRATCH; ++ ++ for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) ++ rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); ++} ++ ++void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) ++{ ++ uint32_t scratch_reg; ++ int i; ++ ++ if (rdev->family >= CHIP_R600) ++ scratch_reg = R600_BIOS_0_SCRATCH; ++ else ++ scratch_reg = RADEON_BIOS_0_SCRATCH; ++ ++ for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) ++ WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); ++} ++ + void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) + { + struct drm_device *dev = encoder->dev; +diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c +index a37cbce..152eef1 100644 +--- a/drivers/gpu/drm/radeon/radeon_clocks.c ++++ b/drivers/gpu/drm/radeon/radeon_clocks.c +@@ -102,10 +102,12 @@ void radeon_get_clock_info(struct drm_device *dev) + p1pll->reference_div = 12; + if (p2pll->reference_div < 2) + p2pll->reference_div = 12; +- if (spll->reference_div < 2) +- spll->reference_div = +- RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & +- RADEON_M_SPLL_REF_DIV_MASK; ++ if (rdev->family < CHIP_RS600) { ++ if (spll->reference_div < 2) ++ spll->reference_div = ++ RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & ++ RADEON_M_SPLL_REF_DIV_MASK; ++ } + if (mpll->reference_div < 2) + mpll->reference_div = spll->reference_div; + } else { +diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c +index 2a027e0..748265a 100644 +--- a/drivers/gpu/drm/radeon/radeon_combios.c ++++ b/drivers/gpu/drm/radeon/radeon_combios.c +@@ -863,8 +863,10 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder + int tmp, i; + struct radeon_encoder_lvds *lvds = NULL; + +- if (rdev->bios == NULL) +- return radeon_legacy_get_lvds_info_from_regs(rdev); ++ if (rdev->bios == NULL) { ++ lvds = radeon_legacy_get_lvds_info_from_regs(rdev); ++ goto out; ++ } + + lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); + +@@ -965,11 +967,13 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder + lvds->native_mode.flags = 0; + } + } +- encoder->native_mode = lvds->native_mode; + } else { + DRM_INFO("No panel info found in BIOS\n"); +- return radeon_legacy_get_lvds_info_from_regs(rdev); ++ lvds = radeon_legacy_get_lvds_info_from_regs(rdev); + } ++out: ++ if (lvds) ++ encoder->native_mode = lvds->native_mode; + return lvds; + } + +@@ -994,48 +998,37 @@ static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { + {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS480 */ + }; + +-static struct radeon_encoder_int_tmds +- *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev) ++bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, ++ struct radeon_encoder_int_tmds *tmds) + { ++ struct drm_device *dev = encoder->base.dev; ++ struct radeon_device *rdev = dev->dev_private; + int i; +- struct radeon_encoder_int_tmds *tmds = NULL; +- +- tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); +- +- if (!tmds) +- return NULL; + + for (i = 0; i < 4; i++) { + tmds->tmds_pll[i].value = +- default_tmds_pll[rdev->family][i].value; ++ default_tmds_pll[rdev->family][i].value; + tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; + } + +- return tmds; ++ return true; + } + +-struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct +- radeon_encoder +- *encoder) ++bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, ++ struct radeon_encoder_int_tmds *tmds) + { + struct drm_device *dev = encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + uint16_t tmds_info; + int i, n; + uint8_t ver; +- struct radeon_encoder_int_tmds *tmds = NULL; + + if (rdev->bios == NULL) +- return radeon_legacy_get_tmds_info_from_table(rdev); ++ return false; + + tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); + + if (tmds_info) { +- tmds = +- kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); +- +- if (!tmds) +- return NULL; + + ver = RBIOS8(tmds_info); + DRM_INFO("DFP table revision: %d\n", ver); +@@ -1073,6 +1066,23 @@ struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct + } + } else + DRM_INFO("No TMDS info found in BIOS\n"); ++ return true; ++} ++ ++struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct radeon_encoder *encoder) ++{ ++ struct radeon_encoder_int_tmds *tmds = NULL; ++ bool ret; ++ ++ tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); ++ ++ if (!tmds) ++ return NULL; ++ ++ ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); ++ if (ret == false) ++ radeon_legacy_get_tmds_info_from_table(encoder, tmds); ++ + return tmds; + } + +diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c +index 70ede6a..e376be4 100644 +--- a/drivers/gpu/drm/radeon/radeon_connectors.c ++++ b/drivers/gpu/drm/radeon/radeon_connectors.c +@@ -26,8 +26,10 @@ + #include "drmP.h" + #include "drm_edid.h" + #include "drm_crtc_helper.h" ++#include "drm_fb_helper.h" + #include "radeon_drm.h" + #include "radeon.h" ++#include "atom.h" + + extern void + radeon_combios_connected_scratch_regs(struct drm_connector *connector, +@@ -38,6 +40,15 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, + struct drm_encoder *encoder, + bool connected); + ++static void radeon_property_change_mode(struct drm_encoder *encoder) ++{ ++ struct drm_crtc *crtc = encoder->crtc; ++ ++ if (crtc && crtc->enabled) { ++ drm_crtc_helper_set_mode(crtc, &crtc->mode, ++ crtc->x, crtc->y, crtc->fb); ++ } ++} + static void + radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status) + { +@@ -77,6 +88,27 @@ radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_c + } + } + ++struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type) ++{ ++ struct drm_mode_object *obj; ++ struct drm_encoder *encoder; ++ int i; ++ ++ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { ++ if (connector->encoder_ids[i] == 0) ++ break; ++ ++ obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER); ++ if (!obj) ++ continue; ++ ++ encoder = obj_to_encoder(obj); ++ if (encoder->encoder_type == encoder_type) ++ return encoder; ++ } ++ return NULL; ++} ++ + struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector) + { + int enc_id = connector->encoder_ids[0]; +@@ -94,6 +126,53 @@ struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector) + return NULL; + } + ++/* ++ * radeon_connector_analog_encoder_conflict_solve ++ * - search for other connectors sharing this encoder ++ * if priority is true, then set them disconnected if this is connected ++ * if priority is false, set us disconnected if they are connected ++ */ ++static enum drm_connector_status ++radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector, ++ struct drm_encoder *encoder, ++ enum drm_connector_status current_status, ++ bool priority) ++{ ++ struct drm_device *dev = connector->dev; ++ struct drm_connector *conflict; ++ int i; ++ ++ list_for_each_entry(conflict, &dev->mode_config.connector_list, head) { ++ if (conflict == connector) ++ continue; ++ ++ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { ++ if (conflict->encoder_ids[i] == 0) ++ break; ++ ++ /* if the IDs match */ ++ if (conflict->encoder_ids[i] == encoder->base.id) { ++ if (conflict->status != connector_status_connected) ++ continue; ++ ++ if (priority == true) { ++ DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict)); ++ DRM_INFO("in favor of %s\n", drm_get_connector_name(connector)); ++ conflict->status = connector_status_disconnected; ++ radeon_connector_update_scratch_regs(conflict, connector_status_disconnected); ++ } else { ++ DRM_INFO("2: conflicting encoders switching off %s\n", drm_get_connector_name(connector)); ++ DRM_INFO("in favor of %s\n", drm_get_connector_name(conflict)); ++ current_status = connector_status_disconnected; ++ } ++ break; ++ } ++ } ++ } ++ return current_status; ++ ++} ++ + static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder) + { + struct drm_device *dev = encoder->dev; +@@ -126,12 +205,171 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode + return mode; + } + ++static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector) ++{ ++ struct drm_device *dev = encoder->dev; ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct drm_display_mode *mode = NULL; ++ struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; ++ int i; ++ struct mode_size { ++ int w; ++ int h; ++ } common_modes[17] = { ++ { 640, 480}, ++ { 720, 480}, ++ { 800, 600}, ++ { 848, 480}, ++ {1024, 768}, ++ {1152, 768}, ++ {1280, 720}, ++ {1280, 800}, ++ {1280, 854}, ++ {1280, 960}, ++ {1280, 1024}, ++ {1440, 900}, ++ {1400, 1050}, ++ {1680, 1050}, ++ {1600, 1200}, ++ {1920, 1080}, ++ {1920, 1200} ++ }; ++ ++ for (i = 0; i < 17; i++) { ++ if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { ++ if (common_modes[i].w > native_mode->panel_xres || ++ common_modes[i].h > native_mode->panel_yres || ++ (common_modes[i].w == native_mode->panel_xres && ++ common_modes[i].h == native_mode->panel_yres)) ++ continue; ++ } ++ if (common_modes[i].w < 320 || common_modes[i].h < 200) ++ continue; ++ ++ mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); ++ drm_mode_probed_add(connector, mode); ++ } ++} ++ + int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property, + uint64_t val) + { ++ struct drm_device *dev = connector->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct drm_encoder *encoder; ++ struct radeon_encoder *radeon_encoder; ++ ++ if (property == rdev->mode_info.coherent_mode_property) { ++ struct radeon_encoder_atom_dig *dig; ++ ++ /* need to find digital encoder on connector */ ++ encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); ++ if (!encoder) ++ return 0; ++ ++ radeon_encoder = to_radeon_encoder(encoder); ++ ++ if (!radeon_encoder->enc_priv) ++ return 0; ++ ++ dig = radeon_encoder->enc_priv; ++ dig->coherent_mode = val ? true : false; ++ radeon_property_change_mode(&radeon_encoder->base); ++ } ++ ++ if (property == rdev->mode_info.tv_std_property) { ++ encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC); ++ if (!encoder) { ++ encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC); ++ } ++ ++ if (!encoder) ++ return 0; ++ ++ radeon_encoder = to_radeon_encoder(encoder); ++ if (!radeon_encoder->enc_priv) ++ return 0; ++ if (rdev->is_atom_bios) { ++ struct radeon_encoder_atom_dac *dac_int; ++ dac_int = radeon_encoder->enc_priv; ++ dac_int->tv_std = val; ++ } else { ++ struct radeon_encoder_tv_dac *dac_int; ++ dac_int = radeon_encoder->enc_priv; ++ dac_int->tv_std = val; ++ } ++ radeon_property_change_mode(&radeon_encoder->base); ++ } ++ ++ if (property == rdev->mode_info.load_detect_property) { ++ struct radeon_connector *radeon_connector = ++ to_radeon_connector(connector); ++ ++ if (val == 0) ++ radeon_connector->dac_load_detect = false; ++ else ++ radeon_connector->dac_load_detect = true; ++ } ++ ++ if (property == rdev->mode_info.tmds_pll_property) { ++ struct radeon_encoder_int_tmds *tmds = NULL; ++ bool ret = false; ++ /* need to find digital encoder on connector */ ++ encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); ++ if (!encoder) ++ return 0; ++ ++ radeon_encoder = to_radeon_encoder(encoder); ++ ++ tmds = radeon_encoder->enc_priv; ++ if (!tmds) ++ return 0; ++ ++ if (val == 0) { ++ if (rdev->is_atom_bios) ++ ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds); ++ else ++ ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds); ++ } ++ if (val == 1 || ret == false) { ++ radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds); ++ } ++ radeon_property_change_mode(&radeon_encoder->base); ++ } ++ + return 0; + } + ++static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; ++ ++ /* Try to get native mode details from EDID if necessary */ ++ if (!native_mode->dotclock) { ++ struct drm_display_mode *t, *mode; ++ ++ list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { ++ if (mode->hdisplay == native_mode->panel_xres && ++ mode->vdisplay == native_mode->panel_yres) { ++ native_mode->hblank = mode->htotal - mode->hdisplay; ++ native_mode->hoverplus = mode->hsync_start - mode->hdisplay; ++ native_mode->hsync_width = mode->hsync_end - mode->hsync_start; ++ native_mode->vblank = mode->vtotal - mode->vdisplay; ++ native_mode->voverplus = mode->vsync_start - mode->vdisplay; ++ native_mode->vsync_width = mode->vsync_end - mode->vsync_start; ++ native_mode->dotclock = mode->clock; ++ DRM_INFO("Determined LVDS native mode details from EDID\n"); ++ break; ++ } ++ } ++ } ++ if (!native_mode->dotclock) { ++ DRM_INFO("No LVDS native mode details, disabling RMX\n"); ++ radeon_encoder->rmx_type = RMX_OFF; ++ } ++} + + static int radeon_lvds_get_modes(struct drm_connector *connector) + { +@@ -143,6 +381,12 @@ static int radeon_lvds_get_modes(struct drm_connector *connector) + if (radeon_connector->ddc_bus) { + ret = radeon_ddc_get_modes(radeon_connector); + if (ret > 0) { ++ encoder = radeon_best_single_encoder(connector); ++ if (encoder) { ++ radeon_fixup_lvds_native_mode(encoder, connector); ++ /* add scaled modes */ ++ radeon_add_common_modes(encoder, connector); ++ } + return ret; + } + } +@@ -156,7 +400,10 @@ static int radeon_lvds_get_modes(struct drm_connector *connector) + if (mode) { + ret = 1; + drm_mode_probed_add(connector, mode); ++ /* add scaled modes */ ++ radeon_add_common_modes(encoder, connector); + } ++ + return ret; + } + +@@ -186,6 +433,42 @@ static void radeon_connector_destroy(struct drm_connector *connector) + kfree(connector); + } + ++static int radeon_lvds_set_property(struct drm_connector *connector, ++ struct drm_property *property, ++ uint64_t value) ++{ ++ struct drm_device *dev = connector->dev; ++ struct radeon_encoder *radeon_encoder; ++ enum radeon_rmx_type rmx_type; ++ ++ DRM_DEBUG("\n"); ++ if (property != dev->mode_config.scaling_mode_property) ++ return 0; ++ ++ if (connector->encoder) ++ radeon_encoder = to_radeon_encoder(connector->encoder); ++ else { ++ struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; ++ radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector)); ++ } ++ ++ switch (value) { ++ case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; ++ case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; ++ case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; ++ default: ++ case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; ++ } ++ if (radeon_encoder->rmx_type == rmx_type) ++ return 0; ++ ++ radeon_encoder->rmx_type = rmx_type; ++ ++ radeon_property_change_mode(&radeon_encoder->base); ++ return 0; ++} ++ ++ + struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = { + .get_modes = radeon_lvds_get_modes, + .mode_valid = radeon_lvds_mode_valid, +@@ -197,7 +480,7 @@ struct drm_connector_funcs radeon_lvds_connector_funcs = { + .detect = radeon_lvds_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = radeon_connector_destroy, +- .set_property = radeon_connector_set_property, ++ .set_property = radeon_lvds_set_property, + }; + + static int radeon_vga_get_modes(struct drm_connector *connector) +@@ -213,7 +496,6 @@ static int radeon_vga_get_modes(struct drm_connector *connector) + static int radeon_vga_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) + { +- + return MODE_OK; + } + +@@ -225,22 +507,24 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect + bool dret; + enum drm_connector_status ret = connector_status_disconnected; + ++ encoder = radeon_best_single_encoder(connector); ++ if (!encoder) ++ ret = connector_status_disconnected; ++ + radeon_i2c_do_lock(radeon_connector, 1); + dret = radeon_ddc_probe(radeon_connector); + radeon_i2c_do_lock(radeon_connector, 0); + if (dret) + ret = connector_status_connected; + else { +- /* if EDID fails to a load detect */ +- encoder = radeon_best_single_encoder(connector); +- if (!encoder) +- ret = connector_status_disconnected; +- else { ++ if (radeon_connector->dac_load_detect) { + encoder_funcs = encoder->helper_private; + ret = encoder_funcs->detect(encoder, connector); + } + } + ++ if (ret == connector_status_connected) ++ ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); + radeon_connector_update_scratch_regs(connector, ret); + return ret; + } +@@ -259,21 +543,97 @@ struct drm_connector_funcs radeon_vga_connector_funcs = { + .set_property = radeon_connector_set_property, + }; + ++static int radeon_tv_get_modes(struct drm_connector *connector) ++{ ++ struct drm_device *dev = connector->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct drm_display_mode *tv_mode; ++ struct drm_encoder *encoder; ++ ++ encoder = radeon_best_single_encoder(connector); ++ if (!encoder) ++ return 0; ++ ++ /* avivo chips can scale any mode */ ++ if (rdev->family >= CHIP_RS600) ++ /* add scaled modes */ ++ radeon_add_common_modes(encoder, connector); ++ else { ++ /* only 800x600 is supported right now on pre-avivo chips */ ++ tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false); ++ tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; ++ drm_mode_probed_add(connector, tv_mode); ++ } ++ return 1; ++} ++ ++static int radeon_tv_mode_valid(struct drm_connector *connector, ++ struct drm_display_mode *mode) ++{ ++ return MODE_OK; ++} ++ ++static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector) ++{ ++ struct drm_encoder *encoder; ++ struct drm_encoder_helper_funcs *encoder_funcs; ++ struct radeon_connector *radeon_connector = to_radeon_connector(connector); ++ enum drm_connector_status ret = connector_status_disconnected; ++ ++ if (!radeon_connector->dac_load_detect) ++ return ret; ++ ++ encoder = radeon_best_single_encoder(connector); ++ if (!encoder) ++ ret = connector_status_disconnected; ++ else { ++ encoder_funcs = encoder->helper_private; ++ ret = encoder_funcs->detect(encoder, connector); ++ } ++ if (ret == connector_status_connected) ++ ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false); ++ radeon_connector_update_scratch_regs(connector, ret); ++ return ret; ++} ++ ++struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = { ++ .get_modes = radeon_tv_get_modes, ++ .mode_valid = radeon_tv_mode_valid, ++ .best_encoder = radeon_best_single_encoder, ++}; ++ ++struct drm_connector_funcs radeon_tv_connector_funcs = { ++ .dpms = drm_helper_connector_dpms, ++ .detect = radeon_tv_detect, ++ .fill_modes = drm_helper_probe_single_connector_modes, ++ .destroy = radeon_connector_destroy, ++ .set_property = radeon_connector_set_property, ++}; ++ + static int radeon_dvi_get_modes(struct drm_connector *connector) + { + struct radeon_connector *radeon_connector = to_radeon_connector(connector); + int ret; + + ret = radeon_ddc_get_modes(radeon_connector); +- /* reset scratch regs here since radeon_dvi_detect doesn't check digital bit */ +- radeon_connector_update_scratch_regs(connector, connector_status_connected); + return ret; + } + ++/* ++ * DVI is complicated ++ * Do a DDC probe, if DDC probe passes, get the full EDID so ++ * we can do analog/digital monitor detection at this point. ++ * If the monitor is an analog monitor or we got no DDC, ++ * we need to find the DAC encoder object for this connector. ++ * If we got no DDC, we do load detection on the DAC encoder object. ++ * If we got analog DDC or load detection passes on the DAC encoder ++ * we have to check if this analog encoder is shared with anyone else (TV) ++ * if its shared we have to set the other connector to disconnected. ++ */ + static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector) + { + struct radeon_connector *radeon_connector = to_radeon_connector(connector); +- struct drm_encoder *encoder; ++ struct drm_encoder *encoder = NULL; + struct drm_encoder_helper_funcs *encoder_funcs; + struct drm_mode_object *obj; + int i; +@@ -283,9 +643,29 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect + radeon_i2c_do_lock(radeon_connector, 1); + dret = radeon_ddc_probe(radeon_connector); + radeon_i2c_do_lock(radeon_connector, 0); +- if (dret) +- ret = connector_status_connected; +- else { ++ if (dret) { ++ radeon_i2c_do_lock(radeon_connector, 1); ++ radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); ++ radeon_i2c_do_lock(radeon_connector, 0); ++ ++ if (!radeon_connector->edid) { ++ DRM_ERROR("DDC responded but not EDID found for %s\n", ++ drm_get_connector_name(connector)); ++ } else { ++ radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); ++ ++ /* if this isn't a digital monitor ++ then we need to make sure we don't have any ++ TV conflicts */ ++ ret = connector_status_connected; ++ } ++ } ++ ++ if ((ret == connector_status_connected) && (radeon_connector->use_digital == true)) ++ goto out; ++ ++ /* find analog encoder */ ++ if (radeon_connector->dac_load_detect) { + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; +@@ -300,15 +680,23 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect + + encoder_funcs = encoder->helper_private; + if (encoder_funcs->detect) { +- ret = encoder_funcs->detect(encoder, connector); +- if (ret == connector_status_connected) { +- radeon_connector->use_digital = 0; +- break; ++ if (ret != connector_status_connected) { ++ ret = encoder_funcs->detect(encoder, connector); ++ if (ret == connector_status_connected) { ++ radeon_connector->use_digital = false; ++ } + } ++ break; + } + } + } + ++ if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) && ++ encoder) { ++ ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); ++ } ++ ++out: + /* updated in get modes as well since we need to know if it's analog or digital */ + radeon_connector_update_scratch_regs(connector, ret); + return ret; +@@ -332,7 +720,7 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector) + + encoder = obj_to_encoder(obj); + +- if (radeon_connector->use_digital) { ++ if (radeon_connector->use_digital == true) { + if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) + return encoder; + } else { +@@ -356,6 +744,15 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector) + return NULL; + } + ++static void radeon_dvi_force(struct drm_connector *connector) ++{ ++ struct radeon_connector *radeon_connector = to_radeon_connector(connector); ++ if (connector->force == DRM_FORCE_ON) ++ radeon_connector->use_digital = false; ++ if (connector->force == DRM_FORCE_ON_DIGITAL) ++ radeon_connector->use_digital = true; ++} ++ + struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = { + .get_modes = radeon_dvi_get_modes, + .mode_valid = radeon_vga_mode_valid, +@@ -368,6 +765,7 @@ struct drm_connector_funcs radeon_dvi_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = radeon_connector_set_property, + .destroy = radeon_connector_destroy, ++ .force = radeon_dvi_force, + }; + + void +@@ -379,16 +777,15 @@ radeon_add_atom_connector(struct drm_device *dev, + bool linkb, + uint32_t igp_lane_info) + { ++ struct radeon_device *rdev = dev->dev_private; + struct drm_connector *connector; + struct radeon_connector *radeon_connector; + struct radeon_connector_atom_dig *radeon_dig_connector; + uint32_t subpixel_order = SubPixelNone; ++ int ret; + + /* fixme - tv/cv/din */ +- if ((connector_type == DRM_MODE_CONNECTOR_Unknown) || +- (connector_type == DRM_MODE_CONNECTOR_SVIDEO) || +- (connector_type == DRM_MODE_CONNECTOR_Composite) || +- (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) ++ if (connector_type == DRM_MODE_CONNECTOR_Unknown) + return; + + /* see if we already added it */ +@@ -411,21 +808,33 @@ radeon_add_atom_connector(struct drm_device *dev, + switch (connector_type) { + case DRM_MODE_CONNECTOR_VGA: + drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); + if (!radeon_connector->ddc_bus) + goto failed; + } ++ radeon_connector->dac_load_detect = true; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.load_detect_property, ++ 1); + break; + case DRM_MODE_CONNECTOR_DVIA: + drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); + if (!radeon_connector->ddc_bus) + goto failed; + } ++ radeon_connector->dac_load_detect = true; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.load_detect_property, ++ 1); + break; + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_DVID: +@@ -436,13 +845,22 @@ radeon_add_atom_connector(struct drm_device *dev, + radeon_dig_connector->igp_lane_info = igp_lane_info; + radeon_connector->con_priv = radeon_dig_connector; + drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); + if (!radeon_connector->ddc_bus) + goto failed; + } + subpixel_order = SubPixelHorizontalRGB; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.coherent_mode_property, ++ 1); ++ radeon_connector->dac_load_detect = true; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.load_detect_property, ++ 1); + break; + case DRM_MODE_CONNECTOR_HDMIA: + case DRM_MODE_CONNECTOR_HDMIB: +@@ -453,12 +871,17 @@ radeon_add_atom_connector(struct drm_device *dev, + radeon_dig_connector->igp_lane_info = igp_lane_info; + radeon_connector->con_priv = radeon_dig_connector; + drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "HDMI"); + if (!radeon_connector->ddc_bus) + goto failed; + } ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.coherent_mode_property, ++ 1); + subpixel_order = SubPixelHorizontalRGB; + break; + case DRM_MODE_CONNECTOR_DisplayPort: +@@ -469,7 +892,9 @@ radeon_add_atom_connector(struct drm_device *dev, + radeon_dig_connector->igp_lane_info = igp_lane_info; + radeon_connector->con_priv = radeon_dig_connector; + drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP"); + if (!radeon_connector->ddc_bus) +@@ -480,6 +905,16 @@ radeon_add_atom_connector(struct drm_device *dev, + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_9PinDIN: ++ if (radeon_tv == 1) { ++ drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); ++ if (ret) ++ goto failed; ++ radeon_connector->dac_load_detect = true; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.load_detect_property, ++ 1); ++ } + break; + case DRM_MODE_CONNECTOR_LVDS: + radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); +@@ -489,12 +924,18 @@ radeon_add_atom_connector(struct drm_device *dev, + radeon_dig_connector->igp_lane_info = igp_lane_info; + radeon_connector->con_priv = radeon_dig_connector; + drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); + if (!radeon_connector->ddc_bus) + goto failed; + } ++ drm_mode_create_scaling_mode_property(dev); ++ drm_connector_attach_property(&radeon_connector->base, ++ dev->mode_config.scaling_mode_property, ++ DRM_MODE_SCALE_FULLSCREEN); + subpixel_order = SubPixelHorizontalRGB; + break; + } +@@ -517,15 +958,14 @@ radeon_add_legacy_connector(struct drm_device *dev, + int connector_type, + struct radeon_i2c_bus_rec *i2c_bus) + { ++ struct radeon_device *rdev = dev->dev_private; + struct drm_connector *connector; + struct radeon_connector *radeon_connector; + uint32_t subpixel_order = SubPixelNone; ++ int ret; + + /* fixme - tv/cv/din */ +- if ((connector_type == DRM_MODE_CONNECTOR_Unknown) || +- (connector_type == DRM_MODE_CONNECTOR_SVIDEO) || +- (connector_type == DRM_MODE_CONNECTOR_Composite) || +- (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) ++ if (connector_type == DRM_MODE_CONNECTOR_Unknown) + return; + + /* see if we already added it */ +@@ -548,45 +988,78 @@ radeon_add_legacy_connector(struct drm_device *dev, + switch (connector_type) { + case DRM_MODE_CONNECTOR_VGA: + drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); + if (!radeon_connector->ddc_bus) + goto failed; + } ++ radeon_connector->dac_load_detect = true; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.load_detect_property, ++ 1); + break; + case DRM_MODE_CONNECTOR_DVIA: + drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); + if (!radeon_connector->ddc_bus) + goto failed; + } ++ radeon_connector->dac_load_detect = true; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.load_detect_property, ++ 1); + break; + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_DVID: + drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); + if (!radeon_connector->ddc_bus) + goto failed; ++ radeon_connector->dac_load_detect = true; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.load_detect_property, ++ 1); + } + subpixel_order = SubPixelHorizontalRGB; + break; + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_9PinDIN: ++ if (radeon_tv == 1) { ++ drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); ++ if (ret) ++ goto failed; ++ radeon_connector->dac_load_detect = true; ++ drm_connector_attach_property(&radeon_connector->base, ++ rdev->mode_info.load_detect_property, ++ 1); ++ } + break; + case DRM_MODE_CONNECTOR_LVDS: + drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); +- drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); ++ ret = drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); ++ if (ret) ++ goto failed; + if (i2c_bus->valid) { + radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); + if (!radeon_connector->ddc_bus) + goto failed; + } ++ drm_connector_attach_property(&radeon_connector->base, ++ dev->mode_config.scaling_mode_property, ++ DRM_MODE_SCALE_FULLSCREEN); + subpixel_order = SubPixelHorizontalRGB; + break; + } +diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c +index 7a52c46..4f7afc7 100644 +--- a/drivers/gpu/drm/radeon/radeon_cp.c ++++ b/drivers/gpu/drm/radeon/radeon_cp.c +@@ -36,10 +36,25 @@ + #include "radeon_drv.h" + #include "r300_reg.h" + +-#include "radeon_microcode.h" +- + #define RADEON_FIFO_DEBUG 0 + ++/* Firmware Names */ ++#define FIRMWARE_R100 "radeon/R100_cp.bin" ++#define FIRMWARE_R200 "radeon/R200_cp.bin" ++#define FIRMWARE_R300 "radeon/R300_cp.bin" ++#define FIRMWARE_R420 "radeon/R420_cp.bin" ++#define FIRMWARE_RS690 "radeon/RS690_cp.bin" ++#define FIRMWARE_RS600 "radeon/RS600_cp.bin" ++#define FIRMWARE_R520 "radeon/R520_cp.bin" ++ ++MODULE_FIRMWARE(FIRMWARE_R100); ++MODULE_FIRMWARE(FIRMWARE_R200); ++MODULE_FIRMWARE(FIRMWARE_R300); ++MODULE_FIRMWARE(FIRMWARE_R420); ++MODULE_FIRMWARE(FIRMWARE_RS690); ++MODULE_FIRMWARE(FIRMWARE_RS600); ++MODULE_FIRMWARE(FIRMWARE_R520); ++ + static int radeon_do_cleanup_cp(struct drm_device * dev); + static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); + +@@ -460,37 +475,34 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv) + */ + + /* Load the microcode for the CP */ +-static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ++static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv) + { +- int i; ++ struct platform_device *pdev; ++ const char *fw_name = NULL; ++ int err; ++ + DRM_DEBUG("\n"); + +- radeon_do_wait_for_idle(dev_priv); ++ pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); ++ err = IS_ERR(pdev); ++ if (err) { ++ printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); ++ return -EINVAL; ++ } + +- RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { + DRM_INFO("Loading R100 Microcode\n"); +- for (i = 0; i < 256; i++) { +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, +- R100_cp_microcode[i][1]); +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, +- R100_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_R100; + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { + DRM_INFO("Loading R200 Microcode\n"); +- for (i = 0; i < 256; i++) { +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, +- R200_cp_microcode[i][1]); +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, +- R200_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_R200; + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || +@@ -498,39 +510,19 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { + DRM_INFO("Loading R300 Microcode\n"); +- for (i = 0; i < 256; i++) { +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, +- R300_cp_microcode[i][1]); +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, +- R300_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_R300; + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { + DRM_INFO("Loading R400 Microcode\n"); +- for (i = 0; i < 256; i++) { +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, +- R420_cp_microcode[i][1]); +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, +- R420_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_R420; + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { + DRM_INFO("Loading RS690/RS740 Microcode\n"); +- for (i = 0; i < 256; i++) { +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, +- RS690_cp_microcode[i][1]); +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, +- RS690_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_RS690; + } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { + DRM_INFO("Loading RS600 Microcode\n"); +- for (i = 0; i < 256; i++) { +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, +- RS600_cp_microcode[i][1]); +- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, +- RS600_cp_microcode[i][0]); +- } ++ fw_name = FIRMWARE_RS600; + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || +@@ -538,11 +530,41 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { + DRM_INFO("Loading R500 Microcode\n"); +- for (i = 0; i < 256; i++) { ++ fw_name = FIRMWARE_R520; ++ } ++ ++ err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); ++ platform_device_unregister(pdev); ++ if (err) { ++ printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", ++ fw_name); ++ } else if (dev_priv->me_fw->size % 8) { ++ printk(KERN_ERR ++ "radeon_cp: Bogus length %zu in firmware \"%s\"\n", ++ dev_priv->me_fw->size, fw_name); ++ err = -EINVAL; ++ release_firmware(dev_priv->me_fw); ++ dev_priv->me_fw = NULL; ++ } ++ return err; ++} ++ ++static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv) ++{ ++ const __be32 *fw_data; ++ int i, size; ++ ++ radeon_do_wait_for_idle(dev_priv); ++ ++ if (dev_priv->me_fw) { ++ size = dev_priv->me_fw->size / 4; ++ fw_data = (const __be32 *)&dev_priv->me_fw->data[0]; ++ RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); ++ for (i = 0; i < size; i += 2) { + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, +- R520_cp_microcode[i][1]); ++ be32_to_cpup(&fw_data[i])); + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, +- R520_cp_microcode[i][0]); ++ be32_to_cpup(&fw_data[i + 1])); + } + } + } +@@ -594,6 +616,18 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) + + dev_priv->cp_running = 1; + ++ /* on r420, any DMA from CP to system memory while 2D is active ++ * can cause a hang. workaround is to queue a CP RESYNC token ++ */ ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) { ++ BEGIN_RING(3); ++ OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1)); ++ OUT_RING(5); /* scratch reg 5 */ ++ OUT_RING(0xdeadbeef); ++ ADVANCE_RING(); ++ COMMIT_RING(); ++ } ++ + BEGIN_RING(8); + /* isync can only be written through cp on r5xx write it here */ + OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); +@@ -631,8 +665,19 @@ static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) + */ + static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) + { ++ RING_LOCALS; + DRM_DEBUG("\n"); + ++ /* finish the pending CP_RESYNC token */ ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) { ++ BEGIN_RING(2); ++ OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); ++ OUT_RING(R300_RB3D_DC_FINISH); ++ ADVANCE_RING(); ++ COMMIT_RING(); ++ radeon_do_wait_for_idle(dev_priv); ++ } ++ + RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); + + dev_priv->cp_running = 0; +@@ -1495,6 +1540,14 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, + radeon_set_pcigart(dev_priv, 1); + } + ++ if (!dev_priv->me_fw) { ++ int err = radeon_cp_init_microcode(dev_priv); ++ if (err) { ++ DRM_ERROR("Failed to load firmware!\n"); ++ radeon_do_cleanup_cp(dev); ++ return err; ++ } ++ } + radeon_cp_load_microcode(dev_priv); + radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); + +@@ -1764,6 +1817,14 @@ void radeon_do_release(struct drm_device * dev) + r600_do_cleanup_cp(dev); + else + radeon_do_cleanup_cp(dev); ++ if (dev_priv->me_fw) { ++ release_firmware(dev_priv->me_fw); ++ dev_priv->me_fw = NULL; ++ } ++ if (dev_priv->pfp_fw) { ++ release_firmware(dev_priv->pfp_fw); ++ dev_priv->pfp_fw = NULL; ++ } + } + } + +diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c +index a169067..5ab2cf9 100644 +--- a/drivers/gpu/drm/radeon/radeon_cs.c ++++ b/drivers/gpu/drm/radeon/radeon_cs.c +@@ -142,15 +142,31 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) + } + + p->chunks[i].length_dw = user_chunk.length_dw; +- cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; ++ p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; + +- size = p->chunks[i].length_dw * sizeof(uint32_t); +- p->chunks[i].kdata = kzalloc(size, GFP_KERNEL); +- if (p->chunks[i].kdata == NULL) { +- return -ENOMEM; +- } +- if (DRM_COPY_FROM_USER(p->chunks[i].kdata, cdata, size)) { +- return -EFAULT; ++ cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; ++ if (p->chunks[i].chunk_id != RADEON_CHUNK_ID_IB) { ++ size = p->chunks[i].length_dw * sizeof(uint32_t); ++ p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); ++ if (p->chunks[i].kdata == NULL) { ++ return -ENOMEM; ++ } ++ if (DRM_COPY_FROM_USER(p->chunks[i].kdata, ++ p->chunks[i].user_ptr, size)) { ++ return -EFAULT; ++ } ++ } else { ++ p->chunks[i].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); ++ p->chunks[i].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); ++ if (p->chunks[i].kpage[0] == NULL || p->chunks[i].kpage[1] == NULL) { ++ kfree(p->chunks[i].kpage[0]); ++ kfree(p->chunks[i].kpage[1]); ++ return -ENOMEM; ++ } ++ p->chunks[i].kpage_idx[0] = -1; ++ p->chunks[i].kpage_idx[1] = -1; ++ p->chunks[i].last_copied_page = -1; ++ p->chunks[i].last_page_index = ((p->chunks[i].length_dw * 4) - 1) / PAGE_SIZE; + } + } + if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { +@@ -185,10 +201,13 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) + mutex_unlock(&parser->rdev->ddev->struct_mutex); + } + } ++ kfree(parser->track); + kfree(parser->relocs); + kfree(parser->relocs_ptr); + for (i = 0; i < parser->nchunks; i++) { + kfree(parser->chunks[i].kdata); ++ kfree(parser->chunks[i].kpage[0]); ++ kfree(parser->chunks[i].kpage[1]); + } + kfree(parser->chunks); + kfree(parser->chunks_array); +@@ -237,8 +256,14 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + * uncached). */ + ib_chunk = &parser.chunks[parser.chunk_ib_idx]; + parser.ib->length_dw = ib_chunk->length_dw; +- memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4); + r = radeon_cs_parse(&parser); ++ if (r || parser.parser_error) { ++ DRM_ERROR("Invalid command stream !\n"); ++ radeon_cs_parser_fini(&parser, r); ++ mutex_unlock(&rdev->cs_mutex); ++ return r; ++ } ++ r = radeon_cs_finish_pages(&parser); + if (r) { + DRM_ERROR("Invalid command stream !\n"); + radeon_cs_parser_fini(&parser, r); +@@ -253,3 +278,64 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + mutex_unlock(&rdev->cs_mutex); + return r; + } ++ ++int radeon_cs_finish_pages(struct radeon_cs_parser *p) ++{ ++ struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; ++ int i; ++ int size = PAGE_SIZE; ++ ++ for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { ++ if (i == ibc->last_page_index) { ++ size = (ibc->length_dw * 4) % PAGE_SIZE; ++ if (size == 0) ++ size = PAGE_SIZE; ++ } ++ ++ if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)), ++ ibc->user_ptr + (i * PAGE_SIZE), ++ size)) ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) ++{ ++ int new_page; ++ struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; ++ int i; ++ int size = PAGE_SIZE; ++ ++ for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { ++ if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)), ++ ibc->user_ptr + (i * PAGE_SIZE), ++ PAGE_SIZE)) { ++ p->parser_error = -EFAULT; ++ return 0; ++ } ++ } ++ ++ new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; ++ ++ if (pg_idx == ibc->last_page_index) { ++ size = (ibc->length_dw * 4) % PAGE_SIZE; ++ if (size == 0) ++ size = PAGE_SIZE; ++ } ++ ++ if (DRM_COPY_FROM_USER(ibc->kpage[new_page], ++ ibc->user_ptr + (pg_idx * PAGE_SIZE), ++ size)) { ++ p->parser_error = -EFAULT; ++ return 0; ++ } ++ ++ /* copy to IB here */ ++ memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); ++ ++ ibc->last_copied_page = pg_idx; ++ ibc->kpage_idx[new_page] = pg_idx; ++ ++ return new_page; ++} +diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c +index 7693f7c..a6733cf 100644 +--- a/drivers/gpu/drm/radeon/radeon_device.c ++++ b/drivers/gpu/drm/radeon/radeon_device.c +@@ -37,7 +37,7 @@ + /* + * Clear GPU surface registers. + */ +-static void radeon_surface_init(struct radeon_device *rdev) ++void radeon_surface_init(struct radeon_device *rdev) + { + /* FIXME: check this out */ + if (rdev->family < CHIP_R600) { +@@ -56,7 +56,7 @@ static void radeon_surface_init(struct radeon_device *rdev) + /* + * GPU scratch registers helpers function. + */ +-static void radeon_scratch_init(struct radeon_device *rdev) ++void radeon_scratch_init(struct radeon_device *rdev) + { + int i; + +@@ -156,16 +156,18 @@ int radeon_mc_setup(struct radeon_device *rdev) + tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); + rdev->mc.gtt_location = tmp; + } +- DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20); ++ rdev->mc.vram_start = rdev->mc.vram_location; ++ rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; ++ rdev->mc.gtt_start = rdev->mc.gtt_location; ++ rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; ++ DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); + DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", +- rdev->mc.vram_location, +- rdev->mc.vram_location + rdev->mc.mc_vram_size - 1); +- if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size) +- DRM_INFO("radeon: VRAM less than aperture workaround enabled\n"); +- DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); ++ (unsigned)rdev->mc.vram_location, ++ (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); ++ DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); + DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", +- rdev->mc.gtt_location, +- rdev->mc.gtt_location + rdev->mc.gtt_size - 1); ++ (unsigned)rdev->mc.gtt_location, ++ (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); + return 0; + } + +@@ -173,7 +175,7 @@ int radeon_mc_setup(struct radeon_device *rdev) + /* + * GPU helpers function. + */ +-static bool radeon_card_posted(struct radeon_device *rdev) ++bool radeon_card_posted(struct radeon_device *rdev) + { + uint32_t reg; + +@@ -205,6 +207,31 @@ static bool radeon_card_posted(struct radeon_device *rdev) + + } + ++int radeon_dummy_page_init(struct radeon_device *rdev) ++{ ++ rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); ++ if (rdev->dummy_page.page == NULL) ++ return -ENOMEM; ++ rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, ++ 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); ++ if (!rdev->dummy_page.addr) { ++ __free_page(rdev->dummy_page.page); ++ rdev->dummy_page.page = NULL; ++ return -ENOMEM; ++ } ++ return 0; ++} ++ ++void radeon_dummy_page_fini(struct radeon_device *rdev) ++{ ++ if (rdev->dummy_page.page == NULL) ++ return; ++ pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, ++ PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); ++ __free_page(rdev->dummy_page.page); ++ rdev->dummy_page.page = NULL; ++} ++ + + /* + * Registers accessors functions. +@@ -243,6 +270,10 @@ void radeon_register_accessor_init(struct radeon_device *rdev) + rdev->pll_rreg = &r100_pll_rreg; + rdev->pll_wreg = &r100_pll_wreg; + } ++ if (rdev->family >= CHIP_R420) { ++ rdev->mc_rreg = &r420_mc_rreg; ++ rdev->mc_wreg = &r420_mc_wreg; ++ } + if (rdev->family >= CHIP_RV515) { + rdev->mc_rreg = &rv515_mc_rreg; + rdev->mc_wreg = &rv515_mc_wreg; +@@ -289,6 +320,14 @@ int radeon_asic_init(struct radeon_device *rdev) + case CHIP_RV350: + case CHIP_RV380: + rdev->asic = &r300_asic; ++ if (rdev->flags & RADEON_IS_PCIE) { ++ rdev->asic->gart_init = &rv370_pcie_gart_init; ++ rdev->asic->gart_fini = &rv370_pcie_gart_fini; ++ rdev->asic->gart_enable = &rv370_pcie_gart_enable; ++ rdev->asic->gart_disable = &rv370_pcie_gart_disable; ++ rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; ++ rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; ++ } + break; + case CHIP_R420: + case CHIP_R423: +@@ -323,9 +362,15 @@ int radeon_asic_init(struct radeon_device *rdev) + case CHIP_RV635: + case CHIP_RV670: + case CHIP_RS780: ++ case CHIP_RS880: ++ rdev->asic = &r600_asic; ++ break; + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: ++ case CHIP_RV740: ++ rdev->asic = &rv770_asic; ++ break; + default: + /* FIXME: not supported yet */ + return -EINVAL; +@@ -341,7 +386,6 @@ int radeon_clocks_init(struct radeon_device *rdev) + { + int r; + +- radeon_get_clock_info(rdev->ddev); + r = radeon_static_clocks_init(rdev->ddev); + if (r) { + return r; +@@ -436,9 +480,6 @@ void radeon_combios_fini(struct radeon_device *rdev) + { + } + +-int radeon_modeset_init(struct radeon_device *rdev); +-void radeon_modeset_fini(struct radeon_device *rdev); +- + + /* + * Radeon device. +@@ -448,11 +489,12 @@ int radeon_device_init(struct radeon_device *rdev, + struct pci_dev *pdev, + uint32_t flags) + { +- int r, ret; ++ int r; + int dma_bits; + + DRM_INFO("radeon: Initializing kernel modesetting.\n"); + rdev->shutdown = false; ++ rdev->dev = &pdev->dev; + rdev->ddev = ddev; + rdev->pdev = pdev; + rdev->flags = flags; +@@ -461,37 +503,50 @@ int radeon_device_init(struct radeon_device *rdev, + rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + rdev->gpu_lockup = false; ++ rdev->accel_working = false; + /* mutex initialization are all done here so we + * can recall function without having locking issues */ + mutex_init(&rdev->cs_mutex); + mutex_init(&rdev->ib_pool.mutex); + mutex_init(&rdev->cp.mutex); + rwlock_init(&rdev->fence_drv.lock); ++ INIT_LIST_HEAD(&rdev->gem.objects); ++ ++ /* Set asic functions */ ++ r = radeon_asic_init(rdev); ++ if (r) { ++ return r; ++ } + + if (radeon_agpmode == -1) { + rdev->flags &= ~RADEON_IS_AGP; +- if (rdev->family > CHIP_RV515 || +- rdev->family == CHIP_RV380 || +- rdev->family == CHIP_RV410 || +- rdev->family == CHIP_R423) { ++ if (rdev->family >= CHIP_R600) { + DRM_INFO("Forcing AGP to PCIE mode\n"); + rdev->flags |= RADEON_IS_PCIE; ++ } else if (rdev->family >= CHIP_RV515 || ++ rdev->family == CHIP_RV380 || ++ rdev->family == CHIP_RV410 || ++ rdev->family == CHIP_R423) { ++ DRM_INFO("Forcing AGP to PCIE mode\n"); ++ rdev->flags |= RADEON_IS_PCIE; ++ rdev->asic->gart_init = &rv370_pcie_gart_init; ++ rdev->asic->gart_fini = &rv370_pcie_gart_fini; ++ rdev->asic->gart_enable = &rv370_pcie_gart_enable; ++ rdev->asic->gart_disable = &rv370_pcie_gart_disable; ++ rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; ++ rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; + } else { + DRM_INFO("Forcing AGP to PCI mode\n"); + rdev->flags |= RADEON_IS_PCI; ++ rdev->asic->gart_init = &r100_pci_gart_init; ++ rdev->asic->gart_fini = &r100_pci_gart_fini; ++ rdev->asic->gart_enable = &r100_pci_gart_enable; ++ rdev->asic->gart_disable = &r100_pci_gart_disable; ++ rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; ++ rdev->asic->gart_set_page = &r100_pci_gart_set_page; + } + } + +- /* Set asic functions */ +- r = radeon_asic_init(rdev); +- if (r) { +- return r; +- } +- r = radeon_init(rdev); +- if (r) { +- return r; +- } +- + /* set DMA mask + need_dma32 flags. + * PCIE - can handle 40-bits. + * IGP - can handle 40-bits (in theory) +@@ -521,156 +576,143 @@ int radeon_device_init(struct radeon_device *rdev, + DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); + DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); + +- /* Setup errata flags */ +- radeon_errata(rdev); +- /* Initialize scratch registers */ +- radeon_scratch_init(rdev); +- /* Initialize surface registers */ +- radeon_surface_init(rdev); +- +- /* TODO: disable VGA need to use VGA request */ +- /* BIOS*/ +- if (!radeon_get_bios(rdev)) { +- if (ASIC_IS_AVIVO(rdev)) +- return -EINVAL; +- } +- if (rdev->is_atom_bios) { +- r = radeon_atombios_init(rdev); ++ rdev->new_init_path = false; ++ r = radeon_init(rdev); ++ if (r) { ++ return r; ++ } ++ if (!rdev->new_init_path) { ++ /* Setup errata flags */ ++ radeon_errata(rdev); ++ /* Initialize scratch registers */ ++ radeon_scratch_init(rdev); ++ /* Initialize surface registers */ ++ radeon_surface_init(rdev); ++ ++ /* TODO: disable VGA need to use VGA request */ ++ /* BIOS*/ ++ if (!radeon_get_bios(rdev)) { ++ if (ASIC_IS_AVIVO(rdev)) ++ return -EINVAL; ++ } ++ if (rdev->is_atom_bios) { ++ r = radeon_atombios_init(rdev); ++ if (r) { ++ return r; ++ } ++ } else { ++ r = radeon_combios_init(rdev); ++ if (r) { ++ return r; ++ } ++ } ++ /* Reset gpu before posting otherwise ATOM will enter infinite loop */ ++ if (radeon_gpu_reset(rdev)) { ++ /* FIXME: what do we want to do here ? */ ++ } ++ /* check if cards are posted or not */ ++ if (!radeon_card_posted(rdev) && rdev->bios) { ++ DRM_INFO("GPU not posted. posting now...\n"); ++ if (rdev->is_atom_bios) { ++ atom_asic_init(rdev->mode_info.atom_context); ++ } else { ++ radeon_combios_asic_init(rdev->ddev); ++ } ++ } ++ /* Get clock & vram information */ ++ radeon_get_clock_info(rdev->ddev); ++ radeon_vram_info(rdev); ++ /* Initialize clocks */ ++ r = radeon_clocks_init(rdev); + if (r) { + return r; + } +- } else { +- r = radeon_combios_init(rdev); ++ ++ /* Initialize memory controller (also test AGP) */ ++ r = radeon_mc_init(rdev); + if (r) { + return r; + } +- } +- /* Reset gpu before posting otherwise ATOM will enter infinite loop */ +- if (radeon_gpu_reset(rdev)) { +- /* FIXME: what do we want to do here ? */ +- } +- /* check if cards are posted or not */ +- if (!radeon_card_posted(rdev) && rdev->bios) { +- DRM_INFO("GPU not posted. posting now...\n"); +- if (rdev->is_atom_bios) { +- atom_asic_init(rdev->mode_info.atom_context); +- } else { +- radeon_combios_asic_init(rdev->ddev); +- } +- } +- /* Initialize clocks */ +- r = radeon_clocks_init(rdev); +- if (r) { +- return r; +- } +- /* Get vram informations */ +- radeon_vram_info(rdev); +- +- /* Add an MTRR for the VRAM */ +- rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, +- MTRR_TYPE_WRCOMB, 1); +- DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", +- rdev->mc.real_vram_size >> 20, +- (unsigned)rdev->mc.aper_size >> 20); +- DRM_INFO("RAM width %dbits %cDR\n", +- rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); +- /* Initialize memory controller (also test AGP) */ +- r = radeon_mc_init(rdev); +- if (r) { +- return r; +- } +- /* Fence driver */ +- r = radeon_fence_driver_init(rdev); +- if (r) { +- return r; +- } +- r = radeon_irq_kms_init(rdev); +- if (r) { +- return r; +- } +- /* Memory manager */ +- r = radeon_object_init(rdev); +- if (r) { +- return r; +- } +- /* Initialize GART (initialize after TTM so we can allocate +- * memory through TTM but finalize after TTM) */ +- r = radeon_gart_enable(rdev); +- if (!r) { +- r = radeon_gem_init(rdev); +- } +- +- /* 1M ring buffer */ +- if (!r) { +- r = radeon_cp_init(rdev, 1024 * 1024); +- } +- if (!r) { +- r = radeon_wb_init(rdev); ++ /* Fence driver */ ++ r = radeon_fence_driver_init(rdev); + if (r) { +- DRM_ERROR("radeon: failled initializing WB (%d).\n", r); + return r; + } +- } +- if (!r) { +- r = radeon_ib_pool_init(rdev); ++ r = radeon_irq_kms_init(rdev); + if (r) { +- DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); + return r; + } +- } +- if (!r) { +- r = radeon_ib_test(rdev); ++ /* Memory manager */ ++ r = radeon_object_init(rdev); + if (r) { +- DRM_ERROR("radeon: failled testing IB (%d).\n", r); + return r; + } ++ r = radeon_gpu_gart_init(rdev); ++ if (r) ++ return r; ++ /* Initialize GART (initialize after TTM so we can allocate ++ * memory through TTM but finalize after TTM) */ ++ r = radeon_gart_enable(rdev); ++ if (r) ++ return 0; ++ r = radeon_gem_init(rdev); ++ if (r) ++ return 0; ++ ++ /* 1M ring buffer */ ++ r = radeon_cp_init(rdev, 1024 * 1024); ++ if (r) ++ return 0; ++ r = radeon_wb_init(rdev); ++ if (r) ++ DRM_ERROR("radeon: failled initializing WB (%d).\n", r); ++ r = radeon_ib_pool_init(rdev); ++ if (r) ++ return 0; ++ r = radeon_ib_test(rdev); ++ if (r) ++ return 0; ++ rdev->accel_working = true; + } +- ret = r; +- r = radeon_modeset_init(rdev); +- if (r) { +- return r; +- } +- if (!ret) { +- DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); +- } ++ DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); + if (radeon_testing) { + radeon_test_moves(rdev); + } + if (radeon_benchmarking) { + radeon_benchmark(rdev); + } +- return ret; ++ return 0; + } + + void radeon_device_fini(struct radeon_device *rdev) + { +- if (rdev == NULL || rdev->rmmio == NULL) { +- return; +- } + DRM_INFO("radeon: finishing device.\n"); + rdev->shutdown = true; + /* Order matter so becarefull if you rearrange anythings */ +- radeon_modeset_fini(rdev); +- radeon_ib_pool_fini(rdev); +- radeon_cp_fini(rdev); +- radeon_wb_fini(rdev); +- radeon_gem_fini(rdev); +- radeon_object_fini(rdev); +- /* mc_fini must be after object_fini */ +- radeon_mc_fini(rdev); ++ if (!rdev->new_init_path) { ++ radeon_ib_pool_fini(rdev); ++ radeon_cp_fini(rdev); ++ radeon_wb_fini(rdev); ++ radeon_gpu_gart_fini(rdev); ++ radeon_gem_fini(rdev); ++ radeon_mc_fini(rdev); + #if __OS_HAS_AGP +- radeon_agp_fini(rdev); ++ radeon_agp_fini(rdev); + #endif +- radeon_irq_kms_fini(rdev); +- radeon_fence_driver_fini(rdev); +- radeon_clocks_fini(rdev); +- if (rdev->is_atom_bios) { +- radeon_atombios_fini(rdev); ++ radeon_irq_kms_fini(rdev); ++ radeon_fence_driver_fini(rdev); ++ radeon_clocks_fini(rdev); ++ radeon_object_fini(rdev); ++ if (rdev->is_atom_bios) { ++ radeon_atombios_fini(rdev); ++ } else { ++ radeon_combios_fini(rdev); ++ } ++ kfree(rdev->bios); ++ rdev->bios = NULL; + } else { +- radeon_combios_fini(rdev); ++ radeon_fini(rdev); + } +- kfree(rdev->bios); +- rdev->bios = NULL; + iounmap(rdev->rmmio); + rdev->rmmio = NULL; + } +@@ -708,15 +750,19 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) + /* wait for gpu to finish processing current batch */ + radeon_fence_wait_last(rdev); + +- radeon_cp_disable(rdev); +- radeon_gart_disable(rdev); ++ radeon_save_bios_scratch_regs(rdev); + ++ if (!rdev->new_init_path) { ++ radeon_cp_disable(rdev); ++ radeon_gart_disable(rdev); ++ rdev->irq.sw_int = false; ++ radeon_irq_set(rdev); ++ } else { ++ radeon_suspend(rdev); ++ } + /* evict remaining vram memory */ + radeon_object_evict_vram(rdev); + +- rdev->irq.sw_int = false; +- radeon_irq_set(rdev); +- + pci_save_state(dev->pdev); + if (state.event == PM_EVENT_SUSPEND) { + /* Shut down the device */ +@@ -743,38 +789,43 @@ int radeon_resume_kms(struct drm_device *dev) + } + pci_set_master(dev->pdev); + /* Reset gpu before posting otherwise ATOM will enter infinite loop */ +- if (radeon_gpu_reset(rdev)) { +- /* FIXME: what do we want to do here ? */ +- } +- /* post card */ +- if (rdev->is_atom_bios) { +- atom_asic_init(rdev->mode_info.atom_context); ++ if (!rdev->new_init_path) { ++ if (radeon_gpu_reset(rdev)) { ++ /* FIXME: what do we want to do here ? */ ++ } ++ /* post card */ ++ if (rdev->is_atom_bios) { ++ atom_asic_init(rdev->mode_info.atom_context); ++ } else { ++ radeon_combios_asic_init(rdev->ddev); ++ } ++ /* Initialize clocks */ ++ r = radeon_clocks_init(rdev); ++ if (r) { ++ release_console_sem(); ++ return r; ++ } ++ /* Enable IRQ */ ++ rdev->irq.sw_int = true; ++ radeon_irq_set(rdev); ++ /* Initialize GPU Memory Controller */ ++ r = radeon_mc_init(rdev); ++ if (r) { ++ goto out; ++ } ++ r = radeon_gart_enable(rdev); ++ if (r) { ++ goto out; ++ } ++ r = radeon_cp_init(rdev, rdev->cp.ring_size); ++ if (r) { ++ goto out; ++ } + } else { +- radeon_combios_asic_init(rdev->ddev); +- } +- /* Initialize clocks */ +- r = radeon_clocks_init(rdev); +- if (r) { +- release_console_sem(); +- return r; +- } +- /* Enable IRQ */ +- rdev->irq.sw_int = true; +- radeon_irq_set(rdev); +- /* Initialize GPU Memory Controller */ +- r = radeon_mc_init(rdev); +- if (r) { +- goto out; +- } +- r = radeon_gart_enable(rdev); +- if (r) { +- goto out; +- } +- r = radeon_cp_init(rdev, rdev->cp.ring_size); +- if (r) { +- goto out; ++ radeon_resume(rdev); + } + out: ++ radeon_restore_bios_scratch_regs(rdev); + fb_set_suspend(rdev->fbdev_info, 0); + release_console_sem(); + +diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c +index a8fa1bb..5d8141b 100644 +--- a/drivers/gpu/drm/radeon/radeon_display.c ++++ b/drivers/gpu/drm/radeon/radeon_display.c +@@ -158,9 +158,6 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc) + { + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + +- if (radeon_crtc->mode_set.mode) { +- drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode); +- } + drm_crtc_cleanup(crtc); + kfree(radeon_crtc); + } +@@ -189,9 +186,11 @@ static void radeon_crtc_init(struct drm_device *dev, int index) + radeon_crtc->crtc_id = index; + rdev->mode_info.crtcs[index] = radeon_crtc; + ++#if 0 + radeon_crtc->mode_set.crtc = &radeon_crtc->base; + radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); + radeon_crtc->mode_set.num_connectors = 0; ++#endif + + for (i = 0; i < 256; i++) { + radeon_crtc->lut_r[i] = i << 2; +@@ -313,7 +312,7 @@ static void radeon_print_display_setup(struct drm_device *dev) + } + } + +-bool radeon_setup_enc_conn(struct drm_device *dev) ++static bool radeon_setup_enc_conn(struct drm_device *dev) + { + struct radeon_device *rdev = dev->dev_private; + struct drm_connector *drm_connector; +@@ -347,9 +346,13 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) + + if (!radeon_connector->ddc_bus) + return -1; +- radeon_i2c_do_lock(radeon_connector, 1); +- edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); +- radeon_i2c_do_lock(radeon_connector, 0); ++ if (!radeon_connector->edid) { ++ radeon_i2c_do_lock(radeon_connector, 1); ++ edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); ++ radeon_i2c_do_lock(radeon_connector, 0); ++ } else ++ edid = radeon_connector->edid; ++ + if (edid) { + /* update digital bits here */ + if (edid->input & DRM_EDID_INPUT_DIGITAL) +@@ -362,7 +365,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) + return ret; + } + drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); +- return -1; ++ return 0; + } + + static int radeon_ddc_dump(struct drm_connector *connector) +@@ -620,6 +623,83 @@ static const struct drm_mode_config_funcs radeon_mode_funcs = { + .fb_changed = radeonfb_probe, + }; + ++struct drm_prop_enum_list { ++ int type; ++ char *name; ++}; ++ ++static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = ++{ { 0, "driver" }, ++ { 1, "bios" }, ++}; ++ ++static struct drm_prop_enum_list radeon_tv_std_enum_list[] = ++{ { TV_STD_NTSC, "ntsc" }, ++ { TV_STD_PAL, "pal" }, ++ { TV_STD_PAL_M, "pal-m" }, ++ { TV_STD_PAL_60, "pal-60" }, ++ { TV_STD_NTSC_J, "ntsc-j" }, ++ { TV_STD_SCART_PAL, "scart-pal" }, ++ { TV_STD_PAL_CN, "pal-cn" }, ++ { TV_STD_SECAM, "secam" }, ++}; ++ ++int radeon_modeset_create_props(struct radeon_device *rdev) ++{ ++ int i, sz; ++ ++ if (rdev->is_atom_bios) { ++ rdev->mode_info.coherent_mode_property = ++ drm_property_create(rdev->ddev, ++ DRM_MODE_PROP_RANGE, ++ "coherent", 2); ++ if (!rdev->mode_info.coherent_mode_property) ++ return -ENOMEM; ++ ++ rdev->mode_info.coherent_mode_property->values[0] = 0; ++ rdev->mode_info.coherent_mode_property->values[0] = 1; ++ } ++ ++ if (!ASIC_IS_AVIVO(rdev)) { ++ sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); ++ rdev->mode_info.tmds_pll_property = ++ drm_property_create(rdev->ddev, ++ DRM_MODE_PROP_ENUM, ++ "tmds_pll", sz); ++ for (i = 0; i < sz; i++) { ++ drm_property_add_enum(rdev->mode_info.tmds_pll_property, ++ i, ++ radeon_tmds_pll_enum_list[i].type, ++ radeon_tmds_pll_enum_list[i].name); ++ } ++ } ++ ++ rdev->mode_info.load_detect_property = ++ drm_property_create(rdev->ddev, ++ DRM_MODE_PROP_RANGE, ++ "load detection", 2); ++ if (!rdev->mode_info.load_detect_property) ++ return -ENOMEM; ++ rdev->mode_info.load_detect_property->values[0] = 0; ++ rdev->mode_info.load_detect_property->values[0] = 1; ++ ++ drm_mode_create_scaling_mode_property(rdev->ddev); ++ ++ sz = ARRAY_SIZE(radeon_tv_std_enum_list); ++ rdev->mode_info.tv_std_property = ++ drm_property_create(rdev->ddev, ++ DRM_MODE_PROP_ENUM, ++ "tv standard", sz); ++ for (i = 0; i < sz; i++) { ++ drm_property_add_enum(rdev->mode_info.tv_std_property, ++ i, ++ radeon_tv_std_enum_list[i].type, ++ radeon_tv_std_enum_list[i].name); ++ } ++ ++ return 0; ++} ++ + int radeon_modeset_init(struct radeon_device *rdev) + { + int num_crtc = 2, i; +@@ -640,6 +720,10 @@ int radeon_modeset_init(struct radeon_device *rdev) + + rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; + ++ ret = radeon_modeset_create_props(rdev); ++ if (ret) { ++ return ret; ++ } + /* allocate crtcs - TODO single crtc */ + for (i = 0; i < num_crtc; i++) { + radeon_crtc_init(rdev->ddev, i); +@@ -678,7 +762,6 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, + continue; + if (first) { + radeon_crtc->rmx_type = radeon_encoder->rmx_type; +- radeon_crtc->devices = radeon_encoder->devices; + memcpy(&radeon_crtc->native_mode, + &radeon_encoder->native_mode, + sizeof(struct radeon_native_mode)); +diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c +index 0bd5879..7f50fb8 100644 +--- a/drivers/gpu/drm/radeon/radeon_drv.c ++++ b/drivers/gpu/drm/radeon/radeon_drv.c +@@ -38,7 +38,6 @@ + #include <linux/console.h> + + +-#if defined(CONFIG_DRM_RADEON_KMS) + /* + * KMS wrapper. + */ +@@ -63,9 +62,6 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev); + int radeon_driver_irq_postinstall_kms(struct drm_device *dev); + void radeon_driver_irq_uninstall_kms(struct drm_device *dev); + irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); +-int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master); +-void radeon_master_destroy_kms(struct drm_device *dev, +- struct drm_master *master); + int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, + struct drm_file *file_priv); + int radeon_gem_object_init(struct drm_gem_object *obj); +@@ -77,11 +73,9 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma); + int radeon_debugfs_init(struct drm_minor *minor); + void radeon_debugfs_cleanup(struct drm_minor *minor); + #endif +-#endif + + + int radeon_no_wb; +-#if defined(CONFIG_DRM_RADEON_KMS) + int radeon_modeset = -1; + int radeon_dynclks = -1; + int radeon_r4xx_atom = 0; +@@ -91,12 +85,11 @@ int radeon_gart_size = 512; /* default gart size */ + int radeon_benchmarking = 0; + int radeon_testing = 0; + int radeon_connector_table = 0; +-#endif ++int radeon_tv = 1; + + MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); + module_param_named(no_wb, radeon_no_wb, int, 0444); + +-#if defined(CONFIG_DRM_RADEON_KMS) + MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); + module_param_named(modeset, radeon_modeset, int, 0400); + +@@ -123,7 +116,9 @@ module_param_named(test, radeon_testing, int, 0444); + + MODULE_PARM_DESC(connector_table, "Force connector table"); + module_param_named(connector_table, radeon_connector_table, int, 0444); +-#endif ++ ++MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); ++module_param_named(tv, radeon_tv, int, 0444); + + static int radeon_suspend(struct drm_device *dev, pm_message_t state) + { +@@ -215,7 +210,6 @@ static struct drm_driver driver_old = { + .patchlevel = DRIVER_PATCHLEVEL, + }; + +-#if defined(CONFIG_DRM_RADEON_KMS) + static struct drm_driver kms_driver; + + static int __devinit +@@ -263,8 +257,6 @@ static struct drm_driver kms_driver = { + .get_vblank_counter = radeon_get_vblank_counter_kms, + .enable_vblank = radeon_enable_vblank_kms, + .disable_vblank = radeon_disable_vblank_kms, +- .master_create = radeon_master_create_kms, +- .master_destroy = radeon_master_destroy_kms, + #if defined(CONFIG_DEBUG_FS) + .debugfs_init = radeon_debugfs_init, + .debugfs_cleanup = radeon_debugfs_cleanup, +@@ -289,7 +281,7 @@ static struct drm_driver kms_driver = { + .poll = drm_poll, + .fasync = drm_fasync, + #ifdef CONFIG_COMPAT +- .compat_ioctl = NULL, ++ .compat_ioctl = radeon_kms_compat_ioctl, + #endif + }, + +@@ -309,7 +301,6 @@ static struct drm_driver kms_driver = { + .minor = KMS_DRIVER_MINOR, + .patchlevel = KMS_DRIVER_PATCHLEVEL, + }; +-#endif + + static struct drm_driver *driver; + +@@ -317,7 +308,6 @@ static int __init radeon_init(void) + { + driver = &driver_old; + driver->num_ioctls = radeon_max_ioctl; +-#if defined(CONFIG_DRM_RADEON_KMS) + #ifdef CONFIG_VGA_CONSOLE + if (vgacon_text_force() && radeon_modeset == -1) { + DRM_INFO("VGACON disable radeon kernel modesetting.\n"); +@@ -328,8 +318,13 @@ static int __init radeon_init(void) + #endif + /* if enabled by default */ + if (radeon_modeset == -1) { +- DRM_INFO("radeon default to kernel modesetting.\n"); ++#ifdef CONFIG_DRM_RADEON_KMS ++ DRM_INFO("radeon defaulting to kernel modesetting.\n"); + radeon_modeset = 1; ++#else ++ DRM_INFO("radeon defaulting to userspace modesetting.\n"); ++ radeon_modeset = 0; ++#endif + } + if (radeon_modeset == 1) { + DRM_INFO("radeon kernel modesetting enabled.\n"); +@@ -339,7 +334,6 @@ static int __init radeon_init(void) + } + /* if the vga console setting is enabled still + * let modprobe override it */ +-#endif + return drm_init(driver); + } + +diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h +index 6fa32da..350962e 100644 +--- a/drivers/gpu/drm/radeon/radeon_drv.h ++++ b/drivers/gpu/drm/radeon/radeon_drv.h +@@ -31,6 +31,11 @@ + #ifndef __RADEON_DRV_H__ + #define __RADEON_DRV_H__ + ++#include <linux/firmware.h> ++#include <linux/platform_device.h> ++ ++#include "radeon_family.h" ++ + /* General customization: + */ + +@@ -106,75 +111,12 @@ + #define DRIVER_MINOR 31 + #define DRIVER_PATCHLEVEL 0 + +-/* +- * Radeon chip families +- */ +-enum radeon_family { +- CHIP_R100, +- CHIP_RV100, +- CHIP_RS100, +- CHIP_RV200, +- CHIP_RS200, +- CHIP_R200, +- CHIP_RV250, +- CHIP_RS300, +- CHIP_RV280, +- CHIP_R300, +- CHIP_R350, +- CHIP_RV350, +- CHIP_RV380, +- CHIP_R420, +- CHIP_R423, +- CHIP_RV410, +- CHIP_RS400, +- CHIP_RS480, +- CHIP_RS600, +- CHIP_RS690, +- CHIP_RS740, +- CHIP_RV515, +- CHIP_R520, +- CHIP_RV530, +- CHIP_RV560, +- CHIP_RV570, +- CHIP_R580, +- CHIP_R600, +- CHIP_RV610, +- CHIP_RV630, +- CHIP_RV620, +- CHIP_RV635, +- CHIP_RV670, +- CHIP_RS780, +- CHIP_RS880, +- CHIP_RV770, +- CHIP_RV730, +- CHIP_RV710, +- CHIP_RV740, +- CHIP_LAST, +-}; +- + enum radeon_cp_microcode_version { + UCODE_R100, + UCODE_R200, + UCODE_R300, + }; + +-/* +- * Chip flags +- */ +-enum radeon_chip_flags { +- RADEON_FAMILY_MASK = 0x0000ffffUL, +- RADEON_FLAGS_MASK = 0xffff0000UL, +- RADEON_IS_MOBILITY = 0x00010000UL, +- RADEON_IS_IGP = 0x00020000UL, +- RADEON_SINGLE_CRTC = 0x00040000UL, +- RADEON_IS_AGP = 0x00080000UL, +- RADEON_HAS_HIERZ = 0x00100000UL, +- RADEON_IS_PCIE = 0x00200000UL, +- RADEON_NEW_MEMMAP = 0x00400000UL, +- RADEON_IS_PCI = 0x00800000UL, +- RADEON_IS_IGPGART = 0x01000000UL, +-}; +- + typedef struct drm_radeon_freelist { + unsigned int age; + struct drm_buf *buf; +@@ -353,6 +295,14 @@ typedef struct drm_radeon_private { + int r700_sc_hiz_tile_fifo_size; + int r700_sc_earlyz_tile_fifo_fize; + ++ struct mutex cs_mutex; ++ u32 cs_id_scnt; ++ u32 cs_id_wcnt; ++ /* r6xx/r7xx drm blit vertex buffer */ ++ struct drm_buf *blit_vb; ++ ++ /* firmware */ ++ const struct firmware *me_fw, *pfp_fw; + } drm_radeon_private_t; + + typedef struct drm_radeon_buf_priv { +@@ -391,6 +341,9 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, + (off >= gart_start && off <= gart_end)); + } + ++/* radeon_state.c */ ++extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf); ++ + /* radeon_cp.c */ + extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); + extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); +@@ -457,6 +410,8 @@ extern int radeon_driver_open(struct drm_device *dev, + struct drm_file *file_priv); + extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg); ++extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, ++ unsigned long arg); + + extern int radeon_master_create(struct drm_device *dev, struct drm_master *master); + extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); +@@ -482,6 +437,22 @@ extern int r600_cp_dispatch_indirect(struct drm_device *dev, + struct drm_buf *buf, int start, int end); + extern int r600_page_table_init(struct drm_device *dev); + extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); ++extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); ++extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv); ++extern int r600_cp_dispatch_texture(struct drm_device *dev, ++ struct drm_file *file_priv, ++ drm_radeon_texture_t *tex, ++ drm_radeon_tex_image_t *image); ++/* r600_blit.c */ ++extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv); ++extern void r600_done_blit_copy(struct drm_device *dev); ++extern void r600_blit_copy(struct drm_device *dev, ++ uint64_t src_gpu_addr, uint64_t dst_gpu_addr, ++ int size_bytes); ++extern void r600_blit_swap(struct drm_device *dev, ++ uint64_t src_gpu_addr, uint64_t dst_gpu_addr, ++ int sx, int sy, int dx, int dy, ++ int w, int h, int src_pitch, int dst_pitch, int cpp); + + /* Flags for stats.boxes + */ +@@ -1067,6 +1038,9 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); + # define RADEON_CSQ_PRIBM_INDBM (4 << 28) + # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) + ++#define R300_CP_RESYNC_ADDR 0x0778 ++#define R300_CP_RESYNC_DATA 0x077c ++ + #define RADEON_AIC_CNTL 0x01d0 + # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) + # define RS400_MSI_REARM (1 << 3) +@@ -1109,13 +1083,71 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); + # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 + # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 + +-# define R600_IT_INDIRECT_BUFFER 0x00003200 +-# define R600_IT_ME_INITIALIZE 0x00004400 ++# define R600_IT_INDIRECT_BUFFER_END 0x00001700 ++# define R600_IT_SET_PREDICATION 0x00002000 ++# define R600_IT_REG_RMW 0x00002100 ++# define R600_IT_COND_EXEC 0x00002200 ++# define R600_IT_PRED_EXEC 0x00002300 ++# define R600_IT_START_3D_CMDBUF 0x00002400 ++# define R600_IT_DRAW_INDEX_2 0x00002700 ++# define R600_IT_CONTEXT_CONTROL 0x00002800 ++# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 ++# define R600_IT_INDEX_TYPE 0x00002A00 ++# define R600_IT_DRAW_INDEX 0x00002B00 ++# define R600_IT_DRAW_INDEX_AUTO 0x00002D00 ++# define R600_IT_DRAW_INDEX_IMMD 0x00002E00 ++# define R600_IT_NUM_INSTANCES 0x00002F00 ++# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 ++# define R600_IT_INDIRECT_BUFFER_MP 0x00003800 ++# define R600_IT_MEM_SEMAPHORE 0x00003900 ++# define R600_IT_MPEG_INDEX 0x00003A00 ++# define R600_IT_WAIT_REG_MEM 0x00003C00 ++# define R600_IT_MEM_WRITE 0x00003D00 ++# define R600_IT_INDIRECT_BUFFER 0x00003200 ++# define R600_IT_CP_INTERRUPT 0x00004000 ++# define R600_IT_SURFACE_SYNC 0x00004300 ++# define R600_CB0_DEST_BASE_ENA (1 << 6) ++# define R600_TC_ACTION_ENA (1 << 23) ++# define R600_VC_ACTION_ENA (1 << 24) ++# define R600_CB_ACTION_ENA (1 << 25) ++# define R600_DB_ACTION_ENA (1 << 26) ++# define R600_SH_ACTION_ENA (1 << 27) ++# define R600_SMX_ACTION_ENA (1 << 28) ++# define R600_IT_ME_INITIALIZE 0x00004400 + # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) +-# define R600_IT_EVENT_WRITE 0x00004600 +-# define R600_IT_SET_CONFIG_REG 0x00006800 +-# define R600_SET_CONFIG_REG_OFFSET 0x00008000 +-# define R600_SET_CONFIG_REG_END 0x0000ac00 ++# define R600_IT_COND_WRITE 0x00004500 ++# define R600_IT_EVENT_WRITE 0x00004600 ++# define R600_IT_EVENT_WRITE_EOP 0x00004700 ++# define R600_IT_ONE_REG_WRITE 0x00005700 ++# define R600_IT_SET_CONFIG_REG 0x00006800 ++# define R600_SET_CONFIG_REG_OFFSET 0x00008000 ++# define R600_SET_CONFIG_REG_END 0x0000ac00 ++# define R600_IT_SET_CONTEXT_REG 0x00006900 ++# define R600_SET_CONTEXT_REG_OFFSET 0x00028000 ++# define R600_SET_CONTEXT_REG_END 0x00029000 ++# define R600_IT_SET_ALU_CONST 0x00006A00 ++# define R600_SET_ALU_CONST_OFFSET 0x00030000 ++# define R600_SET_ALU_CONST_END 0x00032000 ++# define R600_IT_SET_BOOL_CONST 0x00006B00 ++# define R600_SET_BOOL_CONST_OFFSET 0x0003e380 ++# define R600_SET_BOOL_CONST_END 0x00040000 ++# define R600_IT_SET_LOOP_CONST 0x00006C00 ++# define R600_SET_LOOP_CONST_OFFSET 0x0003e200 ++# define R600_SET_LOOP_CONST_END 0x0003e380 ++# define R600_IT_SET_RESOURCE 0x00006D00 ++# define R600_SET_RESOURCE_OFFSET 0x00038000 ++# define R600_SET_RESOURCE_END 0x0003c000 ++# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0 ++# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1 ++# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2 ++# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3 ++# define R600_IT_SET_SAMPLER 0x00006E00 ++# define R600_SET_SAMPLER_OFFSET 0x0003c000 ++# define R600_SET_SAMPLER_END 0x0003cff0 ++# define R600_IT_SET_CTL_CONST 0x00006F00 ++# define R600_SET_CTL_CONST_OFFSET 0x0003cff0 ++# define R600_SET_CTL_CONST_END 0x0003e200 ++# define R600_IT_SURFACE_BASE_UPDATE 0x00007300 + + #define RADEON_CP_PACKET_MASK 0xC0000000 + #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 +@@ -1593,6 +1625,52 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); + #define R600_CB_COLOR7_BASE 0x2805c + #define R600_CB_COLOR7_FRAG 0x280fc + ++#define R600_CB_COLOR0_SIZE 0x28060 ++#define R600_CB_COLOR0_VIEW 0x28080 ++#define R600_CB_COLOR0_INFO 0x280a0 ++#define R600_CB_COLOR0_TILE 0x280c0 ++#define R600_CB_COLOR0_FRAG 0x280e0 ++#define R600_CB_COLOR0_MASK 0x28100 ++ ++#define AVIVO_D1MODE_VLINE_START_END 0x6538 ++#define AVIVO_D2MODE_VLINE_START_END 0x6d38 ++#define R600_CP_COHER_BASE 0x85f8 ++#define R600_DB_DEPTH_BASE 0x2800c ++#define R600_SQ_PGM_START_FS 0x28894 ++#define R600_SQ_PGM_START_ES 0x28880 ++#define R600_SQ_PGM_START_VS 0x28858 ++#define R600_SQ_PGM_RESOURCES_VS 0x28868 ++#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0 ++#define R600_SQ_PGM_START_GS 0x2886c ++#define R600_SQ_PGM_START_PS 0x28840 ++#define R600_SQ_PGM_RESOURCES_PS 0x28850 ++#define R600_SQ_PGM_EXPORTS_PS 0x28854 ++#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc ++#define R600_VGT_DMA_BASE 0x287e8 ++#define R600_VGT_DMA_BASE_HI 0x287e4 ++#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10 ++#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14 ++#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18 ++#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c ++#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44 ++#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48 ++#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c ++#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50 ++#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8 ++#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8 ++#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8 ++#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08 ++#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc ++#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec ++#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc ++#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c ++ ++#define R600_VGT_PRIMITIVE_TYPE 0x8958 ++ ++#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030 ++#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240 ++#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204 ++ + #define R600_TC_CNTL 0x9608 + # define R600_TC_L2_SIZE(x) ((x) << 5) + # define R600_L2_DISABLE_LATE_HIT (1 << 9) +diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c +index 0a92706..6216467 100644 +--- a/drivers/gpu/drm/radeon/radeon_encoders.c ++++ b/drivers/gpu/drm/radeon/radeon_encoders.c +@@ -126,6 +126,23 @@ radeon_link_encoder_connector(struct drm_device *dev) + } + } + ++void radeon_encoder_set_active_device(struct drm_encoder *encoder) ++{ ++ struct drm_device *dev = encoder->dev; ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct drm_connector *connector; ++ ++ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { ++ if (connector->encoder == encoder) { ++ struct radeon_connector *radeon_connector = to_radeon_connector(connector); ++ radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; ++ DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", ++ radeon_encoder->active_device, radeon_encoder->devices, ++ radeon_connector->devices, encoder->encoder_type); ++ } ++ } ++} ++ + static struct drm_connector * + radeon_get_connector_for_encoder(struct drm_encoder *encoder) + { +@@ -224,9 +241,12 @@ atombios_dac_setup(struct drm_encoder *encoder, int action) + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + DAC_ENCODER_CONTROL_PS_ALLOCATION args; + int index = 0, num = 0; +- /* fixme - fill in enc_priv for atom dac */ ++ struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; + enum radeon_tv_std tv_std = TV_STD_NTSC; + ++ if (dac_info->tv_std) ++ tv_std = dac_info->tv_std; ++ + memset(&args, 0, sizeof(args)); + + switch (radeon_encoder->encoder_id) { +@@ -244,9 +264,9 @@ atombios_dac_setup(struct drm_encoder *encoder, int action) + + args.ucAction = action; + +- if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) + args.ucDacStandard = ATOM_DAC1_PS2; +- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.ucDacStandard = ATOM_DAC1_CV; + else { + switch (tv_std) { +@@ -279,16 +299,19 @@ atombios_tv_setup(struct drm_encoder *encoder, int action) + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + TV_ENCODER_CONTROL_PS_ALLOCATION args; + int index = 0; +- /* fixme - fill in enc_priv for atom dac */ ++ struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; + enum radeon_tv_std tv_std = TV_STD_NTSC; + ++ if (dac_info->tv_std) ++ tv_std = dac_info->tv_std; ++ + memset(&args, 0, sizeof(args)); + + index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); + + args.sTVEncoder.ucAction = action; + +- if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.sTVEncoder.ucTvStandard = ATOM_TV_CV; + else { + switch (tv_std) { +@@ -520,6 +543,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) + + switch (connector->connector_type) { + case DRM_MODE_CONNECTOR_DVII: ++ case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ + if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) + return ATOM_ENCODER_MODE_HDMI; + else if (radeon_connector->use_digital) +@@ -529,7 +553,6 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) + break; + case DRM_MODE_CONNECTOR_DVID: + case DRM_MODE_CONNECTOR_HDMIA: +- case DRM_MODE_CONNECTOR_HDMIB: + default: + if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) + return ATOM_ENCODER_MODE_HDMI; +@@ -825,10 +848,10 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable) + + /* XXX: fix up scratch reg handling */ + temp = RREG32(reg); +- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + WREG32(reg, (ATOM_S3_TV1_ACTIVE | + (radeon_crtc->crtc_id << 18))); +- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); + else + WREG32(reg, 0); +@@ -851,9 +874,19 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) + DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; + int index = 0; + bool is_dig = false; ++ int devices; + + memset(&args, 0, sizeof(args)); + ++ /* on DPMS off we have no idea if active device is meaningful */ ++ if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device) ++ devices = radeon_encoder->devices; ++ else ++ devices = radeon_encoder->active_device; ++ ++ DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", ++ radeon_encoder->encoder_id, mode, radeon_encoder->devices, ++ radeon_encoder->active_device); + switch (radeon_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_TMDS1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: +@@ -881,18 +914,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: +- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) ++ if (devices & (ATOM_DEVICE_TV_SUPPORT)) + index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); +- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ else if (devices & (ATOM_DEVICE_CV_SUPPORT)) + index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); + else + index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC2: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: +- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) ++ if (devices & (ATOM_DEVICE_TV_SUPPORT)) + index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); +- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ else if (devices & (ATOM_DEVICE_CV_SUPPORT)) + index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); + else + index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); +@@ -979,18 +1012,18 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: +- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; +- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; + else + args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC2: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: +- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; +- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; + else + args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; +@@ -1019,17 +1052,17 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) + args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: +- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; +- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else + args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: +- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; +- else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) ++ else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else + args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; +@@ -1097,7 +1130,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, + atombios_set_encoder_crtc_source(encoder); + + if (ASIC_IS_AVIVO(rdev)) { +- if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) + atombios_yuv_setup(encoder, true); + else + atombios_yuv_setup(encoder, false); +@@ -1135,7 +1168,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, + case ENCODER_OBJECT_ID_INTERNAL_DAC2: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + atombios_dac_setup(encoder, ATOM_ENABLE); +- if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) ++ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) + atombios_tv_setup(encoder, ATOM_ENABLE); + break; + } +@@ -1143,11 +1176,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, + } + + static bool +-atombios_dac_load_detect(struct drm_encoder *encoder) ++atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) + { + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct radeon_connector *radeon_connector = to_radeon_connector(connector); + + if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | + ATOM_DEVICE_CV_SUPPORT | +@@ -1168,15 +1202,15 @@ atombios_dac_load_detect(struct drm_encoder *encoder) + else + args.sDacload.ucDacType = ATOM_DAC_B; + +- if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) ++ if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) + args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); +- else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) ++ else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) + args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); +- else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { ++ else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { + args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); + if (crev >= 3) + args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; +- } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { ++ } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { + args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); + if (crev >= 3) + args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; +@@ -1195,9 +1229,10 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct radeon_connector *radeon_connector = to_radeon_connector(connector); + uint32_t bios_0_scratch; + +- if (!atombios_dac_load_detect(encoder)) { ++ if (!atombios_dac_load_detect(encoder, connector)) { + DRM_DEBUG("detect returned false \n"); + return connector_status_unknown; + } +@@ -1207,17 +1242,20 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec + else + bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); + +- DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch); +- if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { ++ DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); ++ if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { + if (bios_0_scratch & ATOM_S0_CRT1_MASK) + return connector_status_connected; +- } else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { ++ } ++ if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { + if (bios_0_scratch & ATOM_S0_CRT2_MASK) + return connector_status_connected; +- } else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { ++ } ++ if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { + if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) + return connector_status_connected; +- } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { ++ } ++ if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { + if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) + return connector_status_connected; /* CTV */ + else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) +@@ -1230,6 +1268,8 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) + { + radeon_atom_output_lock(encoder, true); + radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); ++ ++ radeon_encoder_set_active_device(encoder); + } + + static void radeon_atom_encoder_commit(struct drm_encoder *encoder) +@@ -1238,12 +1278,20 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder) + radeon_atom_output_lock(encoder, false); + } + ++static void radeon_atom_encoder_disable(struct drm_encoder *encoder) ++{ ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); ++ radeon_encoder->active_device = 0; ++} ++ + static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { + .dpms = radeon_atom_encoder_dpms, + .mode_fixup = radeon_atom_mode_fixup, + .prepare = radeon_atom_encoder_prepare, + .mode_set = radeon_atom_encoder_mode_set, + .commit = radeon_atom_encoder_commit, ++ .disable = radeon_atom_encoder_disable, + /* no detect for TMDS/LVDS yet */ + }; + +@@ -1268,6 +1316,18 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = { + .destroy = radeon_enc_destroy, + }; + ++struct radeon_encoder_atom_dac * ++radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) ++{ ++ struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); ++ ++ if (!dac) ++ return NULL; ++ ++ dac->tv_std = TV_STD_NTSC; ++ return dac; ++} ++ + struct radeon_encoder_atom_dig * + radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) + { +@@ -1336,6 +1396,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); ++ radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); + drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); + break; + case ENCODER_OBJECT_ID_INTERNAL_DVO1: +@@ -1345,8 +1406,14 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: +- drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); +- radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); ++ if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { ++ radeon_encoder->rmx_type = RMX_FULL; ++ drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); ++ radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); ++ } else { ++ drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); ++ radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); ++ } + drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); + break; + } +diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h +new file mode 100644 +index 0000000..797972e +--- /dev/null ++++ b/drivers/gpu/drm/radeon/radeon_family.h +@@ -0,0 +1,97 @@ ++/* ++ * Copyright 2008 Advanced Micro Devices, Inc. ++ * Copyright 2008 Red Hat Inc. ++ * Copyright 2009 Jerome Glisse. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++ ++/* this file defines the CHIP_ and family flags used in the pciids, ++ * its is common between kms and non-kms because duplicating it and ++ * changing one place is fail. ++ */ ++#ifndef RADEON_FAMILY_H ++#define RADEON_FAMILY_H ++/* ++ * Radeon chip families ++ */ ++enum radeon_family { ++ CHIP_R100, ++ CHIP_RV100, ++ CHIP_RS100, ++ CHIP_RV200, ++ CHIP_RS200, ++ CHIP_R200, ++ CHIP_RV250, ++ CHIP_RS300, ++ CHIP_RV280, ++ CHIP_R300, ++ CHIP_R350, ++ CHIP_RV350, ++ CHIP_RV380, ++ CHIP_R420, ++ CHIP_R423, ++ CHIP_RV410, ++ CHIP_RS400, ++ CHIP_RS480, ++ CHIP_RS600, ++ CHIP_RS690, ++ CHIP_RS740, ++ CHIP_RV515, ++ CHIP_R520, ++ CHIP_RV530, ++ CHIP_RV560, ++ CHIP_RV570, ++ CHIP_R580, ++ CHIP_R600, ++ CHIP_RV610, ++ CHIP_RV630, ++ CHIP_RV670, ++ CHIP_RV620, ++ CHIP_RV635, ++ CHIP_RS780, ++ CHIP_RS880, ++ CHIP_RV770, ++ CHIP_RV730, ++ CHIP_RV710, ++ CHIP_RV740, ++ CHIP_LAST, ++}; ++ ++/* ++ * Chip flags ++ */ ++enum radeon_chip_flags { ++ RADEON_FAMILY_MASK = 0x0000ffffUL, ++ RADEON_FLAGS_MASK = 0xffff0000UL, ++ RADEON_IS_MOBILITY = 0x00010000UL, ++ RADEON_IS_IGP = 0x00020000UL, ++ RADEON_SINGLE_CRTC = 0x00040000UL, ++ RADEON_IS_AGP = 0x00080000UL, ++ RADEON_HAS_HIERZ = 0x00100000UL, ++ RADEON_IS_PCIE = 0x00200000UL, ++ RADEON_NEW_MEMMAP = 0x00400000UL, ++ RADEON_IS_PCI = 0x00800000UL, ++ RADEON_IS_IGPGART = 0x01000000UL, ++}; ++#endif +diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c +index ec383ed..1ba704e 100644 +--- a/drivers/gpu/drm/radeon/radeon_fb.c ++++ b/drivers/gpu/drm/radeon/radeon_fb.c +@@ -28,15 +28,7 @@ + */ + + #include <linux/module.h> +-#include <linux/kernel.h> +-#include <linux/errno.h> +-#include <linux/string.h> +-#include <linux/mm.h> +-#include <linux/tty.h> +-#include <linux/slab.h> +-#include <linux/delay.h> + #include <linux/fb.h> +-#include <linux/init.h> + + #include "drmP.h" + #include "drm.h" +@@ -45,375 +37,24 @@ + #include "radeon_drm.h" + #include "radeon.h" + ++#include "drm_fb_helper.h" ++ + struct radeon_fb_device { +- struct radeon_device *rdev; +- struct drm_display_mode *mode; ++ struct drm_fb_helper helper; + struct radeon_framebuffer *rfb; +- int crtc_count; +- /* crtc currently bound to this */ +- uint32_t crtc_ids[2]; ++ struct radeon_device *rdev; + }; + +-static int radeonfb_setcolreg(unsigned regno, +- unsigned red, +- unsigned green, +- unsigned blue, +- unsigned transp, +- struct fb_info *info) +-{ +- struct radeon_fb_device *rfbdev = info->par; +- struct drm_device *dev = rfbdev->rdev->ddev; +- struct drm_crtc *crtc; +- int i; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); +- struct drm_mode_set *modeset = &radeon_crtc->mode_set; +- struct drm_framebuffer *fb = modeset->fb; +- +- for (i = 0; i < rfbdev->crtc_count; i++) { +- if (crtc->base.id == rfbdev->crtc_ids[i]) { +- break; +- } +- } +- if (i == rfbdev->crtc_count) { +- continue; +- } +- if (regno > 255) { +- return 1; +- } +- if (fb->depth == 8) { +- radeon_crtc_fb_gamma_set(crtc, red, green, blue, regno); +- return 0; +- } +- +- if (regno < 16) { +- switch (fb->depth) { +- case 15: +- fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | +- ((green & 0xf800) >> 6) | +- ((blue & 0xf800) >> 11); +- break; +- case 16: +- fb->pseudo_palette[regno] = (red & 0xf800) | +- ((green & 0xfc00) >> 5) | +- ((blue & 0xf800) >> 11); +- break; +- case 24: +- case 32: +- fb->pseudo_palette[regno] = +- (((red >> 8) & 0xff) << info->var.red.offset) | +- (((green >> 8) & 0xff) << info->var.green.offset) | +- (((blue >> 8) & 0xff) << info->var.blue.offset); +- break; +- } +- } +- } +- return 0; +-} +- +-static int radeonfb_check_var(struct fb_var_screeninfo *var, +- struct fb_info *info) +-{ +- struct radeon_fb_device *rfbdev = info->par; +- struct radeon_framebuffer *rfb = rfbdev->rfb; +- struct drm_framebuffer *fb = &rfb->base; +- int depth; +- +- if (var->pixclock == -1 || !var->pixclock) { +- return -EINVAL; +- } +- /* Need to resize the fb object !!! */ +- if (var->xres > fb->width || var->yres > fb->height) { +- DRM_ERROR("Requested width/height is greater than current fb " +- "object %dx%d > %dx%d\n", var->xres, var->yres, +- fb->width, fb->height); +- DRM_ERROR("Need resizing code.\n"); +- return -EINVAL; +- } +- +- switch (var->bits_per_pixel) { +- case 16: +- depth = (var->green.length == 6) ? 16 : 15; +- break; +- case 32: +- depth = (var->transp.length > 0) ? 32 : 24; +- break; +- default: +- depth = var->bits_per_pixel; +- break; +- } +- +- switch (depth) { +- case 8: +- var->red.offset = 0; +- var->green.offset = 0; +- var->blue.offset = 0; +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; +- var->transp.length = 0; +- var->transp.offset = 0; +- break; +-#ifdef __LITTLE_ENDIAN +- case 15: +- var->red.offset = 10; +- var->green.offset = 5; +- var->blue.offset = 0; +- var->red.length = 5; +- var->green.length = 5; +- var->blue.length = 5; +- var->transp.length = 1; +- var->transp.offset = 15; +- break; +- case 16: +- var->red.offset = 11; +- var->green.offset = 5; +- var->blue.offset = 0; +- var->red.length = 5; +- var->green.length = 6; +- var->blue.length = 5; +- var->transp.length = 0; +- var->transp.offset = 0; +- break; +- case 24: +- var->red.offset = 16; +- var->green.offset = 8; +- var->blue.offset = 0; +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; +- var->transp.length = 0; +- var->transp.offset = 0; +- break; +- case 32: +- var->red.offset = 16; +- var->green.offset = 8; +- var->blue.offset = 0; +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; +- var->transp.length = 8; +- var->transp.offset = 24; +- break; +-#else +- case 24: +- var->red.offset = 8; +- var->green.offset = 16; +- var->blue.offset = 24; +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; +- var->transp.length = 0; +- var->transp.offset = 0; +- break; +- case 32: +- var->red.offset = 8; +- var->green.offset = 16; +- var->blue.offset = 24; +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; +- var->transp.length = 8; +- var->transp.offset = 0; +- break; +-#endif +- default: +- return -EINVAL; +- } +- return 0; +-} +- +-/* this will let fbcon do the mode init */ +-static int radeonfb_set_par(struct fb_info *info) +-{ +- struct radeon_fb_device *rfbdev = info->par; +- struct drm_device *dev = rfbdev->rdev->ddev; +- struct fb_var_screeninfo *var = &info->var; +- struct drm_crtc *crtc; +- int ret; +- int i; +- +- if (var->pixclock != -1) { +- DRM_ERROR("PIXEL CLCOK SET\n"); +- return -EINVAL; +- } +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); +- +- for (i = 0; i < rfbdev->crtc_count; i++) { +- if (crtc->base.id == rfbdev->crtc_ids[i]) { +- break; +- } +- } +- if (i == rfbdev->crtc_count) { +- continue; +- } +- if (crtc->fb == radeon_crtc->mode_set.fb) { +- mutex_lock(&dev->mode_config.mutex); +- ret = crtc->funcs->set_config(&radeon_crtc->mode_set); +- mutex_unlock(&dev->mode_config.mutex); +- if (ret) { +- return ret; +- } +- } +- } +- return 0; +-} +- +-static int radeonfb_pan_display(struct fb_var_screeninfo *var, +- struct fb_info *info) +-{ +- struct radeon_fb_device *rfbdev = info->par; +- struct drm_device *dev = rfbdev->rdev->ddev; +- struct drm_mode_set *modeset; +- struct drm_crtc *crtc; +- struct radeon_crtc *radeon_crtc; +- int ret = 0; +- int i; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- for (i = 0; i < rfbdev->crtc_count; i++) { +- if (crtc->base.id == rfbdev->crtc_ids[i]) { +- break; +- } +- } +- +- if (i == rfbdev->crtc_count) { +- continue; +- } +- +- radeon_crtc = to_radeon_crtc(crtc); +- modeset = &radeon_crtc->mode_set; +- +- modeset->x = var->xoffset; +- modeset->y = var->yoffset; +- +- if (modeset->num_connectors) { +- mutex_lock(&dev->mode_config.mutex); +- ret = crtc->funcs->set_config(modeset); +- mutex_unlock(&dev->mode_config.mutex); +- if (!ret) { +- info->var.xoffset = var->xoffset; +- info->var.yoffset = var->yoffset; +- } +- } +- } +- return ret; +-} +- +-static void radeonfb_on(struct fb_info *info) +-{ +- struct radeon_fb_device *rfbdev = info->par; +- struct drm_device *dev = rfbdev->rdev->ddev; +- struct drm_crtc *crtc; +- struct drm_encoder *encoder; +- int i; +- +- /* +- * For each CRTC in this fb, find all associated encoders +- * and turn them off, then turn off the CRTC. +- */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; +- +- for (i = 0; i < rfbdev->crtc_count; i++) { +- if (crtc->base.id == rfbdev->crtc_ids[i]) { +- break; +- } +- } +- +- mutex_lock(&dev->mode_config.mutex); +- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); +- mutex_unlock(&dev->mode_config.mutex); +- +- /* Found a CRTC on this fb, now find encoders */ +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- if (encoder->crtc == crtc) { +- struct drm_encoder_helper_funcs *encoder_funcs; +- +- encoder_funcs = encoder->helper_private; +- mutex_lock(&dev->mode_config.mutex); +- encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); +- mutex_unlock(&dev->mode_config.mutex); +- } +- } +- } +-} +- +-static void radeonfb_off(struct fb_info *info, int dpms_mode) +-{ +- struct radeon_fb_device *rfbdev = info->par; +- struct drm_device *dev = rfbdev->rdev->ddev; +- struct drm_crtc *crtc; +- struct drm_encoder *encoder; +- int i; +- +- /* +- * For each CRTC in this fb, find all associated encoders +- * and turn them off, then turn off the CRTC. +- */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; +- +- for (i = 0; i < rfbdev->crtc_count; i++) { +- if (crtc->base.id == rfbdev->crtc_ids[i]) { +- break; +- } +- } +- +- /* Found a CRTC on this fb, now find encoders */ +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- if (encoder->crtc == crtc) { +- struct drm_encoder_helper_funcs *encoder_funcs; +- +- encoder_funcs = encoder->helper_private; +- mutex_lock(&dev->mode_config.mutex); +- encoder_funcs->dpms(encoder, dpms_mode); +- mutex_unlock(&dev->mode_config.mutex); +- } +- } +- if (dpms_mode == DRM_MODE_DPMS_OFF) { +- mutex_lock(&dev->mode_config.mutex); +- crtc_funcs->dpms(crtc, dpms_mode); +- mutex_unlock(&dev->mode_config.mutex); +- } +- } +-} +- +-int radeonfb_blank(int blank, struct fb_info *info) +-{ +- switch (blank) { +- case FB_BLANK_UNBLANK: +- radeonfb_on(info); +- break; +- case FB_BLANK_NORMAL: +- radeonfb_off(info, DRM_MODE_DPMS_STANDBY); +- break; +- case FB_BLANK_HSYNC_SUSPEND: +- radeonfb_off(info, DRM_MODE_DPMS_STANDBY); +- break; +- case FB_BLANK_VSYNC_SUSPEND: +- radeonfb_off(info, DRM_MODE_DPMS_SUSPEND); +- break; +- case FB_BLANK_POWERDOWN: +- radeonfb_off(info, DRM_MODE_DPMS_OFF); +- break; +- } +- return 0; +-} +- + static struct fb_ops radeonfb_ops = { + .owner = THIS_MODULE, +- .fb_check_var = radeonfb_check_var, +- .fb_set_par = radeonfb_set_par, +- .fb_setcolreg = radeonfb_setcolreg, ++ .fb_check_var = drm_fb_helper_check_var, ++ .fb_set_par = drm_fb_helper_set_par, ++ .fb_setcolreg = drm_fb_helper_setcolreg, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +- .fb_pan_display = radeonfb_pan_display, +- .fb_blank = radeonfb_blank, ++ .fb_pan_display = drm_fb_helper_pan_display, ++ .fb_blank = drm_fb_helper_blank, + }; + + /** +@@ -456,21 +97,6 @@ int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc) + } + EXPORT_SYMBOL(radeonfb_resize); + +-static struct drm_mode_set panic_mode; +- +-int radeonfb_panic(struct notifier_block *n, unsigned long ununsed, +- void *panic_str) +-{ +- DRM_ERROR("panic occurred, switching back to text console\n"); +- drm_crtc_helper_set_config(&panic_mode); +- return 0; +-} +-EXPORT_SYMBOL(radeonfb_panic); +- +-static struct notifier_block paniced = { +- .notifier_call = radeonfb_panic, +-}; +- + static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) + { + int aligned = width; +@@ -495,11 +121,17 @@ static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bo + return aligned; + } + +-int radeonfb_create(struct radeon_device *rdev, ++static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { ++ .gamma_set = radeon_crtc_fb_gamma_set, ++}; ++ ++int radeonfb_create(struct drm_device *dev, + uint32_t fb_width, uint32_t fb_height, + uint32_t surface_width, uint32_t surface_height, +- struct radeon_framebuffer **rfb_p) ++ uint32_t surface_depth, uint32_t surface_bpp, ++ struct drm_framebuffer **fb_p) + { ++ struct radeon_device *rdev = dev->dev_private; + struct fb_info *info; + struct radeon_fb_device *rfbdev; + struct drm_framebuffer *fb = NULL; +@@ -513,13 +145,14 @@ int radeonfb_create(struct radeon_device *rdev, + void *fbptr = NULL; + unsigned long tmp; + bool fb_tiled = false; /* useful for testing */ ++ u32 tiling_flags = 0; + + mode_cmd.width = surface_width; + mode_cmd.height = surface_height; +- mode_cmd.bpp = 32; ++ mode_cmd.bpp = surface_bpp; + /* need to align pitch with crtc limits */ + mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8); +- mode_cmd.depth = 24; ++ mode_cmd.depth = surface_depth; + + size = mode_cmd.pitch * mode_cmd.height; + aligned_size = ALIGN(size, PAGE_SIZE); +@@ -537,7 +170,22 @@ int radeonfb_create(struct radeon_device *rdev, + robj = gobj->driver_private; + + if (fb_tiled) +- radeon_object_set_tiling_flags(robj, RADEON_TILING_MACRO|RADEON_TILING_SURFACE, mode_cmd.pitch); ++ tiling_flags = RADEON_TILING_MACRO; ++ ++#ifdef __BIG_ENDIAN ++ switch (mode_cmd.bpp) { ++ case 32: ++ tiling_flags |= RADEON_TILING_SWAP_32BIT; ++ break; ++ case 16: ++ tiling_flags |= RADEON_TILING_SWAP_16BIT; ++ default: ++ break; ++ } ++#endif ++ ++ if (tiling_flags) ++ radeon_object_set_tiling_flags(robj, tiling_flags | RADEON_TILING_SURFACE, mode_cmd.pitch); + mutex_lock(&rdev->ddev->struct_mutex); + fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj); + if (fb == NULL) { +@@ -554,8 +202,8 @@ int radeonfb_create(struct radeon_device *rdev, + + list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list); + ++ *fb_p = fb; + rfb = to_radeon_framebuffer(fb); +- *rfb_p = rfb; + rdev->fbdev_rfb = rfb; + rdev->fbdev_robj = robj; + +@@ -564,7 +212,15 @@ int radeonfb_create(struct radeon_device *rdev, + ret = -ENOMEM; + goto out_unref; + } ++ ++ rdev->fbdev_info = info; + rfbdev = info->par; ++ rfbdev->helper.funcs = &radeon_fb_helper_funcs; ++ rfbdev->helper.dev = dev; ++ ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2, ++ RADEONFB_CONN_LIMIT); ++ if (ret) ++ goto out_unref; + + if (fb_tiled) + radeon_object_check_tiling(robj, 0, 0); +@@ -577,33 +233,19 @@ int radeonfb_create(struct radeon_device *rdev, + memset_io(fbptr, 0, aligned_size); + + strcpy(info->fix.id, "radeondrmfb"); +- info->fix.type = FB_TYPE_PACKED_PIXELS; +- info->fix.visual = FB_VISUAL_TRUECOLOR; +- info->fix.type_aux = 0; +- info->fix.xpanstep = 1; /* doing it in hw */ +- info->fix.ypanstep = 1; /* doing it in hw */ +- info->fix.ywrapstep = 0; +- info->fix.accel = FB_ACCEL_NONE; +- info->fix.type_aux = 0; ++ ++ drm_fb_helper_fill_fix(info, fb->pitch); ++ + info->flags = FBINFO_DEFAULT; + info->fbops = &radeonfb_ops; +- info->fix.line_length = fb->pitch; ++ + tmp = fb_gpuaddr - rdev->mc.vram_location; + info->fix.smem_start = rdev->mc.aper_base + tmp; + info->fix.smem_len = size; + info->screen_base = fbptr; + info->screen_size = size; +- info->pseudo_palette = fb->pseudo_palette; +- info->var.xres_virtual = fb->width; +- info->var.yres_virtual = fb->height; +- info->var.bits_per_pixel = fb->bits_per_pixel; +- info->var.xoffset = 0; +- info->var.yoffset = 0; +- info->var.activate = FB_ACTIVATE_NOW; +- info->var.height = -1; +- info->var.width = -1; +- info->var.xres = fb_width; +- info->var.yres = fb_height; ++ ++ drm_fb_helper_fill_var(info, fb, fb_width, fb_height); + + /* setup aperture base/size for vesafb takeover */ + info->aperture_base = rdev->ddev->mode_config.fb_base; +@@ -626,83 +268,6 @@ int radeonfb_create(struct radeon_device *rdev, + DRM_INFO("fb depth is %d\n", fb->depth); + DRM_INFO(" pitch is %d\n", fb->pitch); + +- switch (fb->depth) { +- case 8: +- info->var.red.offset = 0; +- info->var.green.offset = 0; +- info->var.blue.offset = 0; +- info->var.red.length = 8; /* 8bit DAC */ +- info->var.green.length = 8; +- info->var.blue.length = 8; +- info->var.transp.offset = 0; +- info->var.transp.length = 0; +- break; +-#ifdef __LITTLE_ENDIAN +- case 15: +- info->var.red.offset = 10; +- info->var.green.offset = 5; +- info->var.blue.offset = 0; +- info->var.red.length = 5; +- info->var.green.length = 5; +- info->var.blue.length = 5; +- info->var.transp.offset = 15; +- info->var.transp.length = 1; +- break; +- case 16: +- info->var.red.offset = 11; +- info->var.green.offset = 5; +- info->var.blue.offset = 0; +- info->var.red.length = 5; +- info->var.green.length = 6; +- info->var.blue.length = 5; +- info->var.transp.offset = 0; +- break; +- case 24: +- info->var.red.offset = 16; +- info->var.green.offset = 8; +- info->var.blue.offset = 0; +- info->var.red.length = 8; +- info->var.green.length = 8; +- info->var.blue.length = 8; +- info->var.transp.offset = 0; +- info->var.transp.length = 0; +- break; +- case 32: +- info->var.red.offset = 16; +- info->var.green.offset = 8; +- info->var.blue.offset = 0; +- info->var.red.length = 8; +- info->var.green.length = 8; +- info->var.blue.length = 8; +- info->var.transp.offset = 24; +- info->var.transp.length = 8; +- break; +-#else +- case 24: +- info->var.red.offset = 8; +- info->var.green.offset = 16; +- info->var.blue.offset = 24; +- info->var.red.length = 8; +- info->var.green.length = 8; +- info->var.blue.length = 8; +- info->var.transp.offset = 0; +- info->var.transp.length = 0; +- break; +- case 32: +- info->var.red.offset = 8; +- info->var.green.offset = 16; +- info->var.blue.offset = 24; +- info->var.red.length = 8; +- info->var.green.length = 8; +- info->var.blue.length = 8; +- info->var.transp.offset = 0; +- info->var.transp.length = 8; +- break; +- default: +-#endif +- break; +- } +- + fb->fbdev = info; + rfbdev->rfb = rfb; + rfbdev->rdev = rdev; +@@ -726,148 +291,26 @@ out: + return ret; + } + +-static int radeonfb_single_fb_probe(struct radeon_device *rdev) ++static char *mode_option; ++int radeon_parse_options(char *options) + { +- struct drm_crtc *crtc; +- struct drm_connector *connector; +- unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; +- unsigned int surface_width = 0, surface_height = 0; +- int new_fb = 0; +- int crtc_count = 0; +- int ret, i, conn_count = 0; +- struct radeon_framebuffer *rfb; +- struct fb_info *info; +- struct radeon_fb_device *rfbdev; +- struct drm_mode_set *modeset = NULL; +- +- /* first up get a count of crtcs now in use and new min/maxes width/heights */ +- list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) { +- if (drm_helper_crtc_in_use(crtc)) { +- if (crtc->desired_mode) { +- if (crtc->desired_mode->hdisplay < fb_width) +- fb_width = crtc->desired_mode->hdisplay; +- +- if (crtc->desired_mode->vdisplay < fb_height) +- fb_height = crtc->desired_mode->vdisplay; +- +- if (crtc->desired_mode->hdisplay > surface_width) +- surface_width = crtc->desired_mode->hdisplay; +- +- if (crtc->desired_mode->vdisplay > surface_height) +- surface_height = crtc->desired_mode->vdisplay; +- } +- crtc_count++; +- } +- } ++ char *this_opt; + +- if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { +- /* hmm everyone went away - assume VGA cable just fell out +- and will come back later. */ ++ if (!options || !*options) + return 0; +- } +- +- /* do we have an fb already? */ +- if (list_empty(&rdev->ddev->mode_config.fb_kernel_list)) { +- /* create an fb if we don't have one */ +- ret = radeonfb_create(rdev, fb_width, fb_height, surface_width, surface_height, &rfb); +- if (ret) { +- return -EINVAL; +- } +- new_fb = 1; +- } else { +- struct drm_framebuffer *fb; +- fb = list_first_entry(&rdev->ddev->mode_config.fb_kernel_list, struct drm_framebuffer, filp_head); +- rfb = to_radeon_framebuffer(fb); +- +- /* if someone hotplugs something bigger than we have already allocated, we are pwned. +- As really we can't resize an fbdev that is in the wild currently due to fbdev +- not really being designed for the lower layers moving stuff around under it. +- - so in the grand style of things - punt. */ +- if ((fb->width < surface_width) || (fb->height < surface_height)) { +- DRM_ERROR("Framebuffer not large enough to scale console onto.\n"); +- return -EINVAL; +- } +- } +- +- info = rfb->base.fbdev; +- rdev->fbdev_info = info; +- rfbdev = info->par; + +- crtc_count = 0; +- /* okay we need to setup new connector sets in the crtcs */ +- list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) { +- struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); +- modeset = &radeon_crtc->mode_set; +- modeset->fb = &rfb->base; +- conn_count = 0; +- list_for_each_entry(connector, &rdev->ddev->mode_config.connector_list, head) { +- if (connector->encoder) +- if (connector->encoder->crtc == modeset->crtc) { +- modeset->connectors[conn_count] = connector; +- conn_count++; +- if (conn_count > RADEONFB_CONN_LIMIT) +- BUG(); +- } +- } +- +- for (i = conn_count; i < RADEONFB_CONN_LIMIT; i++) +- modeset->connectors[i] = NULL; +- +- +- rfbdev->crtc_ids[crtc_count++] = crtc->base.id; +- +- modeset->num_connectors = conn_count; +- if (modeset->crtc->desired_mode) { +- if (modeset->mode) { +- drm_mode_destroy(rdev->ddev, modeset->mode); +- } +- modeset->mode = drm_mode_duplicate(rdev->ddev, +- modeset->crtc->desired_mode); +- } +- } +- rfbdev->crtc_count = crtc_count; +- +- if (new_fb) { +- info->var.pixclock = -1; +- if (register_framebuffer(info) < 0) +- return -EINVAL; +- } else { +- radeonfb_set_par(info); ++ while ((this_opt = strsep(&options, ",")) != NULL) { ++ if (!*this_opt) ++ continue; ++ mode_option = this_opt; + } +- printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, +- info->fix.id); +- +- /* Switch back to kernel console on panic */ +- panic_mode = *modeset; +- atomic_notifier_chain_register(&panic_notifier_list, &paniced); +- printk(KERN_INFO "registered panic notifier\n"); +- + return 0; + } + + int radeonfb_probe(struct drm_device *dev) + { +- int ret; +- +- /* something has changed in the lower levels of hell - deal with it +- here */ +- +- /* two modes : a) 1 fb to rule all crtcs. +- b) one fb per crtc. +- two actions 1) new connected device +- 2) device removed. +- case a/1 : if the fb surface isn't big enough - resize the surface fb. +- if the fb size isn't big enough - resize fb into surface. +- if everything big enough configure the new crtc/etc. +- case a/2 : undo the configuration +- possibly resize down the fb to fit the new configuration. +- case b/1 : see if it is on a new crtc - setup a new fb and add it. +- case b/2 : teardown the new fb. +- */ +- ret = radeonfb_single_fb_probe(dev->dev_private); +- return ret; ++ return drm_fb_helper_single_fb_probe(dev, &radeonfb_create); + } +-EXPORT_SYMBOL(radeonfb_probe); + + int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) + { +@@ -880,16 +323,17 @@ int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) + } + info = fb->fbdev; + if (info) { ++ struct radeon_fb_device *rfbdev = info->par; + robj = rfb->obj->driver_private; + unregister_framebuffer(info); + radeon_object_kunmap(robj); + radeon_object_unpin(robj); ++ drm_fb_helper_free(&rfbdev->helper); + framebuffer_release(info); + } + + printk(KERN_INFO "unregistered panic notifier\n"); +- atomic_notifier_chain_unregister(&panic_notifier_list, &paniced); +- memset(&panic_mode, 0, sizeof(struct drm_mode_set)); ++ + return 0; + } + EXPORT_SYMBOL(radeonfb_remove); +diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c +index b4e48dd..3beb26d 100644 +--- a/drivers/gpu/drm/radeon/radeon_fence.c ++++ b/drivers/gpu/drm/radeon/radeon_fence.c +@@ -53,9 +53,9 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) + * away + */ + WREG32(rdev->fence_drv.scratch_reg, fence->seq); +- } else { ++ } else + radeon_fence_ring_emit(rdev, fence); +- } ++ + fence->emited = true; + fence->timeout = jiffies + ((2000 * HZ) / 1000); + list_del(&fence->list); +@@ -168,7 +168,38 @@ bool radeon_fence_signaled(struct radeon_fence *fence) + return signaled; + } + +-int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) ++int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy) ++{ ++ struct radeon_device *rdev; ++ int ret = 0; ++ ++ rdev = fence->rdev; ++ ++ __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); ++ ++ while (1) { ++ if (radeon_fence_signaled(fence)) ++ break; ++ ++ if (time_after_eq(jiffies, fence->timeout)) { ++ ret = -EBUSY; ++ break; ++ } ++ ++ if (lazy) ++ schedule_timeout(1); ++ ++ if (intr && signal_pending(current)) { ++ ret = -ERESTARTSYS; ++ break; ++ } ++ } ++ __set_current_state(TASK_RUNNING); ++ return ret; ++} ++ ++ ++int radeon_fence_wait(struct radeon_fence *fence, bool intr) + { + struct radeon_device *rdev; + unsigned long cur_jiffies; +@@ -176,7 +207,6 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) + bool expired = false; + int r; + +- + if (fence == NULL) { + WARN(1, "Querying an invalid fence : %p !\n", fence); + return 0; +@@ -185,13 +215,22 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) + if (radeon_fence_signaled(fence)) { + return 0; + } ++ ++ if (rdev->family >= CHIP_R600) { ++ r = r600_fence_wait(fence, intr, 0); ++ if (r == -ERESTARTSYS) ++ return -EBUSY; ++ return r; ++ } ++ + retry: + cur_jiffies = jiffies; + timeout = HZ / 100; + if (time_after(fence->timeout, cur_jiffies)) { + timeout = fence->timeout - cur_jiffies; + } +- if (interruptible) { ++ ++ if (intr) { + r = wait_event_interruptible_timeout(rdev->fence_drv.queue, + radeon_fence_signaled(fence), timeout); + if (unlikely(r == -ERESTARTSYS)) { +diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c +index 2977539..a931af0 100644 +--- a/drivers/gpu/drm/radeon/radeon_gart.c ++++ b/drivers/gpu/drm/radeon/radeon_gart.c +@@ -75,7 +75,6 @@ void radeon_gart_table_ram_free(struct radeon_device *rdev) + + int radeon_gart_table_vram_alloc(struct radeon_device *rdev) + { +- uint64_t gpu_addr; + int r; + + if (rdev->gart.table.vram.robj == NULL) { +@@ -88,6 +87,14 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev) + return r; + } + } ++ return 0; ++} ++ ++int radeon_gart_table_vram_pin(struct radeon_device *rdev) ++{ ++ uint64_t gpu_addr; ++ int r; ++ + r = radeon_object_pin(rdev->gart.table.vram.robj, + RADEON_GEM_DOMAIN_VRAM, &gpu_addr); + if (r) { +diff --git a/drivers/gpu/drm/radeon/radeon_ioc32.c b/drivers/gpu/drm/radeon/radeon_ioc32.c +index 56decda..a1bf11d 100644 +--- a/drivers/gpu/drm/radeon/radeon_ioc32.c ++++ b/drivers/gpu/drm/radeon/radeon_ioc32.c +@@ -422,3 +422,18 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) + + return ret; + } ++ ++long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ unsigned int nr = DRM_IOCTL_NR(cmd); ++ int ret; ++ ++ if (nr < DRM_COMMAND_BASE) ++ return drm_compat_ioctl(filp, cmd, arg); ++ ++ lock_kernel(); /* XXX for now */ ++ ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); ++ unlock_kernel(); ++ ++ return ret; ++} +diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c +index 9836c70..b79ecc4 100644 +--- a/drivers/gpu/drm/radeon/radeon_irq.c ++++ b/drivers/gpu/drm/radeon/radeon_irq.c +@@ -188,6 +188,9 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) + u32 stat; + u32 r500_disp_int; + ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ return IRQ_NONE; ++ + /* Only consider the bits we're interested in - others could be used + * outside the DRM + */ +@@ -286,6 +289,9 @@ int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_pr + drm_radeon_irq_emit_t *emit = data; + int result; + ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ return -EINVAL; ++ + LOCK_TEST_WITH_RETURN(dev, file_priv); + + if (!dev_priv) { +@@ -315,6 +321,9 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr + return -EINVAL; + } + ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ return -EINVAL; ++ + return radeon_wait_irq(dev, irqwait->irq_seq); + } + +@@ -326,6 +335,9 @@ void radeon_driver_irq_preinstall(struct drm_device * dev) + (drm_radeon_private_t *) dev->dev_private; + u32 dummy; + ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ return; ++ + /* Disable *all* interrupts */ + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) + RADEON_WRITE(R500_DxMODE_INT_MASK, 0); +@@ -345,6 +357,9 @@ int radeon_driver_irq_postinstall(struct drm_device *dev) + + dev->max_vblank_count = 0x001fffff; + ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ return 0; ++ + radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); + + return 0; +@@ -357,6 +372,9 @@ void radeon_driver_irq_uninstall(struct drm_device * dev) + if (!dev_priv) + return; + ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ return; ++ + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) + RADEON_WRITE(R500_DxMODE_INT_MASK, 0); + /* Disable *all* interrupts */ +diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c +index 9805e4b..1841145 100644 +--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c ++++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c +@@ -28,7 +28,6 @@ + #include "drmP.h" + #include "radeon_drm.h" + #include "radeon_reg.h" +-#include "radeon_microcode.h" + #include "radeon.h" + #include "atom.h" + +diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c +index dce09ad..ba12862 100644 +--- a/drivers/gpu/drm/radeon/radeon_kms.c ++++ b/drivers/gpu/drm/radeon/radeon_kms.c +@@ -54,12 +54,23 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) + flags |= RADEON_IS_PCI; + } + ++ /* radeon_device_init should report only fatal error ++ * like memory allocation failure or iomapping failure, ++ * or memory manager initialization failure, it must ++ * properly initialize the GPU MC controller and permit ++ * VRAM allocation ++ */ + r = radeon_device_init(rdev, dev, dev->pdev, flags); + if (r) { +- DRM_ERROR("Failed to initialize radeon, disabling IOCTL\n"); +- radeon_device_fini(rdev); +- kfree(rdev); +- dev->dev_private = NULL; ++ DRM_ERROR("Fatal error while trying to initialize radeon.\n"); ++ return r; ++ } ++ /* Again modeset_init should fail only on fatal error ++ * otherwise it should provide enough functionalities ++ * for shadowfb to run ++ */ ++ r = radeon_modeset_init(rdev); ++ if (r) { + return r; + } + return 0; +@@ -69,6 +80,9 @@ int radeon_driver_unload_kms(struct drm_device *dev) + { + struct radeon_device *rdev = dev->dev_private; + ++ if (rdev == NULL) ++ return 0; ++ radeon_modeset_fini(rdev); + radeon_device_fini(rdev); + kfree(rdev); + dev->dev_private = NULL; +@@ -98,6 +112,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + case RADEON_INFO_NUM_Z_PIPES: + value = rdev->num_z_pipes; + break; ++ case RADEON_INFO_ACCEL_WORKING: ++ value = rdev->accel_working; ++ break; + default: + DRM_DEBUG("Invalid request %d\n", info->request); + return -EINVAL; +@@ -184,55 +201,6 @@ void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) + + + /* +- * For multiple master (like multiple X). +- */ +-struct drm_radeon_master_private { +- drm_local_map_t *sarea; +- drm_radeon_sarea_t *sarea_priv; +-}; +- +-int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master) +-{ +- struct drm_radeon_master_private *master_priv; +- unsigned long sareapage; +- int ret; +- +- master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); +- if (master_priv == NULL) { +- return -ENOMEM; +- } +- /* prebuild the SAREA */ +- sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE); +- ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, +- _DRM_CONTAINS_LOCK, +- &master_priv->sarea); +- if (ret) { +- DRM_ERROR("SAREA setup failed\n"); +- return ret; +- } +- master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea); +- master_priv->sarea_priv->pfCurrentPage = 0; +- master->driver_priv = master_priv; +- return 0; +-} +- +-void radeon_master_destroy_kms(struct drm_device *dev, +- struct drm_master *master) +-{ +- struct drm_radeon_master_private *master_priv = master->driver_priv; +- +- if (master_priv == NULL) { +- return; +- } +- if (master_priv->sarea) { +- drm_rmmap_locked(dev, master_priv->sarea); +- } +- kfree(master_priv); +- master->driver_priv = NULL; +-} +- +- +-/* + * IOCTL. + */ + int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, +diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +index 0da72f1..2b997a1 100644 +--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c ++++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +@@ -28,6 +28,7 @@ + #include <drm/radeon_drm.h> + #include "radeon_fixed.h" + #include "radeon.h" ++#include "atom.h" + + static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, +@@ -340,6 +341,9 @@ void radeon_legacy_atom_set_surface(struct drm_crtc *crtc) + uint32_t crtc_pitch; + + switch (crtc->fb->bits_per_pixel) { ++ case 8: ++ format = 2; ++ break; + case 15: /* 555 */ + format = 3; + break; +@@ -400,11 +404,33 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, + uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; + uint32_t crtc_pitch, pitch_pixels; + uint32_t tiling_flags; ++ int format; ++ uint32_t gen_cntl_reg, gen_cntl_val; + + DRM_DEBUG("\n"); + + radeon_fb = to_radeon_framebuffer(crtc->fb); + ++ switch (crtc->fb->bits_per_pixel) { ++ case 8: ++ format = 2; ++ break; ++ case 15: /* 555 */ ++ format = 3; ++ break; ++ case 16: /* 565 */ ++ format = 4; ++ break; ++ case 24: /* RGB */ ++ format = 5; ++ break; ++ case 32: /* xRGB */ ++ format = 6; ++ break; ++ default: ++ return false; ++ } ++ + obj = radeon_fb->obj; + if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { + return -EINVAL; +@@ -457,6 +483,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, + } else { + int offset = y * pitch_pixels + x; + switch (crtc->fb->bits_per_pixel) { ++ case 8: ++ offset *= 1; ++ break; + case 15: + case 16: + offset *= 2; +@@ -475,6 +504,16 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, + + base &= ~7; + ++ if (radeon_crtc->crtc_id == 1) ++ gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; ++ else ++ gen_cntl_reg = RADEON_CRTC_GEN_CNTL; ++ ++ gen_cntl_val = RREG32(gen_cntl_reg); ++ gen_cntl_val &= ~(0xf << 8); ++ gen_cntl_val |= (format << 8); ++ WREG32(gen_cntl_reg, gen_cntl_val); ++ + crtc_offset = (u32)base; + + WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); +@@ -501,6 +540,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod + struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ++ struct drm_encoder *encoder; + int format; + int hsync_start; + int hsync_wid; +@@ -509,10 +549,24 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod + uint32_t crtc_h_sync_strt_wid; + uint32_t crtc_v_total_disp; + uint32_t crtc_v_sync_strt_wid; ++ bool is_tv = false; + + DRM_DEBUG("\n"); ++ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { ++ if (encoder->crtc == crtc) { ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { ++ is_tv = true; ++ DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); ++ break; ++ } ++ } ++ } + + switch (crtc->fb->bits_per_pixel) { ++ case 8: ++ format = 2; ++ break; + case 15: /* 555 */ + format = 3; + break; +@@ -642,6 +696,11 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod + WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); + } + ++ if (is_tv) ++ radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, ++ &crtc_h_sync_strt_wid, &crtc_v_total_disp, ++ &crtc_v_sync_strt_wid); ++ + WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); + WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); + WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); +@@ -668,7 +727,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + uint32_t pll_ref_div = 0; + uint32_t pll_fb_post_div = 0; + uint32_t htotal_cntl = 0; +- ++ bool is_tv = false; + struct radeon_pll *pll; + + struct { +@@ -703,6 +762,13 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ ++ if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { ++ is_tv = true; ++ break; ++ } ++ + if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) + pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; + if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { +@@ -766,6 +832,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | + RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); + ++ if (is_tv) { ++ radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, ++ &pll_ref_div, &pll_fb_post_div, ++ &pixclks_cntl); ++ } ++ + WREG32_PLL_P(RADEON_PIXCLKS_CNTL, + RADEON_PIX2CLK_SRC_SEL_CPUCLK, + ~(RADEON_PIX2CLK_SRC_SEL_MASK)); +@@ -820,6 +892,15 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + + WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); + } else { ++ uint32_t pixclks_cntl; ++ ++ ++ if (is_tv) { ++ pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); ++ radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, ++ &pll_fb_post_div, &pixclks_cntl); ++ } ++ + if (rdev->flags & RADEON_IS_MOBILITY) { + /* A temporal workaround for the occational blanking on certain laptop panels. + This appears to related to the PLL divider registers (fail to lock?). +@@ -914,6 +995,8 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + RADEON_VCLK_SRC_SEL_PPLLCLK, + ~(RADEON_VCLK_SRC_SEL_MASK)); + ++ if (is_tv) ++ WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); + } + } + +diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +index 9322675..b1547f7 100644 +--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c ++++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +@@ -29,6 +29,15 @@ + #include "radeon.h" + #include "atom.h" + ++static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) ++{ ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct drm_encoder_helper_funcs *encoder_funcs; ++ ++ encoder_funcs = encoder->helper_private; ++ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); ++ radeon_encoder->active_device = 0; ++} + + static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) + { +@@ -98,6 +107,8 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) + else + radeon_combios_output_lock(encoder, true); + radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); ++ ++ radeon_encoder_set_active_device(encoder); + } + + static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) +@@ -195,6 +206,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { + .prepare = radeon_legacy_lvds_prepare, + .mode_set = radeon_legacy_lvds_mode_set, + .commit = radeon_legacy_lvds_commit, ++ .disable = radeon_legacy_encoder_disable, + }; + + +@@ -260,6 +272,7 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) + else + radeon_combios_output_lock(encoder, true); + radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); ++ radeon_encoder_set_active_device(encoder); + } + + static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) +@@ -402,6 +415,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_fu + .mode_set = radeon_legacy_primary_dac_mode_set, + .commit = radeon_legacy_primary_dac_commit, + .detect = radeon_legacy_primary_dac_detect, ++ .disable = radeon_legacy_encoder_disable, + }; + + +@@ -454,6 +468,7 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) + else + radeon_combios_output_lock(encoder, true); + radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); ++ radeon_encoder_set_active_device(encoder); + } + + static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) +@@ -566,6 +581,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs + .prepare = radeon_legacy_tmds_int_prepare, + .mode_set = radeon_legacy_tmds_int_mode_set, + .commit = radeon_legacy_tmds_int_commit, ++ .disable = radeon_legacy_encoder_disable, + }; + + +@@ -620,6 +636,7 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) + else + radeon_combios_output_lock(encoder, true); + radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); ++ radeon_encoder_set_active_device(encoder); + } + + static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) +@@ -706,6 +723,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs + .prepare = radeon_legacy_tmds_ext_prepare, + .mode_set = radeon_legacy_tmds_ext_mode_set, + .commit = radeon_legacy_tmds_ext_commit, ++ .disable = radeon_legacy_encoder_disable, + }; + + +@@ -727,17 +745,21 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) + { + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; +- /* uint32_t tv_master_cntl = 0; */ +- ++ uint32_t tv_master_cntl = 0; ++ bool is_tv; + DRM_DEBUG("\n"); + ++ is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; ++ + if (rdev->family == CHIP_R200) + fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); + else { +- crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); +- /* FIXME TV */ +- /* tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); */ ++ if (is_tv) ++ tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); ++ else ++ crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); + tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); + } + +@@ -746,20 +768,23 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) + if (rdev->family == CHIP_R200) { + fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); + } else { +- crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; +- /* tv_master_cntl |= RADEON_TV_ON; */ ++ if (is_tv) ++ tv_master_cntl |= RADEON_TV_ON; ++ else ++ crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; ++ + if (rdev->family == CHIP_R420 || +- rdev->family == CHIP_R423 || +- rdev->family == CHIP_RV410) ++ rdev->family == CHIP_R423 || ++ rdev->family == CHIP_RV410) + tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | +- R420_TV_DAC_GDACPD | +- R420_TV_DAC_BDACPD | +- RADEON_TV_DAC_BGSLEEP); ++ R420_TV_DAC_GDACPD | ++ R420_TV_DAC_BDACPD | ++ RADEON_TV_DAC_BGSLEEP); + else + tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | +- RADEON_TV_DAC_GDACPD | +- RADEON_TV_DAC_BDACPD | +- RADEON_TV_DAC_BGSLEEP); ++ RADEON_TV_DAC_GDACPD | ++ RADEON_TV_DAC_BDACPD | ++ RADEON_TV_DAC_BGSLEEP); + } + break; + case DRM_MODE_DPMS_STANDBY: +@@ -768,8 +793,11 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) + if (rdev->family == CHIP_R200) + fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); + else { +- crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; +- /* tv_master_cntl &= ~RADEON_TV_ON; */ ++ if (is_tv) ++ tv_master_cntl &= ~RADEON_TV_ON; ++ else ++ crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; ++ + if (rdev->family == CHIP_R420 || + rdev->family == CHIP_R423 || + rdev->family == CHIP_RV410) +@@ -789,8 +817,10 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) + if (rdev->family == CHIP_R200) { + WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); + } else { +- WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); +- /* WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); */ ++ if (is_tv) ++ WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); ++ else ++ WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); + } + +@@ -809,6 +839,7 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) + else + radeon_combios_output_lock(encoder, true); + radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); ++ radeon_encoder_set_active_device(encoder); + } + + static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) +@@ -831,11 +862,15 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, + struct radeon_device *rdev = dev->dev_private; + struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; +- uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0; ++ uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; ++ bool is_tv = false; + + DRM_DEBUG("\n"); + ++ is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; ++ + if (rdev->family != CHIP_R200) { + tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); + if (rdev->family == CHIP_R420 || +@@ -858,7 +893,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, + } + + /* FIXME TV */ +- if (radeon_encoder->enc_priv) { ++ if (tv_dac) { + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | + RADEON_TV_DAC_NHOLD | +@@ -875,44 +910,93 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, + if (ASIC_IS_R300(rdev)) { + gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; + disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); +- } else if (rdev->family == CHIP_R200) +- fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); ++ } ++ ++ if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) ++ disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); + else + disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); + +- dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; ++ if (rdev->family == CHIP_R200) ++ fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); + +- if (radeon_crtc->crtc_id == 0) { +- if (ASIC_IS_R300(rdev)) { +- disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; +- disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; +- } else if (rdev->family == CHIP_R200) { +- fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | +- RADEON_FP2_DVO_RATE_SEL_SDR); +- } else +- disp_hw_debug |= RADEON_CRT2_DISP1_SEL; ++ if (is_tv) { ++ uint32_t dac_cntl; ++ ++ dac_cntl = RREG32(RADEON_DAC_CNTL); ++ dac_cntl &= ~RADEON_DAC_TVO_EN; ++ WREG32(RADEON_DAC_CNTL, dac_cntl); ++ ++ if (ASIC_IS_R300(rdev)) ++ gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; ++ ++ dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; ++ if (radeon_crtc->crtc_id == 0) { ++ if (ASIC_IS_R300(rdev)) { ++ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; ++ disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | ++ RADEON_DISP_TV_SOURCE_CRTC); ++ } ++ if (rdev->family >= CHIP_R200) { ++ disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; ++ } else { ++ disp_hw_debug |= RADEON_CRT2_DISP1_SEL; ++ } ++ } else { ++ if (ASIC_IS_R300(rdev)) { ++ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; ++ disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; ++ } ++ if (rdev->family >= CHIP_R200) { ++ disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; ++ } else { ++ disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; ++ } ++ } ++ WREG32(RADEON_DAC_CNTL2, dac2_cntl); + } else { +- if (ASIC_IS_R300(rdev)) { +- disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; +- disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; +- } else if (rdev->family == CHIP_R200) { +- fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | +- RADEON_FP2_DVO_RATE_SEL_SDR); +- fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; +- } else +- disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; +- } + +- WREG32(RADEON_DAC_CNTL2, dac2_cntl); ++ dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; ++ ++ if (radeon_crtc->crtc_id == 0) { ++ if (ASIC_IS_R300(rdev)) { ++ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; ++ disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; ++ } else if (rdev->family == CHIP_R200) { ++ fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | ++ RADEON_FP2_DVO_RATE_SEL_SDR); ++ } else ++ disp_hw_debug |= RADEON_CRT2_DISP1_SEL; ++ } else { ++ if (ASIC_IS_R300(rdev)) { ++ disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; ++ disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; ++ } else if (rdev->family == CHIP_R200) { ++ fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | ++ RADEON_FP2_DVO_RATE_SEL_SDR); ++ fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; ++ } else ++ disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; ++ } ++ WREG32(RADEON_DAC_CNTL2, dac2_cntl); ++ } + + if (ASIC_IS_R300(rdev)) { + WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); +- WREG32(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl); +- } else if (rdev->family == CHIP_R200) +- WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); ++ WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); ++ } ++ ++ if (rdev->family >= CHIP_R200) ++ WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); + else + WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); + ++ if (rdev->family == CHIP_R200) ++ WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); ++ ++ if (is_tv) ++ radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); ++ + if (rdev->is_atom_bios) + radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); + else +@@ -920,6 +1004,141 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, + + } + ++static bool r300_legacy_tv_detect(struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct drm_device *dev = encoder->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; ++ uint32_t disp_output_cntl, gpiopad_a, tmp; ++ bool found = false; ++ ++ /* save regs needed */ ++ gpiopad_a = RREG32(RADEON_GPIOPAD_A); ++ dac_cntl2 = RREG32(RADEON_DAC_CNTL2); ++ crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); ++ dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); ++ tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); ++ disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); ++ ++ WREG32_P(RADEON_GPIOPAD_A, 0, ~1); ++ ++ WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); ++ ++ WREG32(RADEON_CRTC2_GEN_CNTL, ++ RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); ++ ++ tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; ++ tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; ++ WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); ++ ++ WREG32(RADEON_DAC_EXT_CNTL, ++ RADEON_DAC2_FORCE_BLANK_OFF_EN | ++ RADEON_DAC2_FORCE_DATA_EN | ++ RADEON_DAC_FORCE_DATA_SEL_RGB | ++ (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); ++ ++ WREG32(RADEON_TV_DAC_CNTL, ++ RADEON_TV_DAC_STD_NTSC | ++ (8 << RADEON_TV_DAC_BGADJ_SHIFT) | ++ (6 << RADEON_TV_DAC_DACADJ_SHIFT)); ++ ++ RREG32(RADEON_TV_DAC_CNTL); ++ mdelay(4); ++ ++ WREG32(RADEON_TV_DAC_CNTL, ++ RADEON_TV_DAC_NBLANK | ++ RADEON_TV_DAC_NHOLD | ++ RADEON_TV_MONITOR_DETECT_EN | ++ RADEON_TV_DAC_STD_NTSC | ++ (8 << RADEON_TV_DAC_BGADJ_SHIFT) | ++ (6 << RADEON_TV_DAC_DACADJ_SHIFT)); ++ ++ RREG32(RADEON_TV_DAC_CNTL); ++ mdelay(6); ++ ++ tmp = RREG32(RADEON_TV_DAC_CNTL); ++ if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { ++ found = true; ++ DRM_DEBUG("S-video TV connection detected\n"); ++ } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { ++ found = true; ++ DRM_DEBUG("Composite TV connection detected\n"); ++ } ++ ++ WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); ++ WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); ++ WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); ++ WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); ++ WREG32(RADEON_DAC_CNTL2, dac_cntl2); ++ WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); ++ return found; ++} ++ ++static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct drm_device *dev = encoder->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ uint32_t tv_dac_cntl, dac_cntl2; ++ uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; ++ bool found = false; ++ ++ if (ASIC_IS_R300(rdev)) ++ return r300_legacy_tv_detect(encoder, connector); ++ ++ dac_cntl2 = RREG32(RADEON_DAC_CNTL2); ++ tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); ++ tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); ++ config_cntl = RREG32(RADEON_CONFIG_CNTL); ++ tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); ++ ++ tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; ++ WREG32(RADEON_DAC_CNTL2, tmp); ++ ++ tmp = tv_master_cntl | RADEON_TV_ON; ++ tmp &= ~(RADEON_TV_ASYNC_RST | ++ RADEON_RESTART_PHASE_FIX | ++ RADEON_CRT_FIFO_CE_EN | ++ RADEON_TV_FIFO_CE_EN | ++ RADEON_RE_SYNC_NOW_SEL_MASK); ++ tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; ++ WREG32(RADEON_TV_MASTER_CNTL, tmp); ++ ++ tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | ++ RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | ++ (8 << RADEON_TV_DAC_BGADJ_SHIFT); ++ ++ if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) ++ tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); ++ else ++ tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); ++ WREG32(RADEON_TV_DAC_CNTL, tmp); ++ ++ tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | ++ RADEON_RED_MX_FORCE_DAC_DATA | ++ RADEON_GRN_MX_FORCE_DAC_DATA | ++ RADEON_BLU_MX_FORCE_DAC_DATA | ++ (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); ++ WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); ++ ++ mdelay(3); ++ tmp = RREG32(RADEON_TV_DAC_CNTL); ++ if (tmp & RADEON_TV_DAC_GDACDET) { ++ found = true; ++ DRM_DEBUG("S-video TV connection detected\n"); ++ } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { ++ found = true; ++ DRM_DEBUG("Composite TV connection detected\n"); ++ } ++ ++ WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); ++ WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); ++ WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); ++ WREG32(RADEON_DAC_CNTL2, dac_cntl2); ++ return found; ++} ++ + static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, + struct drm_connector *connector) + { +@@ -928,9 +1147,29 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder + uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; + uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; + enum drm_connector_status found = connector_status_disconnected; ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + bool color = true; + +- /* FIXME tv */ ++ if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || ++ connector->connector_type == DRM_MODE_CONNECTOR_Composite || ++ connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { ++ bool tv_detect; ++ ++ if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) ++ return connector_status_disconnected; ++ ++ tv_detect = radeon_legacy_tv_detect(encoder, connector); ++ if (tv_detect && tv_dac) ++ found = connector_status_connected; ++ return found; ++ } ++ ++ /* don't probe if the encoder is being used for something else not CRT related */ ++ if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { ++ DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); ++ return connector_status_disconnected; ++ } + + /* save the regs we need */ + pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); +@@ -1013,8 +1252,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder + } + WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); + +- /* return found; */ +- return connector_status_disconnected; ++ return found; + + } + +@@ -1025,6 +1263,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = + .mode_set = radeon_legacy_tv_dac_mode_set, + .commit = radeon_legacy_tv_dac_commit, + .detect = radeon_legacy_tv_dac_detect, ++ .disable = radeon_legacy_encoder_disable, + }; + + +@@ -1032,6 +1271,30 @@ static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { + .destroy = radeon_enc_destroy, + }; + ++ ++static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) ++{ ++ struct drm_device *dev = encoder->base.dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct radeon_encoder_int_tmds *tmds = NULL; ++ bool ret; ++ ++ tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); ++ ++ if (!tmds) ++ return NULL; ++ ++ if (rdev->is_atom_bios) ++ ret = radeon_atombios_get_tmds_info(encoder, tmds); ++ else ++ ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); ++ ++ if (ret == false) ++ radeon_legacy_get_tmds_info_from_table(encoder, tmds); ++ ++ return tmds; ++} ++ + void + radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) + { +@@ -1078,10 +1341,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t + case ENCODER_OBJECT_ID_INTERNAL_TMDS1: + drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); + drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); +- if (rdev->is_atom_bios) +- radeon_encoder->enc_priv = radeon_atombios_get_tmds_info(radeon_encoder); +- else +- radeon_encoder->enc_priv = radeon_combios_get_tmds_info(radeon_encoder); ++ radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC1: + drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); +diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c +new file mode 100644 +index 0000000..3a12bb0 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c +@@ -0,0 +1,904 @@ ++#include "drmP.h" ++#include "drm_crtc_helper.h" ++#include "radeon.h" ++ ++/* ++ * Integrated TV out support based on the GATOS code by ++ * Federico Ulivi <fulivi@lycos.com> ++ */ ++ ++ ++/* ++ * Limits of h/v positions (hPos & vPos) ++ */ ++#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ ++#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ ++ ++/* ++ * Unit for hPos (in TV clock periods) ++ */ ++#define H_POS_UNIT 10 ++ ++/* ++ * Indexes in h. code timing table for horizontal line position adjustment ++ */ ++#define H_TABLE_POS1 6 ++#define H_TABLE_POS2 8 ++ ++/* ++ * Limits of hor. size (hSize) ++ */ ++#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ ++ ++/* tv standard constants */ ++#define NTSC_TV_CLOCK_T 233 ++#define NTSC_TV_VFTOTAL 1 ++#define NTSC_TV_LINES_PER_FRAME 525 ++#define NTSC_TV_ZERO_H_SIZE 479166 ++#define NTSC_TV_H_SIZE_UNIT 9478 ++ ++#define PAL_TV_CLOCK_T 188 ++#define PAL_TV_VFTOTAL 3 ++#define PAL_TV_LINES_PER_FRAME 625 ++#define PAL_TV_ZERO_H_SIZE 473200 ++#define PAL_TV_H_SIZE_UNIT 9360 ++ ++/* tv pll setting for 27 mhz ref clk */ ++#define NTSC_TV_PLL_M_27 22 ++#define NTSC_TV_PLL_N_27 175 ++#define NTSC_TV_PLL_P_27 5 ++ ++#define PAL_TV_PLL_M_27 113 ++#define PAL_TV_PLL_N_27 668 ++#define PAL_TV_PLL_P_27 3 ++ ++/* tv pll setting for 14 mhz ref clk */ ++#define NTSC_TV_PLL_M_14 33 ++#define NTSC_TV_PLL_N_14 693 ++#define NTSC_TV_PLL_P_14 7 ++ ++#define VERT_LEAD_IN_LINES 2 ++#define FRAC_BITS 0xe ++#define FRAC_MASK 0x3fff ++ ++struct radeon_tv_mode_constants { ++ uint16_t hor_resolution; ++ uint16_t ver_resolution; ++ enum radeon_tv_std standard; ++ uint16_t hor_total; ++ uint16_t ver_total; ++ uint16_t hor_start; ++ uint16_t hor_syncstart; ++ uint16_t ver_syncstart; ++ unsigned def_restart; ++ uint16_t crtcPLL_N; ++ uint8_t crtcPLL_M; ++ uint8_t crtcPLL_post_div; ++ unsigned pix_to_tv; ++}; ++ ++static const uint16_t hor_timing_NTSC[] = { ++ 0x0007, ++ 0x003f, ++ 0x0263, ++ 0x0a24, ++ 0x2a6b, ++ 0x0a36, ++ 0x126d, /* H_TABLE_POS1 */ ++ 0x1bfe, ++ 0x1a8f, /* H_TABLE_POS2 */ ++ 0x1ec7, ++ 0x3863, ++ 0x1bfe, ++ 0x1bfe, ++ 0x1a2a, ++ 0x1e95, ++ 0x0e31, ++ 0x201b, ++ 0 ++}; ++ ++static const uint16_t vert_timing_NTSC[] = { ++ 0x2001, ++ 0x200d, ++ 0x1006, ++ 0x0c06, ++ 0x1006, ++ 0x1818, ++ 0x21e3, ++ 0x1006, ++ 0x0c06, ++ 0x1006, ++ 0x1817, ++ 0x21d4, ++ 0x0002, ++ 0 ++}; ++ ++static const uint16_t hor_timing_PAL[] = { ++ 0x0007, ++ 0x0058, ++ 0x027c, ++ 0x0a31, ++ 0x2a77, ++ 0x0a95, ++ 0x124f, /* H_TABLE_POS1 */ ++ 0x1bfe, ++ 0x1b22, /* H_TABLE_POS2 */ ++ 0x1ef9, ++ 0x387c, ++ 0x1bfe, ++ 0x1bfe, ++ 0x1b31, ++ 0x1eb5, ++ 0x0e43, ++ 0x201b, ++ 0 ++}; ++ ++static const uint16_t vert_timing_PAL[] = { ++ 0x2001, ++ 0x200c, ++ 0x1005, ++ 0x0c05, ++ 0x1005, ++ 0x1401, ++ 0x1821, ++ 0x2240, ++ 0x1005, ++ 0x0c05, ++ 0x1005, ++ 0x1401, ++ 0x1822, ++ 0x2230, ++ 0x0002, ++ 0 ++}; ++ ++/********************************************************************** ++ * ++ * availableModes ++ * ++ * Table of all allowed modes for tv output ++ * ++ **********************************************************************/ ++static const struct radeon_tv_mode_constants available_tv_modes[] = { ++ { /* NTSC timing for 27 Mhz ref clk */ ++ 800, /* horResolution */ ++ 600, /* verResolution */ ++ TV_STD_NTSC, /* standard */ ++ 990, /* horTotal */ ++ 740, /* verTotal */ ++ 813, /* horStart */ ++ 824, /* horSyncStart */ ++ 632, /* verSyncStart */ ++ 625592, /* defRestart */ ++ 592, /* crtcPLL_N */ ++ 91, /* crtcPLL_M */ ++ 4, /* crtcPLL_postDiv */ ++ 1022, /* pixToTV */ ++ }, ++ { /* PAL timing for 27 Mhz ref clk */ ++ 800, /* horResolution */ ++ 600, /* verResolution */ ++ TV_STD_PAL, /* standard */ ++ 1144, /* horTotal */ ++ 706, /* verTotal */ ++ 812, /* horStart */ ++ 824, /* horSyncStart */ ++ 669, /* verSyncStart */ ++ 696700, /* defRestart */ ++ 1382, /* crtcPLL_N */ ++ 231, /* crtcPLL_M */ ++ 4, /* crtcPLL_postDiv */ ++ 759, /* pixToTV */ ++ }, ++ { /* NTSC timing for 14 Mhz ref clk */ ++ 800, /* horResolution */ ++ 600, /* verResolution */ ++ TV_STD_NTSC, /* standard */ ++ 1018, /* horTotal */ ++ 727, /* verTotal */ ++ 813, /* horStart */ ++ 840, /* horSyncStart */ ++ 633, /* verSyncStart */ ++ 630627, /* defRestart */ ++ 347, /* crtcPLL_N */ ++ 14, /* crtcPLL_M */ ++ 8, /* crtcPLL_postDiv */ ++ 1022, /* pixToTV */ ++ }, ++}; ++ ++#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) ++ ++static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, ++ uint16_t *pll_ref_freq) ++{ ++ struct drm_device *dev = radeon_encoder->base.dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct radeon_crtc *radeon_crtc; ++ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; ++ const struct radeon_tv_mode_constants *const_ptr; ++ struct radeon_pll *pll; ++ ++ radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); ++ if (radeon_crtc->crtc_id == 1) ++ pll = &rdev->clock.p2pll; ++ else ++ pll = &rdev->clock.p1pll; ++ ++ if (pll_ref_freq) ++ *pll_ref_freq = pll->reference_freq; ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M) { ++ if (pll->reference_freq == 2700) ++ const_ptr = &available_tv_modes[0]; ++ else ++ const_ptr = &available_tv_modes[2]; ++ } else { ++ if (pll->reference_freq == 2700) ++ const_ptr = &available_tv_modes[1]; ++ else ++ const_ptr = &available_tv_modes[1]; /* FIX ME */ ++ } ++ return const_ptr; ++} ++ ++static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; ++static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; ++static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; ++static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; ++ ++static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, ++ unsigned n_wait_loops, unsigned cnt_threshold) ++{ ++ struct drm_device *dev = encoder->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ uint32_t save_pll_test; ++ unsigned int i, j; ++ ++ WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); ++ save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); ++ WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); ++ ++ WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); ++ for (i = 0; i < n_tests; i++) { ++ WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); ++ for (j = 0; j < n_wait_loops; j++) ++ if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) ++ break; ++ } ++ WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); ++ WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); ++} ++ ++ ++static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, ++ uint16_t addr, uint32_t value) ++{ ++ struct drm_device *dev = radeon_encoder->base.dev; ++ struct radeon_device *rdev = dev->dev_private; ++ uint32_t tmp; ++ int i = 0; ++ ++ WREG32(RADEON_TV_HOST_WRITE_DATA, value); ++ ++ WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); ++ WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); ++ ++ do { ++ tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); ++ if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) ++ break; ++ i++; ++ } while (i < 10000); ++ WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); ++} ++ ++#if 0 /* included for completeness */ ++static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) ++{ ++ struct drm_device *dev = radeon_encoder->base.dev; ++ struct radeon_device *rdev = dev->dev_private; ++ uint32_t tmp; ++ int i = 0; ++ ++ WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); ++ WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); ++ ++ do { ++ tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); ++ if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) ++ break; ++ i++; ++ } while (i < 10000); ++ WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); ++ return RREG32(RADEON_TV_HOST_READ_DATA); ++} ++#endif ++ ++static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) ++{ ++ uint16_t h_table; ++ ++ switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { ++ case 0: ++ h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; ++ break; ++ case 1: ++ h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; ++ break; ++ case 2: ++ h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; ++ break; ++ default: ++ h_table = 0; ++ break; ++ } ++ return h_table; ++} ++ ++static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) ++{ ++ uint16_t v_table; ++ ++ switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { ++ case 0: ++ v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; ++ break; ++ case 1: ++ v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; ++ break; ++ case 2: ++ v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; ++ break; ++ default: ++ v_table = 0; ++ break; ++ } ++ return v_table; ++} ++ ++static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) ++{ ++ struct drm_device *dev = radeon_encoder->base.dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; ++ uint16_t h_table, v_table; ++ uint32_t tmp; ++ int i; ++ ++ WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); ++ h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); ++ v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); ++ ++ for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { ++ tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); ++ radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); ++ if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) ++ break; ++ } ++ for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { ++ tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); ++ radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); ++ if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) ++ break; ++ } ++} ++ ++static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) ++{ ++ struct drm_device *dev = radeon_encoder->base.dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; ++ WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); ++ WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); ++ WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); ++} ++ ++static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) ++{ ++ struct drm_device *dev = encoder->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; ++ struct radeon_crtc *radeon_crtc; ++ int restart; ++ unsigned int h_total, v_total, f_total; ++ int v_offset, h_offset; ++ u16 p1, p2, h_inc; ++ bool h_changed; ++ const struct radeon_tv_mode_constants *const_ptr; ++ struct radeon_pll *pll; ++ ++ radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); ++ if (radeon_crtc->crtc_id == 1) ++ pll = &rdev->clock.p2pll; ++ else ++ pll = &rdev->clock.p1pll; ++ ++ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); ++ if (!const_ptr) ++ return false; ++ ++ h_total = const_ptr->hor_total; ++ v_total = const_ptr->ver_total; ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M || ++ tv_dac->tv_std == TV_STD_PAL_60) ++ f_total = NTSC_TV_VFTOTAL + 1; ++ else ++ f_total = PAL_TV_VFTOTAL + 1; ++ ++ /* adjust positions 1&2 in hor. cod timing table */ ++ h_offset = tv_dac->h_pos * H_POS_UNIT; ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M) { ++ h_offset -= 50; ++ p1 = hor_timing_NTSC[H_TABLE_POS1]; ++ p2 = hor_timing_NTSC[H_TABLE_POS2]; ++ } else { ++ p1 = hor_timing_PAL[H_TABLE_POS1]; ++ p2 = hor_timing_PAL[H_TABLE_POS2]; ++ } ++ ++ p1 = (u16)((int)p1 + h_offset); ++ p2 = (u16)((int)p2 - h_offset); ++ ++ h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || ++ p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); ++ ++ tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; ++ tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; ++ ++ /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ ++ h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; ++ ++ /* adjust restart */ ++ restart = const_ptr->def_restart; ++ ++ /* ++ * convert v_pos TV lines to n. of CRTC pixels ++ */ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M || ++ tv_dac->tv_std == TV_STD_PAL_60) ++ v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); ++ else ++ v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); ++ ++ restart -= v_offset + h_offset; ++ ++ DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", ++ const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); ++ ++ tv_dac->tv.hrestart = restart % h_total; ++ restart /= h_total; ++ tv_dac->tv.vrestart = restart % v_total; ++ restart /= v_total; ++ tv_dac->tv.frestart = restart % f_total; ++ ++ DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n", ++ (unsigned)tv_dac->tv.frestart, ++ (unsigned)tv_dac->tv.vrestart, ++ (unsigned)tv_dac->tv.hrestart); ++ ++ /* compute h_inc from hsize */ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M) ++ h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / ++ (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); ++ else ++ h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / ++ (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); ++ ++ tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | ++ ((u32)h_inc << RADEON_H_INC_SHIFT); ++ ++ DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); ++ ++ return h_changed; ++} ++ ++void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ struct drm_device *dev = encoder->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; ++ const struct radeon_tv_mode_constants *const_ptr; ++ struct radeon_crtc *radeon_crtc; ++ int i; ++ uint16_t pll_ref_freq; ++ uint32_t vert_space, flicker_removal, tmp; ++ uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; ++ uint32_t tv_modulator_cntl1, tv_modulator_cntl2; ++ uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; ++ uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal; ++ uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; ++ uint32_t m, n, p; ++ const uint16_t *hor_timing; ++ const uint16_t *vert_timing; ++ ++ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); ++ if (!const_ptr) ++ return; ++ ++ radeon_crtc = to_radeon_crtc(encoder->crtc); ++ ++ tv_master_cntl = (RADEON_VIN_ASYNC_RST | ++ RADEON_CRT_FIFO_CE_EN | ++ RADEON_TV_FIFO_CE_EN | ++ RADEON_TV_ON); ++ ++ if (!ASIC_IS_R300(rdev)) ++ tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J) ++ tv_master_cntl |= RADEON_RESTART_PHASE_FIX; ++ ++ tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | ++ RADEON_SYNC_TIP_LEVEL | ++ RADEON_YFLT_EN | ++ RADEON_UVFLT_EN | ++ (6 << RADEON_CY_FILT_BLEND_SHIFT)); ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J) { ++ tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | ++ (0x3b << RADEON_BLANK_LEVEL_SHIFT); ++ tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | ++ ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); ++ } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { ++ tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; ++ tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | ++ ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); ++ } else { ++ tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | ++ (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | ++ (0x3b << RADEON_BLANK_LEVEL_SHIFT); ++ tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | ++ ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); ++ } ++ ++ ++ tv_rgb_cntl = (RADEON_RGB_DITHER_EN ++ | RADEON_TVOUT_SCALE_EN ++ | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) ++ | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) ++ | RADEON_RGB_ATTEN_SEL(0x3) ++ | RADEON_RGB_ATTEN_VAL(0xc)); ++ ++ if (radeon_crtc->crtc_id == 1) ++ tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; ++ else { ++ if (radeon_crtc->rmx_type != RMX_OFF) ++ tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; ++ else ++ tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; ++ } ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M || ++ tv_dac->tv_std == TV_STD_PAL_60) ++ vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; ++ else ++ vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; ++ ++ tmp = RREG32(RADEON_TV_VSCALER_CNTL1); ++ tmp &= 0xe3ff0000; ++ tmp |= (vert_space * (1 << FRAC_BITS) / 10000); ++ tv_vscaler_cntl1 = tmp; ++ ++ if (pll_ref_freq == 2700) ++ tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; ++ ++ if (const_ptr->hor_resolution == 1024) ++ tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); ++ else ++ tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); ++ ++ /* scale up for int divide */ ++ tmp = const_ptr->ver_total * 2 * 1000; ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M || ++ tv_dac->tv_std == TV_STD_PAL_60) { ++ tmp /= NTSC_TV_LINES_PER_FRAME; ++ } else { ++ tmp /= PAL_TV_LINES_PER_FRAME; ++ } ++ flicker_removal = (tmp + 500) / 1000; ++ ++ if (flicker_removal < 3) ++ flicker_removal = 3; ++ for (i = 0; i < 6; ++i) { ++ if (flicker_removal == SLOPE_limit[i]) ++ break; ++ } ++ ++ tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + ++ 5001) / 10000 / 8 | ((SLOPE_value[i] * ++ (1 << (FRAC_BITS - 1)) / 8) << 16); ++ tv_y_fall_cntl = ++ (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | ++ RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / ++ 1024; ++ tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| ++ (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; ++ ++ tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; ++ tv_vscaler_cntl2 |= (0x10 << 24) | ++ RADEON_DITHER_MODE | ++ RADEON_Y_OUTPUT_DITHER_EN | ++ RADEON_UV_OUTPUT_DITHER_EN | ++ RADEON_UV_TO_BUF_DITHER_EN; ++ ++ tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; ++ tmp = ((16384 * 256 * 10) / tmp + 5) / 10; ++ tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; ++ tv_dac->tv.timing_cntl = tmp; ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M || ++ tv_dac->tv_std == TV_STD_PAL_60) ++ tv_dac_cntl = tv_dac->ntsc_tvdac_adj; ++ else ++ tv_dac_cntl = tv_dac->pal_tvdac_adj; ++ ++ tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J) ++ tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; ++ else ++ tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J) { ++ if (pll_ref_freq == 2700) { ++ m = NTSC_TV_PLL_M_27; ++ n = NTSC_TV_PLL_N_27; ++ p = NTSC_TV_PLL_P_27; ++ } else { ++ m = NTSC_TV_PLL_M_14; ++ n = NTSC_TV_PLL_N_14; ++ p = NTSC_TV_PLL_P_14; ++ } ++ } else { ++ if (pll_ref_freq == 2700) { ++ m = PAL_TV_PLL_M_27; ++ n = PAL_TV_PLL_N_27; ++ p = PAL_TV_PLL_P_27; ++ } else { ++ m = PAL_TV_PLL_M_27; ++ n = PAL_TV_PLL_N_27; ++ p = PAL_TV_PLL_P_27; ++ } ++ } ++ ++ tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | ++ (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | ++ ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | ++ (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | ++ ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); ++ ++ tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) | ++ ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | ++ ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) | ++ RADEON_TVCLK_SRC_SEL_TVPLL | ++ RADEON_TVPLL_TEST_DIS); ++ ++ tv_dac->tv.tv_uv_adr = 0xc8; ++ ++ if (tv_dac->tv_std == TV_STD_NTSC || ++ tv_dac->tv_std == TV_STD_NTSC_J || ++ tv_dac->tv_std == TV_STD_PAL_M || ++ tv_dac->tv_std == TV_STD_PAL_60) { ++ tv_ftotal = NTSC_TV_VFTOTAL; ++ hor_timing = hor_timing_NTSC; ++ vert_timing = vert_timing_NTSC; ++ } else { ++ hor_timing = hor_timing_PAL; ++ vert_timing = vert_timing_PAL; ++ tv_ftotal = PAL_TV_VFTOTAL; ++ } ++ ++ for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { ++ if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) ++ break; ++ } ++ ++ for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { ++ if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) ++ break; ++ } ++ ++ radeon_legacy_tv_init_restarts(encoder); ++ ++ /* play with DAC_CNTL */ ++ /* play with GPIOPAD_A */ ++ /* DISP_OUTPUT_CNTL */ ++ /* use reference freq */ ++ ++ /* program the TV registers */ ++ WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | ++ RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); ++ ++ tmp = RREG32(RADEON_TV_DAC_CNTL); ++ tmp &= ~RADEON_TV_DAC_NBLANK; ++ tmp |= RADEON_TV_DAC_BGSLEEP | ++ RADEON_TV_DAC_RDACPD | ++ RADEON_TV_DAC_GDACPD | ++ RADEON_TV_DAC_BDACPD; ++ WREG32(RADEON_TV_DAC_CNTL, tmp); ++ ++ /* TV PLL */ ++ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); ++ WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); ++ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); ++ ++ radeon_wait_pll_lock(encoder, 200, 800, 135); ++ ++ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); ++ ++ radeon_wait_pll_lock(encoder, 300, 160, 27); ++ radeon_wait_pll_lock(encoder, 200, 800, 135); ++ ++ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); ++ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); ++ ++ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); ++ WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); ++ ++ /* TV HV */ ++ WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); ++ WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); ++ WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); ++ WREG32(RADEON_TV_HSTART, const_ptr->hor_start); ++ ++ WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); ++ WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); ++ WREG32(RADEON_TV_FTOTAL, tv_ftotal); ++ WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); ++ WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); ++ ++ WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); ++ WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); ++ WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); ++ ++ WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | ++ RADEON_CRT_ASYNC_RST)); ++ ++ /* TV restarts */ ++ radeon_legacy_write_tv_restarts(radeon_encoder); ++ ++ /* tv timings */ ++ radeon_restore_tv_timing_tables(radeon_encoder); ++ ++ WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); ++ ++ /* tv std */ ++ WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); ++ WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); ++ WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); ++ WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); ++ WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | ++ RADEON_C_GRN_EN | ++ RADEON_CMP_BLU_EN | ++ RADEON_DAC_DITHER_EN)); ++ ++ WREG32(RADEON_TV_CRC_CNTL, 0); ++ ++ WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); ++ ++ WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | ++ (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); ++ WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | ++ (0x100 << RADEON_Y_GAIN_SHIFT))); ++ ++ WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); ++ ++} ++ ++void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, ++ uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, ++ uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) ++{ ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ const struct radeon_tv_mode_constants *const_ptr; ++ uint32_t tmp; ++ ++ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); ++ if (!const_ptr) ++ return; ++ ++ *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | ++ (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); ++ ++ tmp = *h_sync_strt_wid; ++ tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); ++ tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | ++ (const_ptr->hor_syncstart & 7); ++ *h_sync_strt_wid = tmp; ++ ++ *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | ++ ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); ++ ++ tmp = *v_sync_strt_wid; ++ tmp &= ~RADEON_CRTC_V_SYNC_STRT; ++ tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); ++ *v_sync_strt_wid = tmp; ++} ++ ++static inline int get_post_div(int value) ++{ ++ int post_div; ++ switch (value) { ++ case 1: post_div = 0; break; ++ case 2: post_div = 1; break; ++ case 3: post_div = 4; break; ++ case 4: post_div = 2; break; ++ case 6: post_div = 6; break; ++ case 8: post_div = 3; break; ++ case 12: post_div = 7; break; ++ case 16: ++ default: post_div = 5; break; ++ } ++ return post_div; ++} ++ ++void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, ++ uint32_t *htotal_cntl, uint32_t *ppll_ref_div, ++ uint32_t *ppll_div_3, uint32_t *pixclks_cntl) ++{ ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ const struct radeon_tv_mode_constants *const_ptr; ++ ++ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); ++ if (!const_ptr) ++ return; ++ ++ *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; ++ ++ *ppll_ref_div = const_ptr->crtcPLL_M; ++ ++ *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); ++ *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); ++ *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; ++} ++ ++void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, ++ uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, ++ uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) ++{ ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ const struct radeon_tv_mode_constants *const_ptr; ++ ++ const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); ++ if (!const_ptr) ++ return; ++ ++ *htotal2_cntl = (const_ptr->hor_total & 0x7); ++ ++ *p2pll_ref_div = const_ptr->crtcPLL_M; ++ ++ *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); ++ *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; ++ *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; ++} ++ +diff --git a/drivers/gpu/drm/radeon/radeon_microcode.h b/drivers/gpu/drm/radeon/radeon_microcode.h +deleted file mode 100644 +index a348c9e..0000000 +--- a/drivers/gpu/drm/radeon/radeon_microcode.h ++++ /dev/null +@@ -1,1844 +0,0 @@ +-/* +- * Copyright 2007 Advanced Micro Devices, Inc. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef RADEON_MICROCODE_H +-#define RADEON_MICROCODE_H +- +-/* production radeon ucode r1xx-r6xx */ +-static const u32 R100_cp_microcode[][2] = { +- { 0x21007000, 0000000000 }, +- { 0x20007000, 0000000000 }, +- { 0x000000b4, 0x00000004 }, +- { 0x000000b8, 0x00000004 }, +- { 0x6f5b4d4c, 0000000000 }, +- { 0x4c4c427f, 0000000000 }, +- { 0x5b568a92, 0000000000 }, +- { 0x4ca09c6d, 0000000000 }, +- { 0xad4c4c4c, 0000000000 }, +- { 0x4ce1af3d, 0000000000 }, +- { 0xd8afafaf, 0000000000 }, +- { 0xd64c4cdc, 0000000000 }, +- { 0x4cd10d10, 0000000000 }, +- { 0x000f0000, 0x00000016 }, +- { 0x362f242d, 0000000000 }, +- { 0x00000012, 0x00000004 }, +- { 0x000f0000, 0x00000016 }, +- { 0x362f282d, 0000000000 }, +- { 0x000380e7, 0x00000002 }, +- { 0x04002c97, 0x00000002 }, +- { 0x000f0001, 0x00000016 }, +- { 0x333a3730, 0000000000 }, +- { 0x000077ef, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x00000021, 0x0000001a }, +- { 0x00004000, 0x0000001e }, +- { 0x00061000, 0x00000002 }, +- { 0x00000021, 0x0000001a }, +- { 0x00004000, 0x0000001e }, +- { 0x00061000, 0x00000002 }, +- { 0x00000021, 0x0000001a }, +- { 0x00004000, 0x0000001e }, +- { 0x00000017, 0x00000004 }, +- { 0x0003802b, 0x00000002 }, +- { 0x040067e0, 0x00000002 }, +- { 0x00000017, 0x00000004 }, +- { 0x000077e0, 0x00000002 }, +- { 0x00065000, 0x00000002 }, +- { 0x000037e1, 0x00000002 }, +- { 0x040067e1, 0x00000006 }, +- { 0x000077e0, 0x00000002 }, +- { 0x000077e1, 0x00000002 }, +- { 0x000077e1, 0x00000006 }, +- { 0xffffffff, 0000000000 }, +- { 0x10000000, 0000000000 }, +- { 0x0003802b, 0x00000002 }, +- { 0x040067e0, 0x00000006 }, +- { 0x00007675, 0x00000002 }, +- { 0x00007676, 0x00000002 }, +- { 0x00007677, 0x00000002 }, +- { 0x00007678, 0x00000006 }, +- { 0x0003802c, 0x00000002 }, +- { 0x04002676, 0x00000002 }, +- { 0x00007677, 0x00000002 }, +- { 0x00007678, 0x00000006 }, +- { 0x0000002f, 0x00000018 }, +- { 0x0000002f, 0x00000018 }, +- { 0000000000, 0x00000006 }, +- { 0x00000030, 0x00000018 }, +- { 0x00000030, 0x00000018 }, +- { 0000000000, 0x00000006 }, +- { 0x01605000, 0x00000002 }, +- { 0x00065000, 0x00000002 }, +- { 0x00098000, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x64c0603e, 0x00000004 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x00080000, 0x00000016 }, +- { 0000000000, 0000000000 }, +- { 0x0400251d, 0x00000002 }, +- { 0x00007580, 0x00000002 }, +- { 0x00067581, 0x00000002 }, +- { 0x04002580, 0x00000002 }, +- { 0x00067581, 0x00000002 }, +- { 0x00000049, 0x00000004 }, +- { 0x00005000, 0000000000 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x0000750e, 0x00000002 }, +- { 0x00019000, 0x00000002 }, +- { 0x00011055, 0x00000014 }, +- { 0x00000055, 0x00000012 }, +- { 0x0400250f, 0x00000002 }, +- { 0x0000504f, 0x00000004 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x00007565, 0x00000002 }, +- { 0x00007566, 0x00000002 }, +- { 0x00000058, 0x00000004 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x01e655b4, 0x00000002 }, +- { 0x4401b0e4, 0x00000002 }, +- { 0x01c110e4, 0x00000002 }, +- { 0x26667066, 0x00000018 }, +- { 0x040c2565, 0x00000002 }, +- { 0x00000066, 0x00000018 }, +- { 0x04002564, 0x00000002 }, +- { 0x00007566, 0x00000002 }, +- { 0x0000005d, 0x00000004 }, +- { 0x00401069, 0x00000008 }, +- { 0x00101000, 0x00000002 }, +- { 0x000d80ff, 0x00000002 }, +- { 0x0080006c, 0x00000008 }, +- { 0x000f9000, 0x00000002 }, +- { 0x000e00ff, 0x00000002 }, +- { 0000000000, 0x00000006 }, +- { 0x0000008f, 0x00000018 }, +- { 0x0000005b, 0x00000004 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x00007576, 0x00000002 }, +- { 0x00065000, 0x00000002 }, +- { 0x00009000, 0x00000002 }, +- { 0x00041000, 0x00000002 }, +- { 0x0c00350e, 0x00000002 }, +- { 0x00049000, 0x00000002 }, +- { 0x00051000, 0x00000002 }, +- { 0x01e785f8, 0x00000002 }, +- { 0x00200000, 0x00000002 }, +- { 0x0060007e, 0x0000000c }, +- { 0x00007563, 0x00000002 }, +- { 0x006075f0, 0x00000021 }, +- { 0x20007073, 0x00000004 }, +- { 0x00005073, 0x00000004 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x00007576, 0x00000002 }, +- { 0x00007577, 0x00000002 }, +- { 0x0000750e, 0x00000002 }, +- { 0x0000750f, 0x00000002 }, +- { 0x00a05000, 0x00000002 }, +- { 0x00600083, 0x0000000c }, +- { 0x006075f0, 0x00000021 }, +- { 0x000075f8, 0x00000002 }, +- { 0x00000083, 0x00000004 }, +- { 0x000a750e, 0x00000002 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x0020750f, 0x00000002 }, +- { 0x00600086, 0x00000004 }, +- { 0x00007570, 0x00000002 }, +- { 0x00007571, 0x00000002 }, +- { 0x00007572, 0x00000006 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x00005000, 0x00000002 }, +- { 0x00a05000, 0x00000002 }, +- { 0x00007568, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x00000095, 0x0000000c }, +- { 0x00058000, 0x00000002 }, +- { 0x0c607562, 0x00000002 }, +- { 0x00000097, 0x00000004 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x00600096, 0x00000004 }, +- { 0x400070e5, 0000000000 }, +- { 0x000380e6, 0x00000002 }, +- { 0x040025c5, 0x00000002 }, +- { 0x000380e5, 0x00000002 }, +- { 0x000000a8, 0x0000001c }, +- { 0x000650aa, 0x00000018 }, +- { 0x040025bb, 0x00000002 }, +- { 0x000610ab, 0x00000018 }, +- { 0x040075bc, 0000000000 }, +- { 0x000075bb, 0x00000002 }, +- { 0x000075bc, 0000000000 }, +- { 0x00090000, 0x00000006 }, +- { 0x00090000, 0x00000002 }, +- { 0x000d8002, 0x00000006 }, +- { 0x00007832, 0x00000002 }, +- { 0x00005000, 0x00000002 }, +- { 0x000380e7, 0x00000002 }, +- { 0x04002c97, 0x00000002 }, +- { 0x00007820, 0x00000002 }, +- { 0x00007821, 0x00000002 }, +- { 0x00007800, 0000000000 }, +- { 0x01200000, 0x00000002 }, +- { 0x20077000, 0x00000002 }, +- { 0x01200000, 0x00000002 }, +- { 0x20007000, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x0120751b, 0x00000002 }, +- { 0x8040750a, 0x00000002 }, +- { 0x8040750b, 0x00000002 }, +- { 0x00110000, 0x00000002 }, +- { 0x000380e5, 0x00000002 }, +- { 0x000000c6, 0x0000001c }, +- { 0x000610ab, 0x00000018 }, +- { 0x844075bd, 0x00000002 }, +- { 0x000610aa, 0x00000018 }, +- { 0x840075bb, 0x00000002 }, +- { 0x000610ab, 0x00000018 }, +- { 0x844075bc, 0x00000002 }, +- { 0x000000c9, 0x00000004 }, +- { 0x804075bd, 0x00000002 }, +- { 0x800075bb, 0x00000002 }, +- { 0x804075bc, 0x00000002 }, +- { 0x00108000, 0x00000002 }, +- { 0x01400000, 0x00000002 }, +- { 0x006000cd, 0x0000000c }, +- { 0x20c07000, 0x00000020 }, +- { 0x000000cf, 0x00000012 }, +- { 0x00800000, 0x00000006 }, +- { 0x0080751d, 0x00000006 }, +- { 0000000000, 0000000000 }, +- { 0x0000775c, 0x00000002 }, +- { 0x00a05000, 0x00000002 }, +- { 0x00661000, 0x00000002 }, +- { 0x0460275d, 0x00000020 }, +- { 0x00004000, 0000000000 }, +- { 0x01e00830, 0x00000002 }, +- { 0x21007000, 0000000000 }, +- { 0x6464614d, 0000000000 }, +- { 0x69687420, 0000000000 }, +- { 0x00000073, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x00005000, 0x00000002 }, +- { 0x000380d0, 0x00000002 }, +- { 0x040025e0, 0x00000002 }, +- { 0x000075e1, 0000000000 }, +- { 0x00000001, 0000000000 }, +- { 0x000380e0, 0x00000002 }, +- { 0x04002394, 0x00000002 }, +- { 0x00005000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x00000008, 0000000000 }, +- { 0x00000004, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +-}; +- +-static const u32 R200_cp_microcode[][2] = { +- { 0x21007000, 0000000000 }, +- { 0x20007000, 0000000000 }, +- { 0x000000bf, 0x00000004 }, +- { 0x000000c3, 0x00000004 }, +- { 0x7a685e5d, 0000000000 }, +- { 0x5d5d5588, 0000000000 }, +- { 0x68659197, 0000000000 }, +- { 0x5da19f78, 0000000000 }, +- { 0x5d5d5d5d, 0000000000 }, +- { 0x5dee5d50, 0000000000 }, +- { 0xf2acacac, 0000000000 }, +- { 0xe75df9e9, 0000000000 }, +- { 0xb1dd0e11, 0000000000 }, +- { 0xe2afafaf, 0000000000 }, +- { 0x000f0000, 0x00000016 }, +- { 0x452f232d, 0000000000 }, +- { 0x00000013, 0x00000004 }, +- { 0x000f0000, 0x00000016 }, +- { 0x452f272d, 0000000000 }, +- { 0x000f0001, 0x00000016 }, +- { 0x3e4d4a37, 0000000000 }, +- { 0x000077ef, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x00000020, 0x0000001a }, +- { 0x00004000, 0x0000001e }, +- { 0x00061000, 0x00000002 }, +- { 0x00000020, 0x0000001a }, +- { 0x00004000, 0x0000001e }, +- { 0x00061000, 0x00000002 }, +- { 0x00000020, 0x0000001a }, +- { 0x00004000, 0x0000001e }, +- { 0x00000016, 0x00000004 }, +- { 0x0003802a, 0x00000002 }, +- { 0x040067e0, 0x00000002 }, +- { 0x00000016, 0x00000004 }, +- { 0x000077e0, 0x00000002 }, +- { 0x00065000, 0x00000002 }, +- { 0x000037e1, 0x00000002 }, +- { 0x040067e1, 0x00000006 }, +- { 0x000077e0, 0x00000002 }, +- { 0x000077e1, 0x00000002 }, +- { 0x000077e1, 0x00000006 }, +- { 0xffffffff, 0000000000 }, +- { 0x10000000, 0000000000 }, +- { 0x07f007f0, 0000000000 }, +- { 0x0003802a, 0x00000002 }, +- { 0x040067e0, 0x00000006 }, +- { 0x0003802c, 0x00000002 }, +- { 0x04002741, 0x00000002 }, +- { 0x04002741, 0x00000002 }, +- { 0x04002743, 0x00000002 }, +- { 0x00007675, 0x00000002 }, +- { 0x00007676, 0x00000002 }, +- { 0x00007677, 0x00000002 }, +- { 0x00007678, 0x00000006 }, +- { 0x0003802c, 0x00000002 }, +- { 0x04002741, 0x00000002 }, +- { 0x04002741, 0x00000002 }, +- { 0x04002743, 0x00000002 }, +- { 0x00007676, 0x00000002 }, +- { 0x00007677, 0x00000002 }, +- { 0x00007678, 0x00000006 }, +- { 0x0003802b, 0x00000002 }, +- { 0x04002676, 0x00000002 }, +- { 0x00007677, 0x00000002 }, +- { 0x0003802c, 0x00000002 }, +- { 0x04002741, 0x00000002 }, +- { 0x04002743, 0x00000002 }, +- { 0x00007678, 0x00000006 }, +- { 0x0003802c, 0x00000002 }, +- { 0x04002741, 0x00000002 }, +- { 0x04002741, 0x00000002 }, +- { 0x04002743, 0x00000002 }, +- { 0x00007678, 0x00000006 }, +- { 0x0000002f, 0x00000018 }, +- { 0x0000002f, 0x00000018 }, +- { 0000000000, 0x00000006 }, +- { 0x00000037, 0x00000018 }, +- { 0x00000037, 0x00000018 }, +- { 0000000000, 0x00000006 }, +- { 0x01605000, 0x00000002 }, +- { 0x00065000, 0x00000002 }, +- { 0x00098000, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x64c06051, 0x00000004 }, +- { 0x00080000, 0x00000016 }, +- { 0000000000, 0000000000 }, +- { 0x0400251d, 0x00000002 }, +- { 0x00007580, 0x00000002 }, +- { 0x00067581, 0x00000002 }, +- { 0x04002580, 0x00000002 }, +- { 0x00067581, 0x00000002 }, +- { 0x0000005a, 0x00000004 }, +- { 0x00005000, 0000000000 }, +- { 0x00061000, 0x00000002 }, +- { 0x0000750e, 0x00000002 }, +- { 0x00019000, 0x00000002 }, +- { 0x00011064, 0x00000014 }, +- { 0x00000064, 0x00000012 }, +- { 0x0400250f, 0x00000002 }, +- { 0x0000505e, 0x00000004 }, +- { 0x00007565, 0x00000002 }, +- { 0x00007566, 0x00000002 }, +- { 0x00000065, 0x00000004 }, +- { 0x01e655b4, 0x00000002 }, +- { 0x4401b0f0, 0x00000002 }, +- { 0x01c110f0, 0x00000002 }, +- { 0x26667071, 0x00000018 }, +- { 0x040c2565, 0x00000002 }, +- { 0x00000071, 0x00000018 }, +- { 0x04002564, 0x00000002 }, +- { 0x00007566, 0x00000002 }, +- { 0x00000068, 0x00000004 }, +- { 0x00401074, 0x00000008 }, +- { 0x00101000, 0x00000002 }, +- { 0x000d80ff, 0x00000002 }, +- { 0x00800077, 0x00000008 }, +- { 0x000f9000, 0x00000002 }, +- { 0x000e00ff, 0x00000002 }, +- { 0000000000, 0x00000006 }, +- { 0x00000094, 0x00000018 }, +- { 0x00000068, 0x00000004 }, +- { 0x00007576, 0x00000002 }, +- { 0x00065000, 0x00000002 }, +- { 0x00009000, 0x00000002 }, +- { 0x00041000, 0x00000002 }, +- { 0x0c00350e, 0x00000002 }, +- { 0x00049000, 0x00000002 }, +- { 0x00051000, 0x00000002 }, +- { 0x01e785f8, 0x00000002 }, +- { 0x00200000, 0x00000002 }, +- { 0x00600087, 0x0000000c }, +- { 0x00007563, 0x00000002 }, +- { 0x006075f0, 0x00000021 }, +- { 0x2000707c, 0x00000004 }, +- { 0x0000507c, 0x00000004 }, +- { 0x00007576, 0x00000002 }, +- { 0x00007577, 0x00000002 }, +- { 0x0000750e, 0x00000002 }, +- { 0x0000750f, 0x00000002 }, +- { 0x00a05000, 0x00000002 }, +- { 0x0060008a, 0x0000000c }, +- { 0x006075f0, 0x00000021 }, +- { 0x000075f8, 0x00000002 }, +- { 0x0000008a, 0x00000004 }, +- { 0x000a750e, 0x00000002 }, +- { 0x0020750f, 0x00000002 }, +- { 0x0060008d, 0x00000004 }, +- { 0x00007570, 0x00000002 }, +- { 0x00007571, 0x00000002 }, +- { 0x00007572, 0x00000006 }, +- { 0x00005000, 0x00000002 }, +- { 0x00a05000, 0x00000002 }, +- { 0x00007568, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x00000098, 0x0000000c }, +- { 0x00058000, 0x00000002 }, +- { 0x0c607562, 0x00000002 }, +- { 0x0000009a, 0x00000004 }, +- { 0x00600099, 0x00000004 }, +- { 0x400070f1, 0000000000 }, +- { 0x000380f1, 0x00000002 }, +- { 0x000000a7, 0x0000001c }, +- { 0x000650a9, 0x00000018 }, +- { 0x040025bb, 0x00000002 }, +- { 0x000610aa, 0x00000018 }, +- { 0x040075bc, 0000000000 }, +- { 0x000075bb, 0x00000002 }, +- { 0x000075bc, 0000000000 }, +- { 0x00090000, 0x00000006 }, +- { 0x00090000, 0x00000002 }, +- { 0x000d8002, 0x00000006 }, +- { 0x00005000, 0x00000002 }, +- { 0x00007821, 0x00000002 }, +- { 0x00007800, 0000000000 }, +- { 0x00007821, 0x00000002 }, +- { 0x00007800, 0000000000 }, +- { 0x01665000, 0x00000002 }, +- { 0x000a0000, 0x00000002 }, +- { 0x000671cc, 0x00000002 }, +- { 0x0286f1cd, 0x00000002 }, +- { 0x000000b7, 0x00000010 }, +- { 0x21007000, 0000000000 }, +- { 0x000000be, 0x0000001c }, +- { 0x00065000, 0x00000002 }, +- { 0x000a0000, 0x00000002 }, +- { 0x00061000, 0x00000002 }, +- { 0x000b0000, 0x00000002 }, +- { 0x38067000, 0x00000002 }, +- { 0x000a00ba, 0x00000004 }, +- { 0x20007000, 0000000000 }, +- { 0x01200000, 0x00000002 }, +- { 0x20077000, 0x00000002 }, +- { 0x01200000, 0x00000002 }, +- { 0x20007000, 0000000000 }, +- { 0x00061000, 0x00000002 }, +- { 0x0120751b, 0x00000002 }, +- { 0x8040750a, 0x00000002 }, +- { 0x8040750b, 0x00000002 }, +- { 0x00110000, 0x00000002 }, +- { 0x000380f1, 0x00000002 }, +- { 0x000000d1, 0x0000001c }, +- { 0x000610aa, 0x00000018 }, +- { 0x844075bd, 0x00000002 }, +- { 0x000610a9, 0x00000018 }, +- { 0x840075bb, 0x00000002 }, +- { 0x000610aa, 0x00000018 }, +- { 0x844075bc, 0x00000002 }, +- { 0x000000d4, 0x00000004 }, +- { 0x804075bd, 0x00000002 }, +- { 0x800075bb, 0x00000002 }, +- { 0x804075bc, 0x00000002 }, +- { 0x00108000, 0x00000002 }, +- { 0x01400000, 0x00000002 }, +- { 0x006000d8, 0x0000000c }, +- { 0x20c07000, 0x00000020 }, +- { 0x000000da, 0x00000012 }, +- { 0x00800000, 0x00000006 }, +- { 0x0080751d, 0x00000006 }, +- { 0x000025bb, 0x00000002 }, +- { 0x000040d4, 0x00000004 }, +- { 0x0000775c, 0x00000002 }, +- { 0x00a05000, 0x00000002 }, +- { 0x00661000, 0x00000002 }, +- { 0x0460275d, 0x00000020 }, +- { 0x00004000, 0000000000 }, +- { 0x00007999, 0x00000002 }, +- { 0x00a05000, 0x00000002 }, +- { 0x00661000, 0x00000002 }, +- { 0x0460299b, 0x00000020 }, +- { 0x00004000, 0000000000 }, +- { 0x01e00830, 0x00000002 }, +- { 0x21007000, 0000000000 }, +- { 0x00005000, 0x00000002 }, +- { 0x00038056, 0x00000002 }, +- { 0x040025e0, 0x00000002 }, +- { 0x000075e1, 0000000000 }, +- { 0x00000001, 0000000000 }, +- { 0x000380ed, 0x00000002 }, +- { 0x04007394, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x000078c4, 0x00000002 }, +- { 0x000078c5, 0x00000002 }, +- { 0x000078c6, 0x00000002 }, +- { 0x00007924, 0x00000002 }, +- { 0x00007925, 0x00000002 }, +- { 0x00007926, 0x00000002 }, +- { 0x000000f2, 0x00000004 }, +- { 0x00007924, 0x00000002 }, +- { 0x00007925, 0x00000002 }, +- { 0x00007926, 0x00000002 }, +- { 0x000000f9, 0x00000004 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +-}; +- +-static const u32 R300_cp_microcode[][2] = { +- { 0x4200e000, 0000000000 }, +- { 0x4000e000, 0000000000 }, +- { 0x000000ae, 0x00000008 }, +- { 0x000000b2, 0x00000008 }, +- { 0x67554b4a, 0000000000 }, +- { 0x4a4a4475, 0000000000 }, +- { 0x55527d83, 0000000000 }, +- { 0x4a8c8b65, 0000000000 }, +- { 0x4aef4af6, 0000000000 }, +- { 0x4ae14a4a, 0000000000 }, +- { 0xe4979797, 0000000000 }, +- { 0xdb4aebdd, 0000000000 }, +- { 0x9ccc4a4a, 0000000000 }, +- { 0xd1989898, 0000000000 }, +- { 0x4a0f9ad6, 0000000000 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000d0012, 0x00000038 }, +- { 0x0000e8b4, 0x00000004 }, +- { 0x000d0014, 0x00000038 }, +- { 0x0000e8b6, 0x00000004 }, +- { 0x000d0016, 0x00000038 }, +- { 0x0000e854, 0x00000004 }, +- { 0x000d0018, 0x00000038 }, +- { 0x0000e855, 0x00000004 }, +- { 0x000d001a, 0x00000038 }, +- { 0x0000e856, 0x00000004 }, +- { 0x000d001c, 0x00000038 }, +- { 0x0000e857, 0x00000004 }, +- { 0x000d001e, 0x00000038 }, +- { 0x0000e824, 0x00000004 }, +- { 0x000d0020, 0x00000038 }, +- { 0x0000e825, 0x00000004 }, +- { 0x000d0022, 0x00000038 }, +- { 0x0000e830, 0x00000004 }, +- { 0x000d0024, 0x00000038 }, +- { 0x0000f0c0, 0x00000004 }, +- { 0x000d0026, 0x00000038 }, +- { 0x0000f0c1, 0x00000004 }, +- { 0x000d0028, 0x00000038 }, +- { 0x0000f041, 0x00000004 }, +- { 0x000d002a, 0x00000038 }, +- { 0x0000f184, 0x00000004 }, +- { 0x000d002c, 0x00000038 }, +- { 0x0000f185, 0x00000004 }, +- { 0x000d002e, 0x00000038 }, +- { 0x0000f186, 0x00000004 }, +- { 0x000d0030, 0x00000038 }, +- { 0x0000f187, 0x00000004 }, +- { 0x000d0032, 0x00000038 }, +- { 0x0000f180, 0x00000004 }, +- { 0x000d0034, 0x00000038 }, +- { 0x0000f393, 0x00000004 }, +- { 0x000d0036, 0x00000038 }, +- { 0x0000f38a, 0x00000004 }, +- { 0x000d0038, 0x00000038 }, +- { 0x0000f38e, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000043, 0x00000018 }, +- { 0x00cce800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x0000003a, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x2000451d, 0x00000004 }, +- { 0x0000e580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x08004580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x00000047, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x00032000, 0x00000004 }, +- { 0x00022051, 0x00000028 }, +- { 0x00000051, 0x00000024 }, +- { 0x0800450f, 0x00000004 }, +- { 0x0000a04b, 0x00000008 }, +- { 0x0000e565, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000052, 0x00000008 }, +- { 0x03cca5b4, 0x00000004 }, +- { 0x05432000, 0x00000004 }, +- { 0x00022000, 0x00000004 }, +- { 0x4ccce05e, 0x00000030 }, +- { 0x08274565, 0x00000004 }, +- { 0x0000005e, 0x00000030 }, +- { 0x08004564, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000055, 0x00000008 }, +- { 0x00802061, 0x00000010 }, +- { 0x00202000, 0x00000004 }, +- { 0x001b00ff, 0x00000004 }, +- { 0x01000064, 0x00000010 }, +- { 0x001f2000, 0x00000004 }, +- { 0x001c00ff, 0x00000004 }, +- { 0000000000, 0x0000000c }, +- { 0x00000080, 0x00000030 }, +- { 0x00000055, 0x00000008 }, +- { 0x0000e576, 0x00000004 }, +- { 0x000ca000, 0x00000004 }, +- { 0x00012000, 0x00000004 }, +- { 0x00082000, 0x00000004 }, +- { 0x1800650e, 0x00000004 }, +- { 0x00092000, 0x00000004 }, +- { 0x000a2000, 0x00000004 }, +- { 0x000f0000, 0x00000004 }, +- { 0x00400000, 0x00000004 }, +- { 0x00000074, 0x00000018 }, +- { 0x0000e563, 0x00000004 }, +- { 0x00c0e5f9, 0x000000c2 }, +- { 0x00000069, 0x00000008 }, +- { 0x0000a069, 0x00000008 }, +- { 0x0000e576, 0x00000004 }, +- { 0x0000e577, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x0000e50f, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000077, 0x00000018 }, +- { 0x00c0e5f9, 0x000000c2 }, +- { 0x00000077, 0x00000008 }, +- { 0x0014e50e, 0x00000004 }, +- { 0x0040e50f, 0x00000004 }, +- { 0x00c0007a, 0x00000008 }, +- { 0x0000e570, 0x00000004 }, +- { 0x0000e571, 0x00000004 }, +- { 0x0000e572, 0x0000000c }, +- { 0x0000a000, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x0000e568, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00000084, 0x00000018 }, +- { 0x000b0000, 0x00000004 }, +- { 0x18c0e562, 0x00000004 }, +- { 0x00000086, 0x00000008 }, +- { 0x00c00085, 0x00000008 }, +- { 0x000700e3, 0x00000004 }, +- { 0x00000092, 0x00000038 }, +- { 0x000ca094, 0x00000030 }, +- { 0x080045bb, 0x00000004 }, +- { 0x000c2095, 0x00000030 }, +- { 0x0800e5bc, 0000000000 }, +- { 0x0000e5bb, 0x00000004 }, +- { 0x0000e5bc, 0000000000 }, +- { 0x00120000, 0x0000000c }, +- { 0x00120000, 0x00000004 }, +- { 0x001b0002, 0x0000000c }, +- { 0x0000a000, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e800, 0000000000 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e82e, 0000000000 }, +- { 0x02cca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000ce1cc, 0x00000004 }, +- { 0x050de1cd, 0x00000004 }, +- { 0x00400000, 0x00000004 }, +- { 0x000000a4, 0x00000018 }, +- { 0x00c0a000, 0x00000004 }, +- { 0x000000a1, 0x00000008 }, +- { 0x000000a6, 0x00000020 }, +- { 0x4200e000, 0000000000 }, +- { 0x000000ad, 0x00000038 }, +- { 0x000ca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00160000, 0x00000004 }, +- { 0x700ce000, 0x00000004 }, +- { 0x001400a9, 0x00000008 }, +- { 0x4000e000, 0000000000 }, +- { 0x02400000, 0x00000004 }, +- { 0x400ee000, 0x00000004 }, +- { 0x02400000, 0x00000004 }, +- { 0x4000e000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0240e51b, 0x00000004 }, +- { 0x0080e50a, 0x00000005 }, +- { 0x0080e50b, 0x00000005 }, +- { 0x00220000, 0x00000004 }, +- { 0x000700e3, 0x00000004 }, +- { 0x000000c0, 0x00000038 }, +- { 0x000c2095, 0x00000030 }, +- { 0x0880e5bd, 0x00000005 }, +- { 0x000c2094, 0x00000030 }, +- { 0x0800e5bb, 0x00000005 }, +- { 0x000c2095, 0x00000030 }, +- { 0x0880e5bc, 0x00000005 }, +- { 0x000000c3, 0x00000008 }, +- { 0x0080e5bd, 0x00000005 }, +- { 0x0000e5bb, 0x00000005 }, +- { 0x0080e5bc, 0x00000005 }, +- { 0x00210000, 0x00000004 }, +- { 0x02800000, 0x00000004 }, +- { 0x00c000c7, 0x00000018 }, +- { 0x4180e000, 0x00000040 }, +- { 0x000000c9, 0x00000024 }, +- { 0x01000000, 0x0000000c }, +- { 0x0100e51d, 0x0000000c }, +- { 0x000045bb, 0x00000004 }, +- { 0x000080c3, 0x00000008 }, +- { 0x0000f3ce, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c053cf, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x0000f3d2, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c053d3, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x0000f39d, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c0539e, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x03c00830, 0x00000004 }, +- { 0x4200e000, 0000000000 }, +- { 0x0000a000, 0x00000004 }, +- { 0x200045e0, 0x00000004 }, +- { 0x0000e5e1, 0000000000 }, +- { 0x00000001, 0000000000 }, +- { 0x000700e0, 0x00000004 }, +- { 0x0800e394, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x0000e8c4, 0x00000004 }, +- { 0x0000e8c5, 0x00000004 }, +- { 0x0000e8c6, 0x00000004 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000e4, 0x00000008 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000eb, 0x00000008 }, +- { 0x02c02000, 0x00000004 }, +- { 0x00060000, 0x00000004 }, +- { 0x000000f3, 0x00000034 }, +- { 0x000000f0, 0x00000008 }, +- { 0x00008000, 0x00000004 }, +- { 0xc000e000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x001d0018, 0x00000004 }, +- { 0x001a0001, 0x00000004 }, +- { 0x000000fb, 0x00000034 }, +- { 0x0000004a, 0x00000008 }, +- { 0x0500a04a, 0x00000008 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +-}; +- +-static const u32 R420_cp_microcode[][2] = { +- { 0x4200e000, 0000000000 }, +- { 0x4000e000, 0000000000 }, +- { 0x00000099, 0x00000008 }, +- { 0x0000009d, 0x00000008 }, +- { 0x4a554b4a, 0000000000 }, +- { 0x4a4a4467, 0000000000 }, +- { 0x55526f75, 0000000000 }, +- { 0x4a7e7d65, 0000000000 }, +- { 0xd9d3dff6, 0000000000 }, +- { 0x4ac54a4a, 0000000000 }, +- { 0xc8828282, 0000000000 }, +- { 0xbf4acfc1, 0000000000 }, +- { 0x87b04a4a, 0000000000 }, +- { 0xb5838383, 0000000000 }, +- { 0x4a0f85ba, 0000000000 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000d0012, 0x00000038 }, +- { 0x0000e8b4, 0x00000004 }, +- { 0x000d0014, 0x00000038 }, +- { 0x0000e8b6, 0x00000004 }, +- { 0x000d0016, 0x00000038 }, +- { 0x0000e854, 0x00000004 }, +- { 0x000d0018, 0x00000038 }, +- { 0x0000e855, 0x00000004 }, +- { 0x000d001a, 0x00000038 }, +- { 0x0000e856, 0x00000004 }, +- { 0x000d001c, 0x00000038 }, +- { 0x0000e857, 0x00000004 }, +- { 0x000d001e, 0x00000038 }, +- { 0x0000e824, 0x00000004 }, +- { 0x000d0020, 0x00000038 }, +- { 0x0000e825, 0x00000004 }, +- { 0x000d0022, 0x00000038 }, +- { 0x0000e830, 0x00000004 }, +- { 0x000d0024, 0x00000038 }, +- { 0x0000f0c0, 0x00000004 }, +- { 0x000d0026, 0x00000038 }, +- { 0x0000f0c1, 0x00000004 }, +- { 0x000d0028, 0x00000038 }, +- { 0x0000f041, 0x00000004 }, +- { 0x000d002a, 0x00000038 }, +- { 0x0000f184, 0x00000004 }, +- { 0x000d002c, 0x00000038 }, +- { 0x0000f185, 0x00000004 }, +- { 0x000d002e, 0x00000038 }, +- { 0x0000f186, 0x00000004 }, +- { 0x000d0030, 0x00000038 }, +- { 0x0000f187, 0x00000004 }, +- { 0x000d0032, 0x00000038 }, +- { 0x0000f180, 0x00000004 }, +- { 0x000d0034, 0x00000038 }, +- { 0x0000f393, 0x00000004 }, +- { 0x000d0036, 0x00000038 }, +- { 0x0000f38a, 0x00000004 }, +- { 0x000d0038, 0x00000038 }, +- { 0x0000f38e, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000043, 0x00000018 }, +- { 0x00cce800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x0000003a, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x2000451d, 0x00000004 }, +- { 0x0000e580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x08004580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x00000047, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x00032000, 0x00000004 }, +- { 0x00022051, 0x00000028 }, +- { 0x00000051, 0x00000024 }, +- { 0x0800450f, 0x00000004 }, +- { 0x0000a04b, 0x00000008 }, +- { 0x0000e565, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000052, 0x00000008 }, +- { 0x03cca5b4, 0x00000004 }, +- { 0x05432000, 0x00000004 }, +- { 0x00022000, 0x00000004 }, +- { 0x4ccce05e, 0x00000030 }, +- { 0x08274565, 0x00000004 }, +- { 0x0000005e, 0x00000030 }, +- { 0x08004564, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000055, 0x00000008 }, +- { 0x00802061, 0x00000010 }, +- { 0x00202000, 0x00000004 }, +- { 0x001b00ff, 0x00000004 }, +- { 0x01000064, 0x00000010 }, +- { 0x001f2000, 0x00000004 }, +- { 0x001c00ff, 0x00000004 }, +- { 0000000000, 0x0000000c }, +- { 0x00000072, 0x00000030 }, +- { 0x00000055, 0x00000008 }, +- { 0x0000e576, 0x00000004 }, +- { 0x0000e577, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x0000e50f, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000069, 0x00000018 }, +- { 0x00c0e5f9, 0x000000c2 }, +- { 0x00000069, 0x00000008 }, +- { 0x0014e50e, 0x00000004 }, +- { 0x0040e50f, 0x00000004 }, +- { 0x00c0006c, 0x00000008 }, +- { 0x0000e570, 0x00000004 }, +- { 0x0000e571, 0x00000004 }, +- { 0x0000e572, 0x0000000c }, +- { 0x0000a000, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x0000e568, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00000076, 0x00000018 }, +- { 0x000b0000, 0x00000004 }, +- { 0x18c0e562, 0x00000004 }, +- { 0x00000078, 0x00000008 }, +- { 0x00c00077, 0x00000008 }, +- { 0x000700c7, 0x00000004 }, +- { 0x00000080, 0x00000038 }, +- { 0x0000e5bb, 0x00000004 }, +- { 0x0000e5bc, 0000000000 }, +- { 0x0000a000, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e800, 0000000000 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e82e, 0000000000 }, +- { 0x02cca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000ce1cc, 0x00000004 }, +- { 0x050de1cd, 0x00000004 }, +- { 0x00400000, 0x00000004 }, +- { 0x0000008f, 0x00000018 }, +- { 0x00c0a000, 0x00000004 }, +- { 0x0000008c, 0x00000008 }, +- { 0x00000091, 0x00000020 }, +- { 0x4200e000, 0000000000 }, +- { 0x00000098, 0x00000038 }, +- { 0x000ca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00160000, 0x00000004 }, +- { 0x700ce000, 0x00000004 }, +- { 0x00140094, 0x00000008 }, +- { 0x4000e000, 0000000000 }, +- { 0x02400000, 0x00000004 }, +- { 0x400ee000, 0x00000004 }, +- { 0x02400000, 0x00000004 }, +- { 0x4000e000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0240e51b, 0x00000004 }, +- { 0x0080e50a, 0x00000005 }, +- { 0x0080e50b, 0x00000005 }, +- { 0x00220000, 0x00000004 }, +- { 0x000700c7, 0x00000004 }, +- { 0x000000a4, 0x00000038 }, +- { 0x0080e5bd, 0x00000005 }, +- { 0x0000e5bb, 0x00000005 }, +- { 0x0080e5bc, 0x00000005 }, +- { 0x00210000, 0x00000004 }, +- { 0x02800000, 0x00000004 }, +- { 0x00c000ab, 0x00000018 }, +- { 0x4180e000, 0x00000040 }, +- { 0x000000ad, 0x00000024 }, +- { 0x01000000, 0x0000000c }, +- { 0x0100e51d, 0x0000000c }, +- { 0x000045bb, 0x00000004 }, +- { 0x000080a7, 0x00000008 }, +- { 0x0000f3ce, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c053cf, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x0000f3d2, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c053d3, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x0000f39d, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c0539e, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x03c00830, 0x00000004 }, +- { 0x4200e000, 0000000000 }, +- { 0x0000a000, 0x00000004 }, +- { 0x200045e0, 0x00000004 }, +- { 0x0000e5e1, 0000000000 }, +- { 0x00000001, 0000000000 }, +- { 0x000700c4, 0x00000004 }, +- { 0x0800e394, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x0000e8c4, 0x00000004 }, +- { 0x0000e8c5, 0x00000004 }, +- { 0x0000e8c6, 0x00000004 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000c8, 0x00000008 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000cf, 0x00000008 }, +- { 0x02c02000, 0x00000004 }, +- { 0x00060000, 0x00000004 }, +- { 0x000000d7, 0x00000034 }, +- { 0x000000d4, 0x00000008 }, +- { 0x00008000, 0x00000004 }, +- { 0xc000e000, 0000000000 }, +- { 0x0000e1cc, 0x00000004 }, +- { 0x0500e1cd, 0x00000004 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000000de, 0x00000034 }, +- { 0x000000da, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x0019e1cc, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x0500a000, 0x00000004 }, +- { 0x080041cd, 0x00000004 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000000fb, 0x00000034 }, +- { 0x0000004a, 0x00000008 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x001d0018, 0x00000004 }, +- { 0x001a0001, 0x00000004 }, +- { 0x000000fb, 0x00000034 }, +- { 0x0000004a, 0x00000008 }, +- { 0x0500a04a, 0x00000008 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +-}; +- +-static const u32 RS600_cp_microcode[][2] = { +- { 0x4200e000, 0000000000 }, +- { 0x4000e000, 0000000000 }, +- { 0x000000a0, 0x00000008 }, +- { 0x000000a4, 0x00000008 }, +- { 0x4a554b4a, 0000000000 }, +- { 0x4a4a4467, 0000000000 }, +- { 0x55526f75, 0000000000 }, +- { 0x4a7e7d65, 0000000000 }, +- { 0x4ae74af6, 0000000000 }, +- { 0x4ad34a4a, 0000000000 }, +- { 0xd6898989, 0000000000 }, +- { 0xcd4addcf, 0000000000 }, +- { 0x8ebe4ae2, 0000000000 }, +- { 0xc38a8a8a, 0000000000 }, +- { 0x4a0f8cc8, 0000000000 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000d0012, 0x00000038 }, +- { 0x0000e8b4, 0x00000004 }, +- { 0x000d0014, 0x00000038 }, +- { 0x0000e8b6, 0x00000004 }, +- { 0x000d0016, 0x00000038 }, +- { 0x0000e854, 0x00000004 }, +- { 0x000d0018, 0x00000038 }, +- { 0x0000e855, 0x00000004 }, +- { 0x000d001a, 0x00000038 }, +- { 0x0000e856, 0x00000004 }, +- { 0x000d001c, 0x00000038 }, +- { 0x0000e857, 0x00000004 }, +- { 0x000d001e, 0x00000038 }, +- { 0x0000e824, 0x00000004 }, +- { 0x000d0020, 0x00000038 }, +- { 0x0000e825, 0x00000004 }, +- { 0x000d0022, 0x00000038 }, +- { 0x0000e830, 0x00000004 }, +- { 0x000d0024, 0x00000038 }, +- { 0x0000f0c0, 0x00000004 }, +- { 0x000d0026, 0x00000038 }, +- { 0x0000f0c1, 0x00000004 }, +- { 0x000d0028, 0x00000038 }, +- { 0x0000f041, 0x00000004 }, +- { 0x000d002a, 0x00000038 }, +- { 0x0000f184, 0x00000004 }, +- { 0x000d002c, 0x00000038 }, +- { 0x0000f185, 0x00000004 }, +- { 0x000d002e, 0x00000038 }, +- { 0x0000f186, 0x00000004 }, +- { 0x000d0030, 0x00000038 }, +- { 0x0000f187, 0x00000004 }, +- { 0x000d0032, 0x00000038 }, +- { 0x0000f180, 0x00000004 }, +- { 0x000d0034, 0x00000038 }, +- { 0x0000f393, 0x00000004 }, +- { 0x000d0036, 0x00000038 }, +- { 0x0000f38a, 0x00000004 }, +- { 0x000d0038, 0x00000038 }, +- { 0x0000f38e, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000043, 0x00000018 }, +- { 0x00cce800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x0000003a, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x2000451d, 0x00000004 }, +- { 0x0000e580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x08004580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x00000047, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x00032000, 0x00000004 }, +- { 0x00022051, 0x00000028 }, +- { 0x00000051, 0x00000024 }, +- { 0x0800450f, 0x00000004 }, +- { 0x0000a04b, 0x00000008 }, +- { 0x0000e565, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000052, 0x00000008 }, +- { 0x03cca5b4, 0x00000004 }, +- { 0x05432000, 0x00000004 }, +- { 0x00022000, 0x00000004 }, +- { 0x4ccce05e, 0x00000030 }, +- { 0x08274565, 0x00000004 }, +- { 0x0000005e, 0x00000030 }, +- { 0x08004564, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000055, 0x00000008 }, +- { 0x00802061, 0x00000010 }, +- { 0x00202000, 0x00000004 }, +- { 0x001b00ff, 0x00000004 }, +- { 0x01000064, 0x00000010 }, +- { 0x001f2000, 0x00000004 }, +- { 0x001c00ff, 0x00000004 }, +- { 0000000000, 0x0000000c }, +- { 0x00000072, 0x00000030 }, +- { 0x00000055, 0x00000008 }, +- { 0x0000e576, 0x00000004 }, +- { 0x0000e577, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x0000e50f, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000069, 0x00000018 }, +- { 0x00c0e5f9, 0x000000c2 }, +- { 0x00000069, 0x00000008 }, +- { 0x0014e50e, 0x00000004 }, +- { 0x0040e50f, 0x00000004 }, +- { 0x00c0006c, 0x00000008 }, +- { 0x0000e570, 0x00000004 }, +- { 0x0000e571, 0x00000004 }, +- { 0x0000e572, 0x0000000c }, +- { 0x0000a000, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x0000e568, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00000076, 0x00000018 }, +- { 0x000b0000, 0x00000004 }, +- { 0x18c0e562, 0x00000004 }, +- { 0x00000078, 0x00000008 }, +- { 0x00c00077, 0x00000008 }, +- { 0x000700d5, 0x00000004 }, +- { 0x00000084, 0x00000038 }, +- { 0x000ca086, 0x00000030 }, +- { 0x080045bb, 0x00000004 }, +- { 0x000c2087, 0x00000030 }, +- { 0x0800e5bc, 0000000000 }, +- { 0x0000e5bb, 0x00000004 }, +- { 0x0000e5bc, 0000000000 }, +- { 0x00120000, 0x0000000c }, +- { 0x00120000, 0x00000004 }, +- { 0x001b0002, 0x0000000c }, +- { 0x0000a000, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e800, 0000000000 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e82e, 0000000000 }, +- { 0x02cca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000ce1cc, 0x00000004 }, +- { 0x050de1cd, 0x00000004 }, +- { 0x00400000, 0x00000004 }, +- { 0x00000096, 0x00000018 }, +- { 0x00c0a000, 0x00000004 }, +- { 0x00000093, 0x00000008 }, +- { 0x00000098, 0x00000020 }, +- { 0x4200e000, 0000000000 }, +- { 0x0000009f, 0x00000038 }, +- { 0x000ca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00160000, 0x00000004 }, +- { 0x700ce000, 0x00000004 }, +- { 0x0014009b, 0x00000008 }, +- { 0x4000e000, 0000000000 }, +- { 0x02400000, 0x00000004 }, +- { 0x400ee000, 0x00000004 }, +- { 0x02400000, 0x00000004 }, +- { 0x4000e000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0240e51b, 0x00000004 }, +- { 0x0080e50a, 0x00000005 }, +- { 0x0080e50b, 0x00000005 }, +- { 0x00220000, 0x00000004 }, +- { 0x000700d5, 0x00000004 }, +- { 0x000000b2, 0x00000038 }, +- { 0x000c2087, 0x00000030 }, +- { 0x0880e5bd, 0x00000005 }, +- { 0x000c2086, 0x00000030 }, +- { 0x0800e5bb, 0x00000005 }, +- { 0x000c2087, 0x00000030 }, +- { 0x0880e5bc, 0x00000005 }, +- { 0x000000b5, 0x00000008 }, +- { 0x0080e5bd, 0x00000005 }, +- { 0x0000e5bb, 0x00000005 }, +- { 0x0080e5bc, 0x00000005 }, +- { 0x00210000, 0x00000004 }, +- { 0x02800000, 0x00000004 }, +- { 0x00c000b9, 0x00000018 }, +- { 0x4180e000, 0x00000040 }, +- { 0x000000bb, 0x00000024 }, +- { 0x01000000, 0x0000000c }, +- { 0x0100e51d, 0x0000000c }, +- { 0x000045bb, 0x00000004 }, +- { 0x000080b5, 0x00000008 }, +- { 0x0000f3ce, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c053cf, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x0000f3d2, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c053d3, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x0000f39d, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c0539e, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x03c00830, 0x00000004 }, +- { 0x4200e000, 0000000000 }, +- { 0x0000a000, 0x00000004 }, +- { 0x200045e0, 0x00000004 }, +- { 0x0000e5e1, 0000000000 }, +- { 0x00000001, 0000000000 }, +- { 0x000700d2, 0x00000004 }, +- { 0x0800e394, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x0000e8c4, 0x00000004 }, +- { 0x0000e8c5, 0x00000004 }, +- { 0x0000e8c6, 0x00000004 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000d6, 0x00000008 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000dd, 0x00000008 }, +- { 0x00e00116, 0000000000 }, +- { 0x000700e1, 0x00000004 }, +- { 0x0800401c, 0x00000004 }, +- { 0x200050e7, 0x00000004 }, +- { 0x0000e01d, 0x00000004 }, +- { 0x000000e4, 0x00000008 }, +- { 0x02c02000, 0x00000004 }, +- { 0x00060000, 0x00000004 }, +- { 0x000000eb, 0x00000034 }, +- { 0x000000e8, 0x00000008 }, +- { 0x00008000, 0x00000004 }, +- { 0xc000e000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x001d0018, 0x00000004 }, +- { 0x001a0001, 0x00000004 }, +- { 0x000000fb, 0x00000034 }, +- { 0x0000004a, 0x00000008 }, +- { 0x0500a04a, 0x00000008 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +-}; +- +-static const u32 RS690_cp_microcode[][2] = { +- { 0x000000dd, 0x00000008 }, +- { 0x000000df, 0x00000008 }, +- { 0x000000a0, 0x00000008 }, +- { 0x000000a4, 0x00000008 }, +- { 0x4a554b4a, 0000000000 }, +- { 0x4a4a4467, 0000000000 }, +- { 0x55526f75, 0000000000 }, +- { 0x4a7e7d65, 0000000000 }, +- { 0x4ad74af6, 0000000000 }, +- { 0x4ac94a4a, 0000000000 }, +- { 0xcc898989, 0000000000 }, +- { 0xc34ad3c5, 0000000000 }, +- { 0x8e4a4a4a, 0000000000 }, +- { 0x4a8a8a8a, 0000000000 }, +- { 0x4a0f8c4a, 0000000000 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000d0012, 0x00000038 }, +- { 0x0000e8b4, 0x00000004 }, +- { 0x000d0014, 0x00000038 }, +- { 0x0000e8b6, 0x00000004 }, +- { 0x000d0016, 0x00000038 }, +- { 0x0000e854, 0x00000004 }, +- { 0x000d0018, 0x00000038 }, +- { 0x0000e855, 0x00000004 }, +- { 0x000d001a, 0x00000038 }, +- { 0x0000e856, 0x00000004 }, +- { 0x000d001c, 0x00000038 }, +- { 0x0000e857, 0x00000004 }, +- { 0x000d001e, 0x00000038 }, +- { 0x0000e824, 0x00000004 }, +- { 0x000d0020, 0x00000038 }, +- { 0x0000e825, 0x00000004 }, +- { 0x000d0022, 0x00000038 }, +- { 0x0000e830, 0x00000004 }, +- { 0x000d0024, 0x00000038 }, +- { 0x0000f0c0, 0x00000004 }, +- { 0x000d0026, 0x00000038 }, +- { 0x0000f0c1, 0x00000004 }, +- { 0x000d0028, 0x00000038 }, +- { 0x0000f041, 0x00000004 }, +- { 0x000d002a, 0x00000038 }, +- { 0x0000f184, 0x00000004 }, +- { 0x000d002c, 0x00000038 }, +- { 0x0000f185, 0x00000004 }, +- { 0x000d002e, 0x00000038 }, +- { 0x0000f186, 0x00000004 }, +- { 0x000d0030, 0x00000038 }, +- { 0x0000f187, 0x00000004 }, +- { 0x000d0032, 0x00000038 }, +- { 0x0000f180, 0x00000004 }, +- { 0x000d0034, 0x00000038 }, +- { 0x0000f393, 0x00000004 }, +- { 0x000d0036, 0x00000038 }, +- { 0x0000f38a, 0x00000004 }, +- { 0x000d0038, 0x00000038 }, +- { 0x0000f38e, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000043, 0x00000018 }, +- { 0x00cce800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x0000003a, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x2000451d, 0x00000004 }, +- { 0x0000e580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x08004580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x00000047, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x00032000, 0x00000004 }, +- { 0x00022051, 0x00000028 }, +- { 0x00000051, 0x00000024 }, +- { 0x0800450f, 0x00000004 }, +- { 0x0000a04b, 0x00000008 }, +- { 0x0000e565, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000052, 0x00000008 }, +- { 0x03cca5b4, 0x00000004 }, +- { 0x05432000, 0x00000004 }, +- { 0x00022000, 0x00000004 }, +- { 0x4ccce05e, 0x00000030 }, +- { 0x08274565, 0x00000004 }, +- { 0x0000005e, 0x00000030 }, +- { 0x08004564, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000055, 0x00000008 }, +- { 0x00802061, 0x00000010 }, +- { 0x00202000, 0x00000004 }, +- { 0x001b00ff, 0x00000004 }, +- { 0x01000064, 0x00000010 }, +- { 0x001f2000, 0x00000004 }, +- { 0x001c00ff, 0x00000004 }, +- { 0000000000, 0x0000000c }, +- { 0x00000072, 0x00000030 }, +- { 0x00000055, 0x00000008 }, +- { 0x0000e576, 0x00000004 }, +- { 0x0000e577, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x0000e50f, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000069, 0x00000018 }, +- { 0x00c0e5f9, 0x000000c2 }, +- { 0x00000069, 0x00000008 }, +- { 0x0014e50e, 0x00000004 }, +- { 0x0040e50f, 0x00000004 }, +- { 0x00c0006c, 0x00000008 }, +- { 0x0000e570, 0x00000004 }, +- { 0x0000e571, 0x00000004 }, +- { 0x0000e572, 0x0000000c }, +- { 0x0000a000, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x0000e568, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00000076, 0x00000018 }, +- { 0x000b0000, 0x00000004 }, +- { 0x18c0e562, 0x00000004 }, +- { 0x00000078, 0x00000008 }, +- { 0x00c00077, 0x00000008 }, +- { 0x000700cb, 0x00000004 }, +- { 0x00000084, 0x00000038 }, +- { 0x000ca086, 0x00000030 }, +- { 0x080045bb, 0x00000004 }, +- { 0x000c2087, 0x00000030 }, +- { 0x0800e5bc, 0000000000 }, +- { 0x0000e5bb, 0x00000004 }, +- { 0x0000e5bc, 0000000000 }, +- { 0x00120000, 0x0000000c }, +- { 0x00120000, 0x00000004 }, +- { 0x001b0002, 0x0000000c }, +- { 0x0000a000, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e800, 0000000000 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e82e, 0000000000 }, +- { 0x02cca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000ce1cc, 0x00000004 }, +- { 0x050de1cd, 0x00000004 }, +- { 0x00400000, 0x00000004 }, +- { 0x00000096, 0x00000018 }, +- { 0x00c0a000, 0x00000004 }, +- { 0x00000093, 0x00000008 }, +- { 0x00000098, 0x00000020 }, +- { 0x4200e000, 0000000000 }, +- { 0x0000009f, 0x00000038 }, +- { 0x000ca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00160000, 0x00000004 }, +- { 0x700ce000, 0x00000004 }, +- { 0x0014009b, 0x00000008 }, +- { 0x4000e000, 0000000000 }, +- { 0x02400000, 0x00000004 }, +- { 0x400ee000, 0x00000004 }, +- { 0x02400000, 0x00000004 }, +- { 0x4000e000, 0000000000 }, +- { 0x00100000, 0x0000002c }, +- { 0x00004000, 0000000000 }, +- { 0x080045c8, 0x00000004 }, +- { 0x00240005, 0x00000004 }, +- { 0x08004d0b, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0240e51b, 0x00000004 }, +- { 0x0080e50a, 0x00000005 }, +- { 0x0080e50b, 0x00000005 }, +- { 0x00220000, 0x00000004 }, +- { 0x000700cb, 0x00000004 }, +- { 0x000000b7, 0x00000038 }, +- { 0x000c2087, 0x00000030 }, +- { 0x0880e5bd, 0x00000005 }, +- { 0x000c2086, 0x00000030 }, +- { 0x0800e5bb, 0x00000005 }, +- { 0x000c2087, 0x00000030 }, +- { 0x0880e5bc, 0x00000005 }, +- { 0x000000ba, 0x00000008 }, +- { 0x0080e5bd, 0x00000005 }, +- { 0x0000e5bb, 0x00000005 }, +- { 0x0080e5bc, 0x00000005 }, +- { 0x00210000, 0x00000004 }, +- { 0x02800000, 0x00000004 }, +- { 0x00c000be, 0x00000018 }, +- { 0x4180e000, 0x00000040 }, +- { 0x000000c0, 0x00000024 }, +- { 0x01000000, 0x0000000c }, +- { 0x0100e51d, 0x0000000c }, +- { 0x000045bb, 0x00000004 }, +- { 0x000080ba, 0x00000008 }, +- { 0x03c00830, 0x00000004 }, +- { 0x4200e000, 0000000000 }, +- { 0x0000a000, 0x00000004 }, +- { 0x200045e0, 0x00000004 }, +- { 0x0000e5e1, 0000000000 }, +- { 0x00000001, 0000000000 }, +- { 0x000700c8, 0x00000004 }, +- { 0x0800e394, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x0000e8c4, 0x00000004 }, +- { 0x0000e8c5, 0x00000004 }, +- { 0x0000e8c6, 0x00000004 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000cc, 0x00000008 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000d3, 0x00000008 }, +- { 0x02c02000, 0x00000004 }, +- { 0x00060000, 0x00000004 }, +- { 0x000000db, 0x00000034 }, +- { 0x000000d8, 0x00000008 }, +- { 0x00008000, 0x00000004 }, +- { 0xc000e000, 0000000000 }, +- { 0x000000e1, 0x00000030 }, +- { 0x4200e000, 0000000000 }, +- { 0x000000e1, 0x00000030 }, +- { 0x4000e000, 0000000000 }, +- { 0x0025001b, 0x00000004 }, +- { 0x00230000, 0x00000004 }, +- { 0x00250005, 0x00000004 }, +- { 0x000000e6, 0x00000034 }, +- { 0000000000, 0x0000000c }, +- { 0x00244000, 0x00000004 }, +- { 0x080045c8, 0x00000004 }, +- { 0x00240005, 0x00000004 }, +- { 0x08004d0b, 0x0000000c }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x001d0018, 0x00000004 }, +- { 0x001a0001, 0x00000004 }, +- { 0x000000fb, 0x00000034 }, +- { 0x0000004a, 0x00000008 }, +- { 0x0500a04a, 0x00000008 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +-}; +- +-static const u32 R520_cp_microcode[][2] = { +- { 0x4200e000, 0000000000 }, +- { 0x4000e000, 0000000000 }, +- { 0x00000099, 0x00000008 }, +- { 0x0000009d, 0x00000008 }, +- { 0x4a554b4a, 0000000000 }, +- { 0x4a4a4467, 0000000000 }, +- { 0x55526f75, 0000000000 }, +- { 0x4a7e7d65, 0000000000 }, +- { 0xe0dae6f6, 0000000000 }, +- { 0x4ac54a4a, 0000000000 }, +- { 0xc8828282, 0000000000 }, +- { 0xbf4acfc1, 0000000000 }, +- { 0x87b04ad5, 0000000000 }, +- { 0xb5838383, 0000000000 }, +- { 0x4a0f85ba, 0000000000 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000d0012, 0x00000038 }, +- { 0x0000e8b4, 0x00000004 }, +- { 0x000d0014, 0x00000038 }, +- { 0x0000e8b6, 0x00000004 }, +- { 0x000d0016, 0x00000038 }, +- { 0x0000e854, 0x00000004 }, +- { 0x000d0018, 0x00000038 }, +- { 0x0000e855, 0x00000004 }, +- { 0x000d001a, 0x00000038 }, +- { 0x0000e856, 0x00000004 }, +- { 0x000d001c, 0x00000038 }, +- { 0x0000e857, 0x00000004 }, +- { 0x000d001e, 0x00000038 }, +- { 0x0000e824, 0x00000004 }, +- { 0x000d0020, 0x00000038 }, +- { 0x0000e825, 0x00000004 }, +- { 0x000d0022, 0x00000038 }, +- { 0x0000e830, 0x00000004 }, +- { 0x000d0024, 0x00000038 }, +- { 0x0000f0c0, 0x00000004 }, +- { 0x000d0026, 0x00000038 }, +- { 0x0000f0c1, 0x00000004 }, +- { 0x000d0028, 0x00000038 }, +- { 0x0000e000, 0x00000004 }, +- { 0x000d002a, 0x00000038 }, +- { 0x0000e000, 0x00000004 }, +- { 0x000d002c, 0x00000038 }, +- { 0x0000e000, 0x00000004 }, +- { 0x000d002e, 0x00000038 }, +- { 0x0000e000, 0x00000004 }, +- { 0x000d0030, 0x00000038 }, +- { 0x0000e000, 0x00000004 }, +- { 0x000d0032, 0x00000038 }, +- { 0x0000f180, 0x00000004 }, +- { 0x000d0034, 0x00000038 }, +- { 0x0000f393, 0x00000004 }, +- { 0x000d0036, 0x00000038 }, +- { 0x0000f38a, 0x00000004 }, +- { 0x000d0038, 0x00000038 }, +- { 0x0000f38e, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000043, 0x00000018 }, +- { 0x00cce800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x08004800, 0x00000004 }, +- { 0x0000003a, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x2000451d, 0x00000004 }, +- { 0x0000e580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x08004580, 0x00000004 }, +- { 0x000ce581, 0x00000004 }, +- { 0x00000047, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x00032000, 0x00000004 }, +- { 0x00022051, 0x00000028 }, +- { 0x00000051, 0x00000024 }, +- { 0x0800450f, 0x00000004 }, +- { 0x0000a04b, 0x00000008 }, +- { 0x0000e565, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000052, 0x00000008 }, +- { 0x03cca5b4, 0x00000004 }, +- { 0x05432000, 0x00000004 }, +- { 0x00022000, 0x00000004 }, +- { 0x4ccce05e, 0x00000030 }, +- { 0x08274565, 0x00000004 }, +- { 0x0000005e, 0x00000030 }, +- { 0x08004564, 0x00000004 }, +- { 0x0000e566, 0x00000004 }, +- { 0x00000055, 0x00000008 }, +- { 0x00802061, 0x00000010 }, +- { 0x00202000, 0x00000004 }, +- { 0x001b00ff, 0x00000004 }, +- { 0x01000064, 0x00000010 }, +- { 0x001f2000, 0x00000004 }, +- { 0x001c00ff, 0x00000004 }, +- { 0000000000, 0x0000000c }, +- { 0x00000072, 0x00000030 }, +- { 0x00000055, 0x00000008 }, +- { 0x0000e576, 0x00000004 }, +- { 0x0000e577, 0x00000004 }, +- { 0x0000e50e, 0x00000004 }, +- { 0x0000e50f, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00000069, 0x00000018 }, +- { 0x00c0e5f9, 0x000000c2 }, +- { 0x00000069, 0x00000008 }, +- { 0x0014e50e, 0x00000004 }, +- { 0x0040e50f, 0x00000004 }, +- { 0x00c0006c, 0x00000008 }, +- { 0x0000e570, 0x00000004 }, +- { 0x0000e571, 0x00000004 }, +- { 0x0000e572, 0x0000000c }, +- { 0x0000a000, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x0000e568, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00000076, 0x00000018 }, +- { 0x000b0000, 0x00000004 }, +- { 0x18c0e562, 0x00000004 }, +- { 0x00000078, 0x00000008 }, +- { 0x00c00077, 0x00000008 }, +- { 0x000700c7, 0x00000004 }, +- { 0x00000080, 0x00000038 }, +- { 0x0000e5bb, 0x00000004 }, +- { 0x0000e5bc, 0000000000 }, +- { 0x0000a000, 0x00000004 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e800, 0000000000 }, +- { 0x0000e821, 0x00000004 }, +- { 0x0000e82e, 0000000000 }, +- { 0x02cca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000ce1cc, 0x00000004 }, +- { 0x050de1cd, 0x00000004 }, +- { 0x00400000, 0x00000004 }, +- { 0x0000008f, 0x00000018 }, +- { 0x00c0a000, 0x00000004 }, +- { 0x0000008c, 0x00000008 }, +- { 0x00000091, 0x00000020 }, +- { 0x4200e000, 0000000000 }, +- { 0x00000098, 0x00000038 }, +- { 0x000ca000, 0x00000004 }, +- { 0x00140000, 0x00000004 }, +- { 0x000c2000, 0x00000004 }, +- { 0x00160000, 0x00000004 }, +- { 0x700ce000, 0x00000004 }, +- { 0x00140094, 0x00000008 }, +- { 0x4000e000, 0000000000 }, +- { 0x02400000, 0x00000004 }, +- { 0x400ee000, 0x00000004 }, +- { 0x02400000, 0x00000004 }, +- { 0x4000e000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x0240e51b, 0x00000004 }, +- { 0x0080e50a, 0x00000005 }, +- { 0x0080e50b, 0x00000005 }, +- { 0x00220000, 0x00000004 }, +- { 0x000700c7, 0x00000004 }, +- { 0x000000a4, 0x00000038 }, +- { 0x0080e5bd, 0x00000005 }, +- { 0x0000e5bb, 0x00000005 }, +- { 0x0080e5bc, 0x00000005 }, +- { 0x00210000, 0x00000004 }, +- { 0x02800000, 0x00000004 }, +- { 0x00c000ab, 0x00000018 }, +- { 0x4180e000, 0x00000040 }, +- { 0x000000ad, 0x00000024 }, +- { 0x01000000, 0x0000000c }, +- { 0x0100e51d, 0x0000000c }, +- { 0x000045bb, 0x00000004 }, +- { 0x000080a7, 0x00000008 }, +- { 0x0000f3ce, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c053cf, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x0000f3d2, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c053d3, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x0000f39d, 0x00000004 }, +- { 0x0140a000, 0x00000004 }, +- { 0x00cc2000, 0x00000004 }, +- { 0x08c0539e, 0x00000040 }, +- { 0x00008000, 0000000000 }, +- { 0x03c00830, 0x00000004 }, +- { 0x4200e000, 0000000000 }, +- { 0x0000a000, 0x00000004 }, +- { 0x200045e0, 0x00000004 }, +- { 0x0000e5e1, 0000000000 }, +- { 0x00000001, 0000000000 }, +- { 0x000700c4, 0x00000004 }, +- { 0x0800e394, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x0000e8c4, 0x00000004 }, +- { 0x0000e8c5, 0x00000004 }, +- { 0x0000e8c6, 0x00000004 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000c8, 0x00000008 }, +- { 0x0000e928, 0x00000004 }, +- { 0x0000e929, 0x00000004 }, +- { 0x0000e92a, 0x00000004 }, +- { 0x000000cf, 0x00000008 }, +- { 0xdeadbeef, 0000000000 }, +- { 0x00000116, 0000000000 }, +- { 0x000700d3, 0x00000004 }, +- { 0x080050e7, 0x00000004 }, +- { 0x000700d4, 0x00000004 }, +- { 0x0800401c, 0x00000004 }, +- { 0x0000e01d, 0000000000 }, +- { 0x02c02000, 0x00000004 }, +- { 0x00060000, 0x00000004 }, +- { 0x000000de, 0x00000034 }, +- { 0x000000db, 0x00000008 }, +- { 0x00008000, 0x00000004 }, +- { 0xc000e000, 0000000000 }, +- { 0x0000e1cc, 0x00000004 }, +- { 0x0500e1cd, 0x00000004 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000000e5, 0x00000034 }, +- { 0x000000e1, 0x00000008 }, +- { 0x0000a000, 0000000000 }, +- { 0x0019e1cc, 0x00000004 }, +- { 0x001b0001, 0x00000004 }, +- { 0x0500a000, 0x00000004 }, +- { 0x080041cd, 0x00000004 }, +- { 0x000ca000, 0x00000004 }, +- { 0x000000fb, 0x00000034 }, +- { 0x0000004a, 0x00000008 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0x000c2000, 0x00000004 }, +- { 0x001d0018, 0x00000004 }, +- { 0x001a0001, 0x00000004 }, +- { 0x000000fb, 0x00000034 }, +- { 0x0000004a, 0x00000008 }, +- { 0x0500a04a, 0x00000008 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +- { 0000000000, 0000000000 }, +-}; +- +- +-#endif +diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h +index 3b09a1f..570a587 100644 +--- a/drivers/gpu/drm/radeon/radeon_mode.h ++++ b/drivers/gpu/drm/radeon/radeon_mode.h +@@ -175,6 +175,15 @@ struct radeon_mode_info { + enum radeon_connector_table connector_table; + bool mode_config_initialized; + struct radeon_crtc *crtcs[2]; ++ /* DVI-I properties */ ++ struct drm_property *coherent_mode_property; ++ /* DAC enable load detect */ ++ struct drm_property *load_detect_property; ++ /* TV standard load detect */ ++ struct drm_property *tv_std_property; ++ /* legacy TMDS PLL detect */ ++ struct drm_property *tmds_pll_property; ++ + }; + + struct radeon_native_mode { +@@ -188,6 +197,21 @@ struct radeon_native_mode { + uint32_t flags; + }; + ++#define MAX_H_CODE_TIMING_LEN 32 ++#define MAX_V_CODE_TIMING_LEN 32 ++ ++/* need to store these as reading ++ back code tables is excessive */ ++struct radeon_tv_regs { ++ uint32_t tv_uv_adr; ++ uint32_t timing_cntl; ++ uint32_t hrestart; ++ uint32_t vrestart; ++ uint32_t frestart; ++ uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; ++ uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; ++}; ++ + struct radeon_crtc { + struct drm_crtc base; + int crtc_id; +@@ -195,8 +219,6 @@ struct radeon_crtc { + bool enabled; + bool can_tile; + uint32_t crtc_offset; +- struct radeon_framebuffer *fbdev_fb; +- struct drm_mode_set mode_set; + struct drm_gem_object *cursor_bo; + uint64_t cursor_addr; + int cursor_width; +@@ -204,7 +226,6 @@ struct radeon_crtc { + uint32_t legacy_display_base_addr; + uint32_t legacy_cursor_offset; + enum radeon_rmx_type rmx_type; +- uint32_t devices; + fixed20_12 vsc; + fixed20_12 hsc; + struct radeon_native_mode native_mode; +@@ -236,7 +257,13 @@ struct radeon_encoder_tv_dac { + uint32_t ntsc_tvdac_adj; + uint32_t pal_tvdac_adj; + ++ int h_pos; ++ int v_pos; ++ int h_size; ++ int supported_tv_stds; ++ bool tv_on; + enum radeon_tv_std tv_std; ++ struct radeon_tv_regs tv; + }; + + struct radeon_encoder_int_tmds { +@@ -255,10 +282,15 @@ struct radeon_encoder_atom_dig { + struct radeon_native_mode native_mode; + }; + ++struct radeon_encoder_atom_dac { ++ enum radeon_tv_std tv_std; ++}; ++ + struct radeon_encoder { + struct drm_encoder base; + uint32_t encoder_id; + uint32_t devices; ++ uint32_t active_device; + uint32_t flags; + uint32_t pixel_clock; + enum radeon_rmx_type rmx_type; +@@ -276,8 +308,12 @@ struct radeon_connector { + uint32_t connector_id; + uint32_t devices; + struct radeon_i2c_chan *ddc_bus; +- int use_digital; ++ bool use_digital; ++ /* we need to mind the EDID between detect ++ and get modes due to analog/digital/tvencoder */ ++ struct edid *edid; + void *con_priv; ++ bool dac_load_detect; + }; + + struct radeon_framebuffer { +@@ -310,6 +346,7 @@ struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, i + struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); + extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); + extern int atombios_get_encoder_mode(struct drm_encoder *encoder); ++extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); + + extern void radeon_crtc_load_lut(struct drm_crtc *crtc); + extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, +@@ -337,16 +374,18 @@ extern bool radeon_atom_get_clock_info(struct drm_device *dev); + extern bool radeon_combios_get_clock_info(struct drm_device *dev); + extern struct radeon_encoder_atom_dig * + radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); +-extern struct radeon_encoder_int_tmds * +-radeon_atombios_get_tmds_info(struct radeon_encoder *encoder); ++bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, ++ struct radeon_encoder_int_tmds *tmds); ++bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, ++ struct radeon_encoder_int_tmds *tmds); ++bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, ++ struct radeon_encoder_int_tmds *tmds); + extern struct radeon_encoder_primary_dac * + radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); + extern struct radeon_encoder_tv_dac * + radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); + extern struct radeon_encoder_lvds * + radeon_combios_get_lvds_info(struct radeon_encoder *encoder); +-extern struct radeon_encoder_int_tmds * +-radeon_combios_get_tmds_info(struct radeon_encoder *encoder); + extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); + extern struct radeon_encoder_tv_dac * + radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); +@@ -356,6 +395,8 @@ extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); + extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); + extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); + extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); ++extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); ++extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); + extern void + radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); + extern void +@@ -396,6 +437,19 @@ extern int radeon_static_clocks_init(struct drm_device *dev); + bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); +-void atom_rv515_force_tv_scaler(struct radeon_device *rdev); +- ++void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); ++ ++/* legacy tv */ ++void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, ++ uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, ++ uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); ++void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, ++ uint32_t *htotal_cntl, uint32_t *ppll_ref_div, ++ uint32_t *ppll_div_3, uint32_t *pixclks_cntl); ++void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, ++ uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, ++ uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); ++void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode); + #endif +diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c +index b85fb83..73af463 100644 +--- a/drivers/gpu/drm/radeon/radeon_object.c ++++ b/drivers/gpu/drm/radeon/radeon_object.c +@@ -188,6 +188,7 @@ int radeon_object_kmap(struct radeon_object *robj, void **ptr) + if (ptr) { + *ptr = robj->kptr; + } ++ radeon_object_check_tiling(robj, 0, 0); + return 0; + } + +@@ -200,6 +201,7 @@ void radeon_object_kunmap(struct radeon_object *robj) + } + robj->kptr = NULL; + spin_unlock(&robj->tobj.lock); ++ radeon_object_check_tiling(robj, 0, 0); + ttm_bo_kunmap(&robj->kmap); + } + +@@ -369,6 +371,14 @@ void radeon_object_force_delete(struct radeon_device *rdev) + + int radeon_object_init(struct radeon_device *rdev) + { ++ /* Add an MTRR for the VRAM */ ++ rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, ++ MTRR_TYPE_WRCOMB, 1); ++ DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", ++ rdev->mc.mc_vram_size >> 20, ++ (unsigned long long)rdev->mc.aper_size >> 20); ++ DRM_INFO("RAM width %dbits %cDR\n", ++ rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); + return radeon_ttm_init(rdev); + } + +diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h +index 473e477..10e8af6 100644 +--- a/drivers/gpu/drm/radeon/radeon_object.h ++++ b/drivers/gpu/drm/radeon/radeon_object.h +@@ -37,6 +37,7 @@ + * TTM. + */ + struct radeon_mman { ++ struct ttm_bo_global_ref bo_global_ref; + struct ttm_global_reference mem_global_ref; + bool mem_global_referenced; + struct ttm_bo_device bdev; +diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h +index 4df43f6..bfa1ab9 100644 +--- a/drivers/gpu/drm/radeon/radeon_reg.h ++++ b/drivers/gpu/drm/radeon/radeon_reg.h +@@ -1945,6 +1945,11 @@ + # define RADEON_TXFORMAT_DXT1 (12 << 0) + # define RADEON_TXFORMAT_DXT23 (14 << 0) + # define RADEON_TXFORMAT_DXT45 (15 << 0) ++# define RADEON_TXFORMAT_SHADOW16 (16 << 0) ++# define RADEON_TXFORMAT_SHADOW32 (17 << 0) ++# define RADEON_TXFORMAT_DUDV88 (18 << 0) ++# define RADEON_TXFORMAT_LDUDV655 (19 << 0) ++# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) + # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) + # define RADEON_TXFORMAT_FORMAT_SHIFT 0 + # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) +@@ -2203,7 +2208,7 @@ + # define RADEON_ROP_ENABLE (1 << 6) + # define RADEON_STENCIL_ENABLE (1 << 7) + # define RADEON_Z_ENABLE (1 << 8) +-# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) ++# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9) + # define RADEON_RB3D_COLOR_FORMAT_SHIFT 10 + + # define RADEON_COLOR_FORMAT_ARGB1555 3 +@@ -2773,7 +2778,12 @@ + # define R200_TXFORMAT_DXT1 (12 << 0) + # define R200_TXFORMAT_DXT23 (14 << 0) + # define R200_TXFORMAT_DXT45 (15 << 0) ++# define R200_TXFORMAT_DVDU88 (18 << 0) ++# define R200_TXFORMAT_LDVDU655 (19 << 0) ++# define R200_TXFORMAT_LDVDU8888 (20 << 0) ++# define R200_TXFORMAT_GR1616 (21 << 0) + # define R200_TXFORMAT_ABGR8888 (22 << 0) ++# define R200_TXFORMAT_BGR111110 (23 << 0) + # define R200_TXFORMAT_FORMAT_MASK (31 << 0) + # define R200_TXFORMAT_FORMAT_SHIFT 0 + # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) +@@ -2818,6 +2828,13 @@ + #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ + #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ + ++#define R200_PP_CUBIC_FACES_0 0x2c18 ++#define R200_PP_CUBIC_FACES_1 0x2c38 ++#define R200_PP_CUBIC_FACES_2 0x2c58 ++#define R200_PP_CUBIC_FACES_3 0x2c78 ++#define R200_PP_CUBIC_FACES_4 0x2c98 ++#define R200_PP_CUBIC_FACES_5 0x2cb8 ++ + #define R200_PP_TXOFFSET_0 0x2d00 + # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) + # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) +@@ -2829,11 +2846,44 @@ + # define R200_TXO_MICRO_TILE (1 << 3) + # define R200_TXO_OFFSET_MASK 0xffffffe0 + # define R200_TXO_OFFSET_SHIFT 5 ++#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 ++#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 ++#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c ++#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 ++#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 ++ + #define R200_PP_TXOFFSET_1 0x2d18 ++#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c ++#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 ++#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 ++#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 ++#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c ++ + #define R200_PP_TXOFFSET_2 0x2d30 ++#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 ++#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 ++#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c ++#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 ++#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 ++ + #define R200_PP_TXOFFSET_3 0x2d48 ++#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c ++#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 ++#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 ++#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 ++#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c + #define R200_PP_TXOFFSET_4 0x2d60 ++#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 ++#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 ++#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c ++#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 ++#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 + #define R200_PP_TXOFFSET_5 0x2d78 ++#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c ++#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 ++#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 ++#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 ++#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c + + #define R200_PP_TFACTOR_0 0x2ee0 + #define R200_PP_TFACTOR_1 0x2ee4 +@@ -3175,6 +3225,11 @@ + # define R200_FORCE_INORDER_PROC (1<<31) + #define R200_PP_CNTL_X 0x2cc4 + #define R200_PP_TXMULTI_CTL_0 0x2c1c ++#define R200_PP_TXMULTI_CTL_1 0x2c3c ++#define R200_PP_TXMULTI_CTL_2 0x2c5c ++#define R200_PP_TXMULTI_CTL_3 0x2c7c ++#define R200_PP_TXMULTI_CTL_4 0x2c9c ++#define R200_PP_TXMULTI_CTL_5 0x2cbc + #define R200_SE_VTX_STATE_CNTL 0x2180 + # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) + +@@ -3200,6 +3255,24 @@ + #define RADEON_CP_RB_WPTR 0x0714 + #define RADEON_CP_RB_RPTR_WR 0x071c + ++#define RADEON_SCRATCH_UMSK 0x0770 ++#define RADEON_SCRATCH_ADDR 0x0774 ++ ++#define R600_CP_RB_BASE 0xc100 ++#define R600_CP_RB_CNTL 0xc104 ++# define R600_RB_BUFSZ(x) ((x) << 0) ++# define R600_RB_BLKSZ(x) ((x) << 8) ++# define R600_RB_NO_UPDATE (1 << 27) ++# define R600_RB_RPTR_WR_ENA (1 << 31) ++#define R600_CP_RB_RPTR_WR 0xc108 ++#define R600_CP_RB_RPTR_ADDR 0xc10c ++#define R600_CP_RB_RPTR_ADDR_HI 0xc110 ++#define R600_CP_RB_WPTR 0xc114 ++#define R600_CP_RB_WPTR_ADDR 0xc118 ++#define R600_CP_RB_WPTR_ADDR_HI 0xc11c ++#define R600_CP_RB_RPTR 0x8700 ++#define R600_CP_RB_WPTR_DELAY 0x8704 ++ + #define RADEON_CP_IB_BASE 0x0738 + #define RADEON_CP_IB_BUFSZ 0x073c + +@@ -3260,6 +3333,7 @@ + # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) + # define RADEON_CP_PACKET0_REG_MASK 0x000007ff + # define R300_CP_PACKET0_REG_MASK 0x00001fff ++# define R600_CP_PACKET0_REG_MASK 0x0000ffff + # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff + # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 + +@@ -3407,7 +3481,9 @@ + # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) + # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 + # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 +-# define RADEON_TVOUT_SCALE_EN (1 << 26) ++# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) ++# define RADEON_TVOUT_SCALE_EN (1 << 26) ++# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) + #define RADEON_TV_SYNC_CNTL 0x0808 + # define RADEON_SYNC_OE (1 << 0) + # define RADEON_SYNC_OUT (1 << 1) +diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c +index 60d1593..747b4bf 100644 +--- a/drivers/gpu/drm/radeon/radeon_ring.c ++++ b/drivers/gpu/drm/radeon/radeon_ring.c +@@ -56,10 +56,12 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) + set_bit(i, rdev->ib_pool.alloc_bm); + rdev->ib_pool.ibs[i].length_dw = 0; + *ib = &rdev->ib_pool.ibs[i]; ++ mutex_unlock(&rdev->ib_pool.mutex); + goto out; + } + if (list_empty(&rdev->ib_pool.scheduled_ibs)) { + /* we go do nothings here */ ++ mutex_unlock(&rdev->ib_pool.mutex); + DRM_ERROR("all IB allocated none scheduled.\n"); + r = -EINVAL; + goto out; +@@ -69,10 +71,13 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) + struct radeon_ib, list); + if (nib->fence == NULL) { + /* we go do nothings here */ ++ mutex_unlock(&rdev->ib_pool.mutex); + DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); + r = -EINVAL; + goto out; + } ++ mutex_unlock(&rdev->ib_pool.mutex); ++ + r = radeon_fence_wait(nib->fence, false); + if (r) { + DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, +@@ -81,12 +86,17 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) + goto out; + } + radeon_fence_unref(&nib->fence); ++ + nib->length_dw = 0; ++ ++ /* scheduled list is accessed here */ ++ mutex_lock(&rdev->ib_pool.mutex); + list_del(&nib->list); + INIT_LIST_HEAD(&nib->list); ++ mutex_unlock(&rdev->ib_pool.mutex); ++ + *ib = nib; + out: +- mutex_unlock(&rdev->ib_pool.mutex); + if (r) { + radeon_fence_unref(&fence); + } else { +@@ -111,47 +121,36 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) + } + list_del(&tmp->list); + INIT_LIST_HEAD(&tmp->list); +- if (tmp->fence) { ++ if (tmp->fence) + radeon_fence_unref(&tmp->fence); +- } ++ + tmp->length_dw = 0; + clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); + mutex_unlock(&rdev->ib_pool.mutex); + } + +-static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib) +-{ +- while ((ib->length_dw & rdev->cp.align_mask)) { +- ib->ptr[ib->length_dw++] = PACKET2(0); +- } +-} +- + int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) + { + int r = 0; + +- mutex_lock(&rdev->ib_pool.mutex); +- radeon_ib_align(rdev, ib); + if (!ib->length_dw || !rdev->cp.ready) { + /* TODO: Nothings in the ib we should report. */ +- mutex_unlock(&rdev->ib_pool.mutex); + DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); + return -EINVAL; + } ++ + /* 64 dwords should be enough for fence too */ + r = radeon_ring_lock(rdev, 64); + if (r) { + DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); +- mutex_unlock(&rdev->ib_pool.mutex); + return r; + } +- radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); +- radeon_ring_write(rdev, ib->gpu_addr); +- radeon_ring_write(rdev, ib->length_dw); ++ radeon_ring_ib_execute(rdev, ib); + radeon_fence_emit(rdev, ib->fence); +- radeon_ring_unlock_commit(rdev); ++ mutex_lock(&rdev->ib_pool.mutex); + list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); + mutex_unlock(&rdev->ib_pool.mutex); ++ radeon_ring_unlock_commit(rdev); + return 0; + } + +@@ -162,6 +161,8 @@ int radeon_ib_pool_init(struct radeon_device *rdev) + int i; + int r = 0; + ++ if (rdev->ib_pool.robj) ++ return 0; + /* Allocate 1M object buffer */ + INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); + r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, +@@ -215,69 +216,16 @@ void radeon_ib_pool_fini(struct radeon_device *rdev) + mutex_unlock(&rdev->ib_pool.mutex); + } + +-int radeon_ib_test(struct radeon_device *rdev) +-{ +- struct radeon_ib *ib; +- uint32_t scratch; +- uint32_t tmp = 0; +- unsigned i; +- int r; +- +- r = radeon_scratch_get(rdev, &scratch); +- if (r) { +- DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); +- return r; +- } +- WREG32(scratch, 0xCAFEDEAD); +- r = radeon_ib_get(rdev, &ib); +- if (r) { +- return r; +- } +- ib->ptr[0] = PACKET0(scratch, 0); +- ib->ptr[1] = 0xDEADBEEF; +- ib->ptr[2] = PACKET2(0); +- ib->ptr[3] = PACKET2(0); +- ib->ptr[4] = PACKET2(0); +- ib->ptr[5] = PACKET2(0); +- ib->ptr[6] = PACKET2(0); +- ib->ptr[7] = PACKET2(0); +- ib->length_dw = 8; +- r = radeon_ib_schedule(rdev, ib); +- if (r) { +- radeon_scratch_free(rdev, scratch); +- radeon_ib_free(rdev, &ib); +- return r; +- } +- r = radeon_fence_wait(ib->fence, false); +- if (r) { +- return r; +- } +- for (i = 0; i < rdev->usec_timeout; i++) { +- tmp = RREG32(scratch); +- if (tmp == 0xDEADBEEF) { +- break; +- } +- DRM_UDELAY(1); +- } +- if (i < rdev->usec_timeout) { +- DRM_INFO("ib test succeeded in %u usecs\n", i); +- } else { +- DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", +- scratch, tmp); +- r = -EINVAL; +- } +- radeon_scratch_free(rdev, scratch); +- radeon_ib_free(rdev, &ib); +- return r; +-} +- + + /* + * Ring. + */ + void radeon_ring_free_size(struct radeon_device *rdev) + { +- rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); ++ if (rdev->family >= CHIP_R600) ++ rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); ++ else ++ rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); + /* This works because ring_size is a power of 2 */ + rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); + rdev->cp.ring_free_dw -= rdev->cp.wptr; +@@ -320,11 +268,10 @@ void radeon_ring_unlock_commit(struct radeon_device *rdev) + count_dw_pad = (rdev->cp.align_mask + 1) - + (rdev->cp.wptr & rdev->cp.align_mask); + for (i = 0; i < count_dw_pad; i++) { +- radeon_ring_write(rdev, PACKET2(0)); ++ radeon_ring_write(rdev, 2 << 30); + } + DRM_MEMORYBARRIER(); +- WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); +- (void)RREG32(RADEON_CP_RB_WPTR); ++ radeon_cp_commit(rdev); + mutex_unlock(&rdev->cp.mutex); + } + +@@ -334,46 +281,6 @@ void radeon_ring_unlock_undo(struct radeon_device *rdev) + mutex_unlock(&rdev->cp.mutex); + } + +-int radeon_ring_test(struct radeon_device *rdev) +-{ +- uint32_t scratch; +- uint32_t tmp = 0; +- unsigned i; +- int r; +- +- r = radeon_scratch_get(rdev, &scratch); +- if (r) { +- DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); +- return r; +- } +- WREG32(scratch, 0xCAFEDEAD); +- r = radeon_ring_lock(rdev, 2); +- if (r) { +- DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); +- radeon_scratch_free(rdev, scratch); +- return r; +- } +- radeon_ring_write(rdev, PACKET0(scratch, 0)); +- radeon_ring_write(rdev, 0xDEADBEEF); +- radeon_ring_unlock_commit(rdev); +- for (i = 0; i < rdev->usec_timeout; i++) { +- tmp = RREG32(scratch); +- if (tmp == 0xDEADBEEF) { +- break; +- } +- DRM_UDELAY(1); +- } +- if (i < rdev->usec_timeout) { +- DRM_INFO("ring test succeeded in %d usecs\n", i); +- } else { +- DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", +- scratch, tmp); +- r = -EINVAL; +- } +- radeon_scratch_free(rdev, scratch); +- return r; +-} +- + int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) + { + int r; +diff --git a/drivers/gpu/drm/radeon/radeon_share.h b/drivers/gpu/drm/radeon/radeon_share.h +deleted file mode 100644 +index 63a7735..0000000 +--- a/drivers/gpu/drm/radeon/radeon_share.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * Copyright 2008 Advanced Micro Devices, Inc. +- * Copyright 2008 Red Hat Inc. +- * Copyright 2009 Jerome Glisse. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Dave Airlie +- * Alex Deucher +- * Jerome Glisse +- */ +-#ifndef __RADEON_SHARE_H__ +-#define __RADEON_SHARE_H__ +- +-void r100_vram_init_sizes(struct radeon_device *rdev); +- +-void rs690_line_buffer_adjust(struct radeon_device *rdev, +- struct drm_display_mode *mode1, +- struct drm_display_mode *mode2); +- +-void rv515_bandwidth_avivo_update(struct radeon_device *rdev); +- +-#endif +diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c +index 2882f40..38537d9 100644 +--- a/drivers/gpu/drm/radeon/radeon_state.c ++++ b/drivers/gpu/drm/radeon/radeon_state.c +@@ -1546,7 +1546,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev, + } while (i < nbox); + } + +-static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf) ++void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf) + { + drm_radeon_private_t *dev_priv = dev->dev_private; + struct drm_radeon_master_private *master_priv = master->driver_priv; +@@ -2213,7 +2213,10 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f + if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) + sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; + +- radeon_cp_dispatch_swap(dev, file_priv->master); ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ r600_cp_dispatch_swap(dev, file_priv); ++ else ++ radeon_cp_dispatch_swap(dev, file_priv->master); + sarea_priv->ctx_owner = 0; + + COMMIT_RING(); +@@ -2412,7 +2415,10 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); + +- ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image); ++ else ++ ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); + + return ret; + } +@@ -2495,8 +2501,9 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil + radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); + } + +- if (indirect->discard) ++ if (indirect->discard) { + radeon_cp_discard_buffer(dev, file_priv->master, buf); ++ } + + COMMIT_RING(); + return 0; +@@ -3027,7 +3034,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil + value = GET_SCRATCH(dev_priv, 2); + break; + case RADEON_PARAM_IRQ_NR: +- value = drm_dev_to_irq(dev); ++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) ++ value = 0; ++ else ++ value = drm_dev_to_irq(dev); + break; + case RADEON_PARAM_GART_BASE: + value = dev_priv->gart_vm_start; +@@ -3227,7 +3237,8 @@ struct drm_ioctl_desc radeon_ioctls[] = { + DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), +- DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH) ++ DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH), ++ DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH) + }; + + int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); +diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c +index 15c3531..c729cd1 100644 +--- a/drivers/gpu/drm/radeon/radeon_ttm.c ++++ b/drivers/gpu/drm/radeon/radeon_ttm.c +@@ -35,11 +35,14 @@ + #include <ttm/ttm_module.h> + #include <drm/drmP.h> + #include <drm/radeon_drm.h> ++#include <linux/seq_file.h> + #include "radeon_reg.h" + #include "radeon.h" + + #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) + ++static int radeon_ttm_debugfs_init(struct radeon_device *rdev); ++ + static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) + { + struct radeon_mman *mman; +@@ -77,9 +80,25 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) + global_ref->release = &radeon_ttm_mem_global_release; + r = ttm_global_item_ref(global_ref); + if (r != 0) { +- DRM_ERROR("Failed referencing a global TTM memory object.\n"); ++ DRM_ERROR("Failed setting up TTM memory accounting " ++ "subsystem.\n"); ++ return r; ++ } ++ ++ rdev->mman.bo_global_ref.mem_glob = ++ rdev->mman.mem_global_ref.object; ++ global_ref = &rdev->mman.bo_global_ref.ref; ++ global_ref->global_type = TTM_GLOBAL_TTM_BO; ++ global_ref->size = sizeof(struct ttm_bo_global); ++ global_ref->init = &ttm_bo_global_init; ++ global_ref->release = &ttm_bo_global_release; ++ r = ttm_global_item_ref(global_ref); ++ if (r != 0) { ++ DRM_ERROR("Failed setting up TTM BO subsystem.\n"); ++ ttm_global_item_unref(&rdev->mman.mem_global_ref); + return r; + } ++ + rdev->mman.mem_global_referenced = true; + return 0; + } +@@ -87,6 +106,7 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) + static void radeon_ttm_global_fini(struct radeon_device *rdev) + { + if (rdev->mman.mem_global_referenced) { ++ ttm_global_item_unref(&rdev->mman.bo_global_ref.ref); + ttm_global_item_unref(&rdev->mman.mem_global_ref); + rdev->mman.mem_global_referenced = false; + } +@@ -286,9 +306,11 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, + r = ttm_bo_move_ttm(bo, true, no_wait, new_mem); + out_cleanup: + if (tmp_mem.mm_node) { +- spin_lock(&rdev->mman.bdev.lru_lock); ++ struct ttm_bo_global *glob = rdev->mman.bdev.glob; ++ ++ spin_lock(&glob->lru_lock); + drm_mm_put_block(tmp_mem.mm_node); +- spin_unlock(&rdev->mman.bdev.lru_lock); ++ spin_unlock(&glob->lru_lock); + return r; + } + return r; +@@ -323,9 +345,11 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, + } + out_cleanup: + if (tmp_mem.mm_node) { +- spin_lock(&rdev->mman.bdev.lru_lock); ++ struct ttm_bo_global *glob = rdev->mman.bdev.glob; ++ ++ spin_lock(&glob->lru_lock); + drm_mm_put_block(tmp_mem.mm_node); +- spin_unlock(&rdev->mman.bdev.lru_lock); ++ spin_unlock(&glob->lru_lock); + return r; + } + return r; +@@ -352,9 +376,8 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, + radeon_move_null(bo, new_mem); + return 0; + } +- if (!rdev->cp.ready) { ++ if (!rdev->cp.ready || rdev->asic->copy == NULL) { + /* use memcpy */ +- DRM_ERROR("CP is not ready use memcpy.\n"); + goto memcpy; + } + +@@ -446,7 +469,7 @@ int radeon_ttm_init(struct radeon_device *rdev) + } + /* No others user of address space so set it to 0 */ + r = ttm_bo_device_init(&rdev->mman.bdev, +- rdev->mman.mem_global_ref.object, ++ rdev->mman.bo_global_ref.ref.object, + &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, + rdev->need_dma32); + if (r) { +@@ -471,7 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev) + return r; + } + DRM_INFO("radeon: %uM of VRAM memory ready\n", +- rdev->mc.real_vram_size / (1024 * 1024)); ++ (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); + r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0, + ((rdev->mc.gtt_size) >> PAGE_SHIFT)); + if (r) { +@@ -479,10 +502,16 @@ int radeon_ttm_init(struct radeon_device *rdev) + return r; + } + DRM_INFO("radeon: %uM of GTT memory ready.\n", +- rdev->mc.gtt_size / (1024 * 1024)); ++ (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); + if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { + rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; + } ++ ++ r = radeon_ttm_debugfs_init(rdev); ++ if (r) { ++ DRM_ERROR("Failed to init debugfs\n"); ++ return r; ++ } + return 0; + } + +@@ -657,3 +686,49 @@ struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev) + gtt->bound = false; + return >t->backend; + } ++ ++#define RADEON_DEBUGFS_MEM_TYPES 2 ++ ++#if defined(CONFIG_DEBUG_FS) ++static int radeon_mm_dump_table(struct seq_file *m, void *data) ++{ ++ struct drm_info_node *node = (struct drm_info_node *)m->private; ++ struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; ++ struct drm_device *dev = node->minor->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ int ret; ++ struct ttm_bo_global *glob = rdev->mman.bdev.glob; ++ ++ spin_lock(&glob->lru_lock); ++ ret = drm_mm_dump_table(m, mm); ++ spin_unlock(&glob->lru_lock); ++ return ret; ++} ++#endif ++ ++static int radeon_ttm_debugfs_init(struct radeon_device *rdev) ++{ ++#if defined(CONFIG_DEBUG_FS) ++ static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES]; ++ static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32]; ++ unsigned i; ++ ++ for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { ++ if (i == 0) ++ sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); ++ else ++ sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); ++ radeon_mem_types_list[i].name = radeon_mem_types_names[i]; ++ radeon_mem_types_list[i].show = &radeon_mm_dump_table; ++ radeon_mem_types_list[i].driver_features = 0; ++ if (i == 0) ++ radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].manager; ++ else ++ radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].manager; ++ ++ } ++ return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES); ++ ++#endif ++ return 0; ++} +diff --git a/drivers/gpu/drm/radeon/reg_srcs/r100 b/drivers/gpu/drm/radeon/reg_srcs/r100 +new file mode 100644 +index 0000000..f7ee062 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/reg_srcs/r100 +@@ -0,0 +1,105 @@ ++r100 0x3294 ++0x1434 SRC_Y_X ++0x1438 DST_Y_X ++0x143C DST_HEIGHT_WIDTH ++0x146C DP_GUI_MASTER_CNTL ++0x1474 BRUSH_Y_X ++0x1478 DP_BRUSH_BKGD_CLR ++0x147C DP_BRUSH_FRGD_CLR ++0x1480 BRUSH_DATA0 ++0x1484 BRUSH_DATA1 ++0x1598 DST_WIDTH_HEIGHT ++0x15C0 CLR_CMP_CNTL ++0x15C4 CLR_CMP_CLR_SRC ++0x15C8 CLR_CMP_CLR_DST ++0x15CC CLR_CMP_MSK ++0x15D8 DP_SRC_FRGD_CLR ++0x15DC DP_SRC_BKGD_CLR ++0x1600 DST_LINE_START ++0x1604 DST_LINE_END ++0x1608 DST_LINE_PATCOUNT ++0x16C0 DP_CNTL ++0x16CC DP_WRITE_MSK ++0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR ++0x16E8 DEFAULT_SC_BOTTOM_RIGHT ++0x16EC SC_TOP_LEFT ++0x16F0 SC_BOTTOM_RIGHT ++0x16F4 SRC_SC_BOTTOM_RIGHT ++0x1714 DSTCACHE_CTLSTAT ++0x1720 WAIT_UNTIL ++0x172C RBBM_GUICNTL ++0x1810 FOG_3D_TABLE_START ++0x1814 FOG_3D_TABLE_END ++0x1a14 FOG_TABLE_INDEX ++0x1a18 FOG_TABLE_DATA ++0x1c14 PP_MISC ++0x1c18 PP_FOG_COLOR ++0x1c1c RE_SOLID_COLOR ++0x1c20 RB3D_BLENDCNTL ++0x1c4c SE_CNTL ++0x1c50 SE_COORD_FMT ++0x1c60 PP_TXCBLEND_0 ++0x1c64 PP_TXABLEND_0 ++0x1c68 PP_TFACTOR_0 ++0x1c78 PP_TXCBLEND_1 ++0x1c7c PP_TXABLEND_1 ++0x1c80 PP_TFACTOR_1 ++0x1c90 PP_TXCBLEND_2 ++0x1c94 PP_TXABLEND_2 ++0x1c98 PP_TFACTOR_2 ++0x1cc8 RE_STIPPLE_ADDR ++0x1ccc RE_STIPPLE_DATA ++0x1cd0 RE_LINE_PATTERN ++0x1cd4 RE_LINE_STATE ++0x1d40 PP_BORDER_COLOR0 ++0x1d44 PP_BORDER_COLOR1 ++0x1d48 PP_BORDER_COLOR2 ++0x1d7c RB3D_STENCILREFMASK ++0x1d80 RB3D_ROPCNTL ++0x1d84 RB3D_PLANEMASK ++0x1d98 VAP_VPORT_XSCALE ++0x1d9C VAP_VPORT_XOFFSET ++0x1da0 VAP_VPORT_YSCALE ++0x1da4 VAP_VPORT_YOFFSET ++0x1da8 VAP_VPORT_ZSCALE ++0x1dac VAP_VPORT_ZOFFSET ++0x1db0 SE_ZBIAS_FACTOR ++0x1db4 SE_ZBIAS_CONSTANT ++0x1db8 SE_LINE_WIDTH ++0x2140 SE_CNTL_STATUS ++0x2200 SE_TCL_VECTOR_INDX_REG ++0x2204 SE_TCL_VECTOR_DATA_REG ++0x2208 SE_TCL_SCALAR_INDX_REG ++0x220c SE_TCL_SCALAR_DATA_REG ++0x2210 SE_TCL_MATERIAL_EMISSIVE_RED ++0x2214 SE_TCL_MATERIAL_EMISSIVE_GREEN ++0x2218 SE_TCL_MATERIAL_EMISSIVE_BLUE ++0x221c SE_TCL_MATERIAL_EMISSIVE_ALPHA ++0x2220 SE_TCL_MATERIAL_AMBIENT_RED ++0x2224 SE_TCL_MATERIAL_AMBIENT_GREEN ++0x2228 SE_TCL_MATERIAL_AMBIENT_BLUE ++0x222c SE_TCL_MATERIAL_AMBIENT_ALPHA ++0x2230 SE_TCL_MATERIAL_DIFFUSE_RED ++0x2234 SE_TCL_MATERIAL_DIFFUSE_GREEN ++0x2238 SE_TCL_MATERIAL_DIFFUSE_BLUE ++0x223c SE_TCL_MATERIAL_DIFFUSE_ALPHA ++0x2240 SE_TCL_MATERIAL_SPECULAR_RED ++0x2244 SE_TCL_MATERIAL_SPECULAR_GREEN ++0x2248 SE_TCL_MATERIAL_SPECULAR_BLUE ++0x224c SE_TCL_MATERIAL_SPECULAR_ALPHA ++0x2250 SE_TCL_SHININESS ++0x2254 SE_TCL_OUTPUT_VTX_FMT ++0x2258 SE_TCL_OUTPUT_VTX_SEL ++0x225c SE_TCL_MATRIX_SELECT_0 ++0x2260 SE_TCL_MATRIX_SELECT_1 ++0x2264 SE_TCL_UCP_VERT_BLEND_CNTL ++0x2268 SE_TCL_TEXTURE_PROC_CTL ++0x226c SE_TCL_LIGHT_MODEL_CTL ++0x2270 SE_TCL_PER_LIGHT_CTL_0 ++0x2274 SE_TCL_PER_LIGHT_CTL_1 ++0x2278 SE_TCL_PER_LIGHT_CTL_2 ++0x227c SE_TCL_PER_LIGHT_CTL_3 ++0x2284 SE_TCL_STATE_FLUSH ++0x26c0 RE_TOP_LEFT ++0x26c4 RE_MISC ++0x3290 RB3D_ZPASS_DATA +diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200 +new file mode 100644 +index 0000000..6021c88 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/reg_srcs/r200 +@@ -0,0 +1,184 @@ ++r200 0x3294 ++0x1434 SRC_Y_X ++0x1438 DST_Y_X ++0x143C DST_HEIGHT_WIDTH ++0x146C DP_GUI_MASTER_CNTL ++0x1474 BRUSH_Y_X ++0x1478 DP_BRUSH_BKGD_CLR ++0x147C DP_BRUSH_FRGD_CLR ++0x1480 BRUSH_DATA0 ++0x1484 BRUSH_DATA1 ++0x1598 DST_WIDTH_HEIGHT ++0x15C0 CLR_CMP_CNTL ++0x15C4 CLR_CMP_CLR_SRC ++0x15C8 CLR_CMP_CLR_DST ++0x15CC CLR_CMP_MSK ++0x15D8 DP_SRC_FRGD_CLR ++0x15DC DP_SRC_BKGD_CLR ++0x1600 DST_LINE_START ++0x1604 DST_LINE_END ++0x1608 DST_LINE_PATCOUNT ++0x16C0 DP_CNTL ++0x16CC DP_WRITE_MSK ++0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR ++0x16E8 DEFAULT_SC_BOTTOM_RIGHT ++0x16EC SC_TOP_LEFT ++0x16F0 SC_BOTTOM_RIGHT ++0x16F4 SRC_SC_BOTTOM_RIGHT ++0x1714 DSTCACHE_CTLSTAT ++0x1720 WAIT_UNTIL ++0x172C RBBM_GUICNTL ++0x1c14 PP_MISC ++0x1c18 PP_FOG_COLOR ++0x1c1c RE_SOLID_COLOR ++0x1c20 RB3D_BLENDCNTL ++0x1c4c SE_CNTL ++0x1c50 RE_CNTL ++0x1cc8 RE_STIPPLE_ADDR ++0x1ccc RE_STIPPLE_DATA ++0x1cd0 RE_LINE_PATTERN ++0x1cd4 RE_LINE_STATE ++0x1cd8 RE_SCISSOR_TL_0 ++0x1cdc RE_SCISSOR_BR_0 ++0x1ce0 RE_SCISSOR_TL_1 ++0x1ce4 RE_SCISSOR_BR_1 ++0x1ce8 RE_SCISSOR_TL_2 ++0x1cec RE_SCISSOR_BR_2 ++0x1d60 RB3D_DEPTHXY_OFFSET ++0x1d7c RB3D_STENCILREFMASK ++0x1d80 RB3D_ROPCNTL ++0x1d84 RB3D_PLANEMASK ++0x1d98 VAP_VPORT_XSCALE ++0x1d9c VAP_VPORT_XOFFSET ++0x1da0 VAP_VPORT_YSCALE ++0x1da4 VAP_VPORT_YOFFSET ++0x1da8 VAP_VPORT_ZSCALE ++0x1dac VAP_VPORT_ZOFFSET ++0x1db0 SE_ZBIAS_FACTOR ++0x1db4 SE_ZBIAS_CONSTANT ++0x1db8 SE_LINE_WIDTH ++0x2080 SE_VAP_CNTL ++0x2090 SE_TCL_OUTPUT_VTX_FMT_0 ++0x2094 SE_TCL_OUTPUT_VTX_FMT_1 ++0x20b0 SE_VTE_CNTL ++0x2140 SE_CNTL_STATUS ++0x2180 SE_VTX_STATE_CNTL ++0x2200 SE_TCL_VECTOR_INDX_REG ++0x2204 SE_TCL_VECTOR_DATA_REG ++0x2208 SE_TCL_SCALAR_INDX_REG ++0x220c SE_TCL_SCALAR_DATA_REG ++0x2230 SE_TCL_MATRIX_SEL_0 ++0x2234 SE_TCL_MATRIX_SEL_1 ++0x2238 SE_TCL_MATRIX_SEL_2 ++0x223c SE_TCL_MATRIX_SEL_3 ++0x2240 SE_TCL_MATRIX_SEL_4 ++0x2250 SE_TCL_OUTPUT_VTX_COMP_SEL ++0x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0 ++0x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1 ++0x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2 ++0x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3 ++0x2268 SE_TCL_LIGHT_MODEL_CTL_0 ++0x226c SE_TCL_LIGHT_MODEL_CTL_1 ++0x2270 SE_TCL_PER_LIGHT_CTL_0 ++0x2274 SE_TCL_PER_LIGHT_CTL_1 ++0x2278 SE_TCL_PER_LIGHT_CTL_2 ++0x227c SE_TCL_PER_LIGHT_CTL_3 ++0x2284 VAP_PVS_STATE_FLUSH_REG ++0x22a8 SE_TCL_TEX_PROC_CTL_2 ++0x22ac SE_TCL_TEX_PROC_CTL_3 ++0x22b0 SE_TCL_TEX_PROC_CTL_0 ++0x22b4 SE_TCL_TEX_PROC_CTL_1 ++0x22b8 SE_TCL_TEX_CYL_WRAP_CTL ++0x22c0 SE_TCL_UCP_VERT_BLEND_CNTL ++0x22c4 SE_TCL_POINT_SPRITE_CNTL ++0x2648 RE_POINTSIZE ++0x26c0 RE_TOP_LEFT ++0x26c4 RE_MISC ++0x26f0 RE_AUX_SCISSOR_CNTL ++0x2c14 PP_BORDER_COLOR_0 ++0x2c34 PP_BORDER_COLOR_1 ++0x2c54 PP_BORDER_COLOR_2 ++0x2c74 PP_BORDER_COLOR_3 ++0x2c94 PP_BORDER_COLOR_4 ++0x2cb4 PP_BORDER_COLOR_5 ++0x2cc4 PP_CNTL_X ++0x2cf8 PP_TRI_PERF ++0x2cfc PP_PERF_CNTL ++0x2d9c PP_TAM_DEBUG3 ++0x2ee0 PP_TFACTOR_0 ++0x2ee4 PP_TFACTOR_1 ++0x2ee8 PP_TFACTOR_2 ++0x2eec PP_TFACTOR_3 ++0x2ef0 PP_TFACTOR_4 ++0x2ef4 PP_TFACTOR_5 ++0x2ef8 PP_TFACTOR_6 ++0x2efc PP_TFACTOR_7 ++0x2f00 PP_TXCBLEND_0 ++0x2f04 PP_TXCBLEND2_0 ++0x2f08 PP_TXABLEND_0 ++0x2f0c PP_TXABLEND2_0 ++0x2f10 PP_TXCBLEND_1 ++0x2f14 PP_TXCBLEND2_1 ++0x2f18 PP_TXABLEND_1 ++0x2f1c PP_TXABLEND2_1 ++0x2f20 PP_TXCBLEND_2 ++0x2f24 PP_TXCBLEND2_2 ++0x2f28 PP_TXABLEND_2 ++0x2f2c PP_TXABLEND2_2 ++0x2f30 PP_TXCBLEND_3 ++0x2f34 PP_TXCBLEND2_3 ++0x2f38 PP_TXABLEND_3 ++0x2f3c PP_TXABLEND2_3 ++0x2f40 PP_TXCBLEND_4 ++0x2f44 PP_TXCBLEND2_4 ++0x2f48 PP_TXABLEND_4 ++0x2f4c PP_TXABLEND2_4 ++0x2f50 PP_TXCBLEND_5 ++0x2f54 PP_TXCBLEND2_5 ++0x2f58 PP_TXABLEND_5 ++0x2f5c PP_TXABLEND2_5 ++0x2f60 PP_TXCBLEND_6 ++0x2f64 PP_TXCBLEND2_6 ++0x2f68 PP_TXABLEND_6 ++0x2f6c PP_TXABLEND2_6 ++0x2f70 PP_TXCBLEND_7 ++0x2f74 PP_TXCBLEND2_7 ++0x2f78 PP_TXABLEND_7 ++0x2f7c PP_TXABLEND2_7 ++0x2f80 PP_TXCBLEND_8 ++0x2f84 PP_TXCBLEND2_8 ++0x2f88 PP_TXABLEND_8 ++0x2f8c PP_TXABLEND2_8 ++0x2f90 PP_TXCBLEND_9 ++0x2f94 PP_TXCBLEND2_9 ++0x2f98 PP_TXABLEND_9 ++0x2f9c PP_TXABLEND2_9 ++0x2fa0 PP_TXCBLEND_10 ++0x2fa4 PP_TXCBLEND2_10 ++0x2fa8 PP_TXABLEND_10 ++0x2fac PP_TXABLEND2_10 ++0x2fb0 PP_TXCBLEND_11 ++0x2fb4 PP_TXCBLEND2_11 ++0x2fb8 PP_TXABLEND_11 ++0x2fbc PP_TXABLEND2_11 ++0x2fc0 PP_TXCBLEND_12 ++0x2fc4 PP_TXCBLEND2_12 ++0x2fc8 PP_TXABLEND_12 ++0x2fcc PP_TXABLEND2_12 ++0x2fd0 PP_TXCBLEND_13 ++0x2fd4 PP_TXCBLEND2_13 ++0x2fd8 PP_TXABLEND_13 ++0x2fdc PP_TXABLEND2_13 ++0x2fe0 PP_TXCBLEND_14 ++0x2fe4 PP_TXCBLEND2_14 ++0x2fe8 PP_TXABLEND_14 ++0x2fec PP_TXABLEND2_14 ++0x2ff0 PP_TXCBLEND_15 ++0x2ff4 PP_TXCBLEND2_15 ++0x2ff8 PP_TXABLEND_15 ++0x2ffc PP_TXABLEND2_15 ++0x3218 RB3D_BLENCOLOR ++0x321c RB3D_ABLENDCNTL ++0x3220 RB3D_CBLENDCNTL ++0x3290 RB3D_ZPASS_DATA ++ +diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300 +new file mode 100644 +index 0000000..19c4663 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/reg_srcs/r300 +@@ -0,0 +1,729 @@ ++r300 0x4f60 ++0x1434 SRC_Y_X ++0x1438 DST_Y_X ++0x143C DST_HEIGHT_WIDTH ++0x146C DP_GUI_MASTER_CNTL ++0x1474 BRUSH_Y_X ++0x1478 DP_BRUSH_BKGD_CLR ++0x147C DP_BRUSH_FRGD_CLR ++0x1480 BRUSH_DATA0 ++0x1484 BRUSH_DATA1 ++0x1598 DST_WIDTH_HEIGHT ++0x15C0 CLR_CMP_CNTL ++0x15C4 CLR_CMP_CLR_SRC ++0x15C8 CLR_CMP_CLR_DST ++0x15CC CLR_CMP_MSK ++0x15D8 DP_SRC_FRGD_CLR ++0x15DC DP_SRC_BKGD_CLR ++0x1600 DST_LINE_START ++0x1604 DST_LINE_END ++0x1608 DST_LINE_PATCOUNT ++0x16C0 DP_CNTL ++0x16CC DP_WRITE_MSK ++0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR ++0x16E8 DEFAULT_SC_BOTTOM_RIGHT ++0x16EC SC_TOP_LEFT ++0x16F0 SC_BOTTOM_RIGHT ++0x16F4 SRC_SC_BOTTOM_RIGHT ++0x1714 DSTCACHE_CTLSTAT ++0x1720 WAIT_UNTIL ++0x172C RBBM_GUICNTL ++0x1D98 VAP_VPORT_XSCALE ++0x1D9C VAP_VPORT_XOFFSET ++0x1DA0 VAP_VPORT_YSCALE ++0x1DA4 VAP_VPORT_YOFFSET ++0x1DA8 VAP_VPORT_ZSCALE ++0x1DAC VAP_VPORT_ZOFFSET ++0x2080 VAP_CNTL ++0x2090 VAP_OUT_VTX_FMT_0 ++0x2094 VAP_OUT_VTX_FMT_1 ++0x20B0 VAP_VTE_CNTL ++0x2138 VAP_VF_MIN_VTX_INDX ++0x2140 VAP_CNTL_STATUS ++0x2150 VAP_PROG_STREAM_CNTL_0 ++0x2154 VAP_PROG_STREAM_CNTL_1 ++0x2158 VAP_PROG_STREAM_CNTL_2 ++0x215C VAP_PROG_STREAM_CNTL_3 ++0x2160 VAP_PROG_STREAM_CNTL_4 ++0x2164 VAP_PROG_STREAM_CNTL_5 ++0x2168 VAP_PROG_STREAM_CNTL_6 ++0x216C VAP_PROG_STREAM_CNTL_7 ++0x2180 VAP_VTX_STATE_CNTL ++0x2184 VAP_VSM_VTX_ASSM ++0x2188 VAP_VTX_STATE_IND_REG_0 ++0x218C VAP_VTX_STATE_IND_REG_1 ++0x2190 VAP_VTX_STATE_IND_REG_2 ++0x2194 VAP_VTX_STATE_IND_REG_3 ++0x2198 VAP_VTX_STATE_IND_REG_4 ++0x219C VAP_VTX_STATE_IND_REG_5 ++0x21A0 VAP_VTX_STATE_IND_REG_6 ++0x21A4 VAP_VTX_STATE_IND_REG_7 ++0x21A8 VAP_VTX_STATE_IND_REG_8 ++0x21AC VAP_VTX_STATE_IND_REG_9 ++0x21B0 VAP_VTX_STATE_IND_REG_10 ++0x21B4 VAP_VTX_STATE_IND_REG_11 ++0x21B8 VAP_VTX_STATE_IND_REG_12 ++0x21BC VAP_VTX_STATE_IND_REG_13 ++0x21C0 VAP_VTX_STATE_IND_REG_14 ++0x21C4 VAP_VTX_STATE_IND_REG_15 ++0x21DC VAP_PSC_SGN_NORM_CNTL ++0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 ++0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 ++0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 ++0x21EC VAP_PROG_STREAM_CNTL_EXT_3 ++0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 ++0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 ++0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 ++0x21FC VAP_PROG_STREAM_CNTL_EXT_7 ++0x2200 VAP_PVS_VECTOR_INDX_REG ++0x2204 VAP_PVS_VECTOR_DATA_REG ++0x2208 VAP_PVS_VECTOR_DATA_REG_128 ++0x221C VAP_CLIP_CNTL ++0x2220 VAP_GB_VERT_CLIP_ADJ ++0x2224 VAP_GB_VERT_DISC_ADJ ++0x2228 VAP_GB_HORZ_CLIP_ADJ ++0x222C VAP_GB_HORZ_DISC_ADJ ++0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 ++0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 ++0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 ++0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 ++0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 ++0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 ++0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 ++0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 ++0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 ++0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 ++0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 ++0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 ++0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 ++0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 ++0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 ++0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 ++0x2284 VAP_PVS_STATE_FLUSH_REG ++0x2288 VAP_PVS_VTX_TIMEOUT_REG ++0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 ++0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 ++0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 ++0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 ++0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 ++0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 ++0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 ++0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 ++0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 ++0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 ++0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 ++0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 ++0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 ++0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 ++0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 ++0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 ++0x22D0 VAP_PVS_CODE_CNTL_0 ++0x22D4 VAP_PVS_CONST_CNTL ++0x22D8 VAP_PVS_CODE_CNTL_1 ++0x22DC VAP_PVS_FLOW_CNTL_OPC ++0x342C RB2D_DSTCACHE_CTLSTAT ++0x4000 GB_VAP_RASTER_VTX_FMT_0 ++0x4004 GB_VAP_RASTER_VTX_FMT_1 ++0x4008 GB_ENABLE ++0x401C GB_SELECT ++0x4020 GB_AA_CONFIG ++0x4024 GB_FIFO_SIZE ++0x4100 TX_INVALTAGS ++0x4200 GA_POINT_S0 ++0x4204 GA_POINT_T0 ++0x4208 GA_POINT_S1 ++0x420C GA_POINT_T1 ++0x4214 GA_TRIANGLE_STIPPLE ++0x421C GA_POINT_SIZE ++0x4230 GA_POINT_MINMAX ++0x4234 GA_LINE_CNTL ++0x4238 GA_LINE_STIPPLE_CONFIG ++0x4260 GA_LINE_STIPPLE_VALUE ++0x4264 GA_LINE_S0 ++0x4268 GA_LINE_S1 ++0x4278 GA_COLOR_CONTROL ++0x427C GA_SOLID_RG ++0x4280 GA_SOLID_BA ++0x4288 GA_POLY_MODE ++0x428C GA_ROUND_MODE ++0x4290 GA_OFFSET ++0x4294 GA_FOG_SCALE ++0x4298 GA_FOG_OFFSET ++0x42A0 SU_TEX_WRAP ++0x42A4 SU_POLY_OFFSET_FRONT_SCALE ++0x42A8 SU_POLY_OFFSET_FRONT_OFFSET ++0x42AC SU_POLY_OFFSET_BACK_SCALE ++0x42B0 SU_POLY_OFFSET_BACK_OFFSET ++0x42B4 SU_POLY_OFFSET_ENABLE ++0x42B8 SU_CULL_MODE ++0x42C0 SU_DEPTH_SCALE ++0x42C4 SU_DEPTH_OFFSET ++0x42C8 SU_REG_DEST ++0x4300 RS_COUNT ++0x4304 RS_INST_COUNT ++0x4310 RS_IP_0 ++0x4314 RS_IP_1 ++0x4318 RS_IP_2 ++0x431C RS_IP_3 ++0x4320 RS_IP_4 ++0x4324 RS_IP_5 ++0x4328 RS_IP_6 ++0x432C RS_IP_7 ++0x4330 RS_INST_0 ++0x4334 RS_INST_1 ++0x4338 RS_INST_2 ++0x433C RS_INST_3 ++0x4340 RS_INST_4 ++0x4344 RS_INST_5 ++0x4348 RS_INST_6 ++0x434C RS_INST_7 ++0x4350 RS_INST_8 ++0x4354 RS_INST_9 ++0x4358 RS_INST_10 ++0x435C RS_INST_11 ++0x4360 RS_INST_12 ++0x4364 RS_INST_13 ++0x4368 RS_INST_14 ++0x436C RS_INST_15 ++0x43A4 SC_HYPERZ_EN ++0x43A8 SC_EDGERULE ++0x43B0 SC_CLIP_0_A ++0x43B4 SC_CLIP_0_B ++0x43B8 SC_CLIP_1_A ++0x43BC SC_CLIP_1_B ++0x43C0 SC_CLIP_2_A ++0x43C4 SC_CLIP_2_B ++0x43C8 SC_CLIP_3_A ++0x43CC SC_CLIP_3_B ++0x43D0 SC_CLIP_RULE ++0x43E0 SC_SCISSOR0 ++0x43E8 SC_SCREENDOOR ++0x4440 TX_FILTER1_0 ++0x4444 TX_FILTER1_1 ++0x4448 TX_FILTER1_2 ++0x444C TX_FILTER1_3 ++0x4450 TX_FILTER1_4 ++0x4454 TX_FILTER1_5 ++0x4458 TX_FILTER1_6 ++0x445C TX_FILTER1_7 ++0x4460 TX_FILTER1_8 ++0x4464 TX_FILTER1_9 ++0x4468 TX_FILTER1_10 ++0x446C TX_FILTER1_11 ++0x4470 TX_FILTER1_12 ++0x4474 TX_FILTER1_13 ++0x4478 TX_FILTER1_14 ++0x447C TX_FILTER1_15 ++0x4580 TX_CHROMA_KEY_0 ++0x4584 TX_CHROMA_KEY_1 ++0x4588 TX_CHROMA_KEY_2 ++0x458C TX_CHROMA_KEY_3 ++0x4590 TX_CHROMA_KEY_4 ++0x4594 TX_CHROMA_KEY_5 ++0x4598 TX_CHROMA_KEY_6 ++0x459C TX_CHROMA_KEY_7 ++0x45A0 TX_CHROMA_KEY_8 ++0x45A4 TX_CHROMA_KEY_9 ++0x45A8 TX_CHROMA_KEY_10 ++0x45AC TX_CHROMA_KEY_11 ++0x45B0 TX_CHROMA_KEY_12 ++0x45B4 TX_CHROMA_KEY_13 ++0x45B8 TX_CHROMA_KEY_14 ++0x45BC TX_CHROMA_KEY_15 ++0x45C0 TX_BORDER_COLOR_0 ++0x45C4 TX_BORDER_COLOR_1 ++0x45C8 TX_BORDER_COLOR_2 ++0x45CC TX_BORDER_COLOR_3 ++0x45D0 TX_BORDER_COLOR_4 ++0x45D4 TX_BORDER_COLOR_5 ++0x45D8 TX_BORDER_COLOR_6 ++0x45DC TX_BORDER_COLOR_7 ++0x45E0 TX_BORDER_COLOR_8 ++0x45E4 TX_BORDER_COLOR_9 ++0x45E8 TX_BORDER_COLOR_10 ++0x45EC TX_BORDER_COLOR_11 ++0x45F0 TX_BORDER_COLOR_12 ++0x45F4 TX_BORDER_COLOR_13 ++0x45F8 TX_BORDER_COLOR_14 ++0x45FC TX_BORDER_COLOR_15 ++0x4600 US_CONFIG ++0x4604 US_PIXSIZE ++0x4608 US_CODE_OFFSET ++0x460C US_RESET ++0x4610 US_CODE_ADDR_0 ++0x4614 US_CODE_ADDR_1 ++0x4618 US_CODE_ADDR_2 ++0x461C US_CODE_ADDR_3 ++0x4620 US_TEX_INST_0 ++0x4624 US_TEX_INST_1 ++0x4628 US_TEX_INST_2 ++0x462C US_TEX_INST_3 ++0x4630 US_TEX_INST_4 ++0x4634 US_TEX_INST_5 ++0x4638 US_TEX_INST_6 ++0x463C US_TEX_INST_7 ++0x4640 US_TEX_INST_8 ++0x4644 US_TEX_INST_9 ++0x4648 US_TEX_INST_10 ++0x464C US_TEX_INST_11 ++0x4650 US_TEX_INST_12 ++0x4654 US_TEX_INST_13 ++0x4658 US_TEX_INST_14 ++0x465C US_TEX_INST_15 ++0x4660 US_TEX_INST_16 ++0x4664 US_TEX_INST_17 ++0x4668 US_TEX_INST_18 ++0x466C US_TEX_INST_19 ++0x4670 US_TEX_INST_20 ++0x4674 US_TEX_INST_21 ++0x4678 US_TEX_INST_22 ++0x467C US_TEX_INST_23 ++0x4680 US_TEX_INST_24 ++0x4684 US_TEX_INST_25 ++0x4688 US_TEX_INST_26 ++0x468C US_TEX_INST_27 ++0x4690 US_TEX_INST_28 ++0x4694 US_TEX_INST_29 ++0x4698 US_TEX_INST_30 ++0x469C US_TEX_INST_31 ++0x46A4 US_OUT_FMT_0 ++0x46A8 US_OUT_FMT_1 ++0x46AC US_OUT_FMT_2 ++0x46B0 US_OUT_FMT_3 ++0x46B4 US_W_FMT ++0x46C0 US_ALU_RGB_ADDR_0 ++0x46C4 US_ALU_RGB_ADDR_1 ++0x46C8 US_ALU_RGB_ADDR_2 ++0x46CC US_ALU_RGB_ADDR_3 ++0x46D0 US_ALU_RGB_ADDR_4 ++0x46D4 US_ALU_RGB_ADDR_5 ++0x46D8 US_ALU_RGB_ADDR_6 ++0x46DC US_ALU_RGB_ADDR_7 ++0x46E0 US_ALU_RGB_ADDR_8 ++0x46E4 US_ALU_RGB_ADDR_9 ++0x46E8 US_ALU_RGB_ADDR_10 ++0x46EC US_ALU_RGB_ADDR_11 ++0x46F0 US_ALU_RGB_ADDR_12 ++0x46F4 US_ALU_RGB_ADDR_13 ++0x46F8 US_ALU_RGB_ADDR_14 ++0x46FC US_ALU_RGB_ADDR_15 ++0x4700 US_ALU_RGB_ADDR_16 ++0x4704 US_ALU_RGB_ADDR_17 ++0x4708 US_ALU_RGB_ADDR_18 ++0x470C US_ALU_RGB_ADDR_19 ++0x4710 US_ALU_RGB_ADDR_20 ++0x4714 US_ALU_RGB_ADDR_21 ++0x4718 US_ALU_RGB_ADDR_22 ++0x471C US_ALU_RGB_ADDR_23 ++0x4720 US_ALU_RGB_ADDR_24 ++0x4724 US_ALU_RGB_ADDR_25 ++0x4728 US_ALU_RGB_ADDR_26 ++0x472C US_ALU_RGB_ADDR_27 ++0x4730 US_ALU_RGB_ADDR_28 ++0x4734 US_ALU_RGB_ADDR_29 ++0x4738 US_ALU_RGB_ADDR_30 ++0x473C US_ALU_RGB_ADDR_31 ++0x4740 US_ALU_RGB_ADDR_32 ++0x4744 US_ALU_RGB_ADDR_33 ++0x4748 US_ALU_RGB_ADDR_34 ++0x474C US_ALU_RGB_ADDR_35 ++0x4750 US_ALU_RGB_ADDR_36 ++0x4754 US_ALU_RGB_ADDR_37 ++0x4758 US_ALU_RGB_ADDR_38 ++0x475C US_ALU_RGB_ADDR_39 ++0x4760 US_ALU_RGB_ADDR_40 ++0x4764 US_ALU_RGB_ADDR_41 ++0x4768 US_ALU_RGB_ADDR_42 ++0x476C US_ALU_RGB_ADDR_43 ++0x4770 US_ALU_RGB_ADDR_44 ++0x4774 US_ALU_RGB_ADDR_45 ++0x4778 US_ALU_RGB_ADDR_46 ++0x477C US_ALU_RGB_ADDR_47 ++0x4780 US_ALU_RGB_ADDR_48 ++0x4784 US_ALU_RGB_ADDR_49 ++0x4788 US_ALU_RGB_ADDR_50 ++0x478C US_ALU_RGB_ADDR_51 ++0x4790 US_ALU_RGB_ADDR_52 ++0x4794 US_ALU_RGB_ADDR_53 ++0x4798 US_ALU_RGB_ADDR_54 ++0x479C US_ALU_RGB_ADDR_55 ++0x47A0 US_ALU_RGB_ADDR_56 ++0x47A4 US_ALU_RGB_ADDR_57 ++0x47A8 US_ALU_RGB_ADDR_58 ++0x47AC US_ALU_RGB_ADDR_59 ++0x47B0 US_ALU_RGB_ADDR_60 ++0x47B4 US_ALU_RGB_ADDR_61 ++0x47B8 US_ALU_RGB_ADDR_62 ++0x47BC US_ALU_RGB_ADDR_63 ++0x47C0 US_ALU_ALPHA_ADDR_0 ++0x47C4 US_ALU_ALPHA_ADDR_1 ++0x47C8 US_ALU_ALPHA_ADDR_2 ++0x47CC US_ALU_ALPHA_ADDR_3 ++0x47D0 US_ALU_ALPHA_ADDR_4 ++0x47D4 US_ALU_ALPHA_ADDR_5 ++0x47D8 US_ALU_ALPHA_ADDR_6 ++0x47DC US_ALU_ALPHA_ADDR_7 ++0x47E0 US_ALU_ALPHA_ADDR_8 ++0x47E4 US_ALU_ALPHA_ADDR_9 ++0x47E8 US_ALU_ALPHA_ADDR_10 ++0x47EC US_ALU_ALPHA_ADDR_11 ++0x47F0 US_ALU_ALPHA_ADDR_12 ++0x47F4 US_ALU_ALPHA_ADDR_13 ++0x47F8 US_ALU_ALPHA_ADDR_14 ++0x47FC US_ALU_ALPHA_ADDR_15 ++0x4800 US_ALU_ALPHA_ADDR_16 ++0x4804 US_ALU_ALPHA_ADDR_17 ++0x4808 US_ALU_ALPHA_ADDR_18 ++0x480C US_ALU_ALPHA_ADDR_19 ++0x4810 US_ALU_ALPHA_ADDR_20 ++0x4814 US_ALU_ALPHA_ADDR_21 ++0x4818 US_ALU_ALPHA_ADDR_22 ++0x481C US_ALU_ALPHA_ADDR_23 ++0x4820 US_ALU_ALPHA_ADDR_24 ++0x4824 US_ALU_ALPHA_ADDR_25 ++0x4828 US_ALU_ALPHA_ADDR_26 ++0x482C US_ALU_ALPHA_ADDR_27 ++0x4830 US_ALU_ALPHA_ADDR_28 ++0x4834 US_ALU_ALPHA_ADDR_29 ++0x4838 US_ALU_ALPHA_ADDR_30 ++0x483C US_ALU_ALPHA_ADDR_31 ++0x4840 US_ALU_ALPHA_ADDR_32 ++0x4844 US_ALU_ALPHA_ADDR_33 ++0x4848 US_ALU_ALPHA_ADDR_34 ++0x484C US_ALU_ALPHA_ADDR_35 ++0x4850 US_ALU_ALPHA_ADDR_36 ++0x4854 US_ALU_ALPHA_ADDR_37 ++0x4858 US_ALU_ALPHA_ADDR_38 ++0x485C US_ALU_ALPHA_ADDR_39 ++0x4860 US_ALU_ALPHA_ADDR_40 ++0x4864 US_ALU_ALPHA_ADDR_41 ++0x4868 US_ALU_ALPHA_ADDR_42 ++0x486C US_ALU_ALPHA_ADDR_43 ++0x4870 US_ALU_ALPHA_ADDR_44 ++0x4874 US_ALU_ALPHA_ADDR_45 ++0x4878 US_ALU_ALPHA_ADDR_46 ++0x487C US_ALU_ALPHA_ADDR_47 ++0x4880 US_ALU_ALPHA_ADDR_48 ++0x4884 US_ALU_ALPHA_ADDR_49 ++0x4888 US_ALU_ALPHA_ADDR_50 ++0x488C US_ALU_ALPHA_ADDR_51 ++0x4890 US_ALU_ALPHA_ADDR_52 ++0x4894 US_ALU_ALPHA_ADDR_53 ++0x4898 US_ALU_ALPHA_ADDR_54 ++0x489C US_ALU_ALPHA_ADDR_55 ++0x48A0 US_ALU_ALPHA_ADDR_56 ++0x48A4 US_ALU_ALPHA_ADDR_57 ++0x48A8 US_ALU_ALPHA_ADDR_58 ++0x48AC US_ALU_ALPHA_ADDR_59 ++0x48B0 US_ALU_ALPHA_ADDR_60 ++0x48B4 US_ALU_ALPHA_ADDR_61 ++0x48B8 US_ALU_ALPHA_ADDR_62 ++0x48BC US_ALU_ALPHA_ADDR_63 ++0x48C0 US_ALU_RGB_INST_0 ++0x48C4 US_ALU_RGB_INST_1 ++0x48C8 US_ALU_RGB_INST_2 ++0x48CC US_ALU_RGB_INST_3 ++0x48D0 US_ALU_RGB_INST_4 ++0x48D4 US_ALU_RGB_INST_5 ++0x48D8 US_ALU_RGB_INST_6 ++0x48DC US_ALU_RGB_INST_7 ++0x48E0 US_ALU_RGB_INST_8 ++0x48E4 US_ALU_RGB_INST_9 ++0x48E8 US_ALU_RGB_INST_10 ++0x48EC US_ALU_RGB_INST_11 ++0x48F0 US_ALU_RGB_INST_12 ++0x48F4 US_ALU_RGB_INST_13 ++0x48F8 US_ALU_RGB_INST_14 ++0x48FC US_ALU_RGB_INST_15 ++0x4900 US_ALU_RGB_INST_16 ++0x4904 US_ALU_RGB_INST_17 ++0x4908 US_ALU_RGB_INST_18 ++0x490C US_ALU_RGB_INST_19 ++0x4910 US_ALU_RGB_INST_20 ++0x4914 US_ALU_RGB_INST_21 ++0x4918 US_ALU_RGB_INST_22 ++0x491C US_ALU_RGB_INST_23 ++0x4920 US_ALU_RGB_INST_24 ++0x4924 US_ALU_RGB_INST_25 ++0x4928 US_ALU_RGB_INST_26 ++0x492C US_ALU_RGB_INST_27 ++0x4930 US_ALU_RGB_INST_28 ++0x4934 US_ALU_RGB_INST_29 ++0x4938 US_ALU_RGB_INST_30 ++0x493C US_ALU_RGB_INST_31 ++0x4940 US_ALU_RGB_INST_32 ++0x4944 US_ALU_RGB_INST_33 ++0x4948 US_ALU_RGB_INST_34 ++0x494C US_ALU_RGB_INST_35 ++0x4950 US_ALU_RGB_INST_36 ++0x4954 US_ALU_RGB_INST_37 ++0x4958 US_ALU_RGB_INST_38 ++0x495C US_ALU_RGB_INST_39 ++0x4960 US_ALU_RGB_INST_40 ++0x4964 US_ALU_RGB_INST_41 ++0x4968 US_ALU_RGB_INST_42 ++0x496C US_ALU_RGB_INST_43 ++0x4970 US_ALU_RGB_INST_44 ++0x4974 US_ALU_RGB_INST_45 ++0x4978 US_ALU_RGB_INST_46 ++0x497C US_ALU_RGB_INST_47 ++0x4980 US_ALU_RGB_INST_48 ++0x4984 US_ALU_RGB_INST_49 ++0x4988 US_ALU_RGB_INST_50 ++0x498C US_ALU_RGB_INST_51 ++0x4990 US_ALU_RGB_INST_52 ++0x4994 US_ALU_RGB_INST_53 ++0x4998 US_ALU_RGB_INST_54 ++0x499C US_ALU_RGB_INST_55 ++0x49A0 US_ALU_RGB_INST_56 ++0x49A4 US_ALU_RGB_INST_57 ++0x49A8 US_ALU_RGB_INST_58 ++0x49AC US_ALU_RGB_INST_59 ++0x49B0 US_ALU_RGB_INST_60 ++0x49B4 US_ALU_RGB_INST_61 ++0x49B8 US_ALU_RGB_INST_62 ++0x49BC US_ALU_RGB_INST_63 ++0x49C0 US_ALU_ALPHA_INST_0 ++0x49C4 US_ALU_ALPHA_INST_1 ++0x49C8 US_ALU_ALPHA_INST_2 ++0x49CC US_ALU_ALPHA_INST_3 ++0x49D0 US_ALU_ALPHA_INST_4 ++0x49D4 US_ALU_ALPHA_INST_5 ++0x49D8 US_ALU_ALPHA_INST_6 ++0x49DC US_ALU_ALPHA_INST_7 ++0x49E0 US_ALU_ALPHA_INST_8 ++0x49E4 US_ALU_ALPHA_INST_9 ++0x49E8 US_ALU_ALPHA_INST_10 ++0x49EC US_ALU_ALPHA_INST_11 ++0x49F0 US_ALU_ALPHA_INST_12 ++0x49F4 US_ALU_ALPHA_INST_13 ++0x49F8 US_ALU_ALPHA_INST_14 ++0x49FC US_ALU_ALPHA_INST_15 ++0x4A00 US_ALU_ALPHA_INST_16 ++0x4A04 US_ALU_ALPHA_INST_17 ++0x4A08 US_ALU_ALPHA_INST_18 ++0x4A0C US_ALU_ALPHA_INST_19 ++0x4A10 US_ALU_ALPHA_INST_20 ++0x4A14 US_ALU_ALPHA_INST_21 ++0x4A18 US_ALU_ALPHA_INST_22 ++0x4A1C US_ALU_ALPHA_INST_23 ++0x4A20 US_ALU_ALPHA_INST_24 ++0x4A24 US_ALU_ALPHA_INST_25 ++0x4A28 US_ALU_ALPHA_INST_26 ++0x4A2C US_ALU_ALPHA_INST_27 ++0x4A30 US_ALU_ALPHA_INST_28 ++0x4A34 US_ALU_ALPHA_INST_29 ++0x4A38 US_ALU_ALPHA_INST_30 ++0x4A3C US_ALU_ALPHA_INST_31 ++0x4A40 US_ALU_ALPHA_INST_32 ++0x4A44 US_ALU_ALPHA_INST_33 ++0x4A48 US_ALU_ALPHA_INST_34 ++0x4A4C US_ALU_ALPHA_INST_35 ++0x4A50 US_ALU_ALPHA_INST_36 ++0x4A54 US_ALU_ALPHA_INST_37 ++0x4A58 US_ALU_ALPHA_INST_38 ++0x4A5C US_ALU_ALPHA_INST_39 ++0x4A60 US_ALU_ALPHA_INST_40 ++0x4A64 US_ALU_ALPHA_INST_41 ++0x4A68 US_ALU_ALPHA_INST_42 ++0x4A6C US_ALU_ALPHA_INST_43 ++0x4A70 US_ALU_ALPHA_INST_44 ++0x4A74 US_ALU_ALPHA_INST_45 ++0x4A78 US_ALU_ALPHA_INST_46 ++0x4A7C US_ALU_ALPHA_INST_47 ++0x4A80 US_ALU_ALPHA_INST_48 ++0x4A84 US_ALU_ALPHA_INST_49 ++0x4A88 US_ALU_ALPHA_INST_50 ++0x4A8C US_ALU_ALPHA_INST_51 ++0x4A90 US_ALU_ALPHA_INST_52 ++0x4A94 US_ALU_ALPHA_INST_53 ++0x4A98 US_ALU_ALPHA_INST_54 ++0x4A9C US_ALU_ALPHA_INST_55 ++0x4AA0 US_ALU_ALPHA_INST_56 ++0x4AA4 US_ALU_ALPHA_INST_57 ++0x4AA8 US_ALU_ALPHA_INST_58 ++0x4AAC US_ALU_ALPHA_INST_59 ++0x4AB0 US_ALU_ALPHA_INST_60 ++0x4AB4 US_ALU_ALPHA_INST_61 ++0x4AB8 US_ALU_ALPHA_INST_62 ++0x4ABC US_ALU_ALPHA_INST_63 ++0x4BC0 FG_FOG_BLEND ++0x4BC4 FG_FOG_FACTOR ++0x4BC8 FG_FOG_COLOR_R ++0x4BCC FG_FOG_COLOR_G ++0x4BD0 FG_FOG_COLOR_B ++0x4BD4 FG_ALPHA_FUNC ++0x4BD8 FG_DEPTH_SRC ++0x4C00 US_ALU_CONST_R_0 ++0x4C04 US_ALU_CONST_G_0 ++0x4C08 US_ALU_CONST_B_0 ++0x4C0C US_ALU_CONST_A_0 ++0x4C10 US_ALU_CONST_R_1 ++0x4C14 US_ALU_CONST_G_1 ++0x4C18 US_ALU_CONST_B_1 ++0x4C1C US_ALU_CONST_A_1 ++0x4C20 US_ALU_CONST_R_2 ++0x4C24 US_ALU_CONST_G_2 ++0x4C28 US_ALU_CONST_B_2 ++0x4C2C US_ALU_CONST_A_2 ++0x4C30 US_ALU_CONST_R_3 ++0x4C34 US_ALU_CONST_G_3 ++0x4C38 US_ALU_CONST_B_3 ++0x4C3C US_ALU_CONST_A_3 ++0x4C40 US_ALU_CONST_R_4 ++0x4C44 US_ALU_CONST_G_4 ++0x4C48 US_ALU_CONST_B_4 ++0x4C4C US_ALU_CONST_A_4 ++0x4C50 US_ALU_CONST_R_5 ++0x4C54 US_ALU_CONST_G_5 ++0x4C58 US_ALU_CONST_B_5 ++0x4C5C US_ALU_CONST_A_5 ++0x4C60 US_ALU_CONST_R_6 ++0x4C64 US_ALU_CONST_G_6 ++0x4C68 US_ALU_CONST_B_6 ++0x4C6C US_ALU_CONST_A_6 ++0x4C70 US_ALU_CONST_R_7 ++0x4C74 US_ALU_CONST_G_7 ++0x4C78 US_ALU_CONST_B_7 ++0x4C7C US_ALU_CONST_A_7 ++0x4C80 US_ALU_CONST_R_8 ++0x4C84 US_ALU_CONST_G_8 ++0x4C88 US_ALU_CONST_B_8 ++0x4C8C US_ALU_CONST_A_8 ++0x4C90 US_ALU_CONST_R_9 ++0x4C94 US_ALU_CONST_G_9 ++0x4C98 US_ALU_CONST_B_9 ++0x4C9C US_ALU_CONST_A_9 ++0x4CA0 US_ALU_CONST_R_10 ++0x4CA4 US_ALU_CONST_G_10 ++0x4CA8 US_ALU_CONST_B_10 ++0x4CAC US_ALU_CONST_A_10 ++0x4CB0 US_ALU_CONST_R_11 ++0x4CB4 US_ALU_CONST_G_11 ++0x4CB8 US_ALU_CONST_B_11 ++0x4CBC US_ALU_CONST_A_11 ++0x4CC0 US_ALU_CONST_R_12 ++0x4CC4 US_ALU_CONST_G_12 ++0x4CC8 US_ALU_CONST_B_12 ++0x4CCC US_ALU_CONST_A_12 ++0x4CD0 US_ALU_CONST_R_13 ++0x4CD4 US_ALU_CONST_G_13 ++0x4CD8 US_ALU_CONST_B_13 ++0x4CDC US_ALU_CONST_A_13 ++0x4CE0 US_ALU_CONST_R_14 ++0x4CE4 US_ALU_CONST_G_14 ++0x4CE8 US_ALU_CONST_B_14 ++0x4CEC US_ALU_CONST_A_14 ++0x4CF0 US_ALU_CONST_R_15 ++0x4CF4 US_ALU_CONST_G_15 ++0x4CF8 US_ALU_CONST_B_15 ++0x4CFC US_ALU_CONST_A_15 ++0x4D00 US_ALU_CONST_R_16 ++0x4D04 US_ALU_CONST_G_16 ++0x4D08 US_ALU_CONST_B_16 ++0x4D0C US_ALU_CONST_A_16 ++0x4D10 US_ALU_CONST_R_17 ++0x4D14 US_ALU_CONST_G_17 ++0x4D18 US_ALU_CONST_B_17 ++0x4D1C US_ALU_CONST_A_17 ++0x4D20 US_ALU_CONST_R_18 ++0x4D24 US_ALU_CONST_G_18 ++0x4D28 US_ALU_CONST_B_18 ++0x4D2C US_ALU_CONST_A_18 ++0x4D30 US_ALU_CONST_R_19 ++0x4D34 US_ALU_CONST_G_19 ++0x4D38 US_ALU_CONST_B_19 ++0x4D3C US_ALU_CONST_A_19 ++0x4D40 US_ALU_CONST_R_20 ++0x4D44 US_ALU_CONST_G_20 ++0x4D48 US_ALU_CONST_B_20 ++0x4D4C US_ALU_CONST_A_20 ++0x4D50 US_ALU_CONST_R_21 ++0x4D54 US_ALU_CONST_G_21 ++0x4D58 US_ALU_CONST_B_21 ++0x4D5C US_ALU_CONST_A_21 ++0x4D60 US_ALU_CONST_R_22 ++0x4D64 US_ALU_CONST_G_22 ++0x4D68 US_ALU_CONST_B_22 ++0x4D6C US_ALU_CONST_A_22 ++0x4D70 US_ALU_CONST_R_23 ++0x4D74 US_ALU_CONST_G_23 ++0x4D78 US_ALU_CONST_B_23 ++0x4D7C US_ALU_CONST_A_23 ++0x4D80 US_ALU_CONST_R_24 ++0x4D84 US_ALU_CONST_G_24 ++0x4D88 US_ALU_CONST_B_24 ++0x4D8C US_ALU_CONST_A_24 ++0x4D90 US_ALU_CONST_R_25 ++0x4D94 US_ALU_CONST_G_25 ++0x4D98 US_ALU_CONST_B_25 ++0x4D9C US_ALU_CONST_A_25 ++0x4DA0 US_ALU_CONST_R_26 ++0x4DA4 US_ALU_CONST_G_26 ++0x4DA8 US_ALU_CONST_B_26 ++0x4DAC US_ALU_CONST_A_26 ++0x4DB0 US_ALU_CONST_R_27 ++0x4DB4 US_ALU_CONST_G_27 ++0x4DB8 US_ALU_CONST_B_27 ++0x4DBC US_ALU_CONST_A_27 ++0x4DC0 US_ALU_CONST_R_28 ++0x4DC4 US_ALU_CONST_G_28 ++0x4DC8 US_ALU_CONST_B_28 ++0x4DCC US_ALU_CONST_A_28 ++0x4DD0 US_ALU_CONST_R_29 ++0x4DD4 US_ALU_CONST_G_29 ++0x4DD8 US_ALU_CONST_B_29 ++0x4DDC US_ALU_CONST_A_29 ++0x4DE0 US_ALU_CONST_R_30 ++0x4DE4 US_ALU_CONST_G_30 ++0x4DE8 US_ALU_CONST_B_30 ++0x4DEC US_ALU_CONST_A_30 ++0x4DF0 US_ALU_CONST_R_31 ++0x4DF4 US_ALU_CONST_G_31 ++0x4DF8 US_ALU_CONST_B_31 ++0x4DFC US_ALU_CONST_A_31 ++0x4E04 RB3D_BLENDCNTL_R3 ++0x4E08 RB3D_ABLENDCNTL_R3 ++0x4E0C RB3D_COLOR_CHANNEL_MASK ++0x4E10 RB3D_CONSTANT_COLOR ++0x4E14 RB3D_COLOR_CLEAR_VALUE ++0x4E18 RB3D_ROPCNTL_R3 ++0x4E1C RB3D_CLRCMP_FLIPE_R3 ++0x4E20 RB3D_CLRCMP_CLR_R3 ++0x4E24 RB3D_CLRCMP_MSK_R3 ++0x4E48 RB3D_DEBUG_CTL ++0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 ++0x4E50 RB3D_DITHER_CTL ++0x4E54 RB3D_CMASK_OFFSET0 ++0x4E58 RB3D_CMASK_OFFSET1 ++0x4E5C RB3D_CMASK_OFFSET2 ++0x4E60 RB3D_CMASK_OFFSET3 ++0x4E64 RB3D_CMASK_PITCH0 ++0x4E68 RB3D_CMASK_PITCH1 ++0x4E6C RB3D_CMASK_PITCH2 ++0x4E70 RB3D_CMASK_PITCH3 ++0x4E74 RB3D_CMASK_WRINDEX ++0x4E78 RB3D_CMASK_DWORD ++0x4E7C RB3D_CMASK_RDINDEX ++0x4E80 RB3D_AARESOLVE_OFFSET ++0x4E84 RB3D_AARESOLVE_PITCH ++0x4E88 RB3D_AARESOLVE_CTL ++0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD ++0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD ++0x4F04 ZB_ZSTENCILCNTL ++0x4F08 ZB_STENCILREFMASK ++0x4F14 ZB_ZTOP ++0x4F18 ZB_ZCACHE_CTLSTAT ++0x4F1C ZB_BW_CNTL ++0x4F28 ZB_DEPTHCLEARVALUE ++0x4F30 ZB_ZMASK_OFFSET ++0x4F34 ZB_ZMASK_PITCH ++0x4F38 ZB_ZMASK_WRINDEX ++0x4F3C ZB_ZMASK_DWORD ++0x4F40 ZB_ZMASK_RDINDEX ++0x4F44 ZB_HIZ_OFFSET ++0x4F48 ZB_HIZ_WRINDEX ++0x4F4C ZB_HIZ_DWORD ++0x4F50 ZB_HIZ_RDINDEX ++0x4F54 ZB_HIZ_PITCH ++0x4F58 ZB_ZPASS_DATA +diff --git a/drivers/gpu/drm/radeon/reg_srcs/rn50 b/drivers/gpu/drm/radeon/reg_srcs/rn50 +new file mode 100644 +index 0000000..2687b63 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/reg_srcs/rn50 +@@ -0,0 +1,30 @@ ++rn50 0x3294 ++0x1434 SRC_Y_X ++0x1438 DST_Y_X ++0x143C DST_HEIGHT_WIDTH ++0x146C DP_GUI_MASTER_CNTL ++0x1474 BRUSH_Y_X ++0x1478 DP_BRUSH_BKGD_CLR ++0x147C DP_BRUSH_FRGD_CLR ++0x1480 BRUSH_DATA0 ++0x1484 BRUSH_DATA1 ++0x1598 DST_WIDTH_HEIGHT ++0x15C0 CLR_CMP_CNTL ++0x15C4 CLR_CMP_CLR_SRC ++0x15C8 CLR_CMP_CLR_DST ++0x15CC CLR_CMP_MSK ++0x15D8 DP_SRC_FRGD_CLR ++0x15DC DP_SRC_BKGD_CLR ++0x1600 DST_LINE_START ++0x1604 DST_LINE_END ++0x1608 DST_LINE_PATCOUNT ++0x16C0 DP_CNTL ++0x16CC DP_WRITE_MSK ++0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR ++0x16E8 DEFAULT_SC_BOTTOM_RIGHT ++0x16EC SC_TOP_LEFT ++0x16F0 SC_BOTTOM_RIGHT ++0x16F4 SRC_SC_BOTTOM_RIGHT ++0x1714 DSTCACHE_CTLSTAT ++0x1720 WAIT_UNTIL ++0x172C RBBM_GUICNTL +diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600 +new file mode 100644 +index 0000000..8e3c0b8 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/reg_srcs/rs600 +@@ -0,0 +1,729 @@ ++rs600 0x6d40 ++0x1434 SRC_Y_X ++0x1438 DST_Y_X ++0x143C DST_HEIGHT_WIDTH ++0x146C DP_GUI_MASTER_CNTL ++0x1474 BRUSH_Y_X ++0x1478 DP_BRUSH_BKGD_CLR ++0x147C DP_BRUSH_FRGD_CLR ++0x1480 BRUSH_DATA0 ++0x1484 BRUSH_DATA1 ++0x1598 DST_WIDTH_HEIGHT ++0x15C0 CLR_CMP_CNTL ++0x15C4 CLR_CMP_CLR_SRC ++0x15C8 CLR_CMP_CLR_DST ++0x15CC CLR_CMP_MSK ++0x15D8 DP_SRC_FRGD_CLR ++0x15DC DP_SRC_BKGD_CLR ++0x1600 DST_LINE_START ++0x1604 DST_LINE_END ++0x1608 DST_LINE_PATCOUNT ++0x16C0 DP_CNTL ++0x16CC DP_WRITE_MSK ++0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR ++0x16E8 DEFAULT_SC_BOTTOM_RIGHT ++0x16EC SC_TOP_LEFT ++0x16F0 SC_BOTTOM_RIGHT ++0x16F4 SRC_SC_BOTTOM_RIGHT ++0x1714 DSTCACHE_CTLSTAT ++0x1720 WAIT_UNTIL ++0x172C RBBM_GUICNTL ++0x1D98 VAP_VPORT_XSCALE ++0x1D9C VAP_VPORT_XOFFSET ++0x1DA0 VAP_VPORT_YSCALE ++0x1DA4 VAP_VPORT_YOFFSET ++0x1DA8 VAP_VPORT_ZSCALE ++0x1DAC VAP_VPORT_ZOFFSET ++0x2080 VAP_CNTL ++0x2090 VAP_OUT_VTX_FMT_0 ++0x2094 VAP_OUT_VTX_FMT_1 ++0x20B0 VAP_VTE_CNTL ++0x2138 VAP_VF_MIN_VTX_INDX ++0x2140 VAP_CNTL_STATUS ++0x2150 VAP_PROG_STREAM_CNTL_0 ++0x2154 VAP_PROG_STREAM_CNTL_1 ++0x2158 VAP_PROG_STREAM_CNTL_2 ++0x215C VAP_PROG_STREAM_CNTL_3 ++0x2160 VAP_PROG_STREAM_CNTL_4 ++0x2164 VAP_PROG_STREAM_CNTL_5 ++0x2168 VAP_PROG_STREAM_CNTL_6 ++0x216C VAP_PROG_STREAM_CNTL_7 ++0x2180 VAP_VTX_STATE_CNTL ++0x2184 VAP_VSM_VTX_ASSM ++0x2188 VAP_VTX_STATE_IND_REG_0 ++0x218C VAP_VTX_STATE_IND_REG_1 ++0x2190 VAP_VTX_STATE_IND_REG_2 ++0x2194 VAP_VTX_STATE_IND_REG_3 ++0x2198 VAP_VTX_STATE_IND_REG_4 ++0x219C VAP_VTX_STATE_IND_REG_5 ++0x21A0 VAP_VTX_STATE_IND_REG_6 ++0x21A4 VAP_VTX_STATE_IND_REG_7 ++0x21A8 VAP_VTX_STATE_IND_REG_8 ++0x21AC VAP_VTX_STATE_IND_REG_9 ++0x21B0 VAP_VTX_STATE_IND_REG_10 ++0x21B4 VAP_VTX_STATE_IND_REG_11 ++0x21B8 VAP_VTX_STATE_IND_REG_12 ++0x21BC VAP_VTX_STATE_IND_REG_13 ++0x21C0 VAP_VTX_STATE_IND_REG_14 ++0x21C4 VAP_VTX_STATE_IND_REG_15 ++0x21DC VAP_PSC_SGN_NORM_CNTL ++0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 ++0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 ++0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 ++0x21EC VAP_PROG_STREAM_CNTL_EXT_3 ++0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 ++0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 ++0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 ++0x21FC VAP_PROG_STREAM_CNTL_EXT_7 ++0x2200 VAP_PVS_VECTOR_INDX_REG ++0x2204 VAP_PVS_VECTOR_DATA_REG ++0x2208 VAP_PVS_VECTOR_DATA_REG_128 ++0x221C VAP_CLIP_CNTL ++0x2220 VAP_GB_VERT_CLIP_ADJ ++0x2224 VAP_GB_VERT_DISC_ADJ ++0x2228 VAP_GB_HORZ_CLIP_ADJ ++0x222C VAP_GB_HORZ_DISC_ADJ ++0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 ++0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 ++0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 ++0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 ++0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 ++0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 ++0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 ++0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 ++0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 ++0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 ++0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 ++0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 ++0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 ++0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 ++0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 ++0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 ++0x2284 VAP_PVS_STATE_FLUSH_REG ++0x2288 VAP_PVS_VTX_TIMEOUT_REG ++0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 ++0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 ++0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 ++0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 ++0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 ++0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 ++0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 ++0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 ++0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 ++0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 ++0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 ++0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 ++0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 ++0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 ++0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 ++0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 ++0x22D0 VAP_PVS_CODE_CNTL_0 ++0x22D4 VAP_PVS_CONST_CNTL ++0x22D8 VAP_PVS_CODE_CNTL_1 ++0x22DC VAP_PVS_FLOW_CNTL_OPC ++0x342C RB2D_DSTCACHE_CTLSTAT ++0x4000 GB_VAP_RASTER_VTX_FMT_0 ++0x4004 GB_VAP_RASTER_VTX_FMT_1 ++0x4008 GB_ENABLE ++0x401C GB_SELECT ++0x4020 GB_AA_CONFIG ++0x4024 GB_FIFO_SIZE ++0x4100 TX_INVALTAGS ++0x4200 GA_POINT_S0 ++0x4204 GA_POINT_T0 ++0x4208 GA_POINT_S1 ++0x420C GA_POINT_T1 ++0x4214 GA_TRIANGLE_STIPPLE ++0x421C GA_POINT_SIZE ++0x4230 GA_POINT_MINMAX ++0x4234 GA_LINE_CNTL ++0x4238 GA_LINE_STIPPLE_CONFIG ++0x4260 GA_LINE_STIPPLE_VALUE ++0x4264 GA_LINE_S0 ++0x4268 GA_LINE_S1 ++0x4278 GA_COLOR_CONTROL ++0x427C GA_SOLID_RG ++0x4280 GA_SOLID_BA ++0x4288 GA_POLY_MODE ++0x428C GA_ROUND_MODE ++0x4290 GA_OFFSET ++0x4294 GA_FOG_SCALE ++0x4298 GA_FOG_OFFSET ++0x42A0 SU_TEX_WRAP ++0x42A4 SU_POLY_OFFSET_FRONT_SCALE ++0x42A8 SU_POLY_OFFSET_FRONT_OFFSET ++0x42AC SU_POLY_OFFSET_BACK_SCALE ++0x42B0 SU_POLY_OFFSET_BACK_OFFSET ++0x42B4 SU_POLY_OFFSET_ENABLE ++0x42B8 SU_CULL_MODE ++0x42C0 SU_DEPTH_SCALE ++0x42C4 SU_DEPTH_OFFSET ++0x42C8 SU_REG_DEST ++0x4300 RS_COUNT ++0x4304 RS_INST_COUNT ++0x4310 RS_IP_0 ++0x4314 RS_IP_1 ++0x4318 RS_IP_2 ++0x431C RS_IP_3 ++0x4320 RS_IP_4 ++0x4324 RS_IP_5 ++0x4328 RS_IP_6 ++0x432C RS_IP_7 ++0x4330 RS_INST_0 ++0x4334 RS_INST_1 ++0x4338 RS_INST_2 ++0x433C RS_INST_3 ++0x4340 RS_INST_4 ++0x4344 RS_INST_5 ++0x4348 RS_INST_6 ++0x434C RS_INST_7 ++0x4350 RS_INST_8 ++0x4354 RS_INST_9 ++0x4358 RS_INST_10 ++0x435C RS_INST_11 ++0x4360 RS_INST_12 ++0x4364 RS_INST_13 ++0x4368 RS_INST_14 ++0x436C RS_INST_15 ++0x43A4 SC_HYPERZ_EN ++0x43A8 SC_EDGERULE ++0x43B0 SC_CLIP_0_A ++0x43B4 SC_CLIP_0_B ++0x43B8 SC_CLIP_1_A ++0x43BC SC_CLIP_1_B ++0x43C0 SC_CLIP_2_A ++0x43C4 SC_CLIP_2_B ++0x43C8 SC_CLIP_3_A ++0x43CC SC_CLIP_3_B ++0x43D0 SC_CLIP_RULE ++0x43E0 SC_SCISSOR0 ++0x43E8 SC_SCREENDOOR ++0x4440 TX_FILTER1_0 ++0x4444 TX_FILTER1_1 ++0x4448 TX_FILTER1_2 ++0x444C TX_FILTER1_3 ++0x4450 TX_FILTER1_4 ++0x4454 TX_FILTER1_5 ++0x4458 TX_FILTER1_6 ++0x445C TX_FILTER1_7 ++0x4460 TX_FILTER1_8 ++0x4464 TX_FILTER1_9 ++0x4468 TX_FILTER1_10 ++0x446C TX_FILTER1_11 ++0x4470 TX_FILTER1_12 ++0x4474 TX_FILTER1_13 ++0x4478 TX_FILTER1_14 ++0x447C TX_FILTER1_15 ++0x4580 TX_CHROMA_KEY_0 ++0x4584 TX_CHROMA_KEY_1 ++0x4588 TX_CHROMA_KEY_2 ++0x458C TX_CHROMA_KEY_3 ++0x4590 TX_CHROMA_KEY_4 ++0x4594 TX_CHROMA_KEY_5 ++0x4598 TX_CHROMA_KEY_6 ++0x459C TX_CHROMA_KEY_7 ++0x45A0 TX_CHROMA_KEY_8 ++0x45A4 TX_CHROMA_KEY_9 ++0x45A8 TX_CHROMA_KEY_10 ++0x45AC TX_CHROMA_KEY_11 ++0x45B0 TX_CHROMA_KEY_12 ++0x45B4 TX_CHROMA_KEY_13 ++0x45B8 TX_CHROMA_KEY_14 ++0x45BC TX_CHROMA_KEY_15 ++0x45C0 TX_BORDER_COLOR_0 ++0x45C4 TX_BORDER_COLOR_1 ++0x45C8 TX_BORDER_COLOR_2 ++0x45CC TX_BORDER_COLOR_3 ++0x45D0 TX_BORDER_COLOR_4 ++0x45D4 TX_BORDER_COLOR_5 ++0x45D8 TX_BORDER_COLOR_6 ++0x45DC TX_BORDER_COLOR_7 ++0x45E0 TX_BORDER_COLOR_8 ++0x45E4 TX_BORDER_COLOR_9 ++0x45E8 TX_BORDER_COLOR_10 ++0x45EC TX_BORDER_COLOR_11 ++0x45F0 TX_BORDER_COLOR_12 ++0x45F4 TX_BORDER_COLOR_13 ++0x45F8 TX_BORDER_COLOR_14 ++0x45FC TX_BORDER_COLOR_15 ++0x4600 US_CONFIG ++0x4604 US_PIXSIZE ++0x4608 US_CODE_OFFSET ++0x460C US_RESET ++0x4610 US_CODE_ADDR_0 ++0x4614 US_CODE_ADDR_1 ++0x4618 US_CODE_ADDR_2 ++0x461C US_CODE_ADDR_3 ++0x4620 US_TEX_INST_0 ++0x4624 US_TEX_INST_1 ++0x4628 US_TEX_INST_2 ++0x462C US_TEX_INST_3 ++0x4630 US_TEX_INST_4 ++0x4634 US_TEX_INST_5 ++0x4638 US_TEX_INST_6 ++0x463C US_TEX_INST_7 ++0x4640 US_TEX_INST_8 ++0x4644 US_TEX_INST_9 ++0x4648 US_TEX_INST_10 ++0x464C US_TEX_INST_11 ++0x4650 US_TEX_INST_12 ++0x4654 US_TEX_INST_13 ++0x4658 US_TEX_INST_14 ++0x465C US_TEX_INST_15 ++0x4660 US_TEX_INST_16 ++0x4664 US_TEX_INST_17 ++0x4668 US_TEX_INST_18 ++0x466C US_TEX_INST_19 ++0x4670 US_TEX_INST_20 ++0x4674 US_TEX_INST_21 ++0x4678 US_TEX_INST_22 ++0x467C US_TEX_INST_23 ++0x4680 US_TEX_INST_24 ++0x4684 US_TEX_INST_25 ++0x4688 US_TEX_INST_26 ++0x468C US_TEX_INST_27 ++0x4690 US_TEX_INST_28 ++0x4694 US_TEX_INST_29 ++0x4698 US_TEX_INST_30 ++0x469C US_TEX_INST_31 ++0x46A4 US_OUT_FMT_0 ++0x46A8 US_OUT_FMT_1 ++0x46AC US_OUT_FMT_2 ++0x46B0 US_OUT_FMT_3 ++0x46B4 US_W_FMT ++0x46C0 US_ALU_RGB_ADDR_0 ++0x46C4 US_ALU_RGB_ADDR_1 ++0x46C8 US_ALU_RGB_ADDR_2 ++0x46CC US_ALU_RGB_ADDR_3 ++0x46D0 US_ALU_RGB_ADDR_4 ++0x46D4 US_ALU_RGB_ADDR_5 ++0x46D8 US_ALU_RGB_ADDR_6 ++0x46DC US_ALU_RGB_ADDR_7 ++0x46E0 US_ALU_RGB_ADDR_8 ++0x46E4 US_ALU_RGB_ADDR_9 ++0x46E8 US_ALU_RGB_ADDR_10 ++0x46EC US_ALU_RGB_ADDR_11 ++0x46F0 US_ALU_RGB_ADDR_12 ++0x46F4 US_ALU_RGB_ADDR_13 ++0x46F8 US_ALU_RGB_ADDR_14 ++0x46FC US_ALU_RGB_ADDR_15 ++0x4700 US_ALU_RGB_ADDR_16 ++0x4704 US_ALU_RGB_ADDR_17 ++0x4708 US_ALU_RGB_ADDR_18 ++0x470C US_ALU_RGB_ADDR_19 ++0x4710 US_ALU_RGB_ADDR_20 ++0x4714 US_ALU_RGB_ADDR_21 ++0x4718 US_ALU_RGB_ADDR_22 ++0x471C US_ALU_RGB_ADDR_23 ++0x4720 US_ALU_RGB_ADDR_24 ++0x4724 US_ALU_RGB_ADDR_25 ++0x4728 US_ALU_RGB_ADDR_26 ++0x472C US_ALU_RGB_ADDR_27 ++0x4730 US_ALU_RGB_ADDR_28 ++0x4734 US_ALU_RGB_ADDR_29 ++0x4738 US_ALU_RGB_ADDR_30 ++0x473C US_ALU_RGB_ADDR_31 ++0x4740 US_ALU_RGB_ADDR_32 ++0x4744 US_ALU_RGB_ADDR_33 ++0x4748 US_ALU_RGB_ADDR_34 ++0x474C US_ALU_RGB_ADDR_35 ++0x4750 US_ALU_RGB_ADDR_36 ++0x4754 US_ALU_RGB_ADDR_37 ++0x4758 US_ALU_RGB_ADDR_38 ++0x475C US_ALU_RGB_ADDR_39 ++0x4760 US_ALU_RGB_ADDR_40 ++0x4764 US_ALU_RGB_ADDR_41 ++0x4768 US_ALU_RGB_ADDR_42 ++0x476C US_ALU_RGB_ADDR_43 ++0x4770 US_ALU_RGB_ADDR_44 ++0x4774 US_ALU_RGB_ADDR_45 ++0x4778 US_ALU_RGB_ADDR_46 ++0x477C US_ALU_RGB_ADDR_47 ++0x4780 US_ALU_RGB_ADDR_48 ++0x4784 US_ALU_RGB_ADDR_49 ++0x4788 US_ALU_RGB_ADDR_50 ++0x478C US_ALU_RGB_ADDR_51 ++0x4790 US_ALU_RGB_ADDR_52 ++0x4794 US_ALU_RGB_ADDR_53 ++0x4798 US_ALU_RGB_ADDR_54 ++0x479C US_ALU_RGB_ADDR_55 ++0x47A0 US_ALU_RGB_ADDR_56 ++0x47A4 US_ALU_RGB_ADDR_57 ++0x47A8 US_ALU_RGB_ADDR_58 ++0x47AC US_ALU_RGB_ADDR_59 ++0x47B0 US_ALU_RGB_ADDR_60 ++0x47B4 US_ALU_RGB_ADDR_61 ++0x47B8 US_ALU_RGB_ADDR_62 ++0x47BC US_ALU_RGB_ADDR_63 ++0x47C0 US_ALU_ALPHA_ADDR_0 ++0x47C4 US_ALU_ALPHA_ADDR_1 ++0x47C8 US_ALU_ALPHA_ADDR_2 ++0x47CC US_ALU_ALPHA_ADDR_3 ++0x47D0 US_ALU_ALPHA_ADDR_4 ++0x47D4 US_ALU_ALPHA_ADDR_5 ++0x47D8 US_ALU_ALPHA_ADDR_6 ++0x47DC US_ALU_ALPHA_ADDR_7 ++0x47E0 US_ALU_ALPHA_ADDR_8 ++0x47E4 US_ALU_ALPHA_ADDR_9 ++0x47E8 US_ALU_ALPHA_ADDR_10 ++0x47EC US_ALU_ALPHA_ADDR_11 ++0x47F0 US_ALU_ALPHA_ADDR_12 ++0x47F4 US_ALU_ALPHA_ADDR_13 ++0x47F8 US_ALU_ALPHA_ADDR_14 ++0x47FC US_ALU_ALPHA_ADDR_15 ++0x4800 US_ALU_ALPHA_ADDR_16 ++0x4804 US_ALU_ALPHA_ADDR_17 ++0x4808 US_ALU_ALPHA_ADDR_18 ++0x480C US_ALU_ALPHA_ADDR_19 ++0x4810 US_ALU_ALPHA_ADDR_20 ++0x4814 US_ALU_ALPHA_ADDR_21 ++0x4818 US_ALU_ALPHA_ADDR_22 ++0x481C US_ALU_ALPHA_ADDR_23 ++0x4820 US_ALU_ALPHA_ADDR_24 ++0x4824 US_ALU_ALPHA_ADDR_25 ++0x4828 US_ALU_ALPHA_ADDR_26 ++0x482C US_ALU_ALPHA_ADDR_27 ++0x4830 US_ALU_ALPHA_ADDR_28 ++0x4834 US_ALU_ALPHA_ADDR_29 ++0x4838 US_ALU_ALPHA_ADDR_30 ++0x483C US_ALU_ALPHA_ADDR_31 ++0x4840 US_ALU_ALPHA_ADDR_32 ++0x4844 US_ALU_ALPHA_ADDR_33 ++0x4848 US_ALU_ALPHA_ADDR_34 ++0x484C US_ALU_ALPHA_ADDR_35 ++0x4850 US_ALU_ALPHA_ADDR_36 ++0x4854 US_ALU_ALPHA_ADDR_37 ++0x4858 US_ALU_ALPHA_ADDR_38 ++0x485C US_ALU_ALPHA_ADDR_39 ++0x4860 US_ALU_ALPHA_ADDR_40 ++0x4864 US_ALU_ALPHA_ADDR_41 ++0x4868 US_ALU_ALPHA_ADDR_42 ++0x486C US_ALU_ALPHA_ADDR_43 ++0x4870 US_ALU_ALPHA_ADDR_44 ++0x4874 US_ALU_ALPHA_ADDR_45 ++0x4878 US_ALU_ALPHA_ADDR_46 ++0x487C US_ALU_ALPHA_ADDR_47 ++0x4880 US_ALU_ALPHA_ADDR_48 ++0x4884 US_ALU_ALPHA_ADDR_49 ++0x4888 US_ALU_ALPHA_ADDR_50 ++0x488C US_ALU_ALPHA_ADDR_51 ++0x4890 US_ALU_ALPHA_ADDR_52 ++0x4894 US_ALU_ALPHA_ADDR_53 ++0x4898 US_ALU_ALPHA_ADDR_54 ++0x489C US_ALU_ALPHA_ADDR_55 ++0x48A0 US_ALU_ALPHA_ADDR_56 ++0x48A4 US_ALU_ALPHA_ADDR_57 ++0x48A8 US_ALU_ALPHA_ADDR_58 ++0x48AC US_ALU_ALPHA_ADDR_59 ++0x48B0 US_ALU_ALPHA_ADDR_60 ++0x48B4 US_ALU_ALPHA_ADDR_61 ++0x48B8 US_ALU_ALPHA_ADDR_62 ++0x48BC US_ALU_ALPHA_ADDR_63 ++0x48C0 US_ALU_RGB_INST_0 ++0x48C4 US_ALU_RGB_INST_1 ++0x48C8 US_ALU_RGB_INST_2 ++0x48CC US_ALU_RGB_INST_3 ++0x48D0 US_ALU_RGB_INST_4 ++0x48D4 US_ALU_RGB_INST_5 ++0x48D8 US_ALU_RGB_INST_6 ++0x48DC US_ALU_RGB_INST_7 ++0x48E0 US_ALU_RGB_INST_8 ++0x48E4 US_ALU_RGB_INST_9 ++0x48E8 US_ALU_RGB_INST_10 ++0x48EC US_ALU_RGB_INST_11 ++0x48F0 US_ALU_RGB_INST_12 ++0x48F4 US_ALU_RGB_INST_13 ++0x48F8 US_ALU_RGB_INST_14 ++0x48FC US_ALU_RGB_INST_15 ++0x4900 US_ALU_RGB_INST_16 ++0x4904 US_ALU_RGB_INST_17 ++0x4908 US_ALU_RGB_INST_18 ++0x490C US_ALU_RGB_INST_19 ++0x4910 US_ALU_RGB_INST_20 ++0x4914 US_ALU_RGB_INST_21 ++0x4918 US_ALU_RGB_INST_22 ++0x491C US_ALU_RGB_INST_23 ++0x4920 US_ALU_RGB_INST_24 ++0x4924 US_ALU_RGB_INST_25 ++0x4928 US_ALU_RGB_INST_26 ++0x492C US_ALU_RGB_INST_27 ++0x4930 US_ALU_RGB_INST_28 ++0x4934 US_ALU_RGB_INST_29 ++0x4938 US_ALU_RGB_INST_30 ++0x493C US_ALU_RGB_INST_31 ++0x4940 US_ALU_RGB_INST_32 ++0x4944 US_ALU_RGB_INST_33 ++0x4948 US_ALU_RGB_INST_34 ++0x494C US_ALU_RGB_INST_35 ++0x4950 US_ALU_RGB_INST_36 ++0x4954 US_ALU_RGB_INST_37 ++0x4958 US_ALU_RGB_INST_38 ++0x495C US_ALU_RGB_INST_39 ++0x4960 US_ALU_RGB_INST_40 ++0x4964 US_ALU_RGB_INST_41 ++0x4968 US_ALU_RGB_INST_42 ++0x496C US_ALU_RGB_INST_43 ++0x4970 US_ALU_RGB_INST_44 ++0x4974 US_ALU_RGB_INST_45 ++0x4978 US_ALU_RGB_INST_46 ++0x497C US_ALU_RGB_INST_47 ++0x4980 US_ALU_RGB_INST_48 ++0x4984 US_ALU_RGB_INST_49 ++0x4988 US_ALU_RGB_INST_50 ++0x498C US_ALU_RGB_INST_51 ++0x4990 US_ALU_RGB_INST_52 ++0x4994 US_ALU_RGB_INST_53 ++0x4998 US_ALU_RGB_INST_54 ++0x499C US_ALU_RGB_INST_55 ++0x49A0 US_ALU_RGB_INST_56 ++0x49A4 US_ALU_RGB_INST_57 ++0x49A8 US_ALU_RGB_INST_58 ++0x49AC US_ALU_RGB_INST_59 ++0x49B0 US_ALU_RGB_INST_60 ++0x49B4 US_ALU_RGB_INST_61 ++0x49B8 US_ALU_RGB_INST_62 ++0x49BC US_ALU_RGB_INST_63 ++0x49C0 US_ALU_ALPHA_INST_0 ++0x49C4 US_ALU_ALPHA_INST_1 ++0x49C8 US_ALU_ALPHA_INST_2 ++0x49CC US_ALU_ALPHA_INST_3 ++0x49D0 US_ALU_ALPHA_INST_4 ++0x49D4 US_ALU_ALPHA_INST_5 ++0x49D8 US_ALU_ALPHA_INST_6 ++0x49DC US_ALU_ALPHA_INST_7 ++0x49E0 US_ALU_ALPHA_INST_8 ++0x49E4 US_ALU_ALPHA_INST_9 ++0x49E8 US_ALU_ALPHA_INST_10 ++0x49EC US_ALU_ALPHA_INST_11 ++0x49F0 US_ALU_ALPHA_INST_12 ++0x49F4 US_ALU_ALPHA_INST_13 ++0x49F8 US_ALU_ALPHA_INST_14 ++0x49FC US_ALU_ALPHA_INST_15 ++0x4A00 US_ALU_ALPHA_INST_16 ++0x4A04 US_ALU_ALPHA_INST_17 ++0x4A08 US_ALU_ALPHA_INST_18 ++0x4A0C US_ALU_ALPHA_INST_19 ++0x4A10 US_ALU_ALPHA_INST_20 ++0x4A14 US_ALU_ALPHA_INST_21 ++0x4A18 US_ALU_ALPHA_INST_22 ++0x4A1C US_ALU_ALPHA_INST_23 ++0x4A20 US_ALU_ALPHA_INST_24 ++0x4A24 US_ALU_ALPHA_INST_25 ++0x4A28 US_ALU_ALPHA_INST_26 ++0x4A2C US_ALU_ALPHA_INST_27 ++0x4A30 US_ALU_ALPHA_INST_28 ++0x4A34 US_ALU_ALPHA_INST_29 ++0x4A38 US_ALU_ALPHA_INST_30 ++0x4A3C US_ALU_ALPHA_INST_31 ++0x4A40 US_ALU_ALPHA_INST_32 ++0x4A44 US_ALU_ALPHA_INST_33 ++0x4A48 US_ALU_ALPHA_INST_34 ++0x4A4C US_ALU_ALPHA_INST_35 ++0x4A50 US_ALU_ALPHA_INST_36 ++0x4A54 US_ALU_ALPHA_INST_37 ++0x4A58 US_ALU_ALPHA_INST_38 ++0x4A5C US_ALU_ALPHA_INST_39 ++0x4A60 US_ALU_ALPHA_INST_40 ++0x4A64 US_ALU_ALPHA_INST_41 ++0x4A68 US_ALU_ALPHA_INST_42 ++0x4A6C US_ALU_ALPHA_INST_43 ++0x4A70 US_ALU_ALPHA_INST_44 ++0x4A74 US_ALU_ALPHA_INST_45 ++0x4A78 US_ALU_ALPHA_INST_46 ++0x4A7C US_ALU_ALPHA_INST_47 ++0x4A80 US_ALU_ALPHA_INST_48 ++0x4A84 US_ALU_ALPHA_INST_49 ++0x4A88 US_ALU_ALPHA_INST_50 ++0x4A8C US_ALU_ALPHA_INST_51 ++0x4A90 US_ALU_ALPHA_INST_52 ++0x4A94 US_ALU_ALPHA_INST_53 ++0x4A98 US_ALU_ALPHA_INST_54 ++0x4A9C US_ALU_ALPHA_INST_55 ++0x4AA0 US_ALU_ALPHA_INST_56 ++0x4AA4 US_ALU_ALPHA_INST_57 ++0x4AA8 US_ALU_ALPHA_INST_58 ++0x4AAC US_ALU_ALPHA_INST_59 ++0x4AB0 US_ALU_ALPHA_INST_60 ++0x4AB4 US_ALU_ALPHA_INST_61 ++0x4AB8 US_ALU_ALPHA_INST_62 ++0x4ABC US_ALU_ALPHA_INST_63 ++0x4BC0 FG_FOG_BLEND ++0x4BC4 FG_FOG_FACTOR ++0x4BC8 FG_FOG_COLOR_R ++0x4BCC FG_FOG_COLOR_G ++0x4BD0 FG_FOG_COLOR_B ++0x4BD4 FG_ALPHA_FUNC ++0x4BD8 FG_DEPTH_SRC ++0x4C00 US_ALU_CONST_R_0 ++0x4C04 US_ALU_CONST_G_0 ++0x4C08 US_ALU_CONST_B_0 ++0x4C0C US_ALU_CONST_A_0 ++0x4C10 US_ALU_CONST_R_1 ++0x4C14 US_ALU_CONST_G_1 ++0x4C18 US_ALU_CONST_B_1 ++0x4C1C US_ALU_CONST_A_1 ++0x4C20 US_ALU_CONST_R_2 ++0x4C24 US_ALU_CONST_G_2 ++0x4C28 US_ALU_CONST_B_2 ++0x4C2C US_ALU_CONST_A_2 ++0x4C30 US_ALU_CONST_R_3 ++0x4C34 US_ALU_CONST_G_3 ++0x4C38 US_ALU_CONST_B_3 ++0x4C3C US_ALU_CONST_A_3 ++0x4C40 US_ALU_CONST_R_4 ++0x4C44 US_ALU_CONST_G_4 ++0x4C48 US_ALU_CONST_B_4 ++0x4C4C US_ALU_CONST_A_4 ++0x4C50 US_ALU_CONST_R_5 ++0x4C54 US_ALU_CONST_G_5 ++0x4C58 US_ALU_CONST_B_5 ++0x4C5C US_ALU_CONST_A_5 ++0x4C60 US_ALU_CONST_R_6 ++0x4C64 US_ALU_CONST_G_6 ++0x4C68 US_ALU_CONST_B_6 ++0x4C6C US_ALU_CONST_A_6 ++0x4C70 US_ALU_CONST_R_7 ++0x4C74 US_ALU_CONST_G_7 ++0x4C78 US_ALU_CONST_B_7 ++0x4C7C US_ALU_CONST_A_7 ++0x4C80 US_ALU_CONST_R_8 ++0x4C84 US_ALU_CONST_G_8 ++0x4C88 US_ALU_CONST_B_8 ++0x4C8C US_ALU_CONST_A_8 ++0x4C90 US_ALU_CONST_R_9 ++0x4C94 US_ALU_CONST_G_9 ++0x4C98 US_ALU_CONST_B_9 ++0x4C9C US_ALU_CONST_A_9 ++0x4CA0 US_ALU_CONST_R_10 ++0x4CA4 US_ALU_CONST_G_10 ++0x4CA8 US_ALU_CONST_B_10 ++0x4CAC US_ALU_CONST_A_10 ++0x4CB0 US_ALU_CONST_R_11 ++0x4CB4 US_ALU_CONST_G_11 ++0x4CB8 US_ALU_CONST_B_11 ++0x4CBC US_ALU_CONST_A_11 ++0x4CC0 US_ALU_CONST_R_12 ++0x4CC4 US_ALU_CONST_G_12 ++0x4CC8 US_ALU_CONST_B_12 ++0x4CCC US_ALU_CONST_A_12 ++0x4CD0 US_ALU_CONST_R_13 ++0x4CD4 US_ALU_CONST_G_13 ++0x4CD8 US_ALU_CONST_B_13 ++0x4CDC US_ALU_CONST_A_13 ++0x4CE0 US_ALU_CONST_R_14 ++0x4CE4 US_ALU_CONST_G_14 ++0x4CE8 US_ALU_CONST_B_14 ++0x4CEC US_ALU_CONST_A_14 ++0x4CF0 US_ALU_CONST_R_15 ++0x4CF4 US_ALU_CONST_G_15 ++0x4CF8 US_ALU_CONST_B_15 ++0x4CFC US_ALU_CONST_A_15 ++0x4D00 US_ALU_CONST_R_16 ++0x4D04 US_ALU_CONST_G_16 ++0x4D08 US_ALU_CONST_B_16 ++0x4D0C US_ALU_CONST_A_16 ++0x4D10 US_ALU_CONST_R_17 ++0x4D14 US_ALU_CONST_G_17 ++0x4D18 US_ALU_CONST_B_17 ++0x4D1C US_ALU_CONST_A_17 ++0x4D20 US_ALU_CONST_R_18 ++0x4D24 US_ALU_CONST_G_18 ++0x4D28 US_ALU_CONST_B_18 ++0x4D2C US_ALU_CONST_A_18 ++0x4D30 US_ALU_CONST_R_19 ++0x4D34 US_ALU_CONST_G_19 ++0x4D38 US_ALU_CONST_B_19 ++0x4D3C US_ALU_CONST_A_19 ++0x4D40 US_ALU_CONST_R_20 ++0x4D44 US_ALU_CONST_G_20 ++0x4D48 US_ALU_CONST_B_20 ++0x4D4C US_ALU_CONST_A_20 ++0x4D50 US_ALU_CONST_R_21 ++0x4D54 US_ALU_CONST_G_21 ++0x4D58 US_ALU_CONST_B_21 ++0x4D5C US_ALU_CONST_A_21 ++0x4D60 US_ALU_CONST_R_22 ++0x4D64 US_ALU_CONST_G_22 ++0x4D68 US_ALU_CONST_B_22 ++0x4D6C US_ALU_CONST_A_22 ++0x4D70 US_ALU_CONST_R_23 ++0x4D74 US_ALU_CONST_G_23 ++0x4D78 US_ALU_CONST_B_23 ++0x4D7C US_ALU_CONST_A_23 ++0x4D80 US_ALU_CONST_R_24 ++0x4D84 US_ALU_CONST_G_24 ++0x4D88 US_ALU_CONST_B_24 ++0x4D8C US_ALU_CONST_A_24 ++0x4D90 US_ALU_CONST_R_25 ++0x4D94 US_ALU_CONST_G_25 ++0x4D98 US_ALU_CONST_B_25 ++0x4D9C US_ALU_CONST_A_25 ++0x4DA0 US_ALU_CONST_R_26 ++0x4DA4 US_ALU_CONST_G_26 ++0x4DA8 US_ALU_CONST_B_26 ++0x4DAC US_ALU_CONST_A_26 ++0x4DB0 US_ALU_CONST_R_27 ++0x4DB4 US_ALU_CONST_G_27 ++0x4DB8 US_ALU_CONST_B_27 ++0x4DBC US_ALU_CONST_A_27 ++0x4DC0 US_ALU_CONST_R_28 ++0x4DC4 US_ALU_CONST_G_28 ++0x4DC8 US_ALU_CONST_B_28 ++0x4DCC US_ALU_CONST_A_28 ++0x4DD0 US_ALU_CONST_R_29 ++0x4DD4 US_ALU_CONST_G_29 ++0x4DD8 US_ALU_CONST_B_29 ++0x4DDC US_ALU_CONST_A_29 ++0x4DE0 US_ALU_CONST_R_30 ++0x4DE4 US_ALU_CONST_G_30 ++0x4DE8 US_ALU_CONST_B_30 ++0x4DEC US_ALU_CONST_A_30 ++0x4DF0 US_ALU_CONST_R_31 ++0x4DF4 US_ALU_CONST_G_31 ++0x4DF8 US_ALU_CONST_B_31 ++0x4DFC US_ALU_CONST_A_31 ++0x4E04 RB3D_BLENDCNTL_R3 ++0x4E08 RB3D_ABLENDCNTL_R3 ++0x4E0C RB3D_COLOR_CHANNEL_MASK ++0x4E10 RB3D_CONSTANT_COLOR ++0x4E14 RB3D_COLOR_CLEAR_VALUE ++0x4E18 RB3D_ROPCNTL_R3 ++0x4E1C RB3D_CLRCMP_FLIPE_R3 ++0x4E20 RB3D_CLRCMP_CLR_R3 ++0x4E24 RB3D_CLRCMP_MSK_R3 ++0x4E48 RB3D_DEBUG_CTL ++0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 ++0x4E50 RB3D_DITHER_CTL ++0x4E54 RB3D_CMASK_OFFSET0 ++0x4E58 RB3D_CMASK_OFFSET1 ++0x4E5C RB3D_CMASK_OFFSET2 ++0x4E60 RB3D_CMASK_OFFSET3 ++0x4E64 RB3D_CMASK_PITCH0 ++0x4E68 RB3D_CMASK_PITCH1 ++0x4E6C RB3D_CMASK_PITCH2 ++0x4E70 RB3D_CMASK_PITCH3 ++0x4E74 RB3D_CMASK_WRINDEX ++0x4E78 RB3D_CMASK_DWORD ++0x4E7C RB3D_CMASK_RDINDEX ++0x4E80 RB3D_AARESOLVE_OFFSET ++0x4E84 RB3D_AARESOLVE_PITCH ++0x4E88 RB3D_AARESOLVE_CTL ++0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD ++0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD ++0x4F04 ZB_ZSTENCILCNTL ++0x4F08 ZB_STENCILREFMASK ++0x4F14 ZB_ZTOP ++0x4F18 ZB_ZCACHE_CTLSTAT ++0x4F1C ZB_BW_CNTL ++0x4F28 ZB_DEPTHCLEARVALUE ++0x4F30 ZB_ZMASK_OFFSET ++0x4F34 ZB_ZMASK_PITCH ++0x4F38 ZB_ZMASK_WRINDEX ++0x4F3C ZB_ZMASK_DWORD ++0x4F40 ZB_ZMASK_RDINDEX ++0x4F44 ZB_HIZ_OFFSET ++0x4F48 ZB_HIZ_WRINDEX ++0x4F4C ZB_HIZ_DWORD ++0x4F50 ZB_HIZ_RDINDEX ++0x4F54 ZB_HIZ_PITCH ++0x4F58 ZB_ZPASS_DATA +diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515 +new file mode 100644 +index 0000000..0102a0d +--- /dev/null ++++ b/drivers/gpu/drm/radeon/reg_srcs/rv515 +@@ -0,0 +1,486 @@ ++rv515 0x6d40 ++0x1434 SRC_Y_X ++0x1438 DST_Y_X ++0x143C DST_HEIGHT_WIDTH ++0x146C DP_GUI_MASTER_CNTL ++0x1474 BRUSH_Y_X ++0x1478 DP_BRUSH_BKGD_CLR ++0x147C DP_BRUSH_FRGD_CLR ++0x1480 BRUSH_DATA0 ++0x1484 BRUSH_DATA1 ++0x1598 DST_WIDTH_HEIGHT ++0x15C0 CLR_CMP_CNTL ++0x15C4 CLR_CMP_CLR_SRC ++0x15C8 CLR_CMP_CLR_DST ++0x15CC CLR_CMP_MSK ++0x15D8 DP_SRC_FRGD_CLR ++0x15DC DP_SRC_BKGD_CLR ++0x1600 DST_LINE_START ++0x1604 DST_LINE_END ++0x1608 DST_LINE_PATCOUNT ++0x16C0 DP_CNTL ++0x16CC DP_WRITE_MSK ++0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR ++0x16E8 DEFAULT_SC_BOTTOM_RIGHT ++0x16EC SC_TOP_LEFT ++0x16F0 SC_BOTTOM_RIGHT ++0x16F4 SRC_SC_BOTTOM_RIGHT ++0x1714 DSTCACHE_CTLSTAT ++0x1720 WAIT_UNTIL ++0x172C RBBM_GUICNTL ++0x1D98 VAP_VPORT_XSCALE ++0x1D9C VAP_VPORT_XOFFSET ++0x1DA0 VAP_VPORT_YSCALE ++0x1DA4 VAP_VPORT_YOFFSET ++0x1DA8 VAP_VPORT_ZSCALE ++0x1DAC VAP_VPORT_ZOFFSET ++0x2080 VAP_CNTL ++0x2090 VAP_OUT_VTX_FMT_0 ++0x2094 VAP_OUT_VTX_FMT_1 ++0x20B0 VAP_VTE_CNTL ++0x2138 VAP_VF_MIN_VTX_INDX ++0x2140 VAP_CNTL_STATUS ++0x2150 VAP_PROG_STREAM_CNTL_0 ++0x2154 VAP_PROG_STREAM_CNTL_1 ++0x2158 VAP_PROG_STREAM_CNTL_2 ++0x215C VAP_PROG_STREAM_CNTL_3 ++0x2160 VAP_PROG_STREAM_CNTL_4 ++0x2164 VAP_PROG_STREAM_CNTL_5 ++0x2168 VAP_PROG_STREAM_CNTL_6 ++0x216C VAP_PROG_STREAM_CNTL_7 ++0x2180 VAP_VTX_STATE_CNTL ++0x2184 VAP_VSM_VTX_ASSM ++0x2188 VAP_VTX_STATE_IND_REG_0 ++0x218C VAP_VTX_STATE_IND_REG_1 ++0x2190 VAP_VTX_STATE_IND_REG_2 ++0x2194 VAP_VTX_STATE_IND_REG_3 ++0x2198 VAP_VTX_STATE_IND_REG_4 ++0x219C VAP_VTX_STATE_IND_REG_5 ++0x21A0 VAP_VTX_STATE_IND_REG_6 ++0x21A4 VAP_VTX_STATE_IND_REG_7 ++0x21A8 VAP_VTX_STATE_IND_REG_8 ++0x21AC VAP_VTX_STATE_IND_REG_9 ++0x21B0 VAP_VTX_STATE_IND_REG_10 ++0x21B4 VAP_VTX_STATE_IND_REG_11 ++0x21B8 VAP_VTX_STATE_IND_REG_12 ++0x21BC VAP_VTX_STATE_IND_REG_13 ++0x21C0 VAP_VTX_STATE_IND_REG_14 ++0x21C4 VAP_VTX_STATE_IND_REG_15 ++0x21DC VAP_PSC_SGN_NORM_CNTL ++0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 ++0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 ++0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 ++0x21EC VAP_PROG_STREAM_CNTL_EXT_3 ++0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 ++0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 ++0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 ++0x21FC VAP_PROG_STREAM_CNTL_EXT_7 ++0x2200 VAP_PVS_VECTOR_INDX_REG ++0x2204 VAP_PVS_VECTOR_DATA_REG ++0x2208 VAP_PVS_VECTOR_DATA_REG_128 ++0x2218 VAP_TEX_TO_COLOR_CNTL ++0x221C VAP_CLIP_CNTL ++0x2220 VAP_GB_VERT_CLIP_ADJ ++0x2224 VAP_GB_VERT_DISC_ADJ ++0x2228 VAP_GB_HORZ_CLIP_ADJ ++0x222C VAP_GB_HORZ_DISC_ADJ ++0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 ++0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 ++0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 ++0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 ++0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 ++0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 ++0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 ++0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 ++0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 ++0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 ++0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 ++0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 ++0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 ++0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 ++0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 ++0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 ++0x2284 VAP_PVS_STATE_FLUSH_REG ++0x2288 VAP_PVS_VTX_TIMEOUT_REG ++0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 ++0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 ++0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 ++0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 ++0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 ++0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 ++0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 ++0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 ++0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 ++0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 ++0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 ++0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 ++0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 ++0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 ++0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 ++0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 ++0x22D0 VAP_PVS_CODE_CNTL_0 ++0x22D4 VAP_PVS_CONST_CNTL ++0x22D8 VAP_PVS_CODE_CNTL_1 ++0x22DC VAP_PVS_FLOW_CNTL_OPC ++0x2500 VAP_PVS_FLOW_CNTL_ADDRS_LW_0 ++0x2504 VAP_PVS_FLOW_CNTL_ADDRS_UW_0 ++0x2508 VAP_PVS_FLOW_CNTL_ADDRS_LW_1 ++0x250C VAP_PVS_FLOW_CNTL_ADDRS_UW_1 ++0x2510 VAP_PVS_FLOW_CNTL_ADDRS_LW_2 ++0x2514 VAP_PVS_FLOW_CNTL_ADDRS_UW_2 ++0x2518 VAP_PVS_FLOW_CNTL_ADDRS_LW_3 ++0x251C VAP_PVS_FLOW_CNTL_ADDRS_UW_3 ++0x2520 VAP_PVS_FLOW_CNTL_ADDRS_LW_4 ++0x2524 VAP_PVS_FLOW_CNTL_ADDRS_UW_4 ++0x2528 VAP_PVS_FLOW_CNTL_ADDRS_LW_5 ++0x252C VAP_PVS_FLOW_CNTL_ADDRS_UW_5 ++0x2530 VAP_PVS_FLOW_CNTL_ADDRS_LW_6 ++0x2534 VAP_PVS_FLOW_CNTL_ADDRS_UW_6 ++0x2538 VAP_PVS_FLOW_CNTL_ADDRS_LW_7 ++0x253C VAP_PVS_FLOW_CNTL_ADDRS_UW_7 ++0x2540 VAP_PVS_FLOW_CNTL_ADDRS_LW_8 ++0x2544 VAP_PVS_FLOW_CNTL_ADDRS_UW_8 ++0x2548 VAP_PVS_FLOW_CNTL_ADDRS_LW_9 ++0x254C VAP_PVS_FLOW_CNTL_ADDRS_UW_9 ++0x2550 VAP_PVS_FLOW_CNTL_ADDRS_LW_10 ++0x2554 VAP_PVS_FLOW_CNTL_ADDRS_UW_10 ++0x2558 VAP_PVS_FLOW_CNTL_ADDRS_LW_11 ++0x255C VAP_PVS_FLOW_CNTL_ADDRS_UW_11 ++0x2560 VAP_PVS_FLOW_CNTL_ADDRS_LW_12 ++0x2564 VAP_PVS_FLOW_CNTL_ADDRS_UW_12 ++0x2568 VAP_PVS_FLOW_CNTL_ADDRS_LW_13 ++0x256C VAP_PVS_FLOW_CNTL_ADDRS_UW_13 ++0x2570 VAP_PVS_FLOW_CNTL_ADDRS_LW_14 ++0x2574 VAP_PVS_FLOW_CNTL_ADDRS_UW_14 ++0x2578 VAP_PVS_FLOW_CNTL_ADDRS_LW_15 ++0x257C VAP_PVS_FLOW_CNTL_ADDRS_UW_15 ++0x342C RB2D_DSTCACHE_CTLSTAT ++0x4000 GB_VAP_RASTER_VTX_FMT_0 ++0x4004 GB_VAP_RASTER_VTX_FMT_1 ++0x4008 GB_ENABLE ++0x401C GB_SELECT ++0x4020 GB_AA_CONFIG ++0x4024 GB_FIFO_SIZE ++0x4100 TX_INVALTAGS ++0x4200 GA_POINT_S0 ++0x4204 GA_POINT_T0 ++0x4208 GA_POINT_S1 ++0x420C GA_POINT_T1 ++0x4214 GA_TRIANGLE_STIPPLE ++0x421C GA_POINT_SIZE ++0x4230 GA_POINT_MINMAX ++0x4234 GA_LINE_CNTL ++0x4238 GA_LINE_STIPPLE_CONFIG ++0x4260 GA_LINE_STIPPLE_VALUE ++0x4264 GA_LINE_S0 ++0x4268 GA_LINE_S1 ++0x4278 GA_COLOR_CONTROL ++0x427C GA_SOLID_RG ++0x4280 GA_SOLID_BA ++0x4288 GA_POLY_MODE ++0x428C GA_ROUND_MODE ++0x4290 GA_OFFSET ++0x4294 GA_FOG_SCALE ++0x4298 GA_FOG_OFFSET ++0x42A0 SU_TEX_WRAP ++0x42A4 SU_POLY_OFFSET_FRONT_SCALE ++0x42A8 SU_POLY_OFFSET_FRONT_OFFSET ++0x42AC SU_POLY_OFFSET_BACK_SCALE ++0x42B0 SU_POLY_OFFSET_BACK_OFFSET ++0x42B4 SU_POLY_OFFSET_ENABLE ++0x42B8 SU_CULL_MODE ++0x42C0 SU_DEPTH_SCALE ++0x42C4 SU_DEPTH_OFFSET ++0x42C8 SU_REG_DEST ++0x4300 RS_COUNT ++0x4304 RS_INST_COUNT ++0x4074 RS_IP_0 ++0x4078 RS_IP_1 ++0x407C RS_IP_2 ++0x4080 RS_IP_3 ++0x4084 RS_IP_4 ++0x4088 RS_IP_5 ++0x408C RS_IP_6 ++0x4090 RS_IP_7 ++0x4094 RS_IP_8 ++0x4098 RS_IP_9 ++0x409C RS_IP_10 ++0x40A0 RS_IP_11 ++0x40A4 RS_IP_12 ++0x40A8 RS_IP_13 ++0x40AC RS_IP_14 ++0x40B0 RS_IP_15 ++0x4320 RS_INST_0 ++0x4324 RS_INST_1 ++0x4328 RS_INST_2 ++0x432C RS_INST_3 ++0x4330 RS_INST_4 ++0x4334 RS_INST_5 ++0x4338 RS_INST_6 ++0x433C RS_INST_7 ++0x4340 RS_INST_8 ++0x4344 RS_INST_9 ++0x4348 RS_INST_10 ++0x434C RS_INST_11 ++0x4350 RS_INST_12 ++0x4354 RS_INST_13 ++0x4358 RS_INST_14 ++0x435C RS_INST_15 ++0x43A4 SC_HYPERZ_EN ++0x43A8 SC_EDGERULE ++0x43B0 SC_CLIP_0_A ++0x43B4 SC_CLIP_0_B ++0x43B8 SC_CLIP_1_A ++0x43BC SC_CLIP_1_B ++0x43C0 SC_CLIP_2_A ++0x43C4 SC_CLIP_2_B ++0x43C8 SC_CLIP_3_A ++0x43CC SC_CLIP_3_B ++0x43D0 SC_CLIP_RULE ++0x43E0 SC_SCISSOR0 ++0x43E8 SC_SCREENDOOR ++0x4440 TX_FILTER1_0 ++0x4444 TX_FILTER1_1 ++0x4448 TX_FILTER1_2 ++0x444C TX_FILTER1_3 ++0x4450 TX_FILTER1_4 ++0x4454 TX_FILTER1_5 ++0x4458 TX_FILTER1_6 ++0x445C TX_FILTER1_7 ++0x4460 TX_FILTER1_8 ++0x4464 TX_FILTER1_9 ++0x4468 TX_FILTER1_10 ++0x446C TX_FILTER1_11 ++0x4470 TX_FILTER1_12 ++0x4474 TX_FILTER1_13 ++0x4478 TX_FILTER1_14 ++0x447C TX_FILTER1_15 ++0x4580 TX_CHROMA_KEY_0 ++0x4584 TX_CHROMA_KEY_1 ++0x4588 TX_CHROMA_KEY_2 ++0x458C TX_CHROMA_KEY_3 ++0x4590 TX_CHROMA_KEY_4 ++0x4594 TX_CHROMA_KEY_5 ++0x4598 TX_CHROMA_KEY_6 ++0x459C TX_CHROMA_KEY_7 ++0x45A0 TX_CHROMA_KEY_8 ++0x45A4 TX_CHROMA_KEY_9 ++0x45A8 TX_CHROMA_KEY_10 ++0x45AC TX_CHROMA_KEY_11 ++0x45B0 TX_CHROMA_KEY_12 ++0x45B4 TX_CHROMA_KEY_13 ++0x45B8 TX_CHROMA_KEY_14 ++0x45BC TX_CHROMA_KEY_15 ++0x45C0 TX_BORDER_COLOR_0 ++0x45C4 TX_BORDER_COLOR_1 ++0x45C8 TX_BORDER_COLOR_2 ++0x45CC TX_BORDER_COLOR_3 ++0x45D0 TX_BORDER_COLOR_4 ++0x45D4 TX_BORDER_COLOR_5 ++0x45D8 TX_BORDER_COLOR_6 ++0x45DC TX_BORDER_COLOR_7 ++0x45E0 TX_BORDER_COLOR_8 ++0x45E4 TX_BORDER_COLOR_9 ++0x45E8 TX_BORDER_COLOR_10 ++0x45EC TX_BORDER_COLOR_11 ++0x45F0 TX_BORDER_COLOR_12 ++0x45F4 TX_BORDER_COLOR_13 ++0x45F8 TX_BORDER_COLOR_14 ++0x45FC TX_BORDER_COLOR_15 ++0x4250 GA_US_VECTOR_INDEX ++0x4254 GA_US_VECTOR_DATA ++0x4600 US_CONFIG ++0x4604 US_PIXSIZE ++0x4620 US_FC_BOOL_CONST ++0x4624 US_FC_CTRL ++0x4630 US_CODE_ADDR ++0x4634 US_CODE_RANGE ++0x4638 US_CODE_OFFSET ++0x46A4 US_OUT_FMT_0 ++0x46A8 US_OUT_FMT_1 ++0x46AC US_OUT_FMT_2 ++0x46B0 US_OUT_FMT_3 ++0x46B4 US_W_FMT ++0x4BC0 FG_FOG_BLEND ++0x4BC4 FG_FOG_FACTOR ++0x4BC8 FG_FOG_COLOR_R ++0x4BCC FG_FOG_COLOR_G ++0x4BD0 FG_FOG_COLOR_B ++0x4BD4 FG_ALPHA_FUNC ++0x4BD8 FG_DEPTH_SRC ++0x4C00 US_ALU_CONST_R_0 ++0x4C04 US_ALU_CONST_G_0 ++0x4C08 US_ALU_CONST_B_0 ++0x4C0C US_ALU_CONST_A_0 ++0x4C10 US_ALU_CONST_R_1 ++0x4C14 US_ALU_CONST_G_1 ++0x4C18 US_ALU_CONST_B_1 ++0x4C1C US_ALU_CONST_A_1 ++0x4C20 US_ALU_CONST_R_2 ++0x4C24 US_ALU_CONST_G_2 ++0x4C28 US_ALU_CONST_B_2 ++0x4C2C US_ALU_CONST_A_2 ++0x4C30 US_ALU_CONST_R_3 ++0x4C34 US_ALU_CONST_G_3 ++0x4C38 US_ALU_CONST_B_3 ++0x4C3C US_ALU_CONST_A_3 ++0x4C40 US_ALU_CONST_R_4 ++0x4C44 US_ALU_CONST_G_4 ++0x4C48 US_ALU_CONST_B_4 ++0x4C4C US_ALU_CONST_A_4 ++0x4C50 US_ALU_CONST_R_5 ++0x4C54 US_ALU_CONST_G_5 ++0x4C58 US_ALU_CONST_B_5 ++0x4C5C US_ALU_CONST_A_5 ++0x4C60 US_ALU_CONST_R_6 ++0x4C64 US_ALU_CONST_G_6 ++0x4C68 US_ALU_CONST_B_6 ++0x4C6C US_ALU_CONST_A_6 ++0x4C70 US_ALU_CONST_R_7 ++0x4C74 US_ALU_CONST_G_7 ++0x4C78 US_ALU_CONST_B_7 ++0x4C7C US_ALU_CONST_A_7 ++0x4C80 US_ALU_CONST_R_8 ++0x4C84 US_ALU_CONST_G_8 ++0x4C88 US_ALU_CONST_B_8 ++0x4C8C US_ALU_CONST_A_8 ++0x4C90 US_ALU_CONST_R_9 ++0x4C94 US_ALU_CONST_G_9 ++0x4C98 US_ALU_CONST_B_9 ++0x4C9C US_ALU_CONST_A_9 ++0x4CA0 US_ALU_CONST_R_10 ++0x4CA4 US_ALU_CONST_G_10 ++0x4CA8 US_ALU_CONST_B_10 ++0x4CAC US_ALU_CONST_A_10 ++0x4CB0 US_ALU_CONST_R_11 ++0x4CB4 US_ALU_CONST_G_11 ++0x4CB8 US_ALU_CONST_B_11 ++0x4CBC US_ALU_CONST_A_11 ++0x4CC0 US_ALU_CONST_R_12 ++0x4CC4 US_ALU_CONST_G_12 ++0x4CC8 US_ALU_CONST_B_12 ++0x4CCC US_ALU_CONST_A_12 ++0x4CD0 US_ALU_CONST_R_13 ++0x4CD4 US_ALU_CONST_G_13 ++0x4CD8 US_ALU_CONST_B_13 ++0x4CDC US_ALU_CONST_A_13 ++0x4CE0 US_ALU_CONST_R_14 ++0x4CE4 US_ALU_CONST_G_14 ++0x4CE8 US_ALU_CONST_B_14 ++0x4CEC US_ALU_CONST_A_14 ++0x4CF0 US_ALU_CONST_R_15 ++0x4CF4 US_ALU_CONST_G_15 ++0x4CF8 US_ALU_CONST_B_15 ++0x4CFC US_ALU_CONST_A_15 ++0x4D00 US_ALU_CONST_R_16 ++0x4D04 US_ALU_CONST_G_16 ++0x4D08 US_ALU_CONST_B_16 ++0x4D0C US_ALU_CONST_A_16 ++0x4D10 US_ALU_CONST_R_17 ++0x4D14 US_ALU_CONST_G_17 ++0x4D18 US_ALU_CONST_B_17 ++0x4D1C US_ALU_CONST_A_17 ++0x4D20 US_ALU_CONST_R_18 ++0x4D24 US_ALU_CONST_G_18 ++0x4D28 US_ALU_CONST_B_18 ++0x4D2C US_ALU_CONST_A_18 ++0x4D30 US_ALU_CONST_R_19 ++0x4D34 US_ALU_CONST_G_19 ++0x4D38 US_ALU_CONST_B_19 ++0x4D3C US_ALU_CONST_A_19 ++0x4D40 US_ALU_CONST_R_20 ++0x4D44 US_ALU_CONST_G_20 ++0x4D48 US_ALU_CONST_B_20 ++0x4D4C US_ALU_CONST_A_20 ++0x4D50 US_ALU_CONST_R_21 ++0x4D54 US_ALU_CONST_G_21 ++0x4D58 US_ALU_CONST_B_21 ++0x4D5C US_ALU_CONST_A_21 ++0x4D60 US_ALU_CONST_R_22 ++0x4D64 US_ALU_CONST_G_22 ++0x4D68 US_ALU_CONST_B_22 ++0x4D6C US_ALU_CONST_A_22 ++0x4D70 US_ALU_CONST_R_23 ++0x4D74 US_ALU_CONST_G_23 ++0x4D78 US_ALU_CONST_B_23 ++0x4D7C US_ALU_CONST_A_23 ++0x4D80 US_ALU_CONST_R_24 ++0x4D84 US_ALU_CONST_G_24 ++0x4D88 US_ALU_CONST_B_24 ++0x4D8C US_ALU_CONST_A_24 ++0x4D90 US_ALU_CONST_R_25 ++0x4D94 US_ALU_CONST_G_25 ++0x4D98 US_ALU_CONST_B_25 ++0x4D9C US_ALU_CONST_A_25 ++0x4DA0 US_ALU_CONST_R_26 ++0x4DA4 US_ALU_CONST_G_26 ++0x4DA8 US_ALU_CONST_B_26 ++0x4DAC US_ALU_CONST_A_26 ++0x4DB0 US_ALU_CONST_R_27 ++0x4DB4 US_ALU_CONST_G_27 ++0x4DB8 US_ALU_CONST_B_27 ++0x4DBC US_ALU_CONST_A_27 ++0x4DC0 US_ALU_CONST_R_28 ++0x4DC4 US_ALU_CONST_G_28 ++0x4DC8 US_ALU_CONST_B_28 ++0x4DCC US_ALU_CONST_A_28 ++0x4DD0 US_ALU_CONST_R_29 ++0x4DD4 US_ALU_CONST_G_29 ++0x4DD8 US_ALU_CONST_B_29 ++0x4DDC US_ALU_CONST_A_29 ++0x4DE0 US_ALU_CONST_R_30 ++0x4DE4 US_ALU_CONST_G_30 ++0x4DE8 US_ALU_CONST_B_30 ++0x4DEC US_ALU_CONST_A_30 ++0x4DF0 US_ALU_CONST_R_31 ++0x4DF4 US_ALU_CONST_G_31 ++0x4DF8 US_ALU_CONST_B_31 ++0x4DFC US_ALU_CONST_A_31 ++0x4E04 RB3D_BLENDCNTL_R3 ++0x4E08 RB3D_ABLENDCNTL_R3 ++0x4E0C RB3D_COLOR_CHANNEL_MASK ++0x4E10 RB3D_CONSTANT_COLOR ++0x4E14 RB3D_COLOR_CLEAR_VALUE ++0x4E18 RB3D_ROPCNTL_R3 ++0x4E1C RB3D_CLRCMP_FLIPE_R3 ++0x4E20 RB3D_CLRCMP_CLR_R3 ++0x4E24 RB3D_CLRCMP_MSK_R3 ++0x4E48 RB3D_DEBUG_CTL ++0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 ++0x4E50 RB3D_DITHER_CTL ++0x4E54 RB3D_CMASK_OFFSET0 ++0x4E58 RB3D_CMASK_OFFSET1 ++0x4E5C RB3D_CMASK_OFFSET2 ++0x4E60 RB3D_CMASK_OFFSET3 ++0x4E64 RB3D_CMASK_PITCH0 ++0x4E68 RB3D_CMASK_PITCH1 ++0x4E6C RB3D_CMASK_PITCH2 ++0x4E70 RB3D_CMASK_PITCH3 ++0x4E74 RB3D_CMASK_WRINDEX ++0x4E78 RB3D_CMASK_DWORD ++0x4E7C RB3D_CMASK_RDINDEX ++0x4E80 RB3D_AARESOLVE_OFFSET ++0x4E84 RB3D_AARESOLVE_PITCH ++0x4E88 RB3D_AARESOLVE_CTL ++0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD ++0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD ++0x4EF8 RB3D_CONSTANT_COLOR_AR ++0x4EFC RB3D_CONSTANT_COLOR_GB ++0x4F04 ZB_ZSTENCILCNTL ++0x4F08 ZB_STENCILREFMASK ++0x4F14 ZB_ZTOP ++0x4F18 ZB_ZCACHE_CTLSTAT ++0x4F1C ZB_BW_CNTL ++0x4F28 ZB_DEPTHCLEARVALUE ++0x4F30 ZB_ZMASK_OFFSET ++0x4F34 ZB_ZMASK_PITCH ++0x4F38 ZB_ZMASK_WRINDEX ++0x4F3C ZB_ZMASK_DWORD ++0x4F40 ZB_ZMASK_RDINDEX ++0x4F44 ZB_HIZ_OFFSET ++0x4F48 ZB_HIZ_WRINDEX ++0x4F4C ZB_HIZ_DWORD ++0x4F50 ZB_HIZ_RDINDEX ++0x4F54 ZB_HIZ_PITCH ++0x4F58 ZB_ZPASS_DATA ++0x4FD4 ZB_STENCILREFMASK_BF +diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c +index b29affd..a3fbdad 100644 +--- a/drivers/gpu/drm/radeon/rs400.c ++++ b/drivers/gpu/drm/radeon/rs400.c +@@ -29,7 +29,6 @@ + #include <drm/drmP.h> + #include "radeon_reg.h" + #include "radeon.h" +-#include "radeon_share.h" + + /* rs400,rs480 depends on : */ + void r100_hdp_reset(struct radeon_device *rdev); +@@ -63,7 +62,7 @@ void rs400_gart_adjust_size(struct radeon_device *rdev) + break; + default: + DRM_ERROR("Unable to use IGP GART size %uM\n", +- rdev->mc.gtt_size >> 20); ++ (unsigned)(rdev->mc.gtt_size >> 20)); + DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); + DRM_ERROR("Forcing to 32M GART size\n"); + rdev->mc.gtt_size = 32 * 1024 * 1024; +@@ -93,20 +92,41 @@ void rs400_gart_tlb_flush(struct radeon_device *rdev) + WREG32_MC(RS480_GART_CACHE_CNTRL, 0); + } + +-int rs400_gart_enable(struct radeon_device *rdev) ++int rs400_gart_init(struct radeon_device *rdev) + { +- uint32_t size_reg; +- uint32_t tmp; + int r; + ++ if (rdev->gart.table.ram.ptr) { ++ WARN(1, "RS400 GART already initialized.\n"); ++ return 0; ++ } ++ /* Check gart size */ ++ switch(rdev->mc.gtt_size / (1024 * 1024)) { ++ case 32: ++ case 64: ++ case 128: ++ case 256: ++ case 512: ++ case 1024: ++ case 2048: ++ break; ++ default: ++ return -EINVAL; ++ } + /* Initialize common gart structure */ + r = radeon_gart_init(rdev); +- if (r) { ++ if (r) + return r; +- } +- if (rs400_debugfs_pcie_gart_info_init(rdev)) { ++ if (rs400_debugfs_pcie_gart_info_init(rdev)) + DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); +- } ++ rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; ++ return radeon_gart_table_ram_alloc(rdev); ++} ++ ++int rs400_gart_enable(struct radeon_device *rdev) ++{ ++ uint32_t size_reg; ++ uint32_t tmp; + + tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); + tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; +@@ -137,13 +157,6 @@ int rs400_gart_enable(struct radeon_device *rdev) + default: + return -EINVAL; + } +- if (rdev->gart.table.ram.ptr == NULL) { +- rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; +- r = radeon_gart_table_ram_alloc(rdev); +- if (r) { +- return r; +- } +- } + /* It should be fine to program it to max value */ + if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { + WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); +@@ -202,6 +215,13 @@ void rs400_gart_disable(struct radeon_device *rdev) + WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); + } + ++void rs400_gart_fini(struct radeon_device *rdev) ++{ ++ rs400_gart_disable(rdev); ++ radeon_gart_table_ram_free(rdev); ++ radeon_gart_fini(rdev); ++} ++ + int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) + { + uint32_t entry; +@@ -256,14 +276,12 @@ int rs400_mc_init(struct radeon_device *rdev) + (void)RREG32(RADEON_HOST_PATH_CNTL); + WREG32(RADEON_HOST_PATH_CNTL, tmp); + (void)RREG32(RADEON_HOST_PATH_CNTL); ++ + return 0; + } + + void rs400_mc_fini(struct radeon_device *rdev) + { +- rs400_gart_disable(rdev); +- radeon_gart_table_ram_free(rdev); +- radeon_gart_fini(rdev); + } + + +diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c +index 02fd11a..4a4fe1c 100644 +--- a/drivers/gpu/drm/radeon/rs600.c ++++ b/drivers/gpu/drm/radeon/rs600.c +@@ -29,6 +29,8 @@ + #include "radeon_reg.h" + #include "radeon.h" + ++#include "rs600_reg_safe.h" ++ + /* rs600 depends on : */ + void r100_hdp_reset(struct radeon_device *rdev); + int r100_gui_wait_for_idle(struct radeon_device *rdev); +@@ -42,7 +44,6 @@ void r420_pipes_init(struct radeon_device *rdev); + */ + void rs600_gpu_init(struct radeon_device *rdev); + int rs600_mc_wait_for_idle(struct radeon_device *rdev); +-void rs600_disable_vga(struct radeon_device *rdev); + + + /* +@@ -66,22 +67,35 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev) + tmp = RREG32_MC(RS600_MC_PT0_CNTL); + } + +-int rs600_gart_enable(struct radeon_device *rdev) ++int rs600_gart_init(struct radeon_device *rdev) + { +- uint32_t tmp; +- int i; + int r; + ++ if (rdev->gart.table.vram.robj) { ++ WARN(1, "RS600 GART already initialized.\n"); ++ return 0; ++ } + /* Initialize common gart structure */ + r = radeon_gart_init(rdev); + if (r) { + return r; + } + rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; +- r = radeon_gart_table_vram_alloc(rdev); +- if (r) { +- return r; ++ return radeon_gart_table_vram_alloc(rdev); ++} ++ ++int rs600_gart_enable(struct radeon_device *rdev) ++{ ++ uint32_t tmp; ++ int r, i; ++ ++ if (rdev->gart.table.vram.robj == NULL) { ++ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); ++ return -EINVAL; + } ++ r = radeon_gart_table_vram_pin(rdev); ++ if (r) ++ return r; + /* FIXME: setup default page */ + WREG32_MC(RS600_MC_PT0_CNTL, + (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | +@@ -136,8 +150,17 @@ void rs600_gart_disable(struct radeon_device *rdev) + tmp = RREG32_MC(RS600_MC_CNTL1); + tmp &= ~RS600_ENABLE_PAGE_TABLES; + WREG32_MC(RS600_MC_CNTL1, tmp); +- radeon_object_kunmap(rdev->gart.table.vram.robj); +- radeon_object_unpin(rdev->gart.table.vram.robj); ++ if (rdev->gart.table.vram.robj) { ++ radeon_object_kunmap(rdev->gart.table.vram.robj); ++ radeon_object_unpin(rdev->gart.table.vram.robj); ++ } ++} ++ ++void rs600_gart_fini(struct radeon_device *rdev) ++{ ++ rs600_gart_disable(rdev); ++ radeon_gart_table_vram_free(rdev); ++ radeon_gart_fini(rdev); + } + + #define R600_PTE_VALID (1 << 0) +@@ -173,6 +196,8 @@ void rs600_mc_disable_clients(struct radeon_device *rdev) + "programming pipes. Bad things might happen.\n"); + } + ++ rv515_vga_render_disable(rdev); ++ + tmp = RREG32(AVIVO_D1VGA_CONTROL); + WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); + tmp = RREG32(AVIVO_D2VGA_CONTROL); +@@ -233,9 +258,6 @@ int rs600_mc_init(struct radeon_device *rdev) + + void rs600_mc_fini(struct radeon_device *rdev) + { +- rs600_gart_disable(rdev); +- radeon_gart_table_vram_free(rdev); +- radeon_gart_fini(rdev); + } + + +@@ -251,11 +273,9 @@ int rs600_irq_set(struct radeon_device *rdev) + tmp |= RADEON_SW_INT_ENABLE; + } + if (rdev->irq.crtc_vblank_int[0]) { +- tmp |= AVIVO_DISPLAY_INT_STATUS; + mode_int |= AVIVO_D1MODE_INT_MASK; + } + if (rdev->irq.crtc_vblank_int[1]) { +- tmp |= AVIVO_DISPLAY_INT_STATUS; + mode_int |= AVIVO_D2MODE_INT_MASK; + } + WREG32(RADEON_GEN_INT_CNTL, tmp); +@@ -324,20 +344,6 @@ u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) + /* + * Global GPU functions + */ +-void rs600_disable_vga(struct radeon_device *rdev) +-{ +- unsigned tmp; +- +- WREG32(0x330, 0); +- WREG32(0x338, 0); +- tmp = RREG32(0x300); +- tmp &= ~(3 << 16); +- WREG32(0x300, tmp); +- WREG32(0x308, (1 << 8)); +- WREG32(0x310, rdev->mc.vram_location); +- WREG32(0x594, 0); +-} +- + int rs600_mc_wait_for_idle(struct radeon_device *rdev) + { + unsigned i; +@@ -363,7 +369,7 @@ void rs600_gpu_init(struct radeon_device *rdev) + { + /* FIXME: HDP same place on rs600 ? */ + r100_hdp_reset(rdev); +- rs600_disable_vga(rdev); ++ rv515_vga_render_disable(rdev); + /* FIXME: is this correct ? */ + r420_pipes_init(rdev); + if (rs600_mc_wait_for_idle(rdev)) { +@@ -410,64 +416,6 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) + WREG32(RS600_MC_DATA, v); + } + +-static const unsigned rs600_reg_safe_bm[219] = { +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, +- 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, +- 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF, +- 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF, +- 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, +- 0x00000000, 0x0000C100, 0x00000000, 0x00000000, +- 0x00000000, 0x00000000, 0x00000000, 0x00000000, +- 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF, +- 0x00000000, 0x00000000, 0x00000000, 0x00000000, +- 0x0003FC01, 0xFFFFFCF8, 0xFF800B19, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +-}; +- + int rs600_init(struct radeon_device *rdev) + { + rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; +diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c +index 8798825..7a0098d 100644 +--- a/drivers/gpu/drm/radeon/rs690.c ++++ b/drivers/gpu/drm/radeon/rs690.c +@@ -40,7 +40,6 @@ void rs400_gart_disable(struct radeon_device *rdev); + int rs400_gart_enable(struct radeon_device *rdev); + void rs400_gart_adjust_size(struct radeon_device *rdev); + void rs600_mc_disable_clients(struct radeon_device *rdev); +-void rs600_disable_vga(struct radeon_device *rdev); + + /* This files gather functions specifics to : + * rs690,rs740 +@@ -94,9 +93,6 @@ int rs690_mc_init(struct radeon_device *rdev) + + void rs690_mc_fini(struct radeon_device *rdev) + { +- rs400_gart_disable(rdev); +- radeon_gart_table_ram_free(rdev); +- radeon_gart_fini(rdev); + } + + +@@ -128,7 +124,7 @@ void rs690_gpu_init(struct radeon_device *rdev) + { + /* FIXME: HDP same place on rs690 ? */ + r100_hdp_reset(rdev); +- rs600_disable_vga(rdev); ++ rv515_vga_render_disable(rdev); + /* FIXME: is this correct ? */ + r420_pipes_init(rdev); + if (rs690_mc_wait_for_idle(rdev)) { +@@ -652,4 +648,3 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) + WREG32(RS690_MC_DATA, v); + WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); + } +- +diff --git a/drivers/gpu/drm/radeon/rs780.c b/drivers/gpu/drm/radeon/rs780.c +deleted file mode 100644 +index 0affcff..0000000 +--- a/drivers/gpu/drm/radeon/rs780.c ++++ /dev/null +@@ -1,102 +0,0 @@ +-/* +- * Copyright 2008 Advanced Micro Devices, Inc. +- * Copyright 2008 Red Hat Inc. +- * Copyright 2009 Jerome Glisse. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Dave Airlie +- * Alex Deucher +- * Jerome Glisse +- */ +-#include "drmP.h" +-#include "radeon_reg.h" +-#include "radeon.h" +- +-/* rs780 depends on : */ +-void rs600_mc_disable_clients(struct radeon_device *rdev); +- +-/* This files gather functions specifics to: +- * rs780 +- * +- * Some of these functions might be used by newer ASICs. +- */ +-int rs780_mc_wait_for_idle(struct radeon_device *rdev); +-void rs780_gpu_init(struct radeon_device *rdev); +- +- +-/* +- * MC +- */ +-int rs780_mc_init(struct radeon_device *rdev) +-{ +- rs780_gpu_init(rdev); +- /* FIXME: implement */ +- +- rs600_mc_disable_clients(rdev); +- if (rs780_mc_wait_for_idle(rdev)) { +- printk(KERN_WARNING "Failed to wait MC idle while " +- "programming pipes. Bad things might happen.\n"); +- } +- return 0; +-} +- +-void rs780_mc_fini(struct radeon_device *rdev) +-{ +- /* FIXME: implement */ +-} +- +- +-/* +- * Global GPU functions +- */ +-void rs780_errata(struct radeon_device *rdev) +-{ +- rdev->pll_errata = 0; +-} +- +-int rs780_mc_wait_for_idle(struct radeon_device *rdev) +-{ +- /* FIXME: implement */ +- return 0; +-} +- +-void rs780_gpu_init(struct radeon_device *rdev) +-{ +- /* FIXME: implement */ +-} +- +- +-/* +- * VRAM info +- */ +-void rs780_vram_get_type(struct radeon_device *rdev) +-{ +- /* FIXME: implement */ +-} +- +-void rs780_vram_info(struct radeon_device *rdev) +-{ +- rs780_vram_get_type(rdev); +- +- /* FIXME: implement */ +- /* Could aper size report 0 ? */ +- rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); +- rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); +-} +diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c +index 0566fb6..e53b5ca 100644 +--- a/drivers/gpu/drm/radeon/rv515.c ++++ b/drivers/gpu/drm/radeon/rv515.c +@@ -27,41 +27,19 @@ + */ + #include <linux/seq_file.h> + #include "drmP.h" +-#include "rv515r.h" ++#include "rv515d.h" + #include "radeon.h" +-#include "radeon_share.h" +- +-/* rv515 depends on : */ +-void r100_hdp_reset(struct radeon_device *rdev); +-int r100_cp_reset(struct radeon_device *rdev); +-int r100_rb2d_reset(struct radeon_device *rdev); +-int r100_gui_wait_for_idle(struct radeon_device *rdev); +-int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); +-int rv370_pcie_gart_enable(struct radeon_device *rdev); +-void rv370_pcie_gart_disable(struct radeon_device *rdev); +-void r420_pipes_init(struct radeon_device *rdev); +-void rs600_mc_disable_clients(struct radeon_device *rdev); +-void rs600_disable_vga(struct radeon_device *rdev); +- +-/* This files gather functions specifics to: +- * rv515 +- * +- * Some of these functions might be used by newer ASICs. +- */ ++#include "atom.h" ++#include "rv515_reg_safe.h" ++ ++/* This files gather functions specifics to: rv515 */ + int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); + int rv515_debugfs_ga_info_init(struct radeon_device *rdev); + void rv515_gpu_init(struct radeon_device *rdev); + int rv515_mc_wait_for_idle(struct radeon_device *rdev); + +- +-/* +- * MC +- */ +-int rv515_mc_init(struct radeon_device *rdev) ++void rv515_debugfs(struct radeon_device *rdev) + { +- uint32_t tmp; +- int r; +- + if (r100_debugfs_rbbm_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for RBBM !\n"); + } +@@ -71,70 +49,8 @@ int rv515_mc_init(struct radeon_device *rdev) + if (rv515_debugfs_ga_info_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for pipes !\n"); + } +- +- rv515_gpu_init(rdev); +- rv370_pcie_gart_disable(rdev); +- +- /* Setup GPU memory space */ +- rdev->mc.vram_location = 0xFFFFFFFFUL; +- rdev->mc.gtt_location = 0xFFFFFFFFUL; +- if (rdev->flags & RADEON_IS_AGP) { +- r = radeon_agp_init(rdev); +- if (r) { +- printk(KERN_WARNING "[drm] Disabling AGP\n"); +- rdev->flags &= ~RADEON_IS_AGP; +- rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; +- } else { +- rdev->mc.gtt_location = rdev->mc.agp_base; +- } +- } +- r = radeon_mc_setup(rdev); +- if (r) { +- return r; +- } +- +- /* Program GPU memory space */ +- rs600_mc_disable_clients(rdev); +- if (rv515_mc_wait_for_idle(rdev)) { +- printk(KERN_WARNING "Failed to wait MC idle while " +- "programming pipes. Bad things might happen.\n"); +- } +- /* Write VRAM size in case we are limiting it */ +- WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); +- tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); +- WREG32(0x134, tmp); +- tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; +- tmp = REG_SET(MC_FB_TOP, tmp >> 16); +- tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); +- WREG32_MC(MC_FB_LOCATION, tmp); +- WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16); +- WREG32(0x310, rdev->mc.vram_location); +- if (rdev->flags & RADEON_IS_AGP) { +- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; +- tmp = REG_SET(MC_AGP_TOP, tmp >> 16); +- tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16); +- WREG32_MC(MC_AGP_LOCATION, tmp); +- WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base); +- WREG32_MC(MC_AGP_BASE_2, 0); +- } else { +- WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF); +- WREG32_MC(MC_AGP_BASE, 0); +- WREG32_MC(MC_AGP_BASE_2, 0); +- } +- return 0; +-} +- +-void rv515_mc_fini(struct radeon_device *rdev) +-{ +- rv370_pcie_gart_disable(rdev); +- radeon_gart_table_vram_free(rdev); +- radeon_gart_fini(rdev); + } + +- +-/* +- * Global GPU functions +- */ + void rv515_ring_start(struct radeon_device *rdev) + { + int r; +@@ -203,11 +119,6 @@ void rv515_ring_start(struct radeon_device *rdev) + radeon_ring_unlock_commit(rdev); + } + +-void rv515_errata(struct radeon_device *rdev) +-{ +- rdev->pll_errata = 0; +-} +- + int rv515_mc_wait_for_idle(struct radeon_device *rdev) + { + unsigned i; +@@ -224,6 +135,12 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev) + return -1; + } + ++void rv515_vga_render_disable(struct radeon_device *rdev) ++{ ++ WREG32(R_000300_VGA_RENDER_CONTROL, ++ RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); ++} ++ + void rv515_gpu_init(struct radeon_device *rdev) + { + unsigned pipe_select_current, gb_pipe_select, tmp; +@@ -236,7 +153,7 @@ void rv515_gpu_init(struct radeon_device *rdev) + "reseting GPU. Bad things might happen.\n"); + } + +- rs600_disable_vga(rdev); ++ rv515_vga_render_disable(rdev); + + r420_pipes_init(rdev); + gb_pipe_select = RREG32(0x402C); +@@ -340,10 +257,6 @@ int rv515_gpu_reset(struct radeon_device *rdev) + return 0; + } + +- +-/* +- * VRAM info +- */ + static void rv515_vram_get_type(struct radeon_device *rdev) + { + uint32_t tmp; +@@ -379,10 +292,6 @@ void rv515_vram_info(struct radeon_device *rdev) + rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); + } + +- +-/* +- * Indirect registers accessor +- */ + uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) + { + uint32_t r; +@@ -400,9 +309,6 @@ void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) + WREG32(MC_IND_INDEX, 0); + } + +-/* +- * Debugfs info +- */ + #if defined(CONFIG_DEBUG_FS) + static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) + { +@@ -464,301 +370,489 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev) + #endif + } + ++void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) ++{ ++ save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); ++ save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); ++ save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); ++ save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); ++ save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); ++ save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); ++ ++ /* Stop all video */ ++ WREG32(R_000330_D1VGA_CONTROL, 0); ++ WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); ++ WREG32(R_000300_VGA_RENDER_CONTROL, 0); ++ WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); ++ WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); ++ WREG32(R_006080_D1CRTC_CONTROL, 0); ++ WREG32(R_006880_D2CRTC_CONTROL, 0); ++ WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); ++ WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); ++} + +-/* +- * Asic initialization +- */ +-static const unsigned r500_reg_safe_bm[219] = { +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, +- 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, +- 0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF, +- 0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF, +- 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, +- 0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF, +- 0x00000000, 0x00000000, 0x00000000, 0x00000000, +- 0x0003FC01, 0x3FFFFCF8, 0xFF800B19, 0xFFDFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +-}; ++void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) ++{ ++ WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); ++ WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); ++ WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); ++ WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); ++ WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); ++ /* Unlock host access */ ++ WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); ++ mdelay(1); ++ /* Restore video state */ ++ WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); ++ WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); ++ WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); ++ WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); ++ WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); ++ WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); ++ WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); ++ WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); ++ WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); ++} + +-int rv515_init(struct radeon_device *rdev) ++void rv515_mc_program(struct radeon_device *rdev) ++{ ++ struct rv515_mc_save save; ++ ++ /* Stops all mc clients */ ++ rv515_mc_stop(rdev, &save); ++ ++ /* Wait for mc idle */ ++ if (rv515_mc_wait_for_idle(rdev)) ++ dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); ++ /* Write VRAM size in case we are limiting it */ ++ WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); ++ /* Program MC, should be a 32bits limited address space */ ++ WREG32_MC(R_000001_MC_FB_LOCATION, ++ S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | ++ S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); ++ WREG32(R_000134_HDP_FB_LOCATION, ++ S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); ++ if (rdev->flags & RADEON_IS_AGP) { ++ WREG32_MC(R_000002_MC_AGP_LOCATION, ++ S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | ++ S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); ++ WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); ++ WREG32_MC(R_000004_MC_AGP_BASE_2, ++ S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); ++ } else { ++ WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); ++ WREG32_MC(R_000003_MC_AGP_BASE, 0); ++ WREG32_MC(R_000004_MC_AGP_BASE_2, 0); ++ } ++ ++ rv515_mc_resume(rdev, &save); ++} ++ ++void rv515_clock_startup(struct radeon_device *rdev) ++{ ++ if (radeon_dynclks != -1 && radeon_dynclks) ++ radeon_atom_set_clock_gating(rdev, 1); ++ /* We need to force on some of the block */ ++ WREG32_PLL(R_00000F_CP_DYN_CNTL, ++ RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); ++ WREG32_PLL(R_000011_E2_DYN_CNTL, ++ RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); ++ WREG32_PLL(R_000013_IDCT_DYN_CNTL, ++ RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); ++} ++ ++static int rv515_startup(struct radeon_device *rdev) ++{ ++ int r; ++ ++ rv515_mc_program(rdev); ++ /* Resume clock */ ++ rv515_clock_startup(rdev); ++ /* Initialize GPU configuration (# pipes, ...) */ ++ rv515_gpu_init(rdev); ++ /* Initialize GART (initialize after TTM so we can allocate ++ * memory through TTM but finalize after TTM) */ ++ if (rdev->flags & RADEON_IS_PCIE) { ++ r = rv370_pcie_gart_enable(rdev); ++ if (r) ++ return r; ++ } ++ /* Enable IRQ */ ++ rdev->irq.sw_int = true; ++ r100_irq_set(rdev); ++ /* 1M ring buffer */ ++ r = r100_cp_init(rdev, 1024 * 1024); ++ if (r) { ++ dev_err(rdev->dev, "failled initializing CP (%d).\n", r); ++ return r; ++ } ++ r = r100_wb_init(rdev); ++ if (r) ++ dev_err(rdev->dev, "failled initializing WB (%d).\n", r); ++ r = r100_ib_init(rdev); ++ if (r) { ++ dev_err(rdev->dev, "failled initializing IB (%d).\n", r); ++ return r; ++ } ++ return 0; ++} ++ ++int rv515_resume(struct radeon_device *rdev) + { +- rdev->config.r300.reg_safe_bm = r500_reg_safe_bm; +- rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm); ++ /* Make sur GART are not working */ ++ if (rdev->flags & RADEON_IS_PCIE) ++ rv370_pcie_gart_disable(rdev); ++ /* Resume clock before doing reset */ ++ rv515_clock_startup(rdev); ++ /* Reset gpu before posting otherwise ATOM will enter infinite loop */ ++ if (radeon_gpu_reset(rdev)) { ++ dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", ++ RREG32(R_000E40_RBBM_STATUS), ++ RREG32(R_0007C0_CP_STAT)); ++ } ++ /* post */ ++ atom_asic_init(rdev->mode_info.atom_context); ++ /* Resume clock after posting */ ++ rv515_clock_startup(rdev); ++ return rv515_startup(rdev); ++} ++ ++int rv515_suspend(struct radeon_device *rdev) ++{ ++ r100_cp_disable(rdev); ++ r100_wb_disable(rdev); ++ r100_irq_disable(rdev); ++ if (rdev->flags & RADEON_IS_PCIE) ++ rv370_pcie_gart_disable(rdev); + return 0; + } + +-void atom_rv515_force_tv_scaler(struct radeon_device *rdev) ++void rv515_set_safe_registers(struct radeon_device *rdev) ++{ ++ rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; ++ rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); ++} ++ ++void rv515_fini(struct radeon_device *rdev) + { ++ rv515_suspend(rdev); ++ r100_cp_fini(rdev); ++ r100_wb_fini(rdev); ++ r100_ib_fini(rdev); ++ radeon_gem_fini(rdev); ++ rv370_pcie_gart_fini(rdev); ++ radeon_agp_fini(rdev); ++ radeon_irq_kms_fini(rdev); ++ radeon_fence_driver_fini(rdev); ++ radeon_object_fini(rdev); ++ radeon_atombios_fini(rdev); ++ kfree(rdev->bios); ++ rdev->bios = NULL; ++} ++ ++int rv515_init(struct radeon_device *rdev) ++{ ++ int r; ++ ++ rdev->new_init_path = true; ++ /* Initialize scratch registers */ ++ radeon_scratch_init(rdev); ++ /* Initialize surface registers */ ++ radeon_surface_init(rdev); ++ /* TODO: disable VGA need to use VGA request */ ++ /* BIOS*/ ++ if (!radeon_get_bios(rdev)) { ++ if (ASIC_IS_AVIVO(rdev)) ++ return -EINVAL; ++ } ++ if (rdev->is_atom_bios) { ++ r = radeon_atombios_init(rdev); ++ if (r) ++ return r; ++ } else { ++ dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); ++ return -EINVAL; ++ } ++ /* Reset gpu before posting otherwise ATOM will enter infinite loop */ ++ if (radeon_gpu_reset(rdev)) { ++ dev_warn(rdev->dev, ++ "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", ++ RREG32(R_000E40_RBBM_STATUS), ++ RREG32(R_0007C0_CP_STAT)); ++ } ++ /* check if cards are posted or not */ ++ if (!radeon_card_posted(rdev) && rdev->bios) { ++ DRM_INFO("GPU not posted. posting now...\n"); ++ atom_asic_init(rdev->mode_info.atom_context); ++ } ++ /* Initialize clocks */ ++ radeon_get_clock_info(rdev->ddev); ++ /* Get vram informations */ ++ rv515_vram_info(rdev); ++ /* Initialize memory controller (also test AGP) */ ++ r = r420_mc_init(rdev); ++ if (r) ++ return r; ++ rv515_debugfs(rdev); ++ /* Fence driver */ ++ r = radeon_fence_driver_init(rdev); ++ if (r) ++ return r; ++ r = radeon_irq_kms_init(rdev); ++ if (r) ++ return r; ++ /* Memory manager */ ++ r = radeon_object_init(rdev); ++ if (r) ++ return r; ++ r = rv370_pcie_gart_init(rdev); ++ if (r) ++ return r; ++ rv515_set_safe_registers(rdev); ++ rdev->accel_working = true; ++ r = rv515_startup(rdev); ++ if (r) { ++ /* Somethings want wront with the accel init stop accel */ ++ dev_err(rdev->dev, "Disabling GPU acceleration\n"); ++ rv515_suspend(rdev); ++ r100_cp_fini(rdev); ++ r100_wb_fini(rdev); ++ r100_ib_fini(rdev); ++ rv370_pcie_gart_fini(rdev); ++ radeon_agp_fini(rdev); ++ radeon_irq_kms_fini(rdev); ++ rdev->accel_working = false; ++ } ++ return 0; ++} + +- WREG32(0x659C, 0x0); +- WREG32(0x6594, 0x705); +- WREG32(0x65A4, 0x10001); +- WREG32(0x65D8, 0x0); +- WREG32(0x65B0, 0x0); +- WREG32(0x65C0, 0x0); +- WREG32(0x65D4, 0x0); +- WREG32(0x6578, 0x0); +- WREG32(0x657C, 0x841880A8); +- WREG32(0x6578, 0x1); +- WREG32(0x657C, 0x84208680); +- WREG32(0x6578, 0x2); +- WREG32(0x657C, 0xBFF880B0); +- WREG32(0x6578, 0x100); +- WREG32(0x657C, 0x83D88088); +- WREG32(0x6578, 0x101); +- WREG32(0x657C, 0x84608680); +- WREG32(0x6578, 0x102); +- WREG32(0x657C, 0xBFF080D0); +- WREG32(0x6578, 0x200); +- WREG32(0x657C, 0x83988068); +- WREG32(0x6578, 0x201); +- WREG32(0x657C, 0x84A08680); +- WREG32(0x6578, 0x202); +- WREG32(0x657C, 0xBFF080F8); +- WREG32(0x6578, 0x300); +- WREG32(0x657C, 0x83588058); +- WREG32(0x6578, 0x301); +- WREG32(0x657C, 0x84E08660); +- WREG32(0x6578, 0x302); +- WREG32(0x657C, 0xBFF88120); +- WREG32(0x6578, 0x400); +- WREG32(0x657C, 0x83188040); +- WREG32(0x6578, 0x401); +- WREG32(0x657C, 0x85008660); +- WREG32(0x6578, 0x402); +- WREG32(0x657C, 0xBFF88150); +- WREG32(0x6578, 0x500); +- WREG32(0x657C, 0x82D88030); +- WREG32(0x6578, 0x501); +- WREG32(0x657C, 0x85408640); +- WREG32(0x6578, 0x502); +- WREG32(0x657C, 0xBFF88180); +- WREG32(0x6578, 0x600); +- WREG32(0x657C, 0x82A08018); +- WREG32(0x6578, 0x601); +- WREG32(0x657C, 0x85808620); +- WREG32(0x6578, 0x602); +- WREG32(0x657C, 0xBFF081B8); +- WREG32(0x6578, 0x700); +- WREG32(0x657C, 0x82608010); +- WREG32(0x6578, 0x701); +- WREG32(0x657C, 0x85A08600); +- WREG32(0x6578, 0x702); +- WREG32(0x657C, 0x800081F0); +- WREG32(0x6578, 0x800); +- WREG32(0x657C, 0x8228BFF8); +- WREG32(0x6578, 0x801); +- WREG32(0x657C, 0x85E085E0); +- WREG32(0x6578, 0x802); +- WREG32(0x657C, 0xBFF88228); +- WREG32(0x6578, 0x10000); +- WREG32(0x657C, 0x82A8BF00); +- WREG32(0x6578, 0x10001); +- WREG32(0x657C, 0x82A08CC0); +- WREG32(0x6578, 0x10002); +- WREG32(0x657C, 0x8008BEF8); +- WREG32(0x6578, 0x10100); +- WREG32(0x657C, 0x81F0BF28); +- WREG32(0x6578, 0x10101); +- WREG32(0x657C, 0x83608CA0); +- WREG32(0x6578, 0x10102); +- WREG32(0x657C, 0x8018BED0); +- WREG32(0x6578, 0x10200); +- WREG32(0x657C, 0x8148BF38); +- WREG32(0x6578, 0x10201); +- WREG32(0x657C, 0x84408C80); +- WREG32(0x6578, 0x10202); +- WREG32(0x657C, 0x8008BEB8); +- WREG32(0x6578, 0x10300); +- WREG32(0x657C, 0x80B0BF78); +- WREG32(0x6578, 0x10301); +- WREG32(0x657C, 0x85008C20); +- WREG32(0x6578, 0x10302); +- WREG32(0x657C, 0x8020BEA0); +- WREG32(0x6578, 0x10400); +- WREG32(0x657C, 0x8028BF90); +- WREG32(0x6578, 0x10401); +- WREG32(0x657C, 0x85E08BC0); +- WREG32(0x6578, 0x10402); +- WREG32(0x657C, 0x8018BE90); +- WREG32(0x6578, 0x10500); +- WREG32(0x657C, 0xBFB8BFB0); +- WREG32(0x6578, 0x10501); +- WREG32(0x657C, 0x86C08B40); +- WREG32(0x6578, 0x10502); +- WREG32(0x657C, 0x8010BE90); +- WREG32(0x6578, 0x10600); +- WREG32(0x657C, 0xBF58BFC8); +- WREG32(0x6578, 0x10601); +- WREG32(0x657C, 0x87A08AA0); +- WREG32(0x6578, 0x10602); +- WREG32(0x657C, 0x8010BE98); +- WREG32(0x6578, 0x10700); +- WREG32(0x657C, 0xBF10BFF0); +- WREG32(0x6578, 0x10701); +- WREG32(0x657C, 0x886089E0); +- WREG32(0x6578, 0x10702); +- WREG32(0x657C, 0x8018BEB0); +- WREG32(0x6578, 0x10800); +- WREG32(0x657C, 0xBED8BFE8); +- WREG32(0x6578, 0x10801); +- WREG32(0x657C, 0x89408940); +- WREG32(0x6578, 0x10802); +- WREG32(0x657C, 0xBFE8BED8); +- WREG32(0x6578, 0x20000); +- WREG32(0x657C, 0x80008000); +- WREG32(0x6578, 0x20001); +- WREG32(0x657C, 0x90008000); +- WREG32(0x6578, 0x20002); +- WREG32(0x657C, 0x80008000); +- WREG32(0x6578, 0x20003); +- WREG32(0x657C, 0x80008000); +- WREG32(0x6578, 0x20100); +- WREG32(0x657C, 0x80108000); +- WREG32(0x6578, 0x20101); +- WREG32(0x657C, 0x8FE0BF70); +- WREG32(0x6578, 0x20102); +- WREG32(0x657C, 0xBFE880C0); +- WREG32(0x6578, 0x20103); +- WREG32(0x657C, 0x80008000); +- WREG32(0x6578, 0x20200); +- WREG32(0x657C, 0x8018BFF8); +- WREG32(0x6578, 0x20201); +- WREG32(0x657C, 0x8F80BF08); +- WREG32(0x6578, 0x20202); +- WREG32(0x657C, 0xBFD081A0); +- WREG32(0x6578, 0x20203); +- WREG32(0x657C, 0xBFF88000); +- WREG32(0x6578, 0x20300); +- WREG32(0x657C, 0x80188000); +- WREG32(0x6578, 0x20301); +- WREG32(0x657C, 0x8EE0BEC0); +- WREG32(0x6578, 0x20302); +- WREG32(0x657C, 0xBFB082A0); +- WREG32(0x6578, 0x20303); +- WREG32(0x657C, 0x80008000); +- WREG32(0x6578, 0x20400); +- WREG32(0x657C, 0x80188000); +- WREG32(0x6578, 0x20401); +- WREG32(0x657C, 0x8E00BEA0); +- WREG32(0x6578, 0x20402); +- WREG32(0x657C, 0xBF8883C0); +- WREG32(0x6578, 0x20403); +- WREG32(0x657C, 0x80008000); +- WREG32(0x6578, 0x20500); +- WREG32(0x657C, 0x80188000); +- WREG32(0x6578, 0x20501); +- WREG32(0x657C, 0x8D00BE90); +- WREG32(0x6578, 0x20502); +- WREG32(0x657C, 0xBF588500); +- WREG32(0x6578, 0x20503); +- WREG32(0x657C, 0x80008008); +- WREG32(0x6578, 0x20600); +- WREG32(0x657C, 0x80188000); +- WREG32(0x6578, 0x20601); +- WREG32(0x657C, 0x8BC0BE98); +- WREG32(0x6578, 0x20602); +- WREG32(0x657C, 0xBF308660); +- WREG32(0x6578, 0x20603); +- WREG32(0x657C, 0x80008008); +- WREG32(0x6578, 0x20700); +- WREG32(0x657C, 0x80108000); +- WREG32(0x6578, 0x20701); +- WREG32(0x657C, 0x8A80BEB0); +- WREG32(0x6578, 0x20702); +- WREG32(0x657C, 0xBF0087C0); +- WREG32(0x6578, 0x20703); +- WREG32(0x657C, 0x80008008); +- WREG32(0x6578, 0x20800); +- WREG32(0x657C, 0x80108000); +- WREG32(0x6578, 0x20801); +- WREG32(0x657C, 0x8920BED0); +- WREG32(0x6578, 0x20802); +- WREG32(0x657C, 0xBED08920); +- WREG32(0x6578, 0x20803); +- WREG32(0x657C, 0x80008010); +- WREG32(0x6578, 0x30000); +- WREG32(0x657C, 0x90008000); +- WREG32(0x6578, 0x30001); +- WREG32(0x657C, 0x80008000); +- WREG32(0x6578, 0x30100); +- WREG32(0x657C, 0x8FE0BF90); +- WREG32(0x6578, 0x30101); +- WREG32(0x657C, 0xBFF880A0); +- WREG32(0x6578, 0x30200); +- WREG32(0x657C, 0x8F60BF40); +- WREG32(0x6578, 0x30201); +- WREG32(0x657C, 0xBFE88180); +- WREG32(0x6578, 0x30300); +- WREG32(0x657C, 0x8EC0BF00); +- WREG32(0x6578, 0x30301); +- WREG32(0x657C, 0xBFC88280); +- WREG32(0x6578, 0x30400); +- WREG32(0x657C, 0x8DE0BEE0); +- WREG32(0x6578, 0x30401); +- WREG32(0x657C, 0xBFA083A0); +- WREG32(0x6578, 0x30500); +- WREG32(0x657C, 0x8CE0BED0); +- WREG32(0x6578, 0x30501); +- WREG32(0x657C, 0xBF7884E0); +- WREG32(0x6578, 0x30600); +- WREG32(0x657C, 0x8BA0BED8); +- WREG32(0x6578, 0x30601); +- WREG32(0x657C, 0xBF508640); +- WREG32(0x6578, 0x30700); +- WREG32(0x657C, 0x8A60BEE8); +- WREG32(0x6578, 0x30701); +- WREG32(0x657C, 0xBF2087A0); +- WREG32(0x6578, 0x30800); +- WREG32(0x657C, 0x8900BF00); +- WREG32(0x6578, 0x30801); +- WREG32(0x657C, 0xBF008900); ++void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) ++{ ++ int index_reg = 0x6578 + crtc->crtc_offset; ++ int data_reg = 0x657c + crtc->crtc_offset; ++ ++ WREG32(0x659C + crtc->crtc_offset, 0x0); ++ WREG32(0x6594 + crtc->crtc_offset, 0x705); ++ WREG32(0x65A4 + crtc->crtc_offset, 0x10001); ++ WREG32(0x65D8 + crtc->crtc_offset, 0x0); ++ WREG32(0x65B0 + crtc->crtc_offset, 0x0); ++ WREG32(0x65C0 + crtc->crtc_offset, 0x0); ++ WREG32(0x65D4 + crtc->crtc_offset, 0x0); ++ WREG32(index_reg, 0x0); ++ WREG32(data_reg, 0x841880A8); ++ WREG32(index_reg, 0x1); ++ WREG32(data_reg, 0x84208680); ++ WREG32(index_reg, 0x2); ++ WREG32(data_reg, 0xBFF880B0); ++ WREG32(index_reg, 0x100); ++ WREG32(data_reg, 0x83D88088); ++ WREG32(index_reg, 0x101); ++ WREG32(data_reg, 0x84608680); ++ WREG32(index_reg, 0x102); ++ WREG32(data_reg, 0xBFF080D0); ++ WREG32(index_reg, 0x200); ++ WREG32(data_reg, 0x83988068); ++ WREG32(index_reg, 0x201); ++ WREG32(data_reg, 0x84A08680); ++ WREG32(index_reg, 0x202); ++ WREG32(data_reg, 0xBFF080F8); ++ WREG32(index_reg, 0x300); ++ WREG32(data_reg, 0x83588058); ++ WREG32(index_reg, 0x301); ++ WREG32(data_reg, 0x84E08660); ++ WREG32(index_reg, 0x302); ++ WREG32(data_reg, 0xBFF88120); ++ WREG32(index_reg, 0x400); ++ WREG32(data_reg, 0x83188040); ++ WREG32(index_reg, 0x401); ++ WREG32(data_reg, 0x85008660); ++ WREG32(index_reg, 0x402); ++ WREG32(data_reg, 0xBFF88150); ++ WREG32(index_reg, 0x500); ++ WREG32(data_reg, 0x82D88030); ++ WREG32(index_reg, 0x501); ++ WREG32(data_reg, 0x85408640); ++ WREG32(index_reg, 0x502); ++ WREG32(data_reg, 0xBFF88180); ++ WREG32(index_reg, 0x600); ++ WREG32(data_reg, 0x82A08018); ++ WREG32(index_reg, 0x601); ++ WREG32(data_reg, 0x85808620); ++ WREG32(index_reg, 0x602); ++ WREG32(data_reg, 0xBFF081B8); ++ WREG32(index_reg, 0x700); ++ WREG32(data_reg, 0x82608010); ++ WREG32(index_reg, 0x701); ++ WREG32(data_reg, 0x85A08600); ++ WREG32(index_reg, 0x702); ++ WREG32(data_reg, 0x800081F0); ++ WREG32(index_reg, 0x800); ++ WREG32(data_reg, 0x8228BFF8); ++ WREG32(index_reg, 0x801); ++ WREG32(data_reg, 0x85E085E0); ++ WREG32(index_reg, 0x802); ++ WREG32(data_reg, 0xBFF88228); ++ WREG32(index_reg, 0x10000); ++ WREG32(data_reg, 0x82A8BF00); ++ WREG32(index_reg, 0x10001); ++ WREG32(data_reg, 0x82A08CC0); ++ WREG32(index_reg, 0x10002); ++ WREG32(data_reg, 0x8008BEF8); ++ WREG32(index_reg, 0x10100); ++ WREG32(data_reg, 0x81F0BF28); ++ WREG32(index_reg, 0x10101); ++ WREG32(data_reg, 0x83608CA0); ++ WREG32(index_reg, 0x10102); ++ WREG32(data_reg, 0x8018BED0); ++ WREG32(index_reg, 0x10200); ++ WREG32(data_reg, 0x8148BF38); ++ WREG32(index_reg, 0x10201); ++ WREG32(data_reg, 0x84408C80); ++ WREG32(index_reg, 0x10202); ++ WREG32(data_reg, 0x8008BEB8); ++ WREG32(index_reg, 0x10300); ++ WREG32(data_reg, 0x80B0BF78); ++ WREG32(index_reg, 0x10301); ++ WREG32(data_reg, 0x85008C20); ++ WREG32(index_reg, 0x10302); ++ WREG32(data_reg, 0x8020BEA0); ++ WREG32(index_reg, 0x10400); ++ WREG32(data_reg, 0x8028BF90); ++ WREG32(index_reg, 0x10401); ++ WREG32(data_reg, 0x85E08BC0); ++ WREG32(index_reg, 0x10402); ++ WREG32(data_reg, 0x8018BE90); ++ WREG32(index_reg, 0x10500); ++ WREG32(data_reg, 0xBFB8BFB0); ++ WREG32(index_reg, 0x10501); ++ WREG32(data_reg, 0x86C08B40); ++ WREG32(index_reg, 0x10502); ++ WREG32(data_reg, 0x8010BE90); ++ WREG32(index_reg, 0x10600); ++ WREG32(data_reg, 0xBF58BFC8); ++ WREG32(index_reg, 0x10601); ++ WREG32(data_reg, 0x87A08AA0); ++ WREG32(index_reg, 0x10602); ++ WREG32(data_reg, 0x8010BE98); ++ WREG32(index_reg, 0x10700); ++ WREG32(data_reg, 0xBF10BFF0); ++ WREG32(index_reg, 0x10701); ++ WREG32(data_reg, 0x886089E0); ++ WREG32(index_reg, 0x10702); ++ WREG32(data_reg, 0x8018BEB0); ++ WREG32(index_reg, 0x10800); ++ WREG32(data_reg, 0xBED8BFE8); ++ WREG32(index_reg, 0x10801); ++ WREG32(data_reg, 0x89408940); ++ WREG32(index_reg, 0x10802); ++ WREG32(data_reg, 0xBFE8BED8); ++ WREG32(index_reg, 0x20000); ++ WREG32(data_reg, 0x80008000); ++ WREG32(index_reg, 0x20001); ++ WREG32(data_reg, 0x90008000); ++ WREG32(index_reg, 0x20002); ++ WREG32(data_reg, 0x80008000); ++ WREG32(index_reg, 0x20003); ++ WREG32(data_reg, 0x80008000); ++ WREG32(index_reg, 0x20100); ++ WREG32(data_reg, 0x80108000); ++ WREG32(index_reg, 0x20101); ++ WREG32(data_reg, 0x8FE0BF70); ++ WREG32(index_reg, 0x20102); ++ WREG32(data_reg, 0xBFE880C0); ++ WREG32(index_reg, 0x20103); ++ WREG32(data_reg, 0x80008000); ++ WREG32(index_reg, 0x20200); ++ WREG32(data_reg, 0x8018BFF8); ++ WREG32(index_reg, 0x20201); ++ WREG32(data_reg, 0x8F80BF08); ++ WREG32(index_reg, 0x20202); ++ WREG32(data_reg, 0xBFD081A0); ++ WREG32(index_reg, 0x20203); ++ WREG32(data_reg, 0xBFF88000); ++ WREG32(index_reg, 0x20300); ++ WREG32(data_reg, 0x80188000); ++ WREG32(index_reg, 0x20301); ++ WREG32(data_reg, 0x8EE0BEC0); ++ WREG32(index_reg, 0x20302); ++ WREG32(data_reg, 0xBFB082A0); ++ WREG32(index_reg, 0x20303); ++ WREG32(data_reg, 0x80008000); ++ WREG32(index_reg, 0x20400); ++ WREG32(data_reg, 0x80188000); ++ WREG32(index_reg, 0x20401); ++ WREG32(data_reg, 0x8E00BEA0); ++ WREG32(index_reg, 0x20402); ++ WREG32(data_reg, 0xBF8883C0); ++ WREG32(index_reg, 0x20403); ++ WREG32(data_reg, 0x80008000); ++ WREG32(index_reg, 0x20500); ++ WREG32(data_reg, 0x80188000); ++ WREG32(index_reg, 0x20501); ++ WREG32(data_reg, 0x8D00BE90); ++ WREG32(index_reg, 0x20502); ++ WREG32(data_reg, 0xBF588500); ++ WREG32(index_reg, 0x20503); ++ WREG32(data_reg, 0x80008008); ++ WREG32(index_reg, 0x20600); ++ WREG32(data_reg, 0x80188000); ++ WREG32(index_reg, 0x20601); ++ WREG32(data_reg, 0x8BC0BE98); ++ WREG32(index_reg, 0x20602); ++ WREG32(data_reg, 0xBF308660); ++ WREG32(index_reg, 0x20603); ++ WREG32(data_reg, 0x80008008); ++ WREG32(index_reg, 0x20700); ++ WREG32(data_reg, 0x80108000); ++ WREG32(index_reg, 0x20701); ++ WREG32(data_reg, 0x8A80BEB0); ++ WREG32(index_reg, 0x20702); ++ WREG32(data_reg, 0xBF0087C0); ++ WREG32(index_reg, 0x20703); ++ WREG32(data_reg, 0x80008008); ++ WREG32(index_reg, 0x20800); ++ WREG32(data_reg, 0x80108000); ++ WREG32(index_reg, 0x20801); ++ WREG32(data_reg, 0x8920BED0); ++ WREG32(index_reg, 0x20802); ++ WREG32(data_reg, 0xBED08920); ++ WREG32(index_reg, 0x20803); ++ WREG32(data_reg, 0x80008010); ++ WREG32(index_reg, 0x30000); ++ WREG32(data_reg, 0x90008000); ++ WREG32(index_reg, 0x30001); ++ WREG32(data_reg, 0x80008000); ++ WREG32(index_reg, 0x30100); ++ WREG32(data_reg, 0x8FE0BF90); ++ WREG32(index_reg, 0x30101); ++ WREG32(data_reg, 0xBFF880A0); ++ WREG32(index_reg, 0x30200); ++ WREG32(data_reg, 0x8F60BF40); ++ WREG32(index_reg, 0x30201); ++ WREG32(data_reg, 0xBFE88180); ++ WREG32(index_reg, 0x30300); ++ WREG32(data_reg, 0x8EC0BF00); ++ WREG32(index_reg, 0x30301); ++ WREG32(data_reg, 0xBFC88280); ++ WREG32(index_reg, 0x30400); ++ WREG32(data_reg, 0x8DE0BEE0); ++ WREG32(index_reg, 0x30401); ++ WREG32(data_reg, 0xBFA083A0); ++ WREG32(index_reg, 0x30500); ++ WREG32(data_reg, 0x8CE0BED0); ++ WREG32(index_reg, 0x30501); ++ WREG32(data_reg, 0xBF7884E0); ++ WREG32(index_reg, 0x30600); ++ WREG32(data_reg, 0x8BA0BED8); ++ WREG32(index_reg, 0x30601); ++ WREG32(data_reg, 0xBF508640); ++ WREG32(index_reg, 0x30700); ++ WREG32(data_reg, 0x8A60BEE8); ++ WREG32(index_reg, 0x30701); ++ WREG32(data_reg, 0xBF2087A0); ++ WREG32(index_reg, 0x30800); ++ WREG32(data_reg, 0x8900BF00); ++ WREG32(index_reg, 0x30801); ++ WREG32(data_reg, 0xBF008900); + } + + struct rv515_watermark { +diff --git a/drivers/gpu/drm/radeon/rv515d.h b/drivers/gpu/drm/radeon/rv515d.h +new file mode 100644 +index 0000000..fc216e4 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/rv515d.h +@@ -0,0 +1,603 @@ ++/* ++ * Copyright 2008 Advanced Micro Devices, Inc. ++ * Copyright 2008 Red Hat Inc. ++ * Copyright 2009 Jerome Glisse. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#ifndef __RV515D_H__ ++#define __RV515D_H__ ++ ++/* ++ * RV515 registers ++ */ ++#define PCIE_INDEX 0x0030 ++#define PCIE_DATA 0x0034 ++#define MC_IND_INDEX 0x0070 ++#define MC_IND_WR_EN (1 << 24) ++#define MC_IND_DATA 0x0074 ++#define RBBM_SOFT_RESET 0x00F0 ++#define CONFIG_MEMSIZE 0x00F8 ++#define HDP_FB_LOCATION 0x0134 ++#define CP_CSQ_CNTL 0x0740 ++#define CP_CSQ_MODE 0x0744 ++#define CP_CSQ_ADDR 0x07F0 ++#define CP_CSQ_DATA 0x07F4 ++#define CP_CSQ_STAT 0x07F8 ++#define CP_CSQ2_STAT 0x07FC ++#define RBBM_STATUS 0x0E40 ++#define DST_PIPE_CONFIG 0x170C ++#define WAIT_UNTIL 0x1720 ++#define WAIT_2D_IDLE (1 << 14) ++#define WAIT_3D_IDLE (1 << 15) ++#define WAIT_2D_IDLECLEAN (1 << 16) ++#define WAIT_3D_IDLECLEAN (1 << 17) ++#define ISYNC_CNTL 0x1724 ++#define ISYNC_ANY2D_IDLE3D (1 << 0) ++#define ISYNC_ANY3D_IDLE2D (1 << 1) ++#define ISYNC_TRIG2D_IDLE3D (1 << 2) ++#define ISYNC_TRIG3D_IDLE2D (1 << 3) ++#define ISYNC_WAIT_IDLEGUI (1 << 4) ++#define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) ++#define VAP_INDEX_OFFSET 0x208C ++#define VAP_PVS_STATE_FLUSH_REG 0x2284 ++#define GB_ENABLE 0x4008 ++#define GB_MSPOS0 0x4010 ++#define MS_X0_SHIFT 0 ++#define MS_Y0_SHIFT 4 ++#define MS_X1_SHIFT 8 ++#define MS_Y1_SHIFT 12 ++#define MS_X2_SHIFT 16 ++#define MS_Y2_SHIFT 20 ++#define MSBD0_Y_SHIFT 24 ++#define MSBD0_X_SHIFT 28 ++#define GB_MSPOS1 0x4014 ++#define MS_X3_SHIFT 0 ++#define MS_Y3_SHIFT 4 ++#define MS_X4_SHIFT 8 ++#define MS_Y4_SHIFT 12 ++#define MS_X5_SHIFT 16 ++#define MS_Y5_SHIFT 20 ++#define MSBD1_SHIFT 24 ++#define GB_TILE_CONFIG 0x4018 ++#define ENABLE_TILING (1 << 0) ++#define PIPE_COUNT_MASK 0x0000000E ++#define PIPE_COUNT_SHIFT 1 ++#define TILE_SIZE_8 (0 << 4) ++#define TILE_SIZE_16 (1 << 4) ++#define TILE_SIZE_32 (2 << 4) ++#define SUBPIXEL_1_12 (0 << 16) ++#define SUBPIXEL_1_16 (1 << 16) ++#define GB_SELECT 0x401C ++#define GB_AA_CONFIG 0x4020 ++#define GB_PIPE_SELECT 0x402C ++#define GA_ENHANCE 0x4274 ++#define GA_DEADLOCK_CNTL (1 << 0) ++#define GA_FASTSYNC_CNTL (1 << 1) ++#define GA_POLY_MODE 0x4288 ++#define FRONT_PTYPE_POINT (0 << 4) ++#define FRONT_PTYPE_LINE (1 << 4) ++#define FRONT_PTYPE_TRIANGE (2 << 4) ++#define BACK_PTYPE_POINT (0 << 7) ++#define BACK_PTYPE_LINE (1 << 7) ++#define BACK_PTYPE_TRIANGE (2 << 7) ++#define GA_ROUND_MODE 0x428C ++#define GEOMETRY_ROUND_TRUNC (0 << 0) ++#define GEOMETRY_ROUND_NEAREST (1 << 0) ++#define COLOR_ROUND_TRUNC (0 << 2) ++#define COLOR_ROUND_NEAREST (1 << 2) ++#define SU_REG_DEST 0x42C8 ++#define RB3D_DSTCACHE_CTLSTAT 0x4E4C ++#define RB3D_DC_FLUSH (2 << 0) ++#define RB3D_DC_FREE (2 << 2) ++#define RB3D_DC_FINISH (1 << 4) ++#define ZB_ZCACHE_CTLSTAT 0x4F18 ++#define ZC_FLUSH (1 << 0) ++#define ZC_FREE (1 << 1) ++#define DC_LB_MEMORY_SPLIT 0x6520 ++#define DC_LB_MEMORY_SPLIT_MASK 0x00000003 ++#define DC_LB_MEMORY_SPLIT_SHIFT 0 ++#define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 ++#define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 ++#define DC_LB_MEMORY_SPLIT_D1_ONLY 2 ++#define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 ++#define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) ++#define DC_LB_DISP1_END_ADR_SHIFT 4 ++#define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 ++#define D1MODE_PRIORITY_A_CNT 0x6548 ++#define MODE_PRIORITY_MARK_MASK 0x00007FFF ++#define MODE_PRIORITY_OFF (1 << 16) ++#define MODE_PRIORITY_ALWAYS_ON (1 << 20) ++#define MODE_PRIORITY_FORCE_MASK (1 << 24) ++#define D1MODE_PRIORITY_B_CNT 0x654C ++#define LB_MAX_REQ_OUTSTANDING 0x6D58 ++#define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F ++#define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 ++#define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 ++#define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 ++#define D2MODE_PRIORITY_A_CNT 0x6D48 ++#define D2MODE_PRIORITY_B_CNT 0x6D4C ++ ++/* ix[MC] registers */ ++#define MC_FB_LOCATION 0x01 ++#define MC_FB_START_MASK 0x0000FFFF ++#define MC_FB_START_SHIFT 0 ++#define MC_FB_TOP_MASK 0xFFFF0000 ++#define MC_FB_TOP_SHIFT 16 ++#define MC_AGP_LOCATION 0x02 ++#define MC_AGP_START_MASK 0x0000FFFF ++#define MC_AGP_START_SHIFT 0 ++#define MC_AGP_TOP_MASK 0xFFFF0000 ++#define MC_AGP_TOP_SHIFT 16 ++#define MC_AGP_BASE 0x03 ++#define MC_AGP_BASE_2 0x04 ++#define MC_CNTL 0x5 ++#define MEM_NUM_CHANNELS_MASK 0x00000003 ++#define MC_STATUS 0x08 ++#define MC_STATUS_IDLE (1 << 4) ++#define MC_MISC_LAT_TIMER 0x09 ++#define MC_CPR_INIT_LAT_MASK 0x0000000F ++#define MC_VF_INIT_LAT_MASK 0x000000F0 ++#define MC_DISP0R_INIT_LAT_MASK 0x00000F00 ++#define MC_DISP0R_INIT_LAT_SHIFT 8 ++#define MC_DISP1R_INIT_LAT_MASK 0x0000F000 ++#define MC_DISP1R_INIT_LAT_SHIFT 12 ++#define MC_FIXED_INIT_LAT_MASK 0x000F0000 ++#define MC_E2R_INIT_LAT_MASK 0x00F00000 ++#define SAME_PAGE_PRIO_MASK 0x0F000000 ++#define MC_GLOBW_INIT_LAT_MASK 0xF0000000 ++ ++ ++/* ++ * PM4 packet ++ */ ++#define CP_PACKET0 0x00000000 ++#define PACKET0_BASE_INDEX_SHIFT 0 ++#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) ++#define PACKET0_COUNT_SHIFT 16 ++#define PACKET0_COUNT_MASK (0x3fff << 16) ++#define CP_PACKET1 0x40000000 ++#define CP_PACKET2 0x80000000 ++#define PACKET2_PAD_SHIFT 0 ++#define PACKET2_PAD_MASK (0x3fffffff << 0) ++#define CP_PACKET3 0xC0000000 ++#define PACKET3_IT_OPCODE_SHIFT 8 ++#define PACKET3_IT_OPCODE_MASK (0xff << 8) ++#define PACKET3_COUNT_SHIFT 16 ++#define PACKET3_COUNT_MASK (0x3fff << 16) ++/* PACKET3 op code */ ++#define PACKET3_NOP 0x10 ++#define PACKET3_3D_DRAW_VBUF 0x28 ++#define PACKET3_3D_DRAW_IMMD 0x29 ++#define PACKET3_3D_DRAW_INDX 0x2A ++#define PACKET3_3D_LOAD_VBPNTR 0x2F ++#define PACKET3_INDX_BUFFER 0x33 ++#define PACKET3_3D_DRAW_VBUF_2 0x34 ++#define PACKET3_3D_DRAW_IMMD_2 0x35 ++#define PACKET3_3D_DRAW_INDX_2 0x36 ++#define PACKET3_BITBLT_MULTI 0x9B ++ ++#define PACKET0(reg, n) (CP_PACKET0 | \ ++ REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ ++ REG_SET(PACKET0_COUNT, (n))) ++#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) ++#define PACKET3(op, n) (CP_PACKET3 | \ ++ REG_SET(PACKET3_IT_OPCODE, (op)) | \ ++ REG_SET(PACKET3_COUNT, (n))) ++ ++#define PACKET_TYPE0 0 ++#define PACKET_TYPE1 1 ++#define PACKET_TYPE2 2 ++#define PACKET_TYPE3 3 ++ ++#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) ++#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) ++#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) ++#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) ++#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) ++ ++/* Registers */ ++#define R_0000F8_CONFIG_MEMSIZE 0x0000F8 ++#define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_0000F8_CONFIG_MEMSIZE 0x00000000 ++#define R_000134_HDP_FB_LOCATION 0x000134 ++#define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) ++#define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) ++#define C_000134_HDP_FB_START 0xFFFF0000 ++#define R_000300_VGA_RENDER_CONTROL 0x000300 ++#define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0) ++#define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F) ++#define C_000300_VGA_BLINK_RATE 0xFFFFFFE0 ++#define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5) ++#define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3) ++#define C_000300_VGA_BLINK_MODE 0xFFFFFF9F ++#define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7) ++#define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1) ++#define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F ++#define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8) ++#define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1) ++#define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF ++#define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16) ++#define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3) ++#define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF ++#define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24) ++#define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1) ++#define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF ++#define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25) ++#define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1) ++#define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF ++#define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310 ++#define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000 ++#define R_000328_VGA_HDP_CONTROL 0x000328 ++#define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0) ++#define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1) ++#define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE ++#define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8) ++#define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1) ++#define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF ++#define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16) ++#define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1) ++#define C_000328_VGA_SOFT_RESET 0xFFFEFFFF ++#define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24) ++#define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1) ++#define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF ++#define R_000330_D1VGA_CONTROL 0x000330 ++#define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) ++#define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) ++#define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE ++#define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) ++#define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) ++#define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF ++#define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) ++#define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) ++#define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF ++#define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) ++#define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) ++#define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF ++#define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) ++#define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) ++#define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF ++#define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24) ++#define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3) ++#define C_000330_D1VGA_ROTATE 0xFCFFFFFF ++#define R_000338_D2VGA_CONTROL 0x000338 ++#define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) ++#define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) ++#define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE ++#define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) ++#define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) ++#define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF ++#define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) ++#define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) ++#define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF ++#define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) ++#define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) ++#define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF ++#define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) ++#define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) ++#define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF ++#define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24) ++#define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3) ++#define C_000338_D2VGA_ROTATE 0xFCFFFFFF ++#define R_0007C0_CP_STAT 0x0007C0 ++#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) ++#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) ++#define C_0007C0_MRU_BUSY 0xFFFFFFFE ++#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) ++#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) ++#define C_0007C0_MWU_BUSY 0xFFFFFFFD ++#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) ++#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) ++#define C_0007C0_RSIU_BUSY 0xFFFFFFFB ++#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) ++#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) ++#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 ++#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) ++#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) ++#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF ++#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) ++#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) ++#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF ++#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) ++#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) ++#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF ++#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) ++#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) ++#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF ++#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) ++#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) ++#define C_0007C0_CSI_BUSY 0xFFFFDFFF ++#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) ++#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) ++#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF ++#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) ++#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) ++#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF ++#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) ++#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) ++#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF ++#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) ++#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) ++#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF ++#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) ++#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) ++#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF ++#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) ++#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) ++#define C_0007C0_CP_BUSY 0x7FFFFFFF ++#define R_000E40_RBBM_STATUS 0x000E40 ++#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) ++#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) ++#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 ++#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) ++#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) ++#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF ++#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) ++#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) ++#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF ++#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) ++#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) ++#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF ++#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) ++#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) ++#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF ++#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) ++#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) ++#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF ++#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) ++#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) ++#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF ++#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) ++#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) ++#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF ++#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) ++#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) ++#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF ++#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) ++#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) ++#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF ++#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) ++#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) ++#define C_000E40_E2_BUSY 0xFFFDFFFF ++#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) ++#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) ++#define C_000E40_RB2D_BUSY 0xFFFBFFFF ++#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) ++#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) ++#define C_000E40_RB3D_BUSY 0xFFF7FFFF ++#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) ++#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) ++#define C_000E40_VAP_BUSY 0xFFEFFFFF ++#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) ++#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) ++#define C_000E40_RE_BUSY 0xFFDFFFFF ++#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) ++#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) ++#define C_000E40_TAM_BUSY 0xFFBFFFFF ++#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) ++#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) ++#define C_000E40_TDM_BUSY 0xFF7FFFFF ++#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) ++#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) ++#define C_000E40_PB_BUSY 0xFEFFFFFF ++#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) ++#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) ++#define C_000E40_TIM_BUSY 0xFDFFFFFF ++#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) ++#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) ++#define C_000E40_GA_BUSY 0xFBFFFFFF ++#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) ++#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) ++#define C_000E40_CBA2D_BUSY 0xF7FFFFFF ++#define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) ++#define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) ++#define C_000E40_RBBM_HIBUSY 0xEFFFFFFF ++#define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) ++#define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) ++#define C_000E40_SKID_CFBUSY 0xDFFFFFFF ++#define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) ++#define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) ++#define C_000E40_VAP_VF_BUSY 0xBFFFFFFF ++#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) ++#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) ++#define C_000E40_GUI_ACTIVE 0x7FFFFFFF ++#define R_006080_D1CRTC_CONTROL 0x006080 ++#define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0) ++#define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) ++#define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE ++#define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) ++#define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) ++#define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF ++#define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) ++#define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) ++#define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF ++#define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) ++#define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) ++#define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF ++#define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) ++#define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) ++#define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF ++#define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8 ++#define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) ++#define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) ++#define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE ++#define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110 ++#define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 ++#define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118 ++#define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 ++#define R_006880_D2CRTC_CONTROL 0x006880 ++#define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0) ++#define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) ++#define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE ++#define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) ++#define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) ++#define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF ++#define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) ++#define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) ++#define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF ++#define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) ++#define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) ++#define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF ++#define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) ++#define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) ++#define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF ++#define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8 ++#define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) ++#define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) ++#define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE ++#define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910 ++#define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 ++#define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918 ++#define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 ++ ++ ++#define R_000001_MC_FB_LOCATION 0x000001 ++#define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0) ++#define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF) ++#define C_000001_MC_FB_START 0xFFFF0000 ++#define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) ++#define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) ++#define C_000001_MC_FB_TOP 0x0000FFFF ++#define R_000002_MC_AGP_LOCATION 0x000002 ++#define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0) ++#define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) ++#define C_000002_MC_AGP_START 0xFFFF0000 ++#define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) ++#define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) ++#define C_000002_MC_AGP_TOP 0x0000FFFF ++#define R_000003_MC_AGP_BASE 0x000003 ++#define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) ++#define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) ++#define C_000003_AGP_BASE_ADDR 0x00000000 ++#define R_000004_MC_AGP_BASE_2 0x000004 ++#define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) ++#define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) ++#define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0 ++ ++ ++#define R_00000F_CP_DYN_CNTL 0x00000F ++#define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0) ++#define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1) ++#define C_00000F_CP_FORCEON 0xFFFFFFFE ++#define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) ++#define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) ++#define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD ++#define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2) ++#define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1) ++#define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB ++#define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3) ++#define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) ++#define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7 ++#define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) ++#define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) ++#define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F ++#define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) ++#define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) ++#define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF ++#define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) ++#define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) ++#define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF ++#define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) ++#define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) ++#define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF ++#define S_00000F_SPARE(x) (((x) & 0x3) << 22) ++#define G_00000F_SPARE(x) (((x) >> 22) & 0x3) ++#define C_00000F_SPARE 0xFF3FFFFF ++#define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) ++#define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) ++#define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF ++#define R_000011_E2_DYN_CNTL 0x000011 ++#define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0) ++#define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1) ++#define C_000011_E2_FORCEON 0xFFFFFFFE ++#define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) ++#define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) ++#define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD ++#define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2) ++#define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1) ++#define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB ++#define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3) ++#define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) ++#define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7 ++#define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) ++#define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) ++#define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F ++#define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) ++#define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) ++#define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF ++#define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) ++#define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) ++#define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF ++#define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) ++#define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) ++#define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF ++#define S_000011_SPARE(x) (((x) & 0x3) << 22) ++#define G_000011_SPARE(x) (((x) >> 22) & 0x3) ++#define C_000011_SPARE 0xFF3FFFFF ++#define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) ++#define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) ++#define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF ++#define R_000013_IDCT_DYN_CNTL 0x000013 ++#define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0) ++#define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1) ++#define C_000013_IDCT_FORCEON 0xFFFFFFFE ++#define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) ++#define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) ++#define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD ++#define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2) ++#define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1) ++#define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB ++#define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3) ++#define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) ++#define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7 ++#define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) ++#define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) ++#define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F ++#define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) ++#define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) ++#define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF ++#define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) ++#define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) ++#define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF ++#define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) ++#define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) ++#define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF ++#define S_000013_SPARE(x) (((x) & 0x3) << 22) ++#define G_000013_SPARE(x) (((x) >> 22) & 0x3) ++#define C_000013_SPARE 0xFF3FFFFF ++#define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) ++#define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) ++#define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/rv515r.h b/drivers/gpu/drm/radeon/rv515r.h +deleted file mode 100644 +index f3cf840..0000000 +--- a/drivers/gpu/drm/radeon/rv515r.h ++++ /dev/null +@@ -1,170 +0,0 @@ +-/* +- * Copyright 2008 Advanced Micro Devices, Inc. +- * Copyright 2008 Red Hat Inc. +- * Copyright 2009 Jerome Glisse. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Dave Airlie +- * Alex Deucher +- * Jerome Glisse +- */ +-#ifndef RV515R_H +-#define RV515R_H +- +-/* RV515 registers */ +-#define PCIE_INDEX 0x0030 +-#define PCIE_DATA 0x0034 +-#define MC_IND_INDEX 0x0070 +-#define MC_IND_WR_EN (1 << 24) +-#define MC_IND_DATA 0x0074 +-#define RBBM_SOFT_RESET 0x00F0 +-#define CONFIG_MEMSIZE 0x00F8 +-#define HDP_FB_LOCATION 0x0134 +-#define CP_CSQ_CNTL 0x0740 +-#define CP_CSQ_MODE 0x0744 +-#define CP_CSQ_ADDR 0x07F0 +-#define CP_CSQ_DATA 0x07F4 +-#define CP_CSQ_STAT 0x07F8 +-#define CP_CSQ2_STAT 0x07FC +-#define RBBM_STATUS 0x0E40 +-#define DST_PIPE_CONFIG 0x170C +-#define WAIT_UNTIL 0x1720 +-#define WAIT_2D_IDLE (1 << 14) +-#define WAIT_3D_IDLE (1 << 15) +-#define WAIT_2D_IDLECLEAN (1 << 16) +-#define WAIT_3D_IDLECLEAN (1 << 17) +-#define ISYNC_CNTL 0x1724 +-#define ISYNC_ANY2D_IDLE3D (1 << 0) +-#define ISYNC_ANY3D_IDLE2D (1 << 1) +-#define ISYNC_TRIG2D_IDLE3D (1 << 2) +-#define ISYNC_TRIG3D_IDLE2D (1 << 3) +-#define ISYNC_WAIT_IDLEGUI (1 << 4) +-#define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) +-#define VAP_INDEX_OFFSET 0x208C +-#define VAP_PVS_STATE_FLUSH_REG 0x2284 +-#define GB_ENABLE 0x4008 +-#define GB_MSPOS0 0x4010 +-#define MS_X0_SHIFT 0 +-#define MS_Y0_SHIFT 4 +-#define MS_X1_SHIFT 8 +-#define MS_Y1_SHIFT 12 +-#define MS_X2_SHIFT 16 +-#define MS_Y2_SHIFT 20 +-#define MSBD0_Y_SHIFT 24 +-#define MSBD0_X_SHIFT 28 +-#define GB_MSPOS1 0x4014 +-#define MS_X3_SHIFT 0 +-#define MS_Y3_SHIFT 4 +-#define MS_X4_SHIFT 8 +-#define MS_Y4_SHIFT 12 +-#define MS_X5_SHIFT 16 +-#define MS_Y5_SHIFT 20 +-#define MSBD1_SHIFT 24 +-#define GB_TILE_CONFIG 0x4018 +-#define ENABLE_TILING (1 << 0) +-#define PIPE_COUNT_MASK 0x0000000E +-#define PIPE_COUNT_SHIFT 1 +-#define TILE_SIZE_8 (0 << 4) +-#define TILE_SIZE_16 (1 << 4) +-#define TILE_SIZE_32 (2 << 4) +-#define SUBPIXEL_1_12 (0 << 16) +-#define SUBPIXEL_1_16 (1 << 16) +-#define GB_SELECT 0x401C +-#define GB_AA_CONFIG 0x4020 +-#define GB_PIPE_SELECT 0x402C +-#define GA_ENHANCE 0x4274 +-#define GA_DEADLOCK_CNTL (1 << 0) +-#define GA_FASTSYNC_CNTL (1 << 1) +-#define GA_POLY_MODE 0x4288 +-#define FRONT_PTYPE_POINT (0 << 4) +-#define FRONT_PTYPE_LINE (1 << 4) +-#define FRONT_PTYPE_TRIANGE (2 << 4) +-#define BACK_PTYPE_POINT (0 << 7) +-#define BACK_PTYPE_LINE (1 << 7) +-#define BACK_PTYPE_TRIANGE (2 << 7) +-#define GA_ROUND_MODE 0x428C +-#define GEOMETRY_ROUND_TRUNC (0 << 0) +-#define GEOMETRY_ROUND_NEAREST (1 << 0) +-#define COLOR_ROUND_TRUNC (0 << 2) +-#define COLOR_ROUND_NEAREST (1 << 2) +-#define SU_REG_DEST 0x42C8 +-#define RB3D_DSTCACHE_CTLSTAT 0x4E4C +-#define RB3D_DC_FLUSH (2 << 0) +-#define RB3D_DC_FREE (2 << 2) +-#define RB3D_DC_FINISH (1 << 4) +-#define ZB_ZCACHE_CTLSTAT 0x4F18 +-#define ZC_FLUSH (1 << 0) +-#define ZC_FREE (1 << 1) +-#define DC_LB_MEMORY_SPLIT 0x6520 +-#define DC_LB_MEMORY_SPLIT_MASK 0x00000003 +-#define DC_LB_MEMORY_SPLIT_SHIFT 0 +-#define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 +-#define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 +-#define DC_LB_MEMORY_SPLIT_D1_ONLY 2 +-#define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 +-#define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) +-#define DC_LB_DISP1_END_ADR_SHIFT 4 +-#define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 +-#define D1MODE_PRIORITY_A_CNT 0x6548 +-#define MODE_PRIORITY_MARK_MASK 0x00007FFF +-#define MODE_PRIORITY_OFF (1 << 16) +-#define MODE_PRIORITY_ALWAYS_ON (1 << 20) +-#define MODE_PRIORITY_FORCE_MASK (1 << 24) +-#define D1MODE_PRIORITY_B_CNT 0x654C +-#define LB_MAX_REQ_OUTSTANDING 0x6D58 +-#define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F +-#define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 +-#define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 +-#define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 +-#define D2MODE_PRIORITY_A_CNT 0x6D48 +-#define D2MODE_PRIORITY_B_CNT 0x6D4C +- +-/* ix[MC] registers */ +-#define MC_FB_LOCATION 0x01 +-#define MC_FB_START_MASK 0x0000FFFF +-#define MC_FB_START_SHIFT 0 +-#define MC_FB_TOP_MASK 0xFFFF0000 +-#define MC_FB_TOP_SHIFT 16 +-#define MC_AGP_LOCATION 0x02 +-#define MC_AGP_START_MASK 0x0000FFFF +-#define MC_AGP_START_SHIFT 0 +-#define MC_AGP_TOP_MASK 0xFFFF0000 +-#define MC_AGP_TOP_SHIFT 16 +-#define MC_AGP_BASE 0x03 +-#define MC_AGP_BASE_2 0x04 +-#define MC_CNTL 0x5 +-#define MEM_NUM_CHANNELS_MASK 0x00000003 +-#define MC_STATUS 0x08 +-#define MC_STATUS_IDLE (1 << 4) +-#define MC_MISC_LAT_TIMER 0x09 +-#define MC_CPR_INIT_LAT_MASK 0x0000000F +-#define MC_VF_INIT_LAT_MASK 0x000000F0 +-#define MC_DISP0R_INIT_LAT_MASK 0x00000F00 +-#define MC_DISP0R_INIT_LAT_SHIFT 8 +-#define MC_DISP1R_INIT_LAT_MASK 0x0000F000 +-#define MC_DISP1R_INIT_LAT_SHIFT 12 +-#define MC_FIXED_INIT_LAT_MASK 0x000F0000 +-#define MC_E2R_INIT_LAT_MASK 0x00F00000 +-#define SAME_PAGE_PRIO_MASK 0x0F000000 +-#define MC_GLOBW_INIT_LAT_MASK 0xF0000000 +- +- +-#endif +- +diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c +index 21d8ffd..e0b97d1 100644 +--- a/drivers/gpu/drm/radeon/rv770.c ++++ b/drivers/gpu/drm/radeon/rv770.c +@@ -25,100 +25,1045 @@ + * Alex Deucher + * Jerome Glisse + */ ++#include <linux/firmware.h> ++#include <linux/platform_device.h> + #include "drmP.h" +-#include "radeon_reg.h" + #include "radeon.h" ++#include "radeon_drm.h" ++#include "rv770d.h" ++#include "atom.h" ++#include "avivod.h" + +-/* rv770,rv730,rv710 depends on : */ +-void rs600_mc_disable_clients(struct radeon_device *rdev); ++#define R700_PFP_UCODE_SIZE 848 ++#define R700_PM4_UCODE_SIZE 1360 + +-/* This files gather functions specifics to: +- * rv770,rv730,rv710 +- * +- * Some of these functions might be used by newer ASICs. +- */ +-int rv770_mc_wait_for_idle(struct radeon_device *rdev); +-void rv770_gpu_init(struct radeon_device *rdev); ++static void rv770_gpu_init(struct radeon_device *rdev); ++void rv770_fini(struct radeon_device *rdev); + + + /* +- * MC ++ * GART + */ +-int rv770_mc_init(struct radeon_device *rdev) ++int rv770_pcie_gart_enable(struct radeon_device *rdev) + { +- uint32_t tmp; ++ u32 tmp; ++ int r, i; + +- rv770_gpu_init(rdev); ++ if (rdev->gart.table.vram.robj == NULL) { ++ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); ++ return -EINVAL; ++ } ++ r = radeon_gart_table_vram_pin(rdev); ++ if (r) ++ return r; ++ /* Setup L2 cache */ ++ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | ++ ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | ++ EFFECTIVE_L2_QUEUE_SIZE(7)); ++ WREG32(VM_L2_CNTL2, 0); ++ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); ++ /* Setup TLB control */ ++ tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | ++ SYSTEM_ACCESS_MODE_NOT_IN_SYS | ++ SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | ++ EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); ++ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); ++ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | ++ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); ++ WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, ++ (u32)(rdev->dummy_page.addr >> 12)); ++ for (i = 1; i < 7; i++) ++ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); + +- /* setup the gart before changing location so we can ask to +- * discard unmapped mc request +- */ +- /* FIXME: disable out of gart access */ +- tmp = rdev->mc.gtt_location / 4096; +- tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp); +- WREG32(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); +- tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; +- tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp); +- WREG32(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); +- +- rs600_mc_disable_clients(rdev); +- if (rv770_mc_wait_for_idle(rdev)) { +- printk(KERN_WARNING "Failed to wait MC idle while " +- "programming pipes. Bad things might happen.\n"); +- } +- +- tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; +- tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24); +- tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24); +- WREG32(R700_MC_VM_FB_LOCATION, tmp); +- tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; +- tmp = REG_SET(R700_MC_AGP_TOP, tmp >> 22); +- WREG32(R700_MC_VM_AGP_TOP, tmp); +- tmp = REG_SET(R700_MC_AGP_BOT, rdev->mc.gtt_location >> 22); +- WREG32(R700_MC_VM_AGP_BOT, tmp); ++ r600_pcie_gart_tlb_flush(rdev); ++ rdev->gart.ready = true; + return 0; + } + +-void rv770_mc_fini(struct radeon_device *rdev) ++void rv770_pcie_gart_disable(struct radeon_device *rdev) + { +- /* FIXME: implement */ ++ u32 tmp; ++ int i; ++ ++ /* Disable all tables */ ++ for (i = 0; i < 7; i++) ++ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); ++ ++ /* Setup L2 cache */ ++ WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | ++ EFFECTIVE_L2_QUEUE_SIZE(7)); ++ WREG32(VM_L2_CNTL2, 0); ++ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); ++ /* Setup TLB control */ ++ tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); ++ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); ++ if (rdev->gart.table.vram.robj) { ++ radeon_object_kunmap(rdev->gart.table.vram.robj); ++ radeon_object_unpin(rdev->gart.table.vram.robj); ++ } ++} ++ ++void rv770_pcie_gart_fini(struct radeon_device *rdev) ++{ ++ rv770_pcie_gart_disable(rdev); ++ radeon_gart_table_vram_free(rdev); ++ radeon_gart_fini(rdev); + } + + + /* +- * Global GPU functions ++ * MC + */ +-void rv770_errata(struct radeon_device *rdev) ++static void rv770_mc_resume(struct radeon_device *rdev) + { +- rdev->pll_errata = 0; ++ u32 d1vga_control, d2vga_control; ++ u32 vga_render_control, vga_hdp_control; ++ u32 d1crtc_control, d2crtc_control; ++ u32 new_d1grph_primary, new_d1grph_secondary; ++ u32 new_d2grph_primary, new_d2grph_secondary; ++ u64 old_vram_start; ++ u32 tmp; ++ int i, j; ++ ++ /* Initialize HDP */ ++ for (i = 0, j = 0; i < 32; i++, j += 0x18) { ++ WREG32((0x2c14 + j), 0x00000000); ++ WREG32((0x2c18 + j), 0x00000000); ++ WREG32((0x2c1c + j), 0x00000000); ++ WREG32((0x2c20 + j), 0x00000000); ++ WREG32((0x2c24 + j), 0x00000000); ++ } ++ WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); ++ ++ d1vga_control = RREG32(D1VGA_CONTROL); ++ d2vga_control = RREG32(D2VGA_CONTROL); ++ vga_render_control = RREG32(VGA_RENDER_CONTROL); ++ vga_hdp_control = RREG32(VGA_HDP_CONTROL); ++ d1crtc_control = RREG32(D1CRTC_CONTROL); ++ d2crtc_control = RREG32(D2CRTC_CONTROL); ++ old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; ++ new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS); ++ new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS); ++ new_d1grph_primary += rdev->mc.vram_start - old_vram_start; ++ new_d1grph_secondary += rdev->mc.vram_start - old_vram_start; ++ new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS); ++ new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS); ++ new_d2grph_primary += rdev->mc.vram_start - old_vram_start; ++ new_d2grph_secondary += rdev->mc.vram_start - old_vram_start; ++ ++ /* Stop all video */ ++ WREG32(D1VGA_CONTROL, 0); ++ WREG32(D2VGA_CONTROL, 0); ++ WREG32(VGA_RENDER_CONTROL, 0); ++ WREG32(D1CRTC_UPDATE_LOCK, 1); ++ WREG32(D2CRTC_UPDATE_LOCK, 1); ++ WREG32(D1CRTC_CONTROL, 0); ++ WREG32(D2CRTC_CONTROL, 0); ++ WREG32(D1CRTC_UPDATE_LOCK, 0); ++ WREG32(D2CRTC_UPDATE_LOCK, 0); ++ ++ mdelay(1); ++ if (r600_mc_wait_for_idle(rdev)) { ++ printk(KERN_WARNING "[drm] MC not idle !\n"); ++ } ++ ++ /* Lockout access through VGA aperture*/ ++ WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); ++ ++ /* Update configuration */ ++ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); ++ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12); ++ WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); ++ tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16; ++ tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); ++ WREG32(MC_VM_FB_LOCATION, tmp); ++ WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); ++ WREG32(HDP_NONSURFACE_INFO, (2 << 7)); ++ WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); ++ if (rdev->flags & RADEON_IS_AGP) { ++ WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16); ++ WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); ++ WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); ++ } else { ++ WREG32(MC_VM_AGP_BASE, 0); ++ WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); ++ WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); ++ } ++ WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary); ++ WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary); ++ WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary); ++ WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary); ++ WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); ++ ++ /* Unlock host access */ ++ WREG32(VGA_HDP_CONTROL, vga_hdp_control); ++ ++ mdelay(1); ++ if (r600_mc_wait_for_idle(rdev)) { ++ printk(KERN_WARNING "[drm] MC not idle !\n"); ++ } ++ ++ /* Restore video state */ ++ WREG32(D1CRTC_UPDATE_LOCK, 1); ++ WREG32(D2CRTC_UPDATE_LOCK, 1); ++ WREG32(D1CRTC_CONTROL, d1crtc_control); ++ WREG32(D2CRTC_CONTROL, d2crtc_control); ++ WREG32(D1CRTC_UPDATE_LOCK, 0); ++ WREG32(D2CRTC_UPDATE_LOCK, 0); ++ WREG32(D1VGA_CONTROL, d1vga_control); ++ WREG32(D2VGA_CONTROL, d2vga_control); ++ WREG32(VGA_RENDER_CONTROL, vga_render_control); ++ ++ /* we need to own VRAM, so turn off the VGA renderer here ++ * to stop it overwriting our objects */ ++ rv515_vga_render_disable(rdev); + } + +-int rv770_mc_wait_for_idle(struct radeon_device *rdev) ++ ++/* ++ * CP. ++ */ ++void r700_cp_stop(struct radeon_device *rdev) + { +- /* FIXME: implement */ +- return 0; ++ WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); + } + +-void rv770_gpu_init(struct radeon_device *rdev) ++ ++static int rv770_cp_load_microcode(struct radeon_device *rdev) + { +- /* FIXME: implement */ ++ const __be32 *fw_data; ++ int i; ++ ++ if (!rdev->me_fw || !rdev->pfp_fw) ++ return -EINVAL; ++ ++ r700_cp_stop(rdev); ++ WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); ++ ++ /* Reset cp */ ++ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); ++ RREG32(GRBM_SOFT_RESET); ++ mdelay(15); ++ WREG32(GRBM_SOFT_RESET, 0); ++ ++ fw_data = (const __be32 *)rdev->pfp_fw->data; ++ WREG32(CP_PFP_UCODE_ADDR, 0); ++ for (i = 0; i < R700_PFP_UCODE_SIZE; i++) ++ WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); ++ WREG32(CP_PFP_UCODE_ADDR, 0); ++ ++ fw_data = (const __be32 *)rdev->me_fw->data; ++ WREG32(CP_ME_RAM_WADDR, 0); ++ for (i = 0; i < R700_PM4_UCODE_SIZE; i++) ++ WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); ++ ++ WREG32(CP_PFP_UCODE_ADDR, 0); ++ WREG32(CP_ME_RAM_WADDR, 0); ++ WREG32(CP_ME_RAM_RADDR, 0); ++ return 0; + } + + + /* +- * VRAM info ++ * Core functions + */ +-void rv770_vram_get_type(struct radeon_device *rdev) ++static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, ++ u32 num_backends, ++ u32 backend_disable_mask) + { +- /* FIXME: implement */ ++ u32 backend_map = 0; ++ u32 enabled_backends_mask; ++ u32 enabled_backends_count; ++ u32 cur_pipe; ++ u32 swizzle_pipe[R7XX_MAX_PIPES]; ++ u32 cur_backend; ++ u32 i; ++ ++ if (num_tile_pipes > R7XX_MAX_PIPES) ++ num_tile_pipes = R7XX_MAX_PIPES; ++ if (num_tile_pipes < 1) ++ num_tile_pipes = 1; ++ if (num_backends > R7XX_MAX_BACKENDS) ++ num_backends = R7XX_MAX_BACKENDS; ++ if (num_backends < 1) ++ num_backends = 1; ++ ++ enabled_backends_mask = 0; ++ enabled_backends_count = 0; ++ for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { ++ if (((backend_disable_mask >> i) & 1) == 0) { ++ enabled_backends_mask |= (1 << i); ++ ++enabled_backends_count; ++ } ++ if (enabled_backends_count == num_backends) ++ break; ++ } ++ ++ if (enabled_backends_count == 0) { ++ enabled_backends_mask = 1; ++ enabled_backends_count = 1; ++ } ++ ++ if (enabled_backends_count != num_backends) ++ num_backends = enabled_backends_count; ++ ++ memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); ++ switch (num_tile_pipes) { ++ case 1: ++ swizzle_pipe[0] = 0; ++ break; ++ case 2: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 1; ++ break; ++ case 3: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 1; ++ break; ++ case 4: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 3; ++ swizzle_pipe[3] = 1; ++ break; ++ case 5: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 4; ++ swizzle_pipe[3] = 1; ++ swizzle_pipe[4] = 3; ++ break; ++ case 6: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 4; ++ swizzle_pipe[3] = 5; ++ swizzle_pipe[4] = 3; ++ swizzle_pipe[5] = 1; ++ break; ++ case 7: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 4; ++ swizzle_pipe[3] = 6; ++ swizzle_pipe[4] = 3; ++ swizzle_pipe[5] = 1; ++ swizzle_pipe[6] = 5; ++ break; ++ case 8: ++ swizzle_pipe[0] = 0; ++ swizzle_pipe[1] = 2; ++ swizzle_pipe[2] = 4; ++ swizzle_pipe[3] = 6; ++ swizzle_pipe[4] = 3; ++ swizzle_pipe[5] = 1; ++ swizzle_pipe[6] = 7; ++ swizzle_pipe[7] = 5; ++ break; ++ } ++ ++ cur_backend = 0; ++ for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { ++ while (((1 << cur_backend) & enabled_backends_mask) == 0) ++ cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; ++ ++ backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); ++ ++ cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; ++ } ++ ++ return backend_map; + } + +-void rv770_vram_info(struct radeon_device *rdev) ++static void rv770_gpu_init(struct radeon_device *rdev) + { +- rv770_vram_get_type(rdev); ++ int i, j, num_qd_pipes; ++ u32 sx_debug_1; ++ u32 smx_dc_ctl0; ++ u32 num_gs_verts_per_thread; ++ u32 vgt_gs_per_es; ++ u32 gs_prim_buffer_depth = 0; ++ u32 sq_ms_fifo_sizes; ++ u32 sq_config; ++ u32 sq_thread_resource_mgmt; ++ u32 hdp_host_path_cntl; ++ u32 sq_dyn_gpr_size_simd_ab_0; ++ u32 backend_map; ++ u32 gb_tiling_config = 0; ++ u32 cc_rb_backend_disable = 0; ++ u32 cc_gc_shader_pipe_config = 0; ++ u32 mc_arb_ramcfg; ++ u32 db_debug4; ++ ++ /* setup chip specs */ ++ switch (rdev->family) { ++ case CHIP_RV770: ++ rdev->config.rv770.max_pipes = 4; ++ rdev->config.rv770.max_tile_pipes = 8; ++ rdev->config.rv770.max_simds = 10; ++ rdev->config.rv770.max_backends = 4; ++ rdev->config.rv770.max_gprs = 256; ++ rdev->config.rv770.max_threads = 248; ++ rdev->config.rv770.max_stack_entries = 512; ++ rdev->config.rv770.max_hw_contexts = 8; ++ rdev->config.rv770.max_gs_threads = 16 * 2; ++ rdev->config.rv770.sx_max_export_size = 128; ++ rdev->config.rv770.sx_max_export_pos_size = 16; ++ rdev->config.rv770.sx_max_export_smx_size = 112; ++ rdev->config.rv770.sq_num_cf_insts = 2; ++ ++ rdev->config.rv770.sx_num_of_sets = 7; ++ rdev->config.rv770.sc_prim_fifo_size = 0xF9; ++ rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; ++ rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; ++ break; ++ case CHIP_RV730: ++ rdev->config.rv770.max_pipes = 2; ++ rdev->config.rv770.max_tile_pipes = 4; ++ rdev->config.rv770.max_simds = 8; ++ rdev->config.rv770.max_backends = 2; ++ rdev->config.rv770.max_gprs = 128; ++ rdev->config.rv770.max_threads = 248; ++ rdev->config.rv770.max_stack_entries = 256; ++ rdev->config.rv770.max_hw_contexts = 8; ++ rdev->config.rv770.max_gs_threads = 16 * 2; ++ rdev->config.rv770.sx_max_export_size = 256; ++ rdev->config.rv770.sx_max_export_pos_size = 32; ++ rdev->config.rv770.sx_max_export_smx_size = 224; ++ rdev->config.rv770.sq_num_cf_insts = 2; ++ ++ rdev->config.rv770.sx_num_of_sets = 7; ++ rdev->config.rv770.sc_prim_fifo_size = 0xf9; ++ rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; ++ rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; ++ if (rdev->config.rv770.sx_max_export_pos_size > 16) { ++ rdev->config.rv770.sx_max_export_pos_size -= 16; ++ rdev->config.rv770.sx_max_export_smx_size += 16; ++ } ++ break; ++ case CHIP_RV710: ++ rdev->config.rv770.max_pipes = 2; ++ rdev->config.rv770.max_tile_pipes = 2; ++ rdev->config.rv770.max_simds = 2; ++ rdev->config.rv770.max_backends = 1; ++ rdev->config.rv770.max_gprs = 256; ++ rdev->config.rv770.max_threads = 192; ++ rdev->config.rv770.max_stack_entries = 256; ++ rdev->config.rv770.max_hw_contexts = 4; ++ rdev->config.rv770.max_gs_threads = 8 * 2; ++ rdev->config.rv770.sx_max_export_size = 128; ++ rdev->config.rv770.sx_max_export_pos_size = 16; ++ rdev->config.rv770.sx_max_export_smx_size = 112; ++ rdev->config.rv770.sq_num_cf_insts = 1; ++ ++ rdev->config.rv770.sx_num_of_sets = 7; ++ rdev->config.rv770.sc_prim_fifo_size = 0x40; ++ rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; ++ rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; ++ break; ++ case CHIP_RV740: ++ rdev->config.rv770.max_pipes = 4; ++ rdev->config.rv770.max_tile_pipes = 4; ++ rdev->config.rv770.max_simds = 8; ++ rdev->config.rv770.max_backends = 4; ++ rdev->config.rv770.max_gprs = 256; ++ rdev->config.rv770.max_threads = 248; ++ rdev->config.rv770.max_stack_entries = 512; ++ rdev->config.rv770.max_hw_contexts = 8; ++ rdev->config.rv770.max_gs_threads = 16 * 2; ++ rdev->config.rv770.sx_max_export_size = 256; ++ rdev->config.rv770.sx_max_export_pos_size = 32; ++ rdev->config.rv770.sx_max_export_smx_size = 224; ++ rdev->config.rv770.sq_num_cf_insts = 2; ++ ++ rdev->config.rv770.sx_num_of_sets = 7; ++ rdev->config.rv770.sc_prim_fifo_size = 0x100; ++ rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; ++ rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; ++ ++ if (rdev->config.rv770.sx_max_export_pos_size > 16) { ++ rdev->config.rv770.sx_max_export_pos_size -= 16; ++ rdev->config.rv770.sx_max_export_smx_size += 16; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ /* Initialize HDP */ ++ j = 0; ++ for (i = 0; i < 32; i++) { ++ WREG32((0x2c14 + j), 0x00000000); ++ WREG32((0x2c18 + j), 0x00000000); ++ WREG32((0x2c1c + j), 0x00000000); ++ WREG32((0x2c20 + j), 0x00000000); ++ WREG32((0x2c24 + j), 0x00000000); ++ j += 0x18; ++ } ++ ++ WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); ++ ++ /* setup tiling, simd, pipe config */ ++ mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); ++ ++ switch (rdev->config.rv770.max_tile_pipes) { ++ case 1: ++ gb_tiling_config |= PIPE_TILING(0); ++ break; ++ case 2: ++ gb_tiling_config |= PIPE_TILING(1); ++ break; ++ case 4: ++ gb_tiling_config |= PIPE_TILING(2); ++ break; ++ case 8: ++ gb_tiling_config |= PIPE_TILING(3); ++ break; ++ default: ++ break; ++ } ++ ++ if (rdev->family == CHIP_RV770) ++ gb_tiling_config |= BANK_TILING(1); ++ else ++ gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK); ++ ++ gb_tiling_config |= GROUP_SIZE(0); ++ ++ if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) { ++ gb_tiling_config |= ROW_TILING(3); ++ gb_tiling_config |= SAMPLE_SPLIT(3); ++ } else { ++ gb_tiling_config |= ++ ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); ++ gb_tiling_config |= ++ SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); ++ } ++ ++ gb_tiling_config |= BANK_SWAPS(1); ++ ++ backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, ++ rdev->config.rv770.max_backends, ++ (0xff << rdev->config.rv770.max_backends) & 0xff); ++ gb_tiling_config |= BACKEND_MAP(backend_map); ++ ++ cc_gc_shader_pipe_config = ++ INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); ++ cc_gc_shader_pipe_config |= ++ INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); ++ ++ cc_rb_backend_disable = ++ BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); ++ ++ WREG32(GB_TILING_CONFIG, gb_tiling_config); ++ WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); ++ WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); ++ ++ WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); ++ WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); ++ WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); ++ ++ WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); ++ WREG32(CGTS_SYS_TCC_DISABLE, 0); ++ WREG32(CGTS_TCC_DISABLE, 0); ++ WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); ++ WREG32(CGTS_USER_TCC_DISABLE, 0); ++ ++ num_qd_pipes = ++ R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK); ++ WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); ++ WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); ++ ++ /* set HW defaults for 3D engine */ ++ WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ++ ROQ_IB2_START(0x2b))); ++ ++ WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); ++ ++ WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | ++ SYNC_GRADIENT | ++ SYNC_WALKER | ++ SYNC_ALIGNER)); ++ ++ sx_debug_1 = RREG32(SX_DEBUG_1); ++ sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; ++ WREG32(SX_DEBUG_1, sx_debug_1); ++ ++ smx_dc_ctl0 = RREG32(SMX_DC_CTL0); ++ smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); ++ smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); ++ WREG32(SMX_DC_CTL0, smx_dc_ctl0); ++ ++ WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | ++ GS_FLUSH_CTL(4) | ++ ACK_FLUSH_CTL(3) | ++ SYNC_FLUSH_CTL)); ++ ++ if (rdev->family == CHIP_RV770) ++ WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f)); ++ else { ++ db_debug4 = RREG32(DB_DEBUG4); ++ db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; ++ WREG32(DB_DEBUG4, db_debug4); ++ } ++ ++ WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | ++ POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | ++ SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); ++ ++ WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | ++ SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | ++ SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); ++ ++ WREG32(PA_SC_MULTI_CHIP_CNTL, 0); ++ ++ WREG32(VGT_NUM_INSTANCES, 1); + +- /* FIXME: implement */ ++ WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); ++ ++ WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); ++ ++ WREG32(CP_PERFMON_CNTL, 0); ++ ++ sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | ++ DONE_FIFO_HIWATER(0xe0) | ++ ALU_UPDATE_FIFO_HIWATER(0x8)); ++ switch (rdev->family) { ++ case CHIP_RV770: ++ sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); ++ break; ++ case CHIP_RV730: ++ case CHIP_RV710: ++ case CHIP_RV740: ++ default: ++ sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); ++ break; ++ } ++ WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); ++ ++ /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT ++ * should be adjusted as needed by the 2D/3D drivers. This just sets default values ++ */ ++ sq_config = RREG32(SQ_CONFIG); ++ sq_config &= ~(PS_PRIO(3) | ++ VS_PRIO(3) | ++ GS_PRIO(3) | ++ ES_PRIO(3)); ++ sq_config |= (DX9_CONSTS | ++ VC_ENABLE | ++ EXPORT_SRC_C | ++ PS_PRIO(0) | ++ VS_PRIO(1) | ++ GS_PRIO(2) | ++ ES_PRIO(3)); ++ if (rdev->family == CHIP_RV710) ++ /* no vertex cache */ ++ sq_config &= ~VC_ENABLE; ++ ++ WREG32(SQ_CONFIG, sq_config); ++ ++ WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | ++ NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | ++ NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); ++ ++ WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | ++ NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); ++ ++ sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | ++ NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | ++ NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); ++ if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) ++ sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); ++ else ++ sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); ++ WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); ++ ++ WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | ++ NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); ++ ++ WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | ++ NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); ++ ++ sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | ++ SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | ++ SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | ++ SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); ++ ++ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); ++ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); ++ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); ++ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); ++ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); ++ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); ++ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); ++ WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); ++ ++ WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | ++ FORCE_EOV_MAX_REZ_CNT(255))); ++ ++ if (rdev->family == CHIP_RV710) ++ WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | ++ AUTO_INVLD_EN(ES_AND_GS_AUTO))); ++ else ++ WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | ++ AUTO_INVLD_EN(ES_AND_GS_AUTO))); ++ ++ switch (rdev->family) { ++ case CHIP_RV770: ++ case CHIP_RV730: ++ case CHIP_RV740: ++ gs_prim_buffer_depth = 384; ++ break; ++ case CHIP_RV710: ++ gs_prim_buffer_depth = 128; ++ break; ++ default: ++ break; ++ } ++ ++ num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; ++ vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; ++ /* Max value for this is 256 */ ++ if (vgt_gs_per_es > 256) ++ vgt_gs_per_es = 256; ++ ++ WREG32(VGT_ES_PER_GS, 128); ++ WREG32(VGT_GS_PER_ES, vgt_gs_per_es); ++ WREG32(VGT_GS_PER_VS, 2); ++ ++ /* more default values. 2D/3D driver should adjust as needed */ ++ WREG32(VGT_GS_VERTEX_REUSE, 16); ++ WREG32(PA_SC_LINE_STIPPLE_STATE, 0); ++ WREG32(VGT_STRMOUT_EN, 0); ++ WREG32(SX_MISC, 0); ++ WREG32(PA_SC_MODE_CNTL, 0); ++ WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); ++ WREG32(PA_SC_AA_CONFIG, 0); ++ WREG32(PA_SC_CLIPRECT_RULE, 0xffff); ++ WREG32(PA_SC_LINE_STIPPLE, 0); ++ WREG32(SPI_INPUT_Z, 0); ++ WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); ++ WREG32(CB_COLOR7_FRAG, 0); ++ ++ /* clear render buffer base addresses */ ++ WREG32(CB_COLOR0_BASE, 0); ++ WREG32(CB_COLOR1_BASE, 0); ++ WREG32(CB_COLOR2_BASE, 0); ++ WREG32(CB_COLOR3_BASE, 0); ++ WREG32(CB_COLOR4_BASE, 0); ++ WREG32(CB_COLOR5_BASE, 0); ++ WREG32(CB_COLOR6_BASE, 0); ++ WREG32(CB_COLOR7_BASE, 0); ++ ++ WREG32(TCP_CNTL, 0); ++ ++ hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); ++ WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); ++ ++ WREG32(PA_SC_MULTI_CHIP_CNTL, 0); ++ ++ WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | ++ NUM_CLIP_SEQ(3))); ++ ++} ++ ++int rv770_mc_init(struct radeon_device *rdev) ++{ ++ fixed20_12 a; ++ u32 tmp; ++ int r; ++ ++ /* Get VRAM informations */ ++ /* FIXME: Don't know how to determine vram width, need to check ++ * vram_width usage ++ */ ++ rdev->mc.vram_width = 128; ++ rdev->mc.vram_is_ddr = true; + /* Could aper size report 0 ? */ + rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); + rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); ++ /* Setup GPU memory space */ ++ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); ++ rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); ++ ++ if (rdev->mc.mc_vram_size > rdev->mc.aper_size) ++ rdev->mc.mc_vram_size = rdev->mc.aper_size; ++ ++ if (rdev->mc.real_vram_size > rdev->mc.aper_size) ++ rdev->mc.real_vram_size = rdev->mc.aper_size; ++ ++ if (rdev->flags & RADEON_IS_AGP) { ++ r = radeon_agp_init(rdev); ++ if (r) ++ return r; ++ /* gtt_size is setup by radeon_agp_init */ ++ rdev->mc.gtt_location = rdev->mc.agp_base; ++ tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; ++ /* Try to put vram before or after AGP because we ++ * we want SYSTEM_APERTURE to cover both VRAM and ++ * AGP so that GPU can catch out of VRAM/AGP access ++ */ ++ if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { ++ /* Enought place before */ ++ rdev->mc.vram_location = rdev->mc.gtt_location - ++ rdev->mc.mc_vram_size; ++ } else if (tmp > rdev->mc.mc_vram_size) { ++ /* Enought place after */ ++ rdev->mc.vram_location = rdev->mc.gtt_location + ++ rdev->mc.gtt_size; ++ } else { ++ /* Try to setup VRAM then AGP might not ++ * not work on some card ++ */ ++ rdev->mc.vram_location = 0x00000000UL; ++ rdev->mc.gtt_location = rdev->mc.mc_vram_size; ++ } ++ } else { ++ rdev->mc.vram_location = 0x00000000UL; ++ rdev->mc.gtt_location = rdev->mc.mc_vram_size; ++ rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; ++ } ++ rdev->mc.vram_start = rdev->mc.vram_location; ++ rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size; ++ rdev->mc.gtt_start = rdev->mc.gtt_location; ++ rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size; ++ /* FIXME: we should enforce default clock in case GPU is not in ++ * default setup ++ */ ++ a.full = rfixed_const(100); ++ rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); ++ rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); ++ return 0; ++} ++int rv770_gpu_reset(struct radeon_device *rdev) ++{ ++ /* FIXME: implement any rv770 specific bits */ ++ return r600_gpu_reset(rdev); ++} ++ ++static int rv770_startup(struct radeon_device *rdev) ++{ ++ int r; ++ ++ radeon_gpu_reset(rdev); ++ rv770_mc_resume(rdev); ++ r = rv770_pcie_gart_enable(rdev); ++ if (r) ++ return r; ++ rv770_gpu_init(rdev); ++ ++ r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, ++ &rdev->r600_blit.shader_gpu_addr); ++ if (r) { ++ DRM_ERROR("failed to pin blit object %d\n", r); ++ return r; ++ } ++ ++ r = radeon_ring_init(rdev, rdev->cp.ring_size); ++ if (r) ++ return r; ++ r = rv770_cp_load_microcode(rdev); ++ if (r) ++ return r; ++ r = r600_cp_resume(rdev); ++ if (r) ++ return r; ++ r = r600_wb_init(rdev); ++ if (r) ++ return r; ++ return 0; ++} ++ ++int rv770_resume(struct radeon_device *rdev) ++{ ++ int r; ++ ++ if (radeon_gpu_reset(rdev)) { ++ /* FIXME: what do we want to do here ? */ ++ } ++ /* post card */ ++ if (rdev->is_atom_bios) { ++ atom_asic_init(rdev->mode_info.atom_context); ++ } else { ++ radeon_combios_asic_init(rdev->ddev); ++ } ++ /* Initialize clocks */ ++ r = radeon_clocks_init(rdev); ++ if (r) { ++ return r; ++ } ++ ++ r = rv770_startup(rdev); ++ if (r) { ++ DRM_ERROR("r600 startup failed on resume\n"); ++ return r; ++ } ++ ++ r = radeon_ib_test(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled testing IB (%d).\n", r); ++ return r; ++ } ++ return r; ++ ++} ++ ++int rv770_suspend(struct radeon_device *rdev) ++{ ++ /* FIXME: we should wait for ring to be empty */ ++ r700_cp_stop(rdev); ++ rdev->cp.ready = false; ++ rv770_pcie_gart_disable(rdev); ++ ++ /* unpin shaders bo */ ++ radeon_object_unpin(rdev->r600_blit.shader_obj); ++ return 0; ++} ++ ++/* Plan is to move initialization in that function and use ++ * helper function so that radeon_device_init pretty much ++ * do nothing more than calling asic specific function. This ++ * should also allow to remove a bunch of callback function ++ * like vram_info. ++ */ ++int rv770_init(struct radeon_device *rdev) ++{ ++ int r; ++ ++ rdev->new_init_path = true; ++ r = radeon_dummy_page_init(rdev); ++ if (r) ++ return r; ++ /* This don't do much */ ++ r = radeon_gem_init(rdev); ++ if (r) ++ return r; ++ /* Read BIOS */ ++ if (!radeon_get_bios(rdev)) { ++ if (ASIC_IS_AVIVO(rdev)) ++ return -EINVAL; ++ } ++ /* Must be an ATOMBIOS */ ++ if (!rdev->is_atom_bios) ++ return -EINVAL; ++ r = radeon_atombios_init(rdev); ++ if (r) ++ return r; ++ /* Post card if necessary */ ++ if (!r600_card_posted(rdev) && rdev->bios) { ++ DRM_INFO("GPU not posted. posting now...\n"); ++ atom_asic_init(rdev->mode_info.atom_context); ++ } ++ /* Initialize scratch registers */ ++ r600_scratch_init(rdev); ++ /* Initialize surface registers */ ++ radeon_surface_init(rdev); ++ radeon_get_clock_info(rdev->ddev); ++ r = radeon_clocks_init(rdev); ++ if (r) ++ return r; ++ /* Fence driver */ ++ r = radeon_fence_driver_init(rdev); ++ if (r) ++ return r; ++ r = rv770_mc_init(rdev); ++ if (r) { ++ if (rdev->flags & RADEON_IS_AGP) { ++ /* Retry with disabling AGP */ ++ rv770_fini(rdev); ++ rdev->flags &= ~RADEON_IS_AGP; ++ return rv770_init(rdev); ++ } ++ return r; ++ } ++ /* Memory manager */ ++ r = radeon_object_init(rdev); ++ if (r) ++ return r; ++ rdev->cp.ring_obj = NULL; ++ r600_ring_init(rdev, 1024 * 1024); ++ ++ if (!rdev->me_fw || !rdev->pfp_fw) { ++ r = r600_cp_init_microcode(rdev); ++ if (r) { ++ DRM_ERROR("Failed to load firmware!\n"); ++ return r; ++ } ++ } ++ ++ r = r600_pcie_gart_init(rdev); ++ if (r) ++ return r; ++ ++ rdev->accel_working = true; ++ r = r600_blit_init(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled blitter (%d).\n", r); ++ rdev->accel_working = false; ++ } ++ ++ r = rv770_startup(rdev); ++ if (r) { ++ if (rdev->flags & RADEON_IS_AGP) { ++ /* Retry with disabling AGP */ ++ rv770_fini(rdev); ++ rdev->flags &= ~RADEON_IS_AGP; ++ return rv770_init(rdev); ++ } ++ rdev->accel_working = false; ++ } ++ if (rdev->accel_working) { ++ r = radeon_ib_pool_init(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); ++ rdev->accel_working = false; ++ } ++ r = radeon_ib_test(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled testing IB (%d).\n", r); ++ rdev->accel_working = false; ++ } ++ } ++ return 0; ++} ++ ++void rv770_fini(struct radeon_device *rdev) ++{ ++ rv770_suspend(rdev); ++ ++ r600_blit_fini(rdev); ++ radeon_ring_fini(rdev); ++ rv770_pcie_gart_fini(rdev); ++ radeon_gem_fini(rdev); ++ radeon_fence_driver_fini(rdev); ++ radeon_clocks_fini(rdev); ++#if __OS_HAS_AGP ++ if (rdev->flags & RADEON_IS_AGP) ++ radeon_agp_fini(rdev); ++#endif ++ radeon_object_fini(rdev); ++ if (rdev->is_atom_bios) { ++ radeon_atombios_fini(rdev); ++ } else { ++ radeon_combios_fini(rdev); ++ } ++ kfree(rdev->bios); ++ rdev->bios = NULL; ++ radeon_dummy_page_fini(rdev); + } +diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h +new file mode 100644 +index 0000000..4b9c3d6 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/rv770d.h +@@ -0,0 +1,341 @@ ++/* ++ * Copyright 2009 Advanced Micro Devices, Inc. ++ * Copyright 2009 Red Hat Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Dave Airlie ++ * Alex Deucher ++ * Jerome Glisse ++ */ ++#ifndef RV770_H ++#define RV770_H ++ ++#define R7XX_MAX_SH_GPRS 256 ++#define R7XX_MAX_TEMP_GPRS 16 ++#define R7XX_MAX_SH_THREADS 256 ++#define R7XX_MAX_SH_STACK_ENTRIES 4096 ++#define R7XX_MAX_BACKENDS 8 ++#define R7XX_MAX_BACKENDS_MASK 0xff ++#define R7XX_MAX_SIMDS 16 ++#define R7XX_MAX_SIMDS_MASK 0xffff ++#define R7XX_MAX_PIPES 8 ++#define R7XX_MAX_PIPES_MASK 0xff ++ ++/* Registers */ ++#define CB_COLOR0_BASE 0x28040 ++#define CB_COLOR1_BASE 0x28044 ++#define CB_COLOR2_BASE 0x28048 ++#define CB_COLOR3_BASE 0x2804C ++#define CB_COLOR4_BASE 0x28050 ++#define CB_COLOR5_BASE 0x28054 ++#define CB_COLOR6_BASE 0x28058 ++#define CB_COLOR7_BASE 0x2805C ++#define CB_COLOR7_FRAG 0x280FC ++ ++#define CC_GC_SHADER_PIPE_CONFIG 0x8950 ++#define CC_RB_BACKEND_DISABLE 0x98F4 ++#define BACKEND_DISABLE(x) ((x) << 16) ++#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 ++ ++#define CGTS_SYS_TCC_DISABLE 0x3F90 ++#define CGTS_TCC_DISABLE 0x9148 ++#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 ++#define CGTS_USER_TCC_DISABLE 0x914C ++ ++#define CONFIG_MEMSIZE 0x5428 ++ ++#define CP_ME_CNTL 0x86D8 ++#define CP_ME_HALT (1<<28) ++#define CP_PFP_HALT (1<<26) ++#define CP_ME_RAM_DATA 0xC160 ++#define CP_ME_RAM_RADDR 0xC158 ++#define CP_ME_RAM_WADDR 0xC15C ++#define CP_MEQ_THRESHOLDS 0x8764 ++#define STQ_SPLIT(x) ((x) << 0) ++#define CP_PERFMON_CNTL 0x87FC ++#define CP_PFP_UCODE_ADDR 0xC150 ++#define CP_PFP_UCODE_DATA 0xC154 ++#define CP_QUEUE_THRESHOLDS 0x8760 ++#define ROQ_IB1_START(x) ((x) << 0) ++#define ROQ_IB2_START(x) ((x) << 8) ++#define CP_RB_CNTL 0xC104 ++#define RB_BUFSZ(x) ((x)<<0) ++#define RB_BLKSZ(x) ((x)<<8) ++#define RB_NO_UPDATE (1<<27) ++#define RB_RPTR_WR_ENA (1<<31) ++#define BUF_SWAP_32BIT (2 << 16) ++#define CP_RB_RPTR 0x8700 ++#define CP_RB_RPTR_ADDR 0xC10C ++#define CP_RB_RPTR_ADDR_HI 0xC110 ++#define CP_RB_RPTR_WR 0xC108 ++#define CP_RB_WPTR 0xC114 ++#define CP_RB_WPTR_ADDR 0xC118 ++#define CP_RB_WPTR_ADDR_HI 0xC11C ++#define CP_RB_WPTR_DELAY 0x8704 ++#define CP_SEM_WAIT_TIMER 0x85BC ++ ++#define DB_DEBUG3 0x98B0 ++#define DB_CLK_OFF_DELAY(x) ((x) << 11) ++#define DB_DEBUG4 0x9B8C ++#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) ++ ++#define DCP_TILING_CONFIG 0x6CA0 ++#define PIPE_TILING(x) ((x) << 1) ++#define BANK_TILING(x) ((x) << 4) ++#define GROUP_SIZE(x) ((x) << 6) ++#define ROW_TILING(x) ((x) << 8) ++#define BANK_SWAPS(x) ((x) << 11) ++#define SAMPLE_SPLIT(x) ((x) << 14) ++#define BACKEND_MAP(x) ((x) << 16) ++ ++#define GB_TILING_CONFIG 0x98F0 ++ ++#define GC_USER_SHADER_PIPE_CONFIG 0x8954 ++#define INACTIVE_QD_PIPES(x) ((x) << 8) ++#define INACTIVE_QD_PIPES_MASK 0x0000FF00 ++#define INACTIVE_SIMDS(x) ((x) << 16) ++#define INACTIVE_SIMDS_MASK 0x00FF0000 ++ ++#define GRBM_CNTL 0x8000 ++#define GRBM_READ_TIMEOUT(x) ((x) << 0) ++#define GRBM_SOFT_RESET 0x8020 ++#define SOFT_RESET_CP (1<<0) ++#define GRBM_STATUS 0x8010 ++#define CMDFIFO_AVAIL_MASK 0x0000000F ++#define GUI_ACTIVE (1<<31) ++#define GRBM_STATUS2 0x8014 ++ ++#define HDP_HOST_PATH_CNTL 0x2C00 ++#define HDP_NONSURFACE_BASE 0x2C04 ++#define HDP_NONSURFACE_INFO 0x2C08 ++#define HDP_NONSURFACE_SIZE 0x2C0C ++#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 ++#define HDP_TILING_CONFIG 0x2F3C ++ ++#define MC_ARB_RAMCFG 0x2760 ++#define NOOFBANK_SHIFT 0 ++#define NOOFBANK_MASK 0x00000003 ++#define NOOFRANK_SHIFT 2 ++#define NOOFRANK_MASK 0x00000004 ++#define NOOFROWS_SHIFT 3 ++#define NOOFROWS_MASK 0x00000038 ++#define NOOFCOLS_SHIFT 6 ++#define NOOFCOLS_MASK 0x000000C0 ++#define CHANSIZE_SHIFT 8 ++#define CHANSIZE_MASK 0x00000100 ++#define BURSTLENGTH_SHIFT 9 ++#define BURSTLENGTH_MASK 0x00000200 ++#define MC_VM_AGP_TOP 0x2028 ++#define MC_VM_AGP_BOT 0x202C ++#define MC_VM_AGP_BASE 0x2030 ++#define MC_VM_FB_LOCATION 0x2024 ++#define MC_VM_MB_L1_TLB0_CNTL 0x2234 ++#define MC_VM_MB_L1_TLB1_CNTL 0x2238 ++#define MC_VM_MB_L1_TLB2_CNTL 0x223C ++#define MC_VM_MB_L1_TLB3_CNTL 0x2240 ++#define ENABLE_L1_TLB (1 << 0) ++#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) ++#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) ++#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) ++#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) ++#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) ++#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) ++#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) ++#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) ++#define MC_VM_MD_L1_TLB0_CNTL 0x2654 ++#define MC_VM_MD_L1_TLB1_CNTL 0x2658 ++#define MC_VM_MD_L1_TLB2_CNTL 0x265C ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C ++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 ++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 ++ ++#define PA_CL_ENHANCE 0x8A14 ++#define CLIP_VTX_REORDER_ENA (1 << 0) ++#define NUM_CLIP_SEQ(x) ((x) << 1) ++#define PA_SC_AA_CONFIG 0x28C04 ++#define PA_SC_CLIPRECT_RULE 0x2820C ++#define PA_SC_EDGERULE 0x28230 ++#define PA_SC_FIFO_SIZE 0x8BCC ++#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) ++#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) ++#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 ++#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) ++#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) ++#define PA_SC_LINE_STIPPLE 0x28A0C ++#define PA_SC_LINE_STIPPLE_STATE 0x8B10 ++#define PA_SC_MODE_CNTL 0x28A4C ++#define PA_SC_MULTI_CHIP_CNTL 0x8B20 ++#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) ++ ++#define SCRATCH_REG0 0x8500 ++#define SCRATCH_REG1 0x8504 ++#define SCRATCH_REG2 0x8508 ++#define SCRATCH_REG3 0x850C ++#define SCRATCH_REG4 0x8510 ++#define SCRATCH_REG5 0x8514 ++#define SCRATCH_REG6 0x8518 ++#define SCRATCH_REG7 0x851C ++#define SCRATCH_UMSK 0x8540 ++#define SCRATCH_ADDR 0x8544 ++ ++#define SMX_DC_CTL0 0xA020 ++#define USE_HASH_FUNCTION (1 << 0) ++#define CACHE_DEPTH(x) ((x) << 1) ++#define FLUSH_ALL_ON_EVENT (1 << 10) ++#define STALL_ON_EVENT (1 << 11) ++#define SMX_EVENT_CTL 0xA02C ++#define ES_FLUSH_CTL(x) ((x) << 0) ++#define GS_FLUSH_CTL(x) ((x) << 3) ++#define ACK_FLUSH_CTL(x) ((x) << 6) ++#define SYNC_FLUSH_CTL (1 << 8) ++ ++#define SPI_CONFIG_CNTL 0x9100 ++#define GPR_WRITE_PRIORITY(x) ((x) << 0) ++#define DISABLE_INTERP_1 (1 << 5) ++#define SPI_CONFIG_CNTL_1 0x913C ++#define VTX_DONE_DELAY(x) ((x) << 0) ++#define INTERP_ONE_PRIM_PER_ROW (1 << 4) ++#define SPI_INPUT_Z 0x286D8 ++#define SPI_PS_IN_CONTROL_0 0x286CC ++#define NUM_INTERP(x) ((x)<<0) ++#define POSITION_ENA (1<<8) ++#define POSITION_CENTROID (1<<9) ++#define POSITION_ADDR(x) ((x)<<10) ++#define PARAM_GEN(x) ((x)<<15) ++#define PARAM_GEN_ADDR(x) ((x)<<19) ++#define BARYC_SAMPLE_CNTL(x) ((x)<<26) ++#define PERSP_GRADIENT_ENA (1<<28) ++#define LINEAR_GRADIENT_ENA (1<<29) ++#define POSITION_SAMPLE (1<<30) ++#define BARYC_AT_SAMPLE_ENA (1<<31) ++ ++#define SQ_CONFIG 0x8C00 ++#define VC_ENABLE (1 << 0) ++#define EXPORT_SRC_C (1 << 1) ++#define DX9_CONSTS (1 << 2) ++#define ALU_INST_PREFER_VECTOR (1 << 3) ++#define DX10_CLAMP (1 << 4) ++#define CLAUSE_SEQ_PRIO(x) ((x) << 8) ++#define PS_PRIO(x) ((x) << 24) ++#define VS_PRIO(x) ((x) << 26) ++#define GS_PRIO(x) ((x) << 28) ++#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 ++#define SIMDA_RING0(x) ((x)<<0) ++#define SIMDA_RING1(x) ((x)<<8) ++#define SIMDB_RING0(x) ((x)<<16) ++#define SIMDB_RING1(x) ((x)<<24) ++#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 ++#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 ++#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC ++#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 ++#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 ++#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 ++#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC ++#define ES_PRIO(x) ((x) << 30) ++#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 ++#define NUM_PS_GPRS(x) ((x) << 0) ++#define NUM_VS_GPRS(x) ((x) << 16) ++#define DYN_GPR_ENABLE (1 << 27) ++#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) ++#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 ++#define NUM_GS_GPRS(x) ((x) << 0) ++#define NUM_ES_GPRS(x) ((x) << 16) ++#define SQ_MS_FIFO_SIZES 0x8CF0 ++#define CACHE_FIFO_SIZE(x) ((x) << 0) ++#define FETCH_FIFO_HIWATER(x) ((x) << 8) ++#define DONE_FIFO_HIWATER(x) ((x) << 16) ++#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) ++#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 ++#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) ++#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) ++#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 ++#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) ++#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) ++#define SQ_THREAD_RESOURCE_MGMT 0x8C0C ++#define NUM_PS_THREADS(x) ((x) << 0) ++#define NUM_VS_THREADS(x) ((x) << 8) ++#define NUM_GS_THREADS(x) ((x) << 16) ++#define NUM_ES_THREADS(x) ((x) << 24) ++ ++#define SX_DEBUG_1 0x9058 ++#define ENABLE_NEW_SMX_ADDRESS (1 << 16) ++#define SX_EXPORT_BUFFER_SIZES 0x900C ++#define COLOR_BUFFER_SIZE(x) ((x) << 0) ++#define POSITION_BUFFER_SIZE(x) ((x) << 8) ++#define SMX_BUFFER_SIZE(x) ((x) << 16) ++#define SX_MISC 0x28350 ++ ++#define TA_CNTL_AUX 0x9508 ++#define DISABLE_CUBE_WRAP (1 << 0) ++#define DISABLE_CUBE_ANISO (1 << 1) ++#define SYNC_GRADIENT (1 << 24) ++#define SYNC_WALKER (1 << 25) ++#define SYNC_ALIGNER (1 << 26) ++#define BILINEAR_PRECISION_6_BIT (0 << 31) ++#define BILINEAR_PRECISION_8_BIT (1 << 31) ++ ++#define TCP_CNTL 0x9610 ++ ++#define VGT_CACHE_INVALIDATION 0x88C4 ++#define CACHE_INVALIDATION(x) ((x)<<0) ++#define VC_ONLY 0 ++#define TC_ONLY 1 ++#define VC_AND_TC 2 ++#define AUTO_INVLD_EN(x) ((x) << 6) ++#define NO_AUTO 0 ++#define ES_AUTO 1 ++#define GS_AUTO 2 ++#define ES_AND_GS_AUTO 3 ++#define VGT_ES_PER_GS 0x88CC ++#define VGT_GS_PER_ES 0x88C8 ++#define VGT_GS_PER_VS 0x88E8 ++#define VGT_GS_VERTEX_REUSE 0x88D4 ++#define VGT_NUM_INSTANCES 0x8974 ++#define VGT_OUT_DEALLOC_CNTL 0x28C5C ++#define DEALLOC_DIST_MASK 0x0000007F ++#define VGT_STRMOUT_EN 0x28AB0 ++#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 ++#define VTX_REUSE_DEPTH_MASK 0x000000FF ++ ++#define VM_CONTEXT0_CNTL 0x1410 ++#define ENABLE_CONTEXT (1 << 0) ++#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) ++#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C ++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 ++#define VM_L2_CNTL 0x1400 ++#define ENABLE_L2_CACHE (1 << 0) ++#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) ++#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) ++#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) ++#define VM_L2_CNTL2 0x1404 ++#define INVALIDATE_ALL_L1_TLBS (1 << 0) ++#define INVALIDATE_L2_CACHE (1 << 1) ++#define VM_L2_CNTL3 0x1408 ++#define BANK_SELECT(x) ((x) << 0) ++#define CACHE_UPDATE_MODE(x) ((x) << 6) ++#define VM_L2_STATUS 0x140C ++#define L2_BUSY (1 << 0) ++ ++#define WAIT_UNTIL 0x8040 ++ ++#endif +diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c +index c2b0d71..87c0625 100644 +--- a/drivers/gpu/drm/ttm/ttm_bo.c ++++ b/drivers/gpu/drm/ttm/ttm_bo.c +@@ -44,6 +44,39 @@ + + static int ttm_bo_setup_vm(struct ttm_buffer_object *bo); + static int ttm_bo_swapout(struct ttm_mem_shrink *shrink); ++static void ttm_bo_global_kobj_release(struct kobject *kobj); ++ ++static struct attribute ttm_bo_count = { ++ .name = "bo_count", ++ .mode = S_IRUGO ++}; ++ ++static ssize_t ttm_bo_global_show(struct kobject *kobj, ++ struct attribute *attr, ++ char *buffer) ++{ ++ struct ttm_bo_global *glob = ++ container_of(kobj, struct ttm_bo_global, kobj); ++ ++ return snprintf(buffer, PAGE_SIZE, "%lu\n", ++ (unsigned long) atomic_read(&glob->bo_count)); ++} ++ ++static struct attribute *ttm_bo_global_attrs[] = { ++ &ttm_bo_count, ++ NULL ++}; ++ ++static struct sysfs_ops ttm_bo_global_ops = { ++ .show = &ttm_bo_global_show ++}; ++ ++static struct kobj_type ttm_bo_glob_kobj_type = { ++ .release = &ttm_bo_global_kobj_release, ++ .sysfs_ops = &ttm_bo_global_ops, ++ .default_attrs = ttm_bo_global_attrs ++}; ++ + + static inline uint32_t ttm_bo_type_flags(unsigned type) + { +@@ -66,10 +99,11 @@ static void ttm_bo_release_list(struct kref *list_kref) + + if (bo->ttm) + ttm_tt_destroy(bo->ttm); ++ atomic_dec(&bo->glob->bo_count); + if (bo->destroy) + bo->destroy(bo); + else { +- ttm_mem_global_free(bdev->mem_glob, bo->acc_size, false); ++ ttm_mem_global_free(bdev->glob->mem_glob, bo->acc_size); + kfree(bo); + } + } +@@ -106,7 +140,7 @@ static void ttm_bo_add_to_lru(struct ttm_buffer_object *bo) + kref_get(&bo->list_kref); + + if (bo->ttm != NULL) { +- list_add_tail(&bo->swap, &bdev->swap_lru); ++ list_add_tail(&bo->swap, &bo->glob->swap_lru); + kref_get(&bo->list_kref); + } + } +@@ -141,7 +175,7 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo, + bool interruptible, + bool no_wait, bool use_sequence, uint32_t sequence) + { +- struct ttm_bo_device *bdev = bo->bdev; ++ struct ttm_bo_global *glob = bo->glob; + int ret; + + while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) { +@@ -153,9 +187,9 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo, + if (no_wait) + return -EBUSY; + +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + ret = ttm_bo_wait_unreserved(bo, interruptible); +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + + if (unlikely(ret)) + return ret; +@@ -181,16 +215,16 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo, + bool interruptible, + bool no_wait, bool use_sequence, uint32_t sequence) + { +- struct ttm_bo_device *bdev = bo->bdev; ++ struct ttm_bo_global *glob = bo->glob; + int put_count = 0; + int ret; + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + ret = ttm_bo_reserve_locked(bo, interruptible, no_wait, use_sequence, + sequence); + if (likely(ret == 0)) + put_count = ttm_bo_del_from_lru(bo); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + + while (put_count--) + kref_put(&bo->list_kref, ttm_bo_ref_bug); +@@ -200,13 +234,13 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo, + + void ttm_bo_unreserve(struct ttm_buffer_object *bo) + { +- struct ttm_bo_device *bdev = bo->bdev; ++ struct ttm_bo_global *glob = bo->glob; + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + ttm_bo_add_to_lru(bo); + atomic_set(&bo->reserved, 0); + wake_up_all(&bo->event_queue); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + } + EXPORT_SYMBOL(ttm_bo_unreserve); + +@@ -217,6 +251,7 @@ EXPORT_SYMBOL(ttm_bo_unreserve); + static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) + { + struct ttm_bo_device *bdev = bo->bdev; ++ struct ttm_bo_global *glob = bo->glob; + int ret = 0; + uint32_t page_flags = 0; + +@@ -232,14 +267,14 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) + page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC; + case ttm_bo_type_kernel: + bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT, +- page_flags, bdev->dummy_read_page); ++ page_flags, glob->dummy_read_page); + if (unlikely(bo->ttm == NULL)) + ret = -ENOMEM; + break; + case ttm_bo_type_user: + bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT, + page_flags | TTM_PAGE_FLAG_USER, +- bdev->dummy_read_page); ++ glob->dummy_read_page); + if (unlikely(bo->ttm == NULL)) + ret = -ENOMEM; + break; +@@ -360,6 +395,7 @@ out_err: + static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) + { + struct ttm_bo_device *bdev = bo->bdev; ++ struct ttm_bo_global *glob = bo->glob; + struct ttm_bo_driver *driver = bdev->driver; + int ret; + +@@ -371,7 +407,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) + + spin_unlock(&bo->lock); + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + ret = ttm_bo_reserve_locked(bo, false, false, false, 0); + BUG_ON(ret); + if (bo->ttm) +@@ -386,7 +422,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) + bo->mem.mm_node = NULL; + } + put_count = ttm_bo_del_from_lru(bo); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + + atomic_set(&bo->reserved, 0); + +@@ -396,14 +432,14 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) + return 0; + } + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + if (list_empty(&bo->ddestroy)) { + void *sync_obj = bo->sync_obj; + void *sync_obj_arg = bo->sync_obj_arg; + + kref_get(&bo->list_kref); + list_add_tail(&bo->ddestroy, &bdev->ddestroy); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + spin_unlock(&bo->lock); + + if (sync_obj) +@@ -413,7 +449,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) + ret = 0; + + } else { +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + spin_unlock(&bo->lock); + ret = -EBUSY; + } +@@ -428,11 +464,12 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) + + static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) + { ++ struct ttm_bo_global *glob = bdev->glob; + struct ttm_buffer_object *entry, *nentry; + struct list_head *list, *next; + int ret; + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + list_for_each_safe(list, next, &bdev->ddestroy) { + entry = list_entry(list, struct ttm_buffer_object, ddestroy); + nentry = NULL; +@@ -449,16 +486,16 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) + } + kref_get(&entry->list_kref); + +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + ret = ttm_bo_cleanup_refs(entry, remove_all); + kref_put(&entry->list_kref, ttm_bo_release_list); + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + if (nentry) { + bool next_onlist = !list_empty(next); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + kref_put(&nentry->list_kref, ttm_bo_release_list); +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + /* + * Someone might have raced us and removed the + * next entry from the list. We don't bother restarting +@@ -472,7 +509,7 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) + break; + } + ret = !list_empty(&bdev->ddestroy); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + + return ret; + } +@@ -522,6 +559,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type, + { + int ret = 0; + struct ttm_bo_device *bdev = bo->bdev; ++ struct ttm_bo_global *glob = bo->glob; + struct ttm_mem_reg evict_mem; + uint32_t proposed_placement; + +@@ -570,12 +608,12 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type, + goto out; + } + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + if (evict_mem.mm_node) { + drm_mm_put_block(evict_mem.mm_node); + evict_mem.mm_node = NULL; + } +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + bo->evicted = true; + out: + return ret; +@@ -590,6 +628,7 @@ static int ttm_bo_mem_force_space(struct ttm_bo_device *bdev, + uint32_t mem_type, + bool interruptible, bool no_wait) + { ++ struct ttm_bo_global *glob = bdev->glob; + struct drm_mm_node *node; + struct ttm_buffer_object *entry; + struct ttm_mem_type_manager *man = &bdev->man[mem_type]; +@@ -603,7 +642,7 @@ retry_pre_get: + if (unlikely(ret != 0)) + return ret; + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + do { + node = drm_mm_search_free(&man->manager, num_pages, + mem->page_alignment, 1); +@@ -624,7 +663,7 @@ retry_pre_get: + if (likely(ret == 0)) + put_count = ttm_bo_del_from_lru(entry); + +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + + if (unlikely(ret != 0)) + return ret; +@@ -640,21 +679,21 @@ retry_pre_get: + if (ret) + return ret; + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + } while (1); + + if (!node) { +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + return -ENOMEM; + } + + node = drm_mm_get_block_atomic(node, num_pages, mem->page_alignment); + if (unlikely(!node)) { +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + goto retry_pre_get; + } + +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + mem->mm_node = node; + mem->mem_type = mem_type; + return 0; +@@ -723,6 +762,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, + bool interruptible, bool no_wait) + { + struct ttm_bo_device *bdev = bo->bdev; ++ struct ttm_bo_global *glob = bo->glob; + struct ttm_mem_type_manager *man; + + uint32_t num_prios = bdev->driver->num_mem_type_prio; +@@ -762,20 +802,20 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, + if (unlikely(ret)) + return ret; + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + node = drm_mm_search_free(&man->manager, + mem->num_pages, + mem->page_alignment, + 1); + if (unlikely(!node)) { +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + break; + } + node = drm_mm_get_block_atomic(node, + mem->num_pages, + mem-> + page_alignment); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + } while (!node); + } + if (node) +@@ -848,7 +888,7 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo, + uint32_t proposed_placement, + bool interruptible, bool no_wait) + { +- struct ttm_bo_device *bdev = bo->bdev; ++ struct ttm_bo_global *glob = bo->glob; + int ret = 0; + struct ttm_mem_reg mem; + +@@ -884,9 +924,9 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo, + + out_unlock: + if (ret && mem.mm_node) { +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + drm_mm_put_block(mem.mm_node); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + } + return ret; + } +@@ -1022,6 +1062,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev, + INIT_LIST_HEAD(&bo->ddestroy); + INIT_LIST_HEAD(&bo->swap); + bo->bdev = bdev; ++ bo->glob = bdev->glob; + bo->type = type; + bo->num_pages = num_pages; + bo->mem.mem_type = TTM_PL_SYSTEM; +@@ -1034,6 +1075,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev, + bo->seq_valid = false; + bo->persistant_swap_storage = persistant_swap_storage; + bo->acc_size = acc_size; ++ atomic_inc(&bo->glob->bo_count); + + ret = ttm_bo_check_placement(bo, flags, 0ULL); + if (unlikely(ret != 0)) +@@ -1072,13 +1114,13 @@ out_err: + } + EXPORT_SYMBOL(ttm_buffer_object_init); + +-static inline size_t ttm_bo_size(struct ttm_bo_device *bdev, ++static inline size_t ttm_bo_size(struct ttm_bo_global *glob, + unsigned long num_pages) + { + size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) & + PAGE_MASK; + +- return bdev->ttm_bo_size + 2 * page_array_size; ++ return glob->ttm_bo_size + 2 * page_array_size; + } + + int ttm_buffer_object_create(struct ttm_bo_device *bdev, +@@ -1093,18 +1135,18 @@ int ttm_buffer_object_create(struct ttm_bo_device *bdev, + { + struct ttm_buffer_object *bo; + int ret; +- struct ttm_mem_global *mem_glob = bdev->mem_glob; ++ struct ttm_mem_global *mem_glob = bdev->glob->mem_glob; + + size_t acc_size = +- ttm_bo_size(bdev, (size + PAGE_SIZE - 1) >> PAGE_SHIFT); +- ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false, false); ++ ttm_bo_size(bdev->glob, (size + PAGE_SIZE - 1) >> PAGE_SHIFT); ++ ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false); + if (unlikely(ret != 0)) + return ret; + + bo = kzalloc(sizeof(*bo), GFP_KERNEL); + + if (unlikely(bo == NULL)) { +- ttm_mem_global_free(mem_glob, acc_size, false); ++ ttm_mem_global_free(mem_glob, acc_size); + return -ENOMEM; + } + +@@ -1150,6 +1192,7 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, + struct list_head *head, + unsigned mem_type, bool allow_errors) + { ++ struct ttm_bo_global *glob = bdev->glob; + struct ttm_buffer_object *entry; + int ret; + int put_count; +@@ -1158,30 +1201,31 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, + * Can't use standard list traversal since we're unlocking. + */ + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + + while (!list_empty(head)) { + entry = list_first_entry(head, struct ttm_buffer_object, lru); + kref_get(&entry->list_kref); + ret = ttm_bo_reserve_locked(entry, false, false, false, 0); + put_count = ttm_bo_del_from_lru(entry); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + while (put_count--) + kref_put(&entry->list_kref, ttm_bo_ref_bug); + BUG_ON(ret); + ret = ttm_bo_leave_list(entry, mem_type, allow_errors); + ttm_bo_unreserve(entry); + kref_put(&entry->list_kref, ttm_bo_release_list); +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + } + +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + + return 0; + } + + int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type) + { ++ struct ttm_bo_global *glob = bdev->glob; + struct ttm_mem_type_manager *man; + int ret = -EINVAL; + +@@ -1204,13 +1248,13 @@ int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type) + if (mem_type > 0) { + ttm_bo_force_list_clean(bdev, &man->lru, mem_type, false); + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + if (drm_mm_clean(&man->manager)) + drm_mm_takedown(&man->manager); + else + ret = -EBUSY; + +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + } + + return ret; +@@ -1284,11 +1328,82 @@ int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type, + } + EXPORT_SYMBOL(ttm_bo_init_mm); + ++static void ttm_bo_global_kobj_release(struct kobject *kobj) ++{ ++ struct ttm_bo_global *glob = ++ container_of(kobj, struct ttm_bo_global, kobj); ++ ++ ttm_mem_unregister_shrink(glob->mem_glob, &glob->shrink); ++ __free_page(glob->dummy_read_page); ++ kfree(glob); ++} ++ ++void ttm_bo_global_release(struct ttm_global_reference *ref) ++{ ++ struct ttm_bo_global *glob = ref->object; ++ ++ kobject_del(&glob->kobj); ++ kobject_put(&glob->kobj); ++} ++EXPORT_SYMBOL(ttm_bo_global_release); ++ ++int ttm_bo_global_init(struct ttm_global_reference *ref) ++{ ++ struct ttm_bo_global_ref *bo_ref = ++ container_of(ref, struct ttm_bo_global_ref, ref); ++ struct ttm_bo_global *glob = ref->object; ++ int ret; ++ ++ mutex_init(&glob->device_list_mutex); ++ spin_lock_init(&glob->lru_lock); ++ glob->mem_glob = bo_ref->mem_glob; ++ glob->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32); ++ ++ if (unlikely(glob->dummy_read_page == NULL)) { ++ ret = -ENOMEM; ++ goto out_no_drp; ++ } ++ ++ INIT_LIST_HEAD(&glob->swap_lru); ++ INIT_LIST_HEAD(&glob->device_list); ++ ++ ttm_mem_init_shrink(&glob->shrink, ttm_bo_swapout); ++ ret = ttm_mem_register_shrink(glob->mem_glob, &glob->shrink); ++ if (unlikely(ret != 0)) { ++ printk(KERN_ERR TTM_PFX ++ "Could not register buffer object swapout.\n"); ++ goto out_no_shrink; ++ } ++ ++ glob->ttm_bo_extra_size = ++ ttm_round_pot(sizeof(struct ttm_tt)) + ++ ttm_round_pot(sizeof(struct ttm_backend)); ++ ++ glob->ttm_bo_size = glob->ttm_bo_extra_size + ++ ttm_round_pot(sizeof(struct ttm_buffer_object)); ++ ++ atomic_set(&glob->bo_count, 0); ++ ++ kobject_init(&glob->kobj, &ttm_bo_glob_kobj_type); ++ ret = kobject_add(&glob->kobj, ttm_get_kobj(), "buffer_objects"); ++ if (unlikely(ret != 0)) ++ kobject_put(&glob->kobj); ++ return ret; ++out_no_shrink: ++ __free_page(glob->dummy_read_page); ++out_no_drp: ++ kfree(glob); ++ return ret; ++} ++EXPORT_SYMBOL(ttm_bo_global_init); ++ ++ + int ttm_bo_device_release(struct ttm_bo_device *bdev) + { + int ret = 0; + unsigned i = TTM_NUM_MEM_TYPES; + struct ttm_mem_type_manager *man; ++ struct ttm_bo_global *glob = bdev->glob; + + while (i--) { + man = &bdev->man[i]; +@@ -1304,100 +1419,74 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev) + } + } + ++ mutex_lock(&glob->device_list_mutex); ++ list_del(&bdev->device_list); ++ mutex_unlock(&glob->device_list_mutex); ++ + if (!cancel_delayed_work(&bdev->wq)) + flush_scheduled_work(); + + while (ttm_bo_delayed_delete(bdev, true)) + ; + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + if (list_empty(&bdev->ddestroy)) + TTM_DEBUG("Delayed destroy list was clean\n"); + + if (list_empty(&bdev->man[0].lru)) + TTM_DEBUG("Swap list was clean\n"); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + +- ttm_mem_unregister_shrink(bdev->mem_glob, &bdev->shrink); + BUG_ON(!drm_mm_clean(&bdev->addr_space_mm)); + write_lock(&bdev->vm_lock); + drm_mm_takedown(&bdev->addr_space_mm); + write_unlock(&bdev->vm_lock); + +- __free_page(bdev->dummy_read_page); + return ret; + } + EXPORT_SYMBOL(ttm_bo_device_release); + +-/* +- * This function is intended to be called on drm driver load. +- * If you decide to call it from firstopen, you must protect the call +- * from a potentially racing ttm_bo_driver_finish in lastclose. +- * (This may happen on X server restart). +- */ +- + int ttm_bo_device_init(struct ttm_bo_device *bdev, +- struct ttm_mem_global *mem_glob, +- struct ttm_bo_driver *driver, uint64_t file_page_offset, ++ struct ttm_bo_global *glob, ++ struct ttm_bo_driver *driver, ++ uint64_t file_page_offset, + bool need_dma32) + { + int ret = -EINVAL; + +- bdev->dummy_read_page = NULL; + rwlock_init(&bdev->vm_lock); +- spin_lock_init(&bdev->lru_lock); +- + bdev->driver = driver; +- bdev->mem_glob = mem_glob; + + memset(bdev->man, 0, sizeof(bdev->man)); + +- bdev->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32); +- if (unlikely(bdev->dummy_read_page == NULL)) { +- ret = -ENOMEM; +- goto out_err0; +- } +- + /* + * Initialize the system memory buffer type. + * Other types need to be driver / IOCTL initialized. + */ + ret = ttm_bo_init_mm(bdev, TTM_PL_SYSTEM, 0, 0); + if (unlikely(ret != 0)) +- goto out_err1; ++ goto out_no_sys; + + bdev->addr_space_rb = RB_ROOT; + ret = drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000); + if (unlikely(ret != 0)) +- goto out_err2; ++ goto out_no_addr_mm; + + INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue); + bdev->nice_mode = true; + INIT_LIST_HEAD(&bdev->ddestroy); +- INIT_LIST_HEAD(&bdev->swap_lru); + bdev->dev_mapping = NULL; ++ bdev->glob = glob; + bdev->need_dma32 = need_dma32; +- ttm_mem_init_shrink(&bdev->shrink, ttm_bo_swapout); +- ret = ttm_mem_register_shrink(mem_glob, &bdev->shrink); +- if (unlikely(ret != 0)) { +- printk(KERN_ERR TTM_PFX +- "Could not register buffer object swapout.\n"); +- goto out_err2; +- } + +- bdev->ttm_bo_extra_size = +- ttm_round_pot(sizeof(struct ttm_tt)) + +- ttm_round_pot(sizeof(struct ttm_backend)); +- +- bdev->ttm_bo_size = bdev->ttm_bo_extra_size + +- ttm_round_pot(sizeof(struct ttm_buffer_object)); ++ mutex_lock(&glob->device_list_mutex); ++ list_add_tail(&bdev->device_list, &glob->device_list); ++ mutex_unlock(&glob->device_list_mutex); + + return 0; +-out_err2: ++out_no_addr_mm: + ttm_bo_clean_mm(bdev, 0); +-out_err1: +- __free_page(bdev->dummy_read_page); +-out_err0: ++out_no_sys: + return ret; + } + EXPORT_SYMBOL(ttm_bo_device_init); +@@ -1647,21 +1736,21 @@ void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo) + + static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) + { +- struct ttm_bo_device *bdev = +- container_of(shrink, struct ttm_bo_device, shrink); ++ struct ttm_bo_global *glob = ++ container_of(shrink, struct ttm_bo_global, shrink); + struct ttm_buffer_object *bo; + int ret = -EBUSY; + int put_count; + uint32_t swap_placement = (TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM); + +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + while (ret == -EBUSY) { +- if (unlikely(list_empty(&bdev->swap_lru))) { +- spin_unlock(&bdev->lru_lock); ++ if (unlikely(list_empty(&glob->swap_lru))) { ++ spin_unlock(&glob->lru_lock); + return -EBUSY; + } + +- bo = list_first_entry(&bdev->swap_lru, ++ bo = list_first_entry(&glob->swap_lru, + struct ttm_buffer_object, swap); + kref_get(&bo->list_kref); + +@@ -1673,16 +1762,16 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) + + ret = ttm_bo_reserve_locked(bo, false, true, false, 0); + if (unlikely(ret == -EBUSY)) { +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + ttm_bo_wait_unreserved(bo, false); + kref_put(&bo->list_kref, ttm_bo_release_list); +- spin_lock(&bdev->lru_lock); ++ spin_lock(&glob->lru_lock); + } + } + + BUG_ON(ret != 0); + put_count = ttm_bo_del_from_lru(bo); +- spin_unlock(&bdev->lru_lock); ++ spin_unlock(&glob->lru_lock); + + while (put_count--) + kref_put(&bo->list_kref, ttm_bo_ref_bug); +@@ -1736,6 +1825,6 @@ out: + + void ttm_bo_swapout_all(struct ttm_bo_device *bdev) + { +- while (ttm_bo_swapout(&bdev->shrink) == 0) ++ while (ttm_bo_swapout(&bdev->glob->shrink) == 0) + ; + } +diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c +index ad4ada0..c70927e 100644 +--- a/drivers/gpu/drm/ttm/ttm_bo_util.c ++++ b/drivers/gpu/drm/ttm/ttm_bo_util.c +@@ -41,9 +41,9 @@ void ttm_bo_free_old_node(struct ttm_buffer_object *bo) + struct ttm_mem_reg *old_mem = &bo->mem; + + if (old_mem->mm_node) { +- spin_lock(&bo->bdev->lru_lock); ++ spin_lock(&bo->glob->lru_lock); + drm_mm_put_block(old_mem->mm_node); +- spin_unlock(&bo->bdev->lru_lock); ++ spin_unlock(&bo->glob->lru_lock); + } + old_mem->mm_node = NULL; + } +diff --git a/drivers/gpu/drm/ttm/ttm_global.c b/drivers/gpu/drm/ttm/ttm_global.c +index 0b14eb1..541744d 100644 +--- a/drivers/gpu/drm/ttm/ttm_global.c ++++ b/drivers/gpu/drm/ttm/ttm_global.c +@@ -71,7 +71,7 @@ int ttm_global_item_ref(struct ttm_global_reference *ref) + + mutex_lock(&item->mutex); + if (item->refcount == 0) { +- item->object = kmalloc(ref->size, GFP_KERNEL); ++ item->object = kzalloc(ref->size, GFP_KERNEL); + if (unlikely(item->object == NULL)) { + ret = -ENOMEM; + goto out_err; +@@ -89,7 +89,6 @@ int ttm_global_item_ref(struct ttm_global_reference *ref) + mutex_unlock(&item->mutex); + return 0; + out_err: +- kfree(item->object); + mutex_unlock(&item->mutex); + item->object = NULL; + return ret; +@@ -105,7 +104,6 @@ void ttm_global_item_unref(struct ttm_global_reference *ref) + BUG_ON(ref->object != item->object); + if (--item->refcount == 0) { + ref->release(ref); +- kfree(item->object); + item->object = NULL; + } + mutex_unlock(&item->mutex); +diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c +index 87323d4..072c281 100644 +--- a/drivers/gpu/drm/ttm/ttm_memory.c ++++ b/drivers/gpu/drm/ttm/ttm_memory.c +@@ -26,15 +26,180 @@ + **************************************************************************/ + + #include "ttm/ttm_memory.h" ++#include "ttm/ttm_module.h" + #include <linux/spinlock.h> + #include <linux/sched.h> + #include <linux/wait.h> + #include <linux/mm.h> + #include <linux/module.h> + +-#define TTM_PFX "[TTM] " + #define TTM_MEMORY_ALLOC_RETRIES 4 + ++struct ttm_mem_zone { ++ struct kobject kobj; ++ struct ttm_mem_global *glob; ++ const char *name; ++ uint64_t zone_mem; ++ uint64_t emer_mem; ++ uint64_t max_mem; ++ uint64_t swap_limit; ++ uint64_t used_mem; ++}; ++ ++static struct attribute ttm_mem_sys = { ++ .name = "zone_memory", ++ .mode = S_IRUGO ++}; ++static struct attribute ttm_mem_emer = { ++ .name = "emergency_memory", ++ .mode = S_IRUGO | S_IWUSR ++}; ++static struct attribute ttm_mem_max = { ++ .name = "available_memory", ++ .mode = S_IRUGO | S_IWUSR ++}; ++static struct attribute ttm_mem_swap = { ++ .name = "swap_limit", ++ .mode = S_IRUGO | S_IWUSR ++}; ++static struct attribute ttm_mem_used = { ++ .name = "used_memory", ++ .mode = S_IRUGO ++}; ++ ++static void ttm_mem_zone_kobj_release(struct kobject *kobj) ++{ ++ struct ttm_mem_zone *zone = ++ container_of(kobj, struct ttm_mem_zone, kobj); ++ ++ printk(KERN_INFO TTM_PFX ++ "Zone %7s: Used memory at exit: %llu kiB.\n", ++ zone->name, (unsigned long long) zone->used_mem >> 10); ++ kfree(zone); ++} ++ ++static ssize_t ttm_mem_zone_show(struct kobject *kobj, ++ struct attribute *attr, ++ char *buffer) ++{ ++ struct ttm_mem_zone *zone = ++ container_of(kobj, struct ttm_mem_zone, kobj); ++ uint64_t val = 0; ++ ++ spin_lock(&zone->glob->lock); ++ if (attr == &ttm_mem_sys) ++ val = zone->zone_mem; ++ else if (attr == &ttm_mem_emer) ++ val = zone->emer_mem; ++ else if (attr == &ttm_mem_max) ++ val = zone->max_mem; ++ else if (attr == &ttm_mem_swap) ++ val = zone->swap_limit; ++ else if (attr == &ttm_mem_used) ++ val = zone->used_mem; ++ spin_unlock(&zone->glob->lock); ++ ++ return snprintf(buffer, PAGE_SIZE, "%llu\n", ++ (unsigned long long) val >> 10); ++} ++ ++static void ttm_check_swapping(struct ttm_mem_global *glob); ++ ++static ssize_t ttm_mem_zone_store(struct kobject *kobj, ++ struct attribute *attr, ++ const char *buffer, ++ size_t size) ++{ ++ struct ttm_mem_zone *zone = ++ container_of(kobj, struct ttm_mem_zone, kobj); ++ int chars; ++ unsigned long val; ++ uint64_t val64; ++ ++ chars = sscanf(buffer, "%lu", &val); ++ if (chars == 0) ++ return size; ++ ++ val64 = val; ++ val64 <<= 10; ++ ++ spin_lock(&zone->glob->lock); ++ if (val64 > zone->zone_mem) ++ val64 = zone->zone_mem; ++ if (attr == &ttm_mem_emer) { ++ zone->emer_mem = val64; ++ if (zone->max_mem > val64) ++ zone->max_mem = val64; ++ } else if (attr == &ttm_mem_max) { ++ zone->max_mem = val64; ++ if (zone->emer_mem < val64) ++ zone->emer_mem = val64; ++ } else if (attr == &ttm_mem_swap) ++ zone->swap_limit = val64; ++ spin_unlock(&zone->glob->lock); ++ ++ ttm_check_swapping(zone->glob); ++ ++ return size; ++} ++ ++static struct attribute *ttm_mem_zone_attrs[] = { ++ &ttm_mem_sys, ++ &ttm_mem_emer, ++ &ttm_mem_max, ++ &ttm_mem_swap, ++ &ttm_mem_used, ++ NULL ++}; ++ ++static struct sysfs_ops ttm_mem_zone_ops = { ++ .show = &ttm_mem_zone_show, ++ .store = &ttm_mem_zone_store ++}; ++ ++static struct kobj_type ttm_mem_zone_kobj_type = { ++ .release = &ttm_mem_zone_kobj_release, ++ .sysfs_ops = &ttm_mem_zone_ops, ++ .default_attrs = ttm_mem_zone_attrs, ++}; ++ ++static void ttm_mem_global_kobj_release(struct kobject *kobj) ++{ ++ struct ttm_mem_global *glob = ++ container_of(kobj, struct ttm_mem_global, kobj); ++ ++ kfree(glob); ++} ++ ++static struct kobj_type ttm_mem_glob_kobj_type = { ++ .release = &ttm_mem_global_kobj_release, ++}; ++ ++static bool ttm_zones_above_swap_target(struct ttm_mem_global *glob, ++ bool from_wq, uint64_t extra) ++{ ++ unsigned int i; ++ struct ttm_mem_zone *zone; ++ uint64_t target; ++ ++ for (i = 0; i < glob->num_zones; ++i) { ++ zone = glob->zones[i]; ++ ++ if (from_wq) ++ target = zone->swap_limit; ++ else if (capable(CAP_SYS_ADMIN)) ++ target = zone->emer_mem; ++ else ++ target = zone->max_mem; ++ ++ target = (extra > target) ? 0ULL : target; ++ ++ if (zone->used_mem > target) ++ return true; ++ } ++ return false; ++} ++ + /** + * At this point we only support a single shrink callback. + * Extend this if needed, perhaps using a linked list of callbacks. +@@ -42,34 +207,17 @@ + * many threads may try to swap out at any given time. + */ + +-static void ttm_shrink(struct ttm_mem_global *glob, bool from_workqueue, ++static void ttm_shrink(struct ttm_mem_global *glob, bool from_wq, + uint64_t extra) + { + int ret; + struct ttm_mem_shrink *shrink; +- uint64_t target; +- uint64_t total_target; + + spin_lock(&glob->lock); + if (glob->shrink == NULL) + goto out; + +- if (from_workqueue) { +- target = glob->swap_limit; +- total_target = glob->total_memory_swap_limit; +- } else if (capable(CAP_SYS_ADMIN)) { +- total_target = glob->emer_total_memory; +- target = glob->emer_memory; +- } else { +- total_target = glob->max_total_memory; +- target = glob->max_memory; +- } +- +- total_target = (extra >= total_target) ? 0 : total_target - extra; +- target = (extra >= target) ? 0 : target - extra; +- +- while (glob->used_memory > target || +- glob->used_total_memory > total_target) { ++ while (ttm_zones_above_swap_target(glob, from_wq, extra)) { + shrink = glob->shrink; + spin_unlock(&glob->lock); + ret = shrink->do_shrink(shrink); +@@ -81,6 +229,8 @@ out: + spin_unlock(&glob->lock); + } + ++ ++ + static void ttm_shrink_work(struct work_struct *work) + { + struct ttm_mem_global *glob = +@@ -89,63 +239,198 @@ static void ttm_shrink_work(struct work_struct *work) + ttm_shrink(glob, true, 0ULL); + } + ++static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob, ++ const struct sysinfo *si) ++{ ++ struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); ++ uint64_t mem; ++ int ret; ++ ++ if (unlikely(!zone)) ++ return -ENOMEM; ++ ++ mem = si->totalram - si->totalhigh; ++ mem *= si->mem_unit; ++ ++ zone->name = "kernel"; ++ zone->zone_mem = mem; ++ zone->max_mem = mem >> 1; ++ zone->emer_mem = (mem >> 1) + (mem >> 2); ++ zone->swap_limit = zone->max_mem - (mem >> 3); ++ zone->used_mem = 0; ++ zone->glob = glob; ++ glob->zone_kernel = zone; ++ kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); ++ ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); ++ if (unlikely(ret != 0)) { ++ kobject_put(&zone->kobj); ++ return ret; ++ } ++ glob->zones[glob->num_zones++] = zone; ++ return 0; ++} ++ ++#ifdef CONFIG_HIGHMEM ++static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob, ++ const struct sysinfo *si) ++{ ++ struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); ++ uint64_t mem; ++ int ret; ++ ++ if (unlikely(!zone)) ++ return -ENOMEM; ++ ++ if (si->totalhigh == 0) ++ return 0; ++ ++ mem = si->totalram; ++ mem *= si->mem_unit; ++ ++ zone->name = "highmem"; ++ zone->zone_mem = mem; ++ zone->max_mem = mem >> 1; ++ zone->emer_mem = (mem >> 1) + (mem >> 2); ++ zone->swap_limit = zone->max_mem - (mem >> 3); ++ zone->used_mem = 0; ++ zone->glob = glob; ++ glob->zone_highmem = zone; ++ kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); ++ ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); ++ if (unlikely(ret != 0)) { ++ kobject_put(&zone->kobj); ++ return ret; ++ } ++ glob->zones[glob->num_zones++] = zone; ++ return 0; ++} ++#else ++static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob, ++ const struct sysinfo *si) ++{ ++ struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); ++ uint64_t mem; ++ int ret; ++ ++ if (unlikely(!zone)) ++ return -ENOMEM; ++ ++ mem = si->totalram; ++ mem *= si->mem_unit; ++ ++ /** ++ * No special dma32 zone needed. ++ */ ++ ++ if (mem <= ((uint64_t) 1ULL << 32)) ++ return 0; ++ ++ /* ++ * Limit max dma32 memory to 4GB for now ++ * until we can figure out how big this ++ * zone really is. ++ */ ++ ++ mem = ((uint64_t) 1ULL << 32); ++ zone->name = "dma32"; ++ zone->zone_mem = mem; ++ zone->max_mem = mem >> 1; ++ zone->emer_mem = (mem >> 1) + (mem >> 2); ++ zone->swap_limit = zone->max_mem - (mem >> 3); ++ zone->used_mem = 0; ++ zone->glob = glob; ++ glob->zone_dma32 = zone; ++ kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); ++ ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); ++ if (unlikely(ret != 0)) { ++ kobject_put(&zone->kobj); ++ return ret; ++ } ++ glob->zones[glob->num_zones++] = zone; ++ return 0; ++} ++#endif ++ + int ttm_mem_global_init(struct ttm_mem_global *glob) + { + struct sysinfo si; +- uint64_t mem; ++ int ret; ++ int i; ++ struct ttm_mem_zone *zone; + + spin_lock_init(&glob->lock); + glob->swap_queue = create_singlethread_workqueue("ttm_swap"); + INIT_WORK(&glob->work, ttm_shrink_work); + init_waitqueue_head(&glob->queue); ++ kobject_init(&glob->kobj, &ttm_mem_glob_kobj_type); ++ ret = kobject_add(&glob->kobj, ++ ttm_get_kobj(), ++ "memory_accounting"); ++ if (unlikely(ret != 0)) { ++ kobject_put(&glob->kobj); ++ return ret; ++ } + + si_meminfo(&si); + +- mem = si.totalram - si.totalhigh; +- mem *= si.mem_unit; +- +- glob->max_memory = mem >> 1; +- glob->emer_memory = (mem >> 1) + (mem >> 2); +- glob->swap_limit = glob->max_memory - (mem >> 3); +- glob->used_memory = 0; +- glob->used_total_memory = 0; +- glob->shrink = NULL; +- +- mem = si.totalram; +- mem *= si.mem_unit; +- +- glob->max_total_memory = mem >> 1; +- glob->emer_total_memory = (mem >> 1) + (mem >> 2); +- +- glob->total_memory_swap_limit = glob->max_total_memory - (mem >> 3); +- +- printk(KERN_INFO TTM_PFX "TTM available graphics memory: %llu MiB\n", +- glob->max_total_memory >> 20); +- printk(KERN_INFO TTM_PFX "TTM available object memory: %llu MiB\n", +- glob->max_memory >> 20); +- ++ ret = ttm_mem_init_kernel_zone(glob, &si); ++ if (unlikely(ret != 0)) ++ goto out_no_zone; ++#ifdef CONFIG_HIGHMEM ++ ret = ttm_mem_init_highmem_zone(glob, &si); ++ if (unlikely(ret != 0)) ++ goto out_no_zone; ++#else ++ ret = ttm_mem_init_dma32_zone(glob, &si); ++ if (unlikely(ret != 0)) ++ goto out_no_zone; ++#endif ++ for (i = 0; i < glob->num_zones; ++i) { ++ zone = glob->zones[i]; ++ printk(KERN_INFO TTM_PFX ++ "Zone %7s: Available graphics memory: %llu kiB.\n", ++ zone->name, (unsigned long long) zone->max_mem >> 10); ++ } + return 0; ++out_no_zone: ++ ttm_mem_global_release(glob); ++ return ret; + } + EXPORT_SYMBOL(ttm_mem_global_init); + + void ttm_mem_global_release(struct ttm_mem_global *glob) + { +- printk(KERN_INFO TTM_PFX "Used total memory is %llu bytes.\n", +- (unsigned long long)glob->used_total_memory); ++ unsigned int i; ++ struct ttm_mem_zone *zone; ++ + flush_workqueue(glob->swap_queue); + destroy_workqueue(glob->swap_queue); + glob->swap_queue = NULL; ++ for (i = 0; i < glob->num_zones; ++i) { ++ zone = glob->zones[i]; ++ kobject_del(&zone->kobj); ++ kobject_put(&zone->kobj); ++ } ++ kobject_del(&glob->kobj); ++ kobject_put(&glob->kobj); + } + EXPORT_SYMBOL(ttm_mem_global_release); + +-static inline void ttm_check_swapping(struct ttm_mem_global *glob) ++static void ttm_check_swapping(struct ttm_mem_global *glob) + { +- bool needs_swapping; ++ bool needs_swapping = false; ++ unsigned int i; ++ struct ttm_mem_zone *zone; + + spin_lock(&glob->lock); +- needs_swapping = (glob->used_memory > glob->swap_limit || +- glob->used_total_memory > +- glob->total_memory_swap_limit); ++ for (i = 0; i < glob->num_zones; ++i) { ++ zone = glob->zones[i]; ++ if (zone->used_mem > zone->swap_limit) { ++ needs_swapping = true; ++ break; ++ } ++ } ++ + spin_unlock(&glob->lock); + + if (unlikely(needs_swapping)) +@@ -153,44 +438,60 @@ static inline void ttm_check_swapping(struct ttm_mem_global *glob) + + } + +-void ttm_mem_global_free(struct ttm_mem_global *glob, +- uint64_t amount, bool himem) ++static void ttm_mem_global_free_zone(struct ttm_mem_global *glob, ++ struct ttm_mem_zone *single_zone, ++ uint64_t amount) + { ++ unsigned int i; ++ struct ttm_mem_zone *zone; ++ + spin_lock(&glob->lock); +- glob->used_total_memory -= amount; +- if (!himem) +- glob->used_memory -= amount; +- wake_up_all(&glob->queue); ++ for (i = 0; i < glob->num_zones; ++i) { ++ zone = glob->zones[i]; ++ if (single_zone && zone != single_zone) ++ continue; ++ zone->used_mem -= amount; ++ } + spin_unlock(&glob->lock); + } + ++void ttm_mem_global_free(struct ttm_mem_global *glob, ++ uint64_t amount) ++{ ++ return ttm_mem_global_free_zone(glob, NULL, amount); ++} ++ + static int ttm_mem_global_reserve(struct ttm_mem_global *glob, +- uint64_t amount, bool himem, bool reserve) ++ struct ttm_mem_zone *single_zone, ++ uint64_t amount, bool reserve) + { + uint64_t limit; +- uint64_t lomem_limit; + int ret = -ENOMEM; ++ unsigned int i; ++ struct ttm_mem_zone *zone; + + spin_lock(&glob->lock); ++ for (i = 0; i < glob->num_zones; ++i) { ++ zone = glob->zones[i]; ++ if (single_zone && zone != single_zone) ++ continue; + +- if (capable(CAP_SYS_ADMIN)) { +- limit = glob->emer_total_memory; +- lomem_limit = glob->emer_memory; +- } else { +- limit = glob->max_total_memory; +- lomem_limit = glob->max_memory; +- } ++ limit = (capable(CAP_SYS_ADMIN)) ? ++ zone->emer_mem : zone->max_mem; + +- if (unlikely(glob->used_total_memory + amount > limit)) +- goto out_unlock; +- if (unlikely(!himem && glob->used_memory + amount > lomem_limit)) +- goto out_unlock; ++ if (zone->used_mem > limit) ++ goto out_unlock; ++ } + + if (reserve) { +- glob->used_total_memory += amount; +- if (!himem) +- glob->used_memory += amount; ++ for (i = 0; i < glob->num_zones; ++i) { ++ zone = glob->zones[i]; ++ if (single_zone && zone != single_zone) ++ continue; ++ zone->used_mem += amount; ++ } + } ++ + ret = 0; + out_unlock: + spin_unlock(&glob->lock); +@@ -199,12 +500,17 @@ out_unlock: + return ret; + } + +-int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, +- bool no_wait, bool interruptible, bool himem) ++ ++static int ttm_mem_global_alloc_zone(struct ttm_mem_global *glob, ++ struct ttm_mem_zone *single_zone, ++ uint64_t memory, ++ bool no_wait, bool interruptible) + { + int count = TTM_MEMORY_ALLOC_RETRIES; + +- while (unlikely(ttm_mem_global_reserve(glob, memory, himem, true) ++ while (unlikely(ttm_mem_global_reserve(glob, ++ single_zone, ++ memory, true) + != 0)) { + if (no_wait) + return -ENOMEM; +@@ -216,6 +522,56 @@ int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, + return 0; + } + ++int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, ++ bool no_wait, bool interruptible) ++{ ++ /** ++ * Normal allocations of kernel memory are registered in ++ * all zones. ++ */ ++ ++ return ttm_mem_global_alloc_zone(glob, NULL, memory, no_wait, ++ interruptible); ++} ++ ++int ttm_mem_global_alloc_page(struct ttm_mem_global *glob, ++ struct page *page, ++ bool no_wait, bool interruptible) ++{ ++ ++ struct ttm_mem_zone *zone = NULL; ++ ++ /** ++ * Page allocations may be registed in a single zone ++ * only if highmem or !dma32. ++ */ ++ ++#ifdef CONFIG_HIGHMEM ++ if (PageHighMem(page) && glob->zone_highmem != NULL) ++ zone = glob->zone_highmem; ++#else ++ if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL) ++ zone = glob->zone_kernel; ++#endif ++ return ttm_mem_global_alloc_zone(glob, zone, PAGE_SIZE, no_wait, ++ interruptible); ++} ++ ++void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page) ++{ ++ struct ttm_mem_zone *zone = NULL; ++ ++#ifdef CONFIG_HIGHMEM ++ if (PageHighMem(page) && glob->zone_highmem != NULL) ++ zone = glob->zone_highmem; ++#else ++ if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL) ++ zone = glob->zone_kernel; ++#endif ++ ttm_mem_global_free_zone(glob, zone, PAGE_SIZE); ++} ++ ++ + size_t ttm_round_pot(size_t size) + { + if ((size & (size - 1)) == 0) +diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c +index 59ce819..9a6edbf 100644 +--- a/drivers/gpu/drm/ttm/ttm_module.c ++++ b/drivers/gpu/drm/ttm/ttm_module.c +@@ -29,16 +29,72 @@ + * Jerome Glisse + */ + #include <linux/module.h> +-#include <ttm/ttm_module.h> ++#include <linux/device.h> ++#include <linux/sched.h> ++#include "ttm/ttm_module.h" ++#include "drm_sysfs.h" ++ ++static DECLARE_WAIT_QUEUE_HEAD(exit_q); ++atomic_t device_released; ++ ++static struct device_type ttm_drm_class_type = { ++ .name = "ttm", ++ /** ++ * Add pm ops here. ++ */ ++}; ++ ++static void ttm_drm_class_device_release(struct device *dev) ++{ ++ atomic_set(&device_released, 1); ++ wake_up_all(&exit_q); ++} ++ ++static struct device ttm_drm_class_device = { ++ .type = &ttm_drm_class_type, ++ .release = &ttm_drm_class_device_release ++}; ++ ++struct kobject *ttm_get_kobj(void) ++{ ++ struct kobject *kobj = &ttm_drm_class_device.kobj; ++ BUG_ON(kobj == NULL); ++ return kobj; ++} + + static int __init ttm_init(void) + { ++ int ret; ++ ++ ret = dev_set_name(&ttm_drm_class_device, "ttm"); ++ if (unlikely(ret != 0)) ++ return ret; ++ + ttm_global_init(); ++ ++ atomic_set(&device_released, 0); ++ ret = drm_class_device_register(&ttm_drm_class_device); ++ if (unlikely(ret != 0)) ++ goto out_no_dev_reg; ++ + return 0; ++out_no_dev_reg: ++ atomic_set(&device_released, 1); ++ wake_up_all(&exit_q); ++ ttm_global_release(); ++ return ret; + } + + static void __exit ttm_exit(void) + { ++ drm_class_device_unregister(&ttm_drm_class_device); ++ ++ /** ++ * Refuse to unload until the TTM device is released. ++ * Not sure this is 100% needed. ++ */ ++ ++ wait_event(exit_q, atomic_read(&device_released) == 1); + ttm_global_release(); + } + +diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c +index b8b6c4a..a55ee1a 100644 +--- a/drivers/gpu/drm/ttm/ttm_tt.c ++++ b/drivers/gpu/drm/ttm/ttm_tt.c +@@ -34,76 +34,13 @@ + #include <linux/pagemap.h> + #include <linux/file.h> + #include <linux/swap.h> ++#include "drm_cache.h" + #include "ttm/ttm_module.h" + #include "ttm/ttm_bo_driver.h" + #include "ttm/ttm_placement.h" + + static int ttm_tt_swapin(struct ttm_tt *ttm); + +-#if defined(CONFIG_X86) +-static void ttm_tt_clflush_page(struct page *page) +-{ +- uint8_t *page_virtual; +- unsigned int i; +- +- if (unlikely(page == NULL)) +- return; +- +- page_virtual = kmap_atomic(page, KM_USER0); +- +- for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size) +- clflush(page_virtual + i); +- +- kunmap_atomic(page_virtual, KM_USER0); +-} +- +-static void ttm_tt_cache_flush_clflush(struct page *pages[], +- unsigned long num_pages) +-{ +- unsigned long i; +- +- mb(); +- for (i = 0; i < num_pages; ++i) +- ttm_tt_clflush_page(*pages++); +- mb(); +-} +-#elif !defined(__powerpc__) +-static void ttm_tt_ipi_handler(void *null) +-{ +- ; +-} +-#endif +- +-void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages) +-{ +- +-#if defined(CONFIG_X86) +- if (cpu_has_clflush) { +- ttm_tt_cache_flush_clflush(pages, num_pages); +- return; +- } +-#elif defined(__powerpc__) +- unsigned long i; +- +- for (i = 0; i < num_pages; ++i) { +- struct page *page = pages[i]; +- void *page_virtual; +- +- if (unlikely(page == NULL)) +- continue; +- +- page_virtual = kmap_atomic(page, KM_USER0); +- flush_dcache_range((unsigned long) page_virtual, +- (unsigned long) page_virtual + PAGE_SIZE); +- kunmap_atomic(page_virtual, KM_USER0); +- } +-#else +- if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0) +- printk(KERN_ERR TTM_PFX +- "Timed out waiting for drm cache flush.\n"); +-#endif +-} +- + /** + * Allocates storage for pointers to the pages that back the ttm. + * +@@ -179,7 +116,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm) + set_page_dirty_lock(page); + + ttm->pages[i] = NULL; +- ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, false); ++ ttm_mem_global_free(ttm->glob->mem_glob, PAGE_SIZE); + put_page(page); + } + ttm->state = tt_unpopulated; +@@ -190,8 +127,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm) + static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) + { + struct page *p; +- struct ttm_bo_device *bdev = ttm->bdev; +- struct ttm_mem_global *mem_glob = bdev->mem_glob; ++ struct ttm_mem_global *mem_glob = ttm->glob->mem_glob; + int ret; + + while (NULL == (p = ttm->pages[index])) { +@@ -200,21 +136,14 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) + if (!p) + return NULL; + +- if (PageHighMem(p)) { +- ret = +- ttm_mem_global_alloc(mem_glob, PAGE_SIZE, +- false, false, true); +- if (unlikely(ret != 0)) +- goto out_err; ++ ret = ttm_mem_global_alloc_page(mem_glob, p, false, false); ++ if (unlikely(ret != 0)) ++ goto out_err; ++ ++ if (PageHighMem(p)) + ttm->pages[--ttm->first_himem_page] = p; +- } else { +- ret = +- ttm_mem_global_alloc(mem_glob, PAGE_SIZE, +- false, false, false); +- if (unlikely(ret != 0)) +- goto out_err; ++ else + ttm->pages[++ttm->last_lomem_page] = p; +- } + } + return p; + out_err: +@@ -310,7 +239,7 @@ static int ttm_tt_set_caching(struct ttm_tt *ttm, + } + + if (ttm->caching_state == tt_cached) +- ttm_tt_cache_flush(ttm->pages, ttm->num_pages); ++ drm_clflush_pages(ttm->pages, ttm->num_pages); + + for (i = 0; i < ttm->num_pages; ++i) { + cur_page = ttm->pages[i]; +@@ -368,8 +297,8 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm) + printk(KERN_ERR TTM_PFX + "Erroneous page count. " + "Leaking pages.\n"); +- ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, +- PageHighMem(cur_page)); ++ ttm_mem_global_free_page(ttm->glob->mem_glob, ++ cur_page); + __free_page(cur_page); + } + } +@@ -414,7 +343,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, + struct mm_struct *mm = tsk->mm; + int ret; + int write = (ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0; +- struct ttm_mem_global *mem_glob = ttm->bdev->mem_glob; ++ struct ttm_mem_global *mem_glob = ttm->glob->mem_glob; + + BUG_ON(num_pages != ttm->num_pages); + BUG_ON((ttm->page_flags & TTM_PAGE_FLAG_USER) == 0); +@@ -424,7 +353,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, + */ + + ret = ttm_mem_global_alloc(mem_glob, num_pages * PAGE_SIZE, +- false, false, false); ++ false, false); + if (unlikely(ret != 0)) + return ret; + +@@ -435,7 +364,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, + + if (ret != num_pages && write) { + ttm_tt_free_user_pages(ttm); +- ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE, false); ++ ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE); + return -ENOMEM; + } + +@@ -459,8 +388,7 @@ struct ttm_tt *ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, + if (!ttm) + return NULL; + +- ttm->bdev = bdev; +- ++ ttm->glob = bdev->glob; + ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; + ttm->first_himem_page = ttm->num_pages; + ttm->last_lomem_page = -1; +diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c +index a85c818..750c71f 100644 +--- a/drivers/video/fbmem.c ++++ b/drivers/video/fbmem.c +@@ -1789,7 +1789,7 @@ static int __init video_setup(char *options) + global = 1; + } + +- if (!global && !strstr(options, "fb:")) { ++ if (!global && !strchr(options, ':')) { + fb_mode_option = options; + global = 1; + } +diff --git a/firmware/Makefile b/firmware/Makefile +index 621de8e..d166a7f 100644 +--- a/firmware/Makefile ++++ b/firmware/Makefile +@@ -42,6 +42,22 @@ fw-shipped-$(CONFIG_COMPUTONE) += intelliport2.bin + fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \ + cxgb3/t3c_psram-1.1.0.bin \ + cxgb3/t3fw-7.4.0.bin ++fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw ++fw-shipped-$(CONFIG_DRM_R128) += r128/r128_cce.bin ++fw-shipped-$(CONFIG_DRM_RADEON) += radeon/R100_cp.bin radeon/R200_cp.bin \ ++ radeon/R300_cp.bin radeon/R420_cp.bin \ ++ radeon/RS690_cp.bin radeon/RS600_cp.bin \ ++ radeon/R520_cp.bin \ ++ radeon/R600_pfp.bin radeon/R600_me.bin \ ++ radeon/RV610_pfp.bin radeon/RV610_me.bin \ ++ radeon/RV630_pfp.bin radeon/RV630_me.bin \ ++ radeon/RV620_pfp.bin radeon/RV620_me.bin \ ++ radeon/RV635_pfp.bin radeon/RV635_me.bin \ ++ radeon/RV670_pfp.bin radeon/RV670_me.bin \ ++ radeon/RS780_pfp.bin radeon/RS780_me.bin \ ++ radeon/RV770_pfp.bin radeon/RV770_me.bin \ ++ radeon/RV730_pfp.bin radeon/RV730_me.bin \ ++ radeon/RV710_pfp.bin radeon/RV710_me.bin + fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin + fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin + fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \ +diff --git a/firmware/WHENCE b/firmware/WHENCE +index 0f5649a..00378ee 100644 +--- a/firmware/WHENCE ++++ b/firmware/WHENCE +@@ -698,3 +698,124 @@ Found in hex form in kernel source, with the following comment: + Copyright (c) 1998-2002 by Paul Davis <pbd@op.net> + + -------------------------------------------------------------------------- ++ ++Driver: mga - Matrox G200/G400/G550 ++ ++File: matrox/g200_warp.fw ++File: matrox/g400_warp.fw ++ ++Licence: ++ ++Copyright 1999 Matrox Graphics Inc. ++All Rights Reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining a ++copy of this software and associated documentation files (the "Software"), ++to deal in the Software without restriction, including without limitation ++the rights to use, copy, modify, merge, publish, distribute, sublicense, ++and/or sell copies of the Software, and to permit persons to whom the ++Software is furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included ++in all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, ++DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR ++OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ ++Found in hex form in kernel source. ++ ++-------------------------------------------------------------------------- ++ ++Driver: r128 - ATI Rage 128 ++ ++File: r128/r128_cce.bin ++ ++Licence: ++ ++Copyright 2000 Advanced Micro Devices, Inc. ++ ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ ++Found in decimal form in kernel source. ++ ++-------------------------------------------------------------------------- ++ ++Driver: radeon - ATI Radeon ++ ++File: radeon/R100_cp.bin ++File: radeon/R200_cp.bin ++File: radeon/R300_cp.bin ++File: radeon/R420_cp.bin ++File: radeon/RS600_cp.bin ++File: radeon/RS690_cp.bin ++File: radeon/R520_cp.bin ++File: radeon/R600_pfp.bin ++File: radeon/R600_me.bin ++File: radeon/RV610_pfp.bin ++File: radeon/RV610_me.bin ++File: radeon/RV630_pfp.bin ++File: radeon/RV630_me.bin ++File: radeon/RV620_pfp.bin ++File: radeon/RV620_me.bin ++File: radeon/RV635_pfp.bin ++File: radeon/RV635_me.bin ++File: radeon/RV670_pfp.bin ++File: radeon/RV670_me.bin ++File: radeon/RS780_pfp.bin ++File: radeon/RS780_me.bin ++File: radeon/RV770_pfp.bin ++File: radeon/RV770_me.bin ++File: radeon/RV730_pfp.bin ++File: radeon/RV730_me.bin ++File: radeon/RV710_pfp.bin ++File: radeon/RV710_me.bin ++ ++Licence: ++ ++ * Copyright 2007-2009 Advanced Micro Devices, Inc. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE ++ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION ++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ ++Found in hex form in kernel source. ++ ++-------------------------------------------------------------------------- +diff --git a/firmware/matrox/g200_warp.H16 b/firmware/matrox/g200_warp.H16 +new file mode 100644 +index 0000000..5064b6f +--- /dev/null ++++ b/firmware/matrox/g200_warp.H16 +@@ -0,0 +1,28 @@ ++/* ++ * WARP pipes are named according to the functions they perform, where ++ * ++ * - T stands for computation of texture stage 0 ++ * - T2 stands for computation of both texture stage 0 and texture stage 1 ++ * - G stands for computation of triangle intensity (Gouraud interpolation) ++ * - Z stands for computation of Z buffer interpolation ++ * - S stands for computation of specular highlight ++ * - A stands for computation of the alpha channel ++ * - F stands for computation of vertex fog interpolation ++ */ ++/* TGZ */ ++:04B8000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9728007EA241F20E9154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2608015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E803800AEA17C12BBD008000E8008000E8B3689725008000E833C033AF3C274FE9573920E9281960EC2B3220E91D3B20E9B30500E0162820E9233B33AD1E2B20E91C8020E9573620E90080A0E94040D8ECFF80C0E990E200E085FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E884FF0AEA008000E8C941C8EC42E100E082FF20EA008000E8008000E8008000E8C840C0EC008000E87FFF20EA008000E8008000E8008000E871 ++/* TGZF */ ++:0548000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E97F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E80D211AB6052131B603802AEA17C12BBD0D2005202FC021C6B3689725008000E833C033AF3C274FE91750569F008000E8370F5C9F00E02F20008000E8281960ECB30500E0008000E8233B33AD008000E8172617DF35174FE9008000E8008000E8008000E839374FE92F2F17AF008000E8008000E8008000E831804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E078FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E877FF0AEA008000E8C941C8EC42E100E075FF20EA008000E8008000E8008000E8C840C0EC008000E872FF20EA008000E8008000E8008000E8BB ++/* TGZA */ ++:04E80000000098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E97D8007EA241F20E9154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D444CB6254454B603802AEA17C12BBD2D20252007C044C6B3689725008000E833C033AF3C274FE91F62579F008000E83F3D5D9F00E00720008000E8281960ECB30500E0008000E8233B33AD008000E81F261FDF9D1F4FE9008000E8008000E8008000E89E3F4FE907071FAF008000E8008000E8008000E89C804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E07AFF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E879FF0AEA008000E8C941C8EC42E100E077FF20EA008000E8008000E8008000E8C840C0EC008000E874FF20EA008000E8008000E8008000E8D9 ++/* TGZAF */ ++:0568000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9838007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26F8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E80D211AB6052131B62D444CB6254454B603802AEA17C12BBD0D2005202FC021C6B3689725008000E833C033AF3C274FE900E0252007C044C61750569F00E02D20370F5C9F00E02F201F62579F00E007203F3D5D9F008000E8008000E8281960ECB30500E0172617DF233B33AD35174FE91F261FDF9D1F4FE99E3F4FE939374FE92F2F17AF008000E807071FAF008000E831804FE9008000E89C804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E074FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E873FF0AEA008000E8C941C8EC42E100E071FF20EA008000E8008000E8008000E8C840C0EC008000E86EFF20EA008000E8008000E8008000E830 ++/* TGZS */ ++:05C0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98B8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2778015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F3F2F5D9F00E08F20A5374FE90F170FAF06C021C4008000E8008000E8A3804FE9062000E01F261FDFA11F4FE9A23F4FE9008000E8008000E806061FAF008000E8008000E8008000E8A0804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E06CFF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E86BFF0AEA008000E8C941C8EC42E100E069FF20EA008000E8008000E8008000E8C840C0EC008000E866FF20EA008000E8008000E8008000E85C ++/* TGZSF */ ++:05E0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E27B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D211AB6052131B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D2005202FC021C63F2F5D9F00E00F201750569FA5374FE906C021C40F170FAF370F5C9F008000E82F2000E0A3804FE9062000E01F261FDF172617DF35174FE9A11F4FE9A23F4FE906061FAF39374FE92F2F17AF008000E8A0804FE9008000E831804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E068FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E867FF0AEA008000E8C941C8EC42E100E065FF20EA008000E8008000E8008000E8C840C0EC008000E862FF20EA008000E8008000E8008000E8F9 ++/* TGZSA */ ++:05E0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E27B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D444CB6054454B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D200520008000E83F2F5D9F00E00F201750569FA5374FE906C021C40F170FAF370F5C9F008000E82FC044C6A3804FE9062000E01F261FDF172617DF9D174FE9A11F4FE9A23F4FE906061FAF00E0AF209E374FE92F172FAFA0804FE9008000E8008000E89C804FE9008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E068FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E867FF0AEA008000E8C941C8EC42E100E065FF20EA008000E8008000E8008000E8C840C0EC008000E862FF20EA008000E8008000E8008000E883 ++/* TGZAF */ ++:05B8000000008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9948007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2808015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D211AB6052131B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D2005202FC021C62D444CB6254454B63F2F5D9F00E00F202D20252007C044C61750569FA5374FE906C021C40F170FAF370F5C9F008000E81E62579F008000E83E3D5D9F00E007202F2000E0A30F4FE9062000E01F261FDF172617DFA11F4FE91E261EDF9D1E4FE935174FE9A23F4FE906061FAF39374FE92F2F17AF07071EAFA0804FE99E3E4FE931804FE99C804FE9008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E063FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E862FF0AEA008000E8C941C8EC42E100E060FF20EA008000E8008000E8008000E8C840C0EC008000E85DFF20EA008000E8008000E8008000E8D8 ++:0000000001FF +diff --git a/firmware/matrox/g400_warp.H16 b/firmware/matrox/g400_warp.H16 +new file mode 100644 +index 0000000..b432d10 +--- /dev/null ++++ b/firmware/matrox/g400_warp.H16 +@@ -0,0 +1,44 @@ ++/* ++ * WARP pipes are named according to the functions they perform, where ++ * ++ * - T stands for computation of texture stage 0 ++ * - T2 stands for computation of both texture stage 0 and texture stage 1 ++ * - G stands for computation of triangle intensity (Gouraud interpolation) ++ * - Z stands for computation of Z buffer interpolation ++ * - S stands for computation of specular highlight ++ * - A stands for computation of the alpha channel ++ * - F stands for computation of vertex fog interpolation ++ */ ++/* TGZ */ ++:0338000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900588015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4A8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A444CB0024454B02A444CB21A4454B21D803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F008000E82A444CB41A4454B439E52C9F383D20E988735EE92A201A202A464EBF1A4656BF31532F9F3E304FE939E52C9F3F384FE90A474FBF024757BF31532F9F3A314FE939E52C9F3B394FE92A434BBF1A4353BF30502E9F36314FE938212C9F37394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9AFFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD6FF20EA008000E84E334ECF573B57CF9DFF20EA57C0BFEA0080A0E90000D8EC59 ++/* TGZF */ ++:0360000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039005D8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4F8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C439E52C9F348020E931532F9F008000E888735EE9008000E827CF75C63C3D20E90A444CB0024454B02A444CB21A4454B220803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F312720E90A444CB4024454B42A454DB61A4555B639E52C9F383D20E90A2002202A201A200A474FBF024757BF30502E9F3E304FE938212C9F3F384FE92A464EBF1A4656BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A434BBF1A4353BF30502E9F35314FE938212C9F39394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9AAFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD3FF20EA008000E84E334ECF573B57CF98FF20EA57C0BFEA0080A0E90000D8EC90 ++/* TGZA */ ++:0358000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039005C8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4E8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E927CF74C63DCF74C20A444CB0024454B02A444CB21A4454B220803AEA0A20022088735EE92A201A2030502E9F32315FE938212C9F33395FE931532F9F9C2720E90A444CB4024454B42A444CB61A4454B639E52C9F383D20E90A2002202A201A200A474FBF024757BF30502E9F3E304FE938212C9F3F384FE92A464EBF1A4656BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A434BBF1A4353BF30502E9F9D314FE938212C9F9E394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9ABFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD3FF20EA008000E84E334ECF573B57CF99FF20EA57C0BFEA0080A0E90000D8EC35 ++/* TGZAF */ ++:0380000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900618015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF538007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C40A444CB0024454B031532F9F343720E939E52C9F3C3D20E92A444CB21A4454B226803AEA0A20022088735EE92A201A203DCF74C227CF74C630502E9F32315FE938212C9F33395FE931532F9F9C2720E90A444CB4024454B42A444CB61A4454B639E52C9F383D20E90A2002202A201A203DCF75C6008000E830502E9F3E304FE938212C9F3F384FE90A454DB6024555B631532F9F3A314FE939E52C9F3B394FE9313D20E90A2002202A464EBF1A4656BF0A474FBF024757BF30502E9F36304FE938212C9F37384FE931532F9F9D314FE939E52C9F9E394FE92A434BBF1A4353BF30502E9F35304FE938212C9F39384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9A6FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFCDFF20EA008000E84E334ECF573B57CF94FF20EA57C0BFEA0080A0E90000D8EC89 ++/* TGZS */ ++:03A0000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900658015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF578007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B229803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE92A454DB21A4555B20A454DB4024555B438212C9F3B394FE90A2002202A201A202A464EBF1A4656BF31532F9F36314FE939E52C9F37394FE930502E9FA7304FE938212C9FA8384FE90A474FBF024757BF31532F9FA4314FE939E52C9FA5394FE92A434BBF1A4353BF30502E9FA1304FE938212C9FA2384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9A2FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFCAFF20EA008000E84E334ECF573B57CF90FF20EA57C0BFEA0080A0E90000D8ECD8 ++/* TGZSF */ ++:03C8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006A8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF5C8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B22E803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF75C62A201A20A7304FE90A20022031532F9F312720E939E52C9FA8384FE92A454DB61A4555B630502E9F36314FE938212C9F37394FE9008000E82A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE90A474FBF024757BF31532F9FA1304FE939E52C9FA2384FE92A434BBF1A4353BF30502E9F35314FE938212C9F39394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E99DFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC5FF20EA008000E84E334ECF573B57CF8BFF20EA57C0BFEA0080A0E90000D8ECD3 ++/* TGZSA */ ++:03C8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006A8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF5C8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B22E803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF74C62A201A20A7304FE90A20022031532F9F9C2720E939E52C9FA8384FE92A444CB61A4454B630502E9F36314FE938212C9F37394FE9008000E82A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE90A474FBF024757BF31532F9FA1304FE939E52C9FA2384FE92A434BBF1A4353BF30502E9F9D314FE938212C9F9E394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E99DFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC5FF20EA008000E84E334ECF573B57CF8BFF20EA57C0BFEA0080A0E90000D8ECA0 ++/* TGZSAF */ ++:03E8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006E8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF608007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B232803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF74C62A201A20A7304FE90A20022031532F9F9C2720E939E52C9FA8384FE92A444CB61A4454B630502E9F36314FE938212C9F37394FE90A454DB6024555B63DCF75C62A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE9313D20E90A2002200A474FBF024757BF30502E9FA1304FE938212C9FA2384FE931532F9F9D314FE939E52C9F9E394FE92A434BBF1A4353BF30502E9F35304FE938212C9F39384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E999FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC1FF20EA008000E84E334ECF573B57CF87FF20EA57C0BFEA0080A0E90000D8EC83 ++/* T2GZ */ ++:0438000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900788015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF698007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A4454B0024464B02A4454B21A4464B225803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F008000E82A4454B41A4464B439E52C9F383D20E988735EE92A201A202A4656BF1A4666BF31532F9F3E304FE939E52C9F3F384FE90A4757BF024767BF31532F9F3A314FE939E52C9F3B394FE92A4353BF1A4363BF30502E9F36314FE938212C9F37394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99FFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBEFF20EA008000E8583358CF693B69CF7DFF20EA57C0BFEA0080A0E90000D8ECAC ++/* T2GZF */ ++:0460000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039007D8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF6E8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C439E52C9F348020E931532F9F008000E888735EE9008000E80FCF75C63C3D20E90A4454B0024464B02A4454B21A4464B228803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F310F20E90A4454B4024464B42A4555B61A4565B639E52C9F383D20E90A2002202A201A200A4757BF024767BF30502E9F3E304FE938212C9F3F384FE92A4656BF1A4666BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A4353BF1A4363BF30502E9F35314FE938212C9F39394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99AFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBBFF20EA008000E8583358CF693B69CF78FF20EA57C0BFEA0080A0E90000D8ECFB ++/* T2GZA */ ++:0458000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039007C8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF6D8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A4454B0024464B02A4454B21A4464B229803AEA0A2002200FCF74C63DCF74C288735EE92A201A2030502E9F32315FE938212C9F33395FE931532F9F9C0F20E90A4454B4024464B42A4454B61A4464B639E52C9F383D20E90A2002202A201A200A4757BF024767BF30502E9F3E304FE938212C9F3F384FE92A4656BF1A4666BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A4353BF1A4363BF30502E9F9D314FE938212C9F9E394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99BFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBAFF20EA008000E8583358CF693B69CF79FF20EA57C0BFEA0080A0E90000D8ECA0 ++/* T2GZAF */ ++:0480000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900818015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF728007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C40A4454B0024464B031532F9F343720E939E52C9F3C3D20E92A4454B21A4464B22E803AEA0A20022088735EE92A201A203DCF74C20FCF74C630502E9F32315FE938212C9F33395FE931532F9F9C0F20E90A4454B4024464B42A4454B61A4464B639E52C9F383D20E90A2002202A201A203DCF75C6008000E830502E9F3E304FE938212C9F3F384FE90A4555B6024565B631532F9F3A314FE939E52C9F3B394FE9313D20E90A2002202A4656BF1A4666BF0A4757BF024767BF30502E9F36304FE938212C9F37384FE931532F9F9D314FE939E52C9F9E394FE92A4353BF1A4363BF30502E9F35304FE938212C9F39384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E996FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFB5FF20EA008000E8583358CF693B69CF74FF20EA57C0BFEA0080A0E90000D8ECDC ++/* T2GZS */ ++:04A0000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900858015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF768007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B231803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE92A4555B21A4565B20A4555B4024565B438212C9F3B394FE92A201A200A2002202A4656BF1A4666BF31532F9F36314FE939E52C9F37394FE930502E9FA7304FE938212C9FA8384FE90A4757BF024767BF31532F9FA4314FE939E52C9FA5394FE92A4353BF1A4363BF30502E9FA1304FE938212C9FA2384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E992FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFB2FF20EA008000E8583358CF693B69CF70FF20EA57C0BFEA0080A0E90000D8EC43 ++/* T2GZSF */ ++:04C8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008A8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7B8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B236803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF75C62A201A20A7304FE90A20022031532F9F310F20E939E52C9FA8384FE92A4555B61A4565B630502E9F36314FE938212C9F37394FE9008000E82A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE90A4757BF024767BF31532F9FA1304FE939E52C9FA2384FE92A4353BF1A4363BF30502E9F35314FE938212C9F39394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E98DFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFADFF20EA008000E8583358CF693B69CF6BFF20EA57C0BFEA0080A0E90000D8EC56 ++/* T2GZSA */ ++:04C8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008A8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7B8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B236803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF74C62A201A20A7304FE90A20022031532F9F9C0F20E939E52C9FA8384FE92A4454B61A4464B630502E9F36314FE938212C9F37394FE9008000E82A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE90A4757BF024767BF31532F9FA1304FE939E52C9FA2384FE92A4353BF1A4363BF30502E9F9D314FE938212C9F9E394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E98DFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFADFF20EA008000E8583358CF693B69CF6BFF20EA57C0BFEA0080A0E90000D8EC23 ++/* T2GZSAF */ ++:04E8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008E8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7F8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B23A803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF74C62A201A20A7304FE90A20022031532F9F9C0F20E939E52C9FA8384FE92A4454B61A4464B630502E9F36314FE938212C9F37394FE90A4555B6024565B63DCF75C62A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE9313D20E90A2002200A4757BF024767BF30502E9FA1304FE938212C9FA2384FE931532F9F9D314FE939E52C9F9E394FE92A4353BF1A4363BF30502E9F35304FE938212C9F39384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E989FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFA9FF20EA008000E8583358CF693B69CF67FF20EA57C0BFEA0080A0E90000D8ECEE ++:0000000001FF +diff --git a/firmware/r128/r128_cce.bin.ihex b/firmware/r128/r128_cce.bin.ihex +new file mode 100644 +index 0000000..4831315 +--- /dev/null ++++ b/firmware/r128/r128_cce.bin.ihex +@@ -0,0 +1,129 @@ ++:1000000000000000108038000000000010003800E0 ++:10001000000000020000008E0000000200000091BD ++:1000200000000000402E2423000000006062124FF8 ++:10003000000000002E2B596D000000007677753E01 ++:1000400000000000898984820000000023BC8B0D21 ++:10005000000000002323232300000000238DABB405 ++:1000600000000000232323230000000100B028002B ++:100070000000000100032800000000010004C0008F ++:100080000000000100030800000000023660300E8E ++:100090000000000B00040000000000000000000051 ++:1000A000000000010200151D0000000100001D0EEF ++:1000B00000000001000039D900000001000019D73C ++:1000C0000000000C0000001C00000001000019D618 ++:1000D0000000000C0000001C0000000200000017DF ++:1000E0000000000B01200000000000000100358A24 ++:1000F0000000000100064000000000090000001E92 ++:100100000000000108D015B4000000101910100004 ++:100110000000000300002000000000000000280094 ++:1001200000000001000308000000000100003D0E77 ++:10013000000000010000C8000000000A0000882A3A ++:10014000000000090000002A000000010200150F55 ++:1001500000000002000028240000000100003D65AE ++:100160000000000100003D66000000020000002BBE ++:100170000000000100F32DB4000000012200D8BFF0 ++:100180000000000100E088BF0000000C1333383786 ++:1001900000000001020615650000000C0000003799 ++:1001A00000000001020015640000000100003D662F ++:1001B000000000020000002E000000040020083AA9 ++:1001C0000000000100080800000000010006C0FF58 ++:1001D000000000040040003D000000010007C800CE ++:1001E00000000001000700FF000000030000000005 ++:1001F0000000000C0000005C000000020000002E67 ++:100200000000000C000000B00000000100003D767E ++:100210000000000100032800000000010000480069 ++:1002200000000001000208000000000106001D0E91 ++:1002300000000001000248000000000100028800E8 ++:100240000000000100F3C5F80000000100100000EC ++:10025000000000060030004E0000000100003D6379 ++:100260000000001080303DF0000000021000384314 ++:1002700000000002000028430000000C000000B055 ++:100280000000000100003D760000000100003D7705 ++:100290000000000100003D0E0000000100003D0FC5 ++:1002A000000000010050280000000006003000524D ++:1002B0000000001080303DF00000000100003DF81B ++:1002C00000000002000000520000000100053D0E89 ++:1002D0000000000100103D0F00000002003000553A ++:1002E0000000000100003D700000000100001E89B8 ++:1002F0000000000100003D710000000300003D729D ++:100300000000000C0000005C000000020000006221 ++:100310000000000100003F280000000100003F270E ++:100320000000000100003E820000000100003E8845 ++:100330000000000100003E660000000100003E6772 ++:100340000000000100003E760000000100003E6851 ++:100350000000000100003E690000000100003E6C4A ++:100360000000000000003E6D0000000100002800B9 ++:1003700000000001005028000000000100003D685E ++:100380000000000100030800000000060000006EED ++:10039000000000010002C0000000000106303D62C4 ++:1003A0000000000200000070000000020030006F3A ++:1003B00000000000200038C0000000010001C0C0A3 ++:1003C0000000000E0000007D0000000C0003287FEC ++:1003D00000000001020015BB0000000C00030880B3 ++:1003E0000000000002003DBC0000000100003DBB19 ++:1003F0000000000000003DBC00000003000480007D ++:100400000000000100048000000000030006C0029C ++:100410000000000100B0280000000000306038003B ++:100420000000000100C028000000000100B008002A ++:100430000000000100D600000000000712801086B6 ++:10044000000000000000280000000001000039CC7E ++:1004500000000001000039CD00000001000039C992 ++:1004600000000001000039CA00000000000039CB84 ++:10047000000000011003B80000000001009000001F ++:100480000000000110003800000000010003080017 ++:100490000000000100903D1B0000000140203D0ACB ++:1004A0000000000140203D0B00000001000880001A ++:1004B000000000010001C0C00000000E0000009F0D ++:1004C0000000000C000308800000000142203DBD38 ++:1004D0000000000C0003087F0000000142003DBB4B ++:1004E0000000000C000308800000000142203DBC19 ++:1004F00000000002000000A20000000140203DBDFD ++:100500000000000140003DBB0000000140203DBC58 ++:1005100000000001000840000000000100A00000F1 ++:1005200000000006003000A6000000101060380037 ++:1005300000000009000000A80000000300400000C7 ++:100540000000000300403D1D00000000000000000E ++:1005500000000000000001000000000E000000AEDE ++:10056000000000010001C0A900000001020015C741 ++:100570000000000C000000B0000000000000280097 ++:10058000000000010001C0AA00000001020015D215 ++:10059000000000010001C0A900000003020015C70F ++:1005A0000000000100003E88000000010001C0BA08 ++:1005B0000000000102001728000000010001C0BB7C ++:1005C000000000010200165A0000000000003E5B1F ++:1005D000000000000000010000000000000010000A ++:1005E000000000010006400B00000009000000BCF4 ++:1005F00000000000000028000000000000000000D3 ++:1006000000000000000000000000000000000000EA ++:1006100000000000000000000000000000000000DA ++:1006200000000000000000000000000000000000CA ++:1006300000000000000000000000000000000000BA ++:1006400000000000000000000000000000000000AA ++:10065000000000000000000000000000000000009A ++:10066000000000000000000000000000000000008A ++:10067000000000000000000000000000000000007A ++:10068000000000000000000000000000000000006A ++:10069000000000000000000000000000000000005A ++:1006A000000000000000000000000000000000004A ++:1006B000000000000000000000000000000000003A ++:1006C000000000000000000000000000000000002A ++:1006D000000000000000000000000000000000001A ++:1006E000000000000000000000000000000000000A ++:1006F00000000000000000000000000000000000FA ++:1007000000000000000000000000000000000000E9 ++:1007100000000000000000000000000000000000D9 ++:1007200000000000000000000000000000000000C9 ++:1007300000000000000000000000000000000000B9 ++:1007400000000000000000000000000000000000A9 ++:100750000000000000000000000000000000000099 ++:100760000000000000000000000000000000000089 ++:100770000000000000000000000000000000000079 ++:100780000000000000000000000000000000000069 ++:100790000000000000000000000000000000000059 ++:1007A0000000000000000000000000000000000049 ++:1007B0000000000000000000000000000000000039 ++:1007C0000000000000000000000000000000000029 ++:1007D0000000000000000000000000000000000019 ++:1007E0000000000000000000000000000000000009 ++:1007F00000000000000000000000000000000000F9 ++:00000001FF +diff --git a/firmware/radeon/R100_cp.bin.ihex b/firmware/radeon/R100_cp.bin.ihex +new file mode 100644 +index 0000000..151647b +--- /dev/null ++++ b/firmware/radeon/R100_cp.bin.ihex +@@ -0,0 +1,130 @@ ++:1000000000000000210070000000000020007000CF ++:1000100000000004000000B400000004000000B86C ++:10002000000000006F5B4D4C000000004C4C427F14 ++:10003000000000005B568A92000000004CA09C6DFE ++:1000400000000000AD4C4C4C000000004CE1AF3D06 ++:1000500000000000D8AFAFAF00000000D64C4CDC71 ++:10006000000000004CD10D1000000016000F000031 ++:1000700000000000362F242D0000000400000012B4 ++:1000800000000016000F000000000000362F282D91 ++:1000900000000002000380E70000000204002C972B ++:1000A00000000016000F000100000000333A373056 ++:1000B00000000002000077EF0000000200061000C0 ++:1000C0000000001A000000210000001E0000400097 ++:1000D00000000002000610000000001A00000021CD ++:1000E0000000001E0000400000000002000610009A ++:1000F0000000001A000000210000001E0000400067 ++:100100000000000400000017000000020003802B24 ++:1001100000000002040067E0000000040000001777 ++:1001200000000002000077E000000002000650001E ++:1001300000000002000037E100000006040067E153 ++:1001400000000002000077E000000002000077E1FC ++:1001500000000006000077E100000000FFFFFFFF45 ++:100160000000000010000000000000020003802BCF ++:1001700000000006040067E0000000020000767541 ++:100180000000000200007676000000020000767792 ++:100190000000000600007678000000020003802CBA ++:1001A00000000002040026760000000200007677BE ++:1001B0000000000600007678000000180000002F04 ++:1001C000000000180000002F0000000600000000E2 ++:1001D000000000180000003000000018000000308F ++:1001E0000000000600000000000000020160500056 ++:1001F000000000020006500000000002000980001C ++:1002000000000002000610000000000464C0603E10 ++:1002100000000002000380E600000002040025C583 ++:1002200000000016000800000000000000000000B0 ++:10023000000000020400251D00000002000075807F ++:100240000000000200067581000000020400258005 ++:100250000000000200067581000000040000004953 ++:10026000000000000000500000000002000380E6D3 ++:1002700000000002040025C5000000020006100076 ++:10028000000000020000750E000000020001900056 ++:10029000000000140001105500000012000000557D ++:1002A000000000020400250F000000040000504F71 ++:1002B00000000002000380E600000002040025C5E3 ++:1002C0000000000200007565000000020000756675 ++:1002D000000000040000005800000002000380E657 ++:1002E00000000002040025C50000000201E655B42C ++:1002F000000000024401B0E40000000201C110E46B ++:10030000000000182666706600000002040C2565D7 ++:1003100000000018000000660000000204002564D0 ++:100320000000000200007566000000040000005D8F ++:1003300000000008004010690000000200101000DA ++:1003400000000002000D80FF000000080080006C2B ++:1003500000000002000F900000000002000E00FFED ++:100360000000000600000000000000180000008FE0 ++:10037000000000040000005B00000002000380E6B3 ++:1003800000000002040025C5000000020000757690 ++:100390000000000200065000000000020000900073 ++:1003A0000000000200041000000000020C00350EE6 ++:1003B0000000000200049000000000020005100090 ++:1003C0000000000201E785F80000000200200000A4 ++:1003D0000000000C0060007E000000020000756359 ++:1003E00000000021006075F0000000042000707320 ++:1003F000000000040000507300000002000380E6CB ++:1004000000000002040025C500000002000075760F ++:100410000000000200007577000000020000750E69 ++:10042000000000020000750F0000000200A0500054 ++:100430000000000C0060008300000021006075F0E7 ++:1004400000000002000075F80000000400000083B6 ++:1004500000000002000A750E00000002000380E6A2 ++:1004600000000002040025C5000000020020750FF6 ++:1004700000000004006000860000000200007570AB ++:100480000000000200007571000000060000757297 ++:1004900000000002000380E600000002040025C501 ++:1004A00000000002000050000000000200A0500008 ++:1004B0000000000200007568000000020006100045 ++:1004C0000000000C00000095000000020005800004 ++:1004D000000000020C60756200000004000000973C ++:1004E00000000002000380E600000002040025C5B1 ++:1004F000000000040060009600000000400070E56D ++:1005000000000002000380E600000002040025C590 ++:1005100000000002000380E50000001C000000A8AD ++:1005200000000018000650AA00000002040025BBCD ++:1005300000000018000610AB00000000040075BCAD ++:1005400000000002000075BB00000000000075BC48 ++:100550000000000600090000000000020009000081 ++:1005600000000006000D800200000002000078324A ++:10057000000000020000500000000002000380E7BD ++:100580000000000204002C97000000020000782008 ++:100590000000000200007821000000000000780048 ++:1005A000000000020120000000000002200770008F ++:1005B0000000000201200000000000022000700086 ++:1005C0000000000200061000000000020120751B60 ++:1005D000000000028040750A000000028040750B98 ++:1005E000000000020011000000000002000380E58E ++:1005F0000000001C000000C600000018000610AB40 ++:1006000000000002844075BD00000018000610AA1A ++:1006100000000002840075BB00000018000610AB4B ++:1006200000000002844075BC00000004000000C906 ++:1006300000000002804075BD00000002800075BB14 ++:1006400000000002804075BC000000020010800025 ++:1006500000000002014000000000000C006000CD1E ++:100660000000002020C0700000000012000000CF39 ++:100670000000000600800000000000060080751DDC ++:100680000000000000000000000000020000775C95 ++:100690000000000200A050000000000200661000F0 ++:1006A000000000200460275D000000000000400002 ++:1006B0000000000201E0083000000000210070008E ++:1006C000000000006464614D00000000696874204F ++:1006D00000000000000000730000000000000000A7 ++:1006E000000000020000500000000002000380D063 ++:1006F00000000002040025E000000000000075E199 ++:10070000000000000000000100000002000380E083 ++:1007100000000002040023940000000000005000CC ++:1007200000000000000000000000000000000000C9 ++:1007300000000000000000080000000000000004AD ++:1007400000000000000000000000000000000000A9 ++:100750000000000000000000000000000000000099 ++:100760000000000000000000000000000000000089 ++:100770000000000000000000000000000000000079 ++:100780000000000000000000000000000000000069 ++:100790000000000000000000000000000000000059 ++:1007A0000000000000000000000000000000000049 ++:1007B0000000000000000000000000000000000039 ++:1007C0000000000000000000000000000000000029 ++:1007D0000000000000000000000000000000000019 ++:1007E0000000000000000000000000000000000009 ++:1007F00000000000000000000000000000000000F9 ++:00000001FF ++/* production radeon ucode r1xx-r6xx */ +diff --git a/firmware/radeon/R200_cp.bin.ihex b/firmware/radeon/R200_cp.bin.ihex +new file mode 100644 +index 0000000..3a0bd73 +--- /dev/null ++++ b/firmware/radeon/R200_cp.bin.ihex +@@ -0,0 +1,130 @@ ++:1000000000000000210070000000000020007000CF ++:1000100000000004000000BF00000004000000C356 ++:10002000000000007A685E5D000000005D5D55889C ++:100030000000000068659197000000005DA19F78B6 ++:10004000000000005D5D5D5D000000005DEE5D5044 ++:1000500000000000F2ACACAC00000000E75DF9E984 ++:1000600000000000B1DD0E1100000000E2AFAFAFF4 ++:1000700000000016000F000000000000452F232D97 ++:10008000000000040000001300000016000F000034 ++:1000900000000000452F272D00000016000F000172 ++:1000A000000000003E4D4A3700000002000077EFDC ++:1000B00000000002000610000000001A00000020EE ++:1000C0000000001E000040000000000200061000BA ++:1000D0000000001A000000200000001E0000400088 ++:1000E00000000002000610000000001A00000020BE ++:1000F0000000001E00004000000000040000001688 ++:10010000000000020003802A00000002040067E0F3 ++:10011000000000040000001600000002000077E06C ++:10012000000000020006500000000002000037E15D ++:1001300000000006040067E100000002000077E014 ++:1001400000000002000077E100000006000077E1F7 ++:1001500000000000FFFFFFFF000000001000000093 ++:100160000000000007F007F0000000020003802AF2 ++:1001700000000006040067E0000000020003802C7D ++:100180000000000204002741000000020400274193 ++:100190000000000204002743000000020000767502 ++:1001A0000000000200007676000000020000767772 ++:1001B0000000000600007678000000020003802C9A ++:1001C0000000000204002741000000020400274153 ++:1001D00000000002040027430000000200007676C1 ++:1001E000000000020000767700000006000076782C ++:1001F000000000020003802B0000000204002676AD ++:100200000000000200007677000000020003802C4E ++:100210000000000204002741000000020400274300 ++:100220000000000600007678000000020003802C29 ++:1002300000000002040027410000000204002741E2 ++:10024000000000020400274300000006000076784A ++:10025000000000180000002F000000180000002F10 ++:100260000000000600000000000000180000003739 ++:100270000000001800000037000000060000000029 ++:100280000000000201605000000000020006500063 ++:1002900000000002000980000000000200061000BB ++:1002A0000000000464C06051000000160008000057 ++:1002B0000000000000000000000000020400251DF6 ++:1002C0000000000200007580000000020006758139 ++:1002D0000000000204002580000000020006758175 ++:1002E000000000040000005A000000000000500060 ++:1002F0000000000200061000000000020000750E61 ++:1003000000000002000190000000001400011064D1 ++:100310000000001200000064000000020400250F2D ++:10032000000000040000505E00000002000075653F ++:100330000000000200007566000000040000006577 ++:100340000000000201E655B4000000024401B0F0D4 ++:100350000000000201C110F0000000182666707154 ++:1003600000000002040C2565000000180000007168 ++:100370000000000204002564000000020000756611 ++:100380000000000400000068000000080040107435 ++:10039000000000020010100000000002000D80FFAD ++:1003A000000000080080007700000002000F9000AD ++:1003B00000000002000E00FF000000060000000028 ++:1003C0000000001800000094000000040000006815 ++:1003D00000000002000075760000000200065000D8 ++:1003E0000000000200009000000000020004100065 ++:1003F000000000020C00350E000000020004900016 ++:1004000000000002000510000000000201E785F86E ++:1004100000000002002000000000000C00600087C7 ++:10042000000000020000756300000021006075F00C ++:10043000000000042000707C000000040000507CDC ++:1004400000000002000075760000000200007577D1 ++:10045000000000020000750E000000020000750F91 ++:100460000000000200A050000000000C0060008AA4 ++:1004700000000021006075F000000002000075F827 ++:10048000000000040000008A00000002000A750E4F ++:10049000000000020020750F000000040060008DC5 ++:1004A000000000020000757000000002000075717D ++:1004B00000000006000075720000000200005000FD ++:1004C0000000000200A0500000000002000075685B ++:1004D00000000002000610000000000C0000009860 ++:1004E0000000000200058000000000020C60756240 ++:1004F000000000040000009A000000040060009961 ++:1005000000000000400070F100000002000380F1D4 ++:100510000000001C000000A700000018000650A901 ++:1005200000000002040025BB00000018000610AA0D ++:1005300000000000040075BC00000002000075BB54 ++:1005400000000000000075BC00000006000900006B ++:10055000000000020009000000000006000D8002FB ++:10056000000000020000500000000002000078219E ++:100570000000000000007800000000020000782168 ++:10058000000000000000780000000002016650003A ++:1005900000000002000A000000000002000671CC0A ++:1005A000000000020286F1CD00000010000000B73C ++:1005B00000000000210070000000001C000000BED0 ++:1005C000000000020006500000000002000A0000C7 ++:1005D000000000020006100000000002000B0000F6 ++:1005E000000000023806700000000004000A00BA93 ++:1005F0000000000020007000000000020120000048 ++:10060000000000022007700000000002012000002E ++:100610000000000020007000000000020006100032 ++:10062000000000020120751B000000028040750AD6 ++:10063000000000028040750B000000020011000065 ++:1006400000000002000380F10000001C000000D147 ++:1006500000000018000610AA00000002844075BDCA ++:1006600000000018000610A900000002840075BBFD ++:1006700000000018000610AA00000002844075BCAB ++:1006800000000004000000D400000002804075BD9E ++:1006900000000002800075BB00000002804075BCB5 ++:1006A0000000000200108000000000020140000075 ++:1006B0000000000C006000D80000002020C0700086 ++:1006C00000000012000000DA0000000600800000B8 ++:1006D000000000060080751D00000002000025BB20 ++:1006E00000000004000040D4000000020000775C1D ++:1006F0000000000200A05000000000020066100090 ++:10070000000000200460275D0000000000004000A1 ++:1007100000000002000079990000000200A05000D3 ++:100720000000000200661000000000200460299B09 ++:1007300000000000000040000000000201E008305E ++:1007400000000000210070000000000200005000C6 ++:10075000000000020003805600000002040025E0B3 ++:1007600000000000000075E1000000000000000132 ++:1007700000000002000380ED0000000004007394FC ++:100780000000000000000000000000000000000069 ++:1007900000000002000078C400000002000078C5DC ++:1007A00000000002000078C600000002000079246A ++:1007B00000000002000079250000000200007926F8 ++:1007C00000000004000000F2000000020000792494 ++:1007D00000000002000079250000000200007926D8 ++:1007E00000000004000000F900000000000000000C ++:1007F00000000000000000000000000000000000F9 ++:00000001FF ++/* production radeon ucode r1xx-r6xx */ +diff --git a/firmware/radeon/R300_cp.bin.ihex b/firmware/radeon/R300_cp.bin.ihex +new file mode 100644 +index 0000000..d307d56 +--- /dev/null ++++ b/firmware/radeon/R300_cp.bin.ihex +@@ -0,0 +1,130 @@ ++:10000000000000004200E000000000004000E000AE ++:1000100000000008000000AE00000008000000B270 ++:100020000000000067554B4A000000004A4A447532 ++:100030000000000055527D83000000004A8C8B6553 ++:10004000000000004AEF4AF6000000004AE14A4A78 ++:1000500000000000E497979700000000DB4AEBDD0A ++:10006000000000009CCC4A4A00000000D1989898FB ++:10007000000000004A0F9AD600000004000CA00007 ++:1000800000000038000D0012000000040000E8B479 ++:1000900000000038000D0014000000040000E8B665 ++:1000A00000000038000D0016000000040000E854B5 ++:1000B00000000038000D0018000000040000E855A2 ++:1000C00000000038000D001A000000040000E8568F ++:1000D00000000038000D001C000000040000E8577C ++:1000E00000000038000D001E000000040000E8249D ++:1000F00000000038000D0020000000040000E8258A ++:1001000000000038000D0022000000040000E8306C ++:1001100000000038000D0024000000040000F0C0C2 ++:1001200000000038000D0026000000040000F0C1AF ++:1001300000000038000D0028000000040000F0411D ++:1001400000000038000D002A000000040000F184C7 ++:1001500000000038000D002C000000040000F185B4 ++:1001600000000038000D002E000000040000F186A1 ++:1001700000000038000D0030000000040000F1878E ++:1001800000000038000D0032000000040000F18083 ++:1001900000000038000D0034000000040000F3935C ++:1001A00000000038000D0036000000040000F38A53 ++:1001B00000000038000D0038000000040000F38E3D ++:1001C000000000040000E821000000040140A0003D ++:1001D00000000018000000430000000400CCE8000C ++:1001E00000000004001B000100000004080048009B ++:1001F00000000004001B000100000004080048008B ++:1002000000000004001B000100000004080048007A ++:10021000000000080000003A000000000000A000FC ++:10022000000000042000451D000000040000E580DF ++:1002300000000004000CE581000000040800458077 ++:1002400000000004000CE5810000000800000047E9 ++:10025000000000000000A00000000004000C2000CE ++:10026000000000040000E50E000000040003200070 ++:10027000000000280002205100000024000000516E ++:10028000000000040800450F000000080000A04B1B ++:10029000000000040000E565000000040000E566C1 ++:1002A00000000008000000520000000403CCA5B4C8 ++:1002B00000000004054320000000000400022000AC ++:1002C000000000304CCCE05E0000000408274565CB ++:1002D000000000300000005E0000000408004564DB ++:1002E000000000040000E566000000080000005562 ++:1002F00000000010008020610000000400202000A9 ++:1003000000000004001B00FF00000010010000645A ++:1003100000000004001F200000000004001C00FF7B ++:100320000000000C00000000000000300000008011 ++:100330000000000800000055000000040000E57601 ++:1003400000000004000CA0000000000400012000D8 ++:100350000000000400082000000000041800650EE2 ++:10036000000000040009200000000004000A200032 ++:1003700000000004000F0000000000040040000026 ++:100380000000001800000074000000040000E56395 ++:10039000000000C200C0E5F900000008000000698C ++:1003A000000000080000A069000000040000E576DD ++:1003B000000000040000E577000000040000E50EE6 ++:1003C000000000040000E50F000000040140A00050 ++:1003D0000000001800000077000000C200C0E5F92E ++:1003E0000000000800000077000000040014E50E83 ++:1003F000000000040040E50F0000000800C0007A83 ++:10040000000000040000E570000000040000E57139 ++:100410000000000C0000E572000000040000A000D5 ++:10042000000000040140A000000000040000E56896 ++:1004300000000004000C20000000001800000084F0 ++:1004400000000004000B00000000000418C0E5627A ++:1004500000000008000000860000000800C00085C1 ++:1004600000000004000700E30000003800000092D4 ++:1004700000000030000CA09400000004080045BB00 ++:1004800000000030000C2095000000000800E5BCD2 ++:10049000000000040000E5BB000000000000E5BC17 ++:1004A0000000000C00120000000000040012000018 ++:1004B0000000000C001B0002000000040000A0006F ++:1004C000000000040000E821000000000000E80037 ++:1004D000000000040000E821000000000000E82EF9 ++:1004E0000000000402CCA000000000040014000082 ++:1004F00000000004000CE1CC00000004050DE1CD7B ++:10050000000000040040000000000018000000A4EB ++:100510000000000400C0A00000000008000000A1CE ++:1005200000000020000000A6000000004200E000E3 ++:1005300000000038000000AD00000004000CA00026 ++:10054000000000040014000000000004000C200063 ++:10055000000000040016000000000004700CE00021 ++:1005600000000008001400A9000000004000E000A6 ++:10057000000000040240000000000004400EE00003 ++:100580000000000402400000000000004000E00005 ++:1005900000000004000C2000000000040240E51BE5 ++:1005A000000000050080E50A000000050080E50B62 ++:1005B000000000040022000000000004000700E327 ++:1005C00000000038000000C000000030000C209542 ++:1005D000000000050880E5BD00000030000C2094FC ++:1005E000000000050800E5BB00000030000C20956D ++:1005F000000000050880E5BC00000008000000C302 ++:10060000000000050080E5BD000000050000E5BB1E ++:10061000000000050080E5BC00000004002100008F ++:1006200000000004028000000000001800C000C7A5 ++:10063000000000404180E00000000024000000C9EC ++:100640000000000C010000000000000C0100E51D8E ++:1006500000000004000045BB00000008000080C34B ++:10066000000000040000F3CE000000040140A000E0 ++:100670000000000400CC20000000004008C053CF60 ++:100680000000000000008000000000040000F3D221 ++:10069000000000040140A0000000000400CC200085 ++:1006A0000000004008C053D300000000000080009C ++:1006B000000000040000F39D000000040140A000C1 ++:1006C0000000000400CC20000000004008C0539E41 ++:1006D00000000000000080000000000403C008309B ++:1006E000000000004200E000000000040000A00044 ++:1006F00000000004200045E0000000000000E5E1EB ++:10070000000000000000000100000004000700E0FD ++:10071000000000000800E39400000000000000005A ++:10072000000000040000E8C4000000040000E8C568 ++:10073000000000040000E8C6000000040000E928F2 ++:10074000000000040000E929000000040000E92A7C ++:1007500000000008000000E4000000040000E92898 ++:10076000000000040000E929000000040000E92A5C ++:1007700000000008000000EB0000000402C02000A0 ++:10078000000000040006000000000034000000F338 ++:1007900000000008000000F00000000400008000DD ++:1007A00000000000C000E0000000000000000000A9 ++:1007B00000000004000C200000000004001D0018D0 ++:1007C00000000004001A000100000034000000FBDB ++:1007D000000000080000004A000000080500A04AD0 ++:1007E0000000000000000000000000000000000009 ++:1007F00000000000000000000000000000000000F9 ++:00000001FF ++/* production radeon ucode r1xx-r6xx */ +diff --git a/firmware/radeon/R420_cp.bin.ihex b/firmware/radeon/R420_cp.bin.ihex +new file mode 100644 +index 0000000..3815891 +--- /dev/null ++++ b/firmware/radeon/R420_cp.bin.ihex +@@ -0,0 +1,130 @@ ++:10000000000000004200E000000000004000E000AE ++:100010000000000800000099000000080000009D9A ++:10002000000000004A554B4A000000004A4A44675D ++:100030000000000055526F75000000004A7E7D658B ++:1000400000000000D9D3DFF6000000004AC54A4A8C ++:1000500000000000C882828200000000BF4ACFC1B9 ++:100060000000000087B04A4A00000000B583838387 ++:10007000000000004A0F85BA00000004000CA00038 ++:1000800000000038000D0012000000040000E8B479 ++:1000900000000038000D0014000000040000E8B665 ++:1000A00000000038000D0016000000040000E854B5 ++:1000B00000000038000D0018000000040000E855A2 ++:1000C00000000038000D001A000000040000E8568F ++:1000D00000000038000D001C000000040000E8577C ++:1000E00000000038000D001E000000040000E8249D ++:1000F00000000038000D0020000000040000E8258A ++:1001000000000038000D0022000000040000E8306C ++:1001100000000038000D0024000000040000F0C0C2 ++:1001200000000038000D0026000000040000F0C1AF ++:1001300000000038000D0028000000040000F0411D ++:1001400000000038000D002A000000040000F184C7 ++:1001500000000038000D002C000000040000F185B4 ++:1001600000000038000D002E000000040000F186A1 ++:1001700000000038000D0030000000040000F1878E ++:1001800000000038000D0032000000040000F18083 ++:1001900000000038000D0034000000040000F3935C ++:1001A00000000038000D0036000000040000F38A53 ++:1001B00000000038000D0038000000040000F38E3D ++:1001C000000000040000E821000000040140A0003D ++:1001D00000000018000000430000000400CCE8000C ++:1001E00000000004001B000100000004080048009B ++:1001F00000000004001B000100000004080048008B ++:1002000000000004001B000100000004080048007A ++:10021000000000080000003A000000000000A000FC ++:10022000000000042000451D000000040000E580DF ++:1002300000000004000CE581000000040800458077 ++:1002400000000004000CE5810000000800000047E9 ++:10025000000000000000A00000000004000C2000CE ++:10026000000000040000E50E000000040003200070 ++:10027000000000280002205100000024000000516E ++:10028000000000040800450F000000080000A04B1B ++:10029000000000040000E565000000040000E566C1 ++:1002A00000000008000000520000000403CCA5B4C8 ++:1002B00000000004054320000000000400022000AC ++:1002C000000000304CCCE05E0000000408274565CB ++:1002D000000000300000005E0000000408004564DB ++:1002E000000000040000E566000000080000005562 ++:1002F00000000010008020610000000400202000A9 ++:1003000000000004001B00FF00000010010000645A ++:1003100000000004001F200000000004001C00FF7B ++:100320000000000C0000000000000030000000721F ++:100330000000000800000055000000040000E57601 ++:10034000000000040000E577000000040000E50E56 ++:10035000000000040000E50F000000040140A000C0 ++:100360000000001800000069000000C200C0E5F9AC ++:100370000000000800000069000000040014E50E01 ++:10038000000000040040E50F0000000800C0006C01 ++:10039000000000040000E570000000040000E571AA ++:1003A0000000000C0000E572000000040000A00046 ++:1003B000000000040140A000000000040000E56807 ++:1003C00000000004000C200000000018000000766F ++:1003D00000000004000B00000000000418C0E562EB ++:1003E00000000008000000780000000800C000774E ++:1003F00000000004000700C7000000380000008073 ++:10040000000000040000E5BB000000000000E5BCA7 ++:10041000000000040000A000000000040000E8212B ++:10042000000000000000E800000000040000E821D7 ++:10043000000000000000E82E0000000402CCA00034 ++:10044000000000040014000000000004000CE1CCD7 ++:1004500000000004050DE1CD000000040040000094 ++:10046000000000180000008F0000000400C0A00081 ++:10047000000000080000008C000000200000009137 ++:10048000000000004200E00000000038000000987A ++:1004900000000004000CA000000000040014000094 ++:1004A00000000004000C2000000000040016000002 ++:1004B00000000004700CE00000000008001400942C ++:1004C000000000004000E0000000000402400000C6 ++:1004D00000000004400EE0000000000402400000A4 ++:1004E000000000004000E00000000004000C2000BC ++:1004F000000000040240E51B000000050080E50A42 ++:10050000000000050080E50B000000040022000050 ++:1005100000000004000700C700000038000000A42D ++:10052000000000050080E5BD000000050000E5BBFF ++:10053000000000050080E5BC000000040021000070 ++:1005400000000004028000000000001800C000ABA2 ++:10055000000000404180E00000000024000000ADE9 ++:100560000000000C010000000000000C0100E51D6F ++:1005700000000004000045BB00000008000080A748 ++:10058000000000040000F3CE000000040140A000C1 ++:100590000000000400CC20000000004008C053CF41 ++:1005A0000000000000008000000000040000F3D202 ++:1005B000000000040140A0000000000400CC200066 ++:1005C0000000004008C053D300000000000080007D ++:1005D000000000040000F39D000000040140A000A2 ++:1005E0000000000400CC20000000004008C0539E22 ++:1005F00000000000000080000000000403C008307C ++:10060000000000004200E000000000040000A00024 ++:1006100000000004200045E0000000000000E5E1CB ++:10062000000000000000000100000004000700C4FA ++:10063000000000000800E39400000000000000003B ++:10064000000000040000E8C4000000040000E8C549 ++:10065000000000040000E8C6000000040000E928D3 ++:10066000000000040000E929000000040000E92A5D ++:1006700000000008000000C8000000040000E92895 ++:10068000000000040000E929000000040000E92A3D ++:1006900000000008000000CF0000000402C020009D ++:1006A000000000040006000000000034000000D735 ++:1006B00000000008000000D40000000400008000DA ++:1006C00000000000C000E000000000040000E1CCD9 ++:1006D000000000040500E1CD00000004000CA000B3 ++:1006E00000000034000000DE00000008000000DA16 ++:1006F000000000000000A000000000040019E1CC90 ++:1007000000000004001B0001000000040500A00020 ++:1007100000000004080041CD00000004000CA0000F ++:1007200000000034000000FB000000080000004A48 ++:1007300000000000000000000000000000000000B9 ++:1007400000000000000000000000000000000000A9 ++:100750000000000000000000000000000000000099 ++:100760000000000000000000000000000000000089 ++:100770000000000000000000000000000000000079 ++:100780000000000000000000000000000000000069 ++:100790000000000000000000000000000000000059 ++:1007A0000000000000000000000000000000000049 ++:1007B00000000004000C200000000004001D0018D0 ++:1007C00000000004001A000100000034000000FBDB ++:1007D000000000080000004A000000080500A04AD0 ++:1007E0000000000000000000000000000000000009 ++:1007F00000000000000000000000000000000000F9 ++:00000001FF ++/* production radeon ucode r1xx-r6xx */ +diff --git a/firmware/radeon/R520_cp.bin.ihex b/firmware/radeon/R520_cp.bin.ihex +new file mode 100644 +index 0000000..372ff82 +--- /dev/null ++++ b/firmware/radeon/R520_cp.bin.ihex +@@ -0,0 +1,130 @@ ++:10000000000000004200E000000000004000E000AE ++:100010000000000800000099000000080000009D9A ++:10002000000000004A554B4A000000004A4A44675D ++:100030000000000055526F75000000004A7E7D658B ++:1000400000000000E0DAE6F6000000004AC54A4A77 ++:1000500000000000C882828200000000BF4ACFC1B9 ++:100060000000000087B04AD500000000B5838383FC ++:10007000000000004A0F85BA00000004000CA00038 ++:1000800000000038000D0012000000040000E8B479 ++:1000900000000038000D0014000000040000E8B665 ++:1000A00000000038000D0016000000040000E854B5 ++:1000B00000000038000D0018000000040000E855A2 ++:1000C00000000038000D001A000000040000E8568F ++:1000D00000000038000D001C000000040000E8577C ++:1000E00000000038000D001E000000040000E8249D ++:1000F00000000038000D0020000000040000E8258A ++:1001000000000038000D0022000000040000E8306C ++:1001100000000038000D0024000000040000F0C0C2 ++:1001200000000038000D0026000000040000F0C1AF ++:1001300000000038000D0028000000040000E0006E ++:1001400000000038000D002A000000040000E0005C ++:1001500000000038000D002C000000040000E0004A ++:1001600000000038000D002E000000040000E00038 ++:1001700000000038000D0030000000040000E00026 ++:1001800000000038000D0032000000040000F18083 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++:100610000000000000008000000000040000F3D291 ++:10062000000000040140A0000000000400CC2000F5 ++:100630000000004008C053D300000000000080000C ++:10064000000000040000F39D000000040140A00031 ++:100650000000000400CC20000000004008C0539EB1 ++:1006600000000000000080000000000403C008300B ++:10067000000000004200E000000000040000A000B4 ++:1006800000000004200045E0000000000000E5E15B ++:10069000000000000000000100000004000700D27C ++:1006A000000000000800E3940000000000000000CB ++:1006B000000000040000E8C4000000040000E8C5D9 ++:1006C000000000040000E8C6000000040000E92863 ++:1006D000000000040000E929000000040000E92AED ++:1006E00000000008000000D6000000040000E92817 ++:1006F000000000040000E929000000040000E92ACD ++:1007000000000008000000DD0000000000E001160D ++:1007100000000004000700E1000000040800401C85 ++:1007200000000004200050E7000000040000E01D6D ++:1007300000000008000000E40000000402C02000E7 ++:10074000000000040006000000000034000000EB80 ++:1007500000000008000000E8000000040000800025 ++:1007600000000000C000E0000000000000000000E9 ++:100770000000000000000000000000000000000079 ++:100780000000000000000000000000000000000069 ++:100790000000000000000000000000000000000059 ++:1007A0000000000000000000000000000000000049 ++:1007B00000000004000C200000000004001D0018D0 ++:1007C00000000004001A000100000034000000FBDB ++:1007D000000000080000004A000000080500A04AD0 ++:1007E0000000000000000000000000000000000009 ++:1007F00000000000000000000000000000000000F9 ++:00000001FF ++/* production radeon ucode r1xx-r6xx */ +diff --git a/firmware/radeon/RS690_cp.bin.ihex b/firmware/radeon/RS690_cp.bin.ihex +new file mode 100644 +index 0000000..6896274 +--- /dev/null ++++ b/firmware/radeon/RS690_cp.bin.ihex +@@ -0,0 +1,130 @@ ++:1000000000000008000000DD00000008000000DF24 ++:1000100000000008000000A000000008000000A48C ++:10002000000000004A554B4A000000004A4A44675D ++:100030000000000055526F75000000004A7E7D658B ++:10004000000000004AD74AF6000000004AC94A4AA8 ++:1000500000000000CC89898900000000C34AD3C594 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++:1006F000000000004200E00000000030000000E1C7 ++:10070000000000004000E000000000040025001B85 ++:100710000000000400230000000000040025000584 ++:1007200000000034000000E60000000C00000000A3 ++:10073000000000040024400000000004080045C838 ++:1007400000000004002400050000000C08004D0B10 ++:100750000000000000000000000000000000000099 ++:100760000000000000000000000000000000000089 ++:100770000000000000000000000000000000000079 ++:100780000000000000000000000000000000000069 ++:100790000000000000000000000000000000000059 ++:1007A0000000000000000000000000000000000049 ++:1007B00000000004000C200000000004001D0018D0 ++:1007C00000000004001A000100000034000000FBDB ++:1007D000000000080000004A000000080500A04AD0 ++:1007E0000000000000000000000000000000000009 ++:1007F00000000000000000000000000000000000F9 ++:00000001FF ++/* production radeon ucode r1xx-r6xx */ +diff --git a/firmware/radeon/RS780_me.bin.ihex b/firmware/radeon/RS780_me.bin.ihex +new file mode 100644 +index 0000000..6479c10 +--- /dev/null ++++ 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++:100C3000002301E90026004C0027005F0020011B73 ++:100C4000002800930029004F002A0084002B006533 ++:100C5000002F008E003200D90034023300360075B8 ++:100C60000039010B003C01FD003F00A0004102489B ++:100C7000004401950048019E004901C6004A01D088 ++:100C8000005502260056022E0060000A0061002A6C ++:100C90000062003000630030006400300065003006 ++:100CA0000066003000670030006800370069003FD0 ++:100CB000006A0047006B0047006C0047006D00476A ++:100CC000006E0047006F0047007000470073025F2E ++:100CD000007B024100000005000000050000000547 ++:100CE00000000005000000050000000500000005F0 ++:100CF00000000005000000050000000500000005E0 ++:100D000000000005000000050000000500000005CF ++:100D100000000005000000050000000500000005BF ++:100D200000000005000000050000000500000005AF ++:100D3000000000050000000500000005000000059F ++:00000001FF +diff --git a/include/drm/drmP.h b/include/drm/drmP.h +index 45b67d9..eeefb63 100644 +--- a/include/drm/drmP.h ++++ b/include/drm/drmP.h +@@ -88,7 +88,37 @@ struct drm_device; + #define DRM_UT_CORE 0x01 + #define DRM_UT_DRIVER 0x02 + #define DRM_UT_KMS 0x04 +-#define DRM_UT_MODE 0x08 ++/* ++ * Three debug levels are defined. ++ * drm_core, drm_driver, drm_kms ++ * drm_core level can be used in the generic drm code. For example: ++ * drm_ioctl, drm_mm, drm_memory ++ * The macro definiton of DRM_DEBUG is used. ++ * DRM_DEBUG(fmt, args...) ++ * The debug info by using the DRM_DEBUG can be obtained by adding ++ * the boot option of "drm.debug=1". ++ * ++ * drm_driver level can be used in the specific drm driver. It is used ++ * to add the debug info related with the drm driver. For example: ++ * i915_drv, i915_dma, i915_gem, radeon_drv, ++ * The macro definition of DRM_DEBUG_DRIVER can be used. ++ * DRM_DEBUG_DRIVER(fmt, args...) ++ * The debug info by using the DRM_DEBUG_DRIVER can be obtained by ++ * adding the boot option of "drm.debug=0x02" ++ * ++ * drm_kms level can be used in the KMS code related with specific drm driver. ++ * It is used to add the debug info related with KMS mode. For example: ++ * the connector/crtc , ++ * The macro definition of DRM_DEBUG_KMS can be used. ++ * DRM_DEBUG_KMS(fmt, args...) ++ * The debug info by using the DRM_DEBUG_KMS can be obtained by ++ * adding the boot option of "drm.debug=0x04" ++ * ++ * If we add the boot option of "drm.debug=0x06", we can get the debug info by ++ * using the DRM_DEBUG_KMS and DRM_DEBUG_DRIVER. ++ * If we add the boot option of "drm.debug=0x05", we can get the debug info by ++ * using the DRM_DEBUG_KMS and DRM_DEBUG. ++ */ + + extern void drm_ut_debug_printk(unsigned int request_level, + const char *prefix, +@@ -174,19 +204,14 @@ extern void drm_ut_debug_printk(unsigned int request_level, + __func__, fmt, ##args); \ + } while (0) + +-#define DRM_DEBUG_DRIVER(prefix, fmt, args...) \ ++#define DRM_DEBUG_DRIVER(fmt, args...) \ + do { \ +- drm_ut_debug_printk(DRM_UT_DRIVER, prefix, \ ++ drm_ut_debug_printk(DRM_UT_DRIVER, DRM_NAME, \ + __func__, fmt, ##args); \ + } while (0) +-#define DRM_DEBUG_KMS(prefix, fmt, args...) \ +- do { \ +- drm_ut_debug_printk(DRM_UT_KMS, prefix, \ +- __func__, fmt, ##args); \ +- } while (0) +-#define DRM_DEBUG_MODE(prefix, fmt, args...) \ ++#define DRM_DEBUG_KMS(fmt, args...) \ + do { \ +- drm_ut_debug_printk(DRM_UT_MODE, prefix, \ ++ drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, \ + __func__, fmt, ##args); \ + } while (0) + #define DRM_LOG(fmt, args...) \ +@@ -210,9 +235,8 @@ extern void drm_ut_debug_printk(unsigned int request_level, + NULL, fmt, ##args); \ + } while (0) + #else +-#define DRM_DEBUG_DRIVER(prefix, fmt, args...) do { } while (0) +-#define DRM_DEBUG_KMS(prefix, fmt, args...) do { } while (0) +-#define DRM_DEBUG_MODE(prefix, fmt, args...) do { } while (0) ++#define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0) ++#define DRM_DEBUG_KMS(fmt, args...) do { } while (0) + #define DRM_DEBUG(fmt, arg...) do { } while (0) + #define DRM_LOG(fmt, arg...) do { } while (0) + #define DRM_LOG_KMS(fmt, args...) do { } while (0) +@@ -1417,7 +1441,7 @@ drm_gem_object_unreference(struct drm_gem_object *obj) + + int drm_gem_handle_create(struct drm_file *file_priv, + struct drm_gem_object *obj, +- int *handlep); ++ u32 *handlep); + + static inline void + drm_gem_object_handle_reference(struct drm_gem_object *obj) +@@ -1443,7 +1467,7 @@ drm_gem_object_handle_unreference(struct drm_gem_object *obj) + + struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev, + struct drm_file *filp, +- int handle); ++ u32 handle); + int drm_gem_close_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); + int drm_gem_flink_ioctl(struct drm_device *dev, void *data, +diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h +new file mode 100644 +index 0000000..7bfb063 +--- /dev/null ++++ b/include/drm/drm_cache.h +@@ -0,0 +1,38 @@ ++/************************************************************************** ++ * ++ * Copyright 2009 Red Hat Inc. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sub license, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, ++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR ++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE ++ * USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * ++ **************************************************************************/ ++/* ++ * Authors: ++ * Dave Airlie <airlied@redhat.com> ++ */ ++ ++#ifndef _DRM_CACHE_H_ ++#define _DRM_CACHE_H_ ++ ++void drm_clflush_pages(struct page *pages[], unsigned long num_pages); ++ ++#endif +diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h +index 7300fb8..b69347b 100644 +--- a/include/drm/drm_crtc.h ++++ b/include/drm/drm_crtc.h +@@ -259,6 +259,8 @@ struct drm_framebuffer { + void *fbdev; + u32 pseudo_palette[17]; + struct list_head filp_head; ++ /* if you are using the helper */ ++ void *helper_private; + }; + + struct drm_property_blob { +@@ -385,6 +387,7 @@ struct drm_crtc { + * @get_modes: get mode list for this connector + * @set_property: property for this connector may need update + * @destroy: make object go away ++ * @force: notify the driver the connector is forced on + * + * Each CRTC may have one or more connectors attached to it. The functions + * below allow the core DRM code to control connectors, enumerate available modes, +@@ -399,6 +402,7 @@ struct drm_connector_funcs { + int (*set_property)(struct drm_connector *connector, struct drm_property *property, + uint64_t val); + void (*destroy)(struct drm_connector *connector); ++ void (*force)(struct drm_connector *connector); + }; + + struct drm_encoder_funcs { +@@ -427,6 +431,13 @@ struct drm_encoder { + void *helper_private; + }; + ++enum drm_connector_force { ++ DRM_FORCE_UNSPECIFIED, ++ DRM_FORCE_OFF, ++ DRM_FORCE_ON, /* force on analog part normally */ ++ DRM_FORCE_ON_DIGITAL, /* for DVI-I use digital connector */ ++}; ++ + /** + * drm_connector - central DRM connector control structure + * @crtc: CRTC this connector is currently connected to, NULL if none +@@ -476,9 +487,12 @@ struct drm_connector { + + void *helper_private; + ++ /* forced on connector */ ++ enum drm_connector_force force; + uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER]; + uint32_t force_encoder_id; + struct drm_encoder *encoder; /* currently active encoder */ ++ void *fb_helper_private; + }; + + /** +@@ -572,6 +586,12 @@ struct drm_mode_config { + struct drm_property *tv_right_margin_property; + struct drm_property *tv_top_margin_property; + struct drm_property *tv_bottom_margin_property; ++ struct drm_property *tv_brightness_property; ++ struct drm_property *tv_contrast_property; ++ struct drm_property *tv_flicker_reduction_property; ++ struct drm_property *tv_overscan_property; ++ struct drm_property *tv_saturation_property; ++ struct drm_property *tv_hue_property; + + /* Optional properties */ + struct drm_property *scaling_mode_property; +@@ -736,4 +756,12 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev, + extern int drm_mode_gamma_set_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); + extern bool drm_detect_hdmi_monitor(struct edid *edid); ++extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, ++ int hdisplay, int vdisplay, int vrefresh, ++ bool reduced, bool interlaced, bool margins); ++extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, ++ int hdisplay, int vdisplay, int vrefresh, ++ bool interlaced, int margins); ++extern int drm_add_modes_noedid(struct drm_connector *connector, ++ int hdisplay, int vdisplay); + #endif /* __DRM_CRTC_H__ */ +diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h +index 6769ff6..ef47dfd 100644 +--- a/include/drm/drm_crtc_helper.h ++++ b/include/drm/drm_crtc_helper.h +@@ -39,6 +39,7 @@ + + #include <linux/fb.h> + ++#include "drm_fb_helper.h" + struct drm_crtc_helper_funcs { + /* + * Control power levels on the CRTC. If the mode passed in is +@@ -79,6 +80,8 @@ struct drm_encoder_helper_funcs { + /* detect for DAC style encoders */ + enum drm_connector_status (*detect)(struct drm_encoder *encoder, + struct drm_connector *connector); ++ /* disable encoder when not in use - more explicit than dpms off */ ++ void (*disable)(struct drm_encoder *encoder); + }; + + struct drm_connector_helper_funcs { +@@ -98,6 +101,7 @@ extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, + int x, int y, + struct drm_framebuffer *old_fb); + extern bool drm_helper_crtc_in_use(struct drm_crtc *crtc); ++extern bool drm_helper_encoder_in_use(struct drm_encoder *encoder); + + extern void drm_helper_connector_dpms(struct drm_connector *connector, int mode); + +@@ -116,10 +120,11 @@ static inline void drm_encoder_helper_add(struct drm_encoder *encoder, + encoder->helper_private = (void *)funcs; + } + +-static inline void drm_connector_helper_add(struct drm_connector *connector, ++static inline int drm_connector_helper_add(struct drm_connector *connector, + const struct drm_connector_helper_funcs *funcs) + { + connector->helper_private = (void *)funcs; ++ return drm_fb_helper_add_connector(connector); + } + + extern int drm_helper_resume_force_mode(struct drm_device *dev); +diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h +new file mode 100644 +index 0000000..2f65633 +--- /dev/null ++++ b/include/drm/drm_encoder_slave.h +@@ -0,0 +1,162 @@ ++/* ++ * Copyright (C) 2009 Francisco Jerez. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining ++ * a copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sublicense, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial ++ * portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE ++ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION ++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#ifndef __DRM_ENCODER_SLAVE_H__ ++#define __DRM_ENCODER_SLAVE_H__ ++ ++#include "drmP.h" ++#include "drm_crtc.h" ++ ++/** ++ * struct drm_encoder_slave_funcs - Entry points exposed by a slave encoder driver ++ * @set_config: Initialize any encoder-specific modesetting parameters. ++ * The meaning of the @params parameter is implementation ++ * dependent. It will usually be a structure with DVO port ++ * data format settings or timings. It's not required for ++ * the new parameters to take effect until the next mode ++ * is set. ++ * ++ * Most of its members are analogous to the function pointers in ++ * &drm_encoder_helper_funcs and they can optionally be used to ++ * initialize the latter. Connector-like methods (e.g. @get_modes and ++ * @set_property) will typically be wrapped around and only be called ++ * if the encoder is the currently selected one for the connector. ++ */ ++struct drm_encoder_slave_funcs { ++ void (*set_config)(struct drm_encoder *encoder, ++ void *params); ++ ++ void (*destroy)(struct drm_encoder *encoder); ++ void (*dpms)(struct drm_encoder *encoder, int mode); ++ void (*save)(struct drm_encoder *encoder); ++ void (*restore)(struct drm_encoder *encoder); ++ bool (*mode_fixup)(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode); ++ int (*mode_valid)(struct drm_encoder *encoder, ++ struct drm_display_mode *mode); ++ void (*mode_set)(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode); ++ ++ enum drm_connector_status (*detect)(struct drm_encoder *encoder, ++ struct drm_connector *connector); ++ int (*get_modes)(struct drm_encoder *encoder, ++ struct drm_connector *connector); ++ int (*create_resources)(struct drm_encoder *encoder, ++ struct drm_connector *connector); ++ int (*set_property)(struct drm_encoder *encoder, ++ struct drm_connector *connector, ++ struct drm_property *property, ++ uint64_t val); ++ ++}; ++ ++/** ++ * struct drm_encoder_slave - Slave encoder struct ++ * @base: DRM encoder object. ++ * @slave_funcs: Slave encoder callbacks. ++ * @slave_priv: Slave encoder private data. ++ * @bus_priv: Bus specific data. ++ * ++ * A &drm_encoder_slave has two sets of callbacks, @slave_funcs and the ++ * ones in @base. The former are never actually called by the common ++ * CRTC code, it's just a convenience for splitting the encoder ++ * functions in an upper, GPU-specific layer and a (hopefully) ++ * GPU-agnostic lower layer: It's the GPU driver responsibility to ++ * call the slave methods when appropriate. ++ * ++ * drm_i2c_encoder_init() provides a way to get an implementation of ++ * this. ++ */ ++struct drm_encoder_slave { ++ struct drm_encoder base; ++ ++ struct drm_encoder_slave_funcs *slave_funcs; ++ void *slave_priv; ++ void *bus_priv; ++}; ++#define to_encoder_slave(x) container_of((x), struct drm_encoder_slave, base) ++ ++int drm_i2c_encoder_init(struct drm_device *dev, ++ struct drm_encoder_slave *encoder, ++ struct i2c_adapter *adap, ++ const struct i2c_board_info *info); ++ ++ ++/** ++ * struct drm_i2c_encoder_driver ++ * ++ * Describes a device driver for an encoder connected to the GPU ++ * through an I2C bus. In addition to the entry points in @i2c_driver ++ * an @encoder_init function should be provided. It will be called to ++ * give the driver an opportunity to allocate any per-encoder data ++ * structures and to initialize the @slave_funcs and (optionally) ++ * @slave_priv members of @encoder. ++ */ ++struct drm_i2c_encoder_driver { ++ struct i2c_driver i2c_driver; ++ ++ int (*encoder_init)(struct i2c_client *client, ++ struct drm_device *dev, ++ struct drm_encoder_slave *encoder); ++ ++}; ++#define to_drm_i2c_encoder_driver(x) container_of((x), \ ++ struct drm_i2c_encoder_driver, \ ++ i2c_driver) ++ ++/** ++ * drm_i2c_encoder_get_client - Get the I2C client corresponding to an encoder ++ */ ++static inline struct i2c_client *drm_i2c_encoder_get_client(struct drm_encoder *encoder) ++{ ++ return (struct i2c_client *)to_encoder_slave(encoder)->bus_priv; ++} ++ ++/** ++ * drm_i2c_encoder_register - Register an I2C encoder driver ++ * @owner: Module containing the driver. ++ * @driver: Driver to be registered. ++ */ ++static inline int drm_i2c_encoder_register(struct module *owner, ++ struct drm_i2c_encoder_driver *driver) ++{ ++ return i2c_register_driver(owner, &driver->i2c_driver); ++} ++ ++/** ++ * drm_i2c_encoder_unregister - Unregister an I2C encoder driver ++ * @driver: Driver to be unregistered. ++ */ ++static inline void drm_i2c_encoder_unregister(struct drm_i2c_encoder_driver *driver) ++{ ++ i2c_del_driver(&driver->i2c_driver); ++} ++ ++void drm_i2c_encoder_destroy(struct drm_encoder *encoder); ++ ++#endif +diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h +new file mode 100644 +index 0000000..4aa5740 +--- /dev/null ++++ b/include/drm/drm_fb_helper.h +@@ -0,0 +1,106 @@ ++/* ++ * Copyright (c) 2006-2009 Red Hat Inc. ++ * Copyright (c) 2006-2008 Intel Corporation ++ * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> ++ * ++ * DRM framebuffer helper functions ++ * ++ * Permission to use, copy, modify, distribute, and sell this software and its ++ * documentation for any purpose is hereby granted without fee, provided that ++ * the above copyright notice appear in all copies and that both that copyright ++ * notice and this permission notice appear in supporting documentation, and ++ * that the name of the copyright holders not be used in advertising or ++ * publicity pertaining to distribution of the software without specific, ++ * written prior permission. The copyright holders make no representations ++ * about the suitability of this software for any purpose. It is provided "as ++ * is" without express or implied warranty. ++ * ++ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, ++ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO ++ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR ++ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, ++ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER ++ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE ++ * OF THIS SOFTWARE. ++ * ++ * Authors: ++ * Dave Airlie <airlied@linux.ie> ++ * Jesse Barnes <jesse.barnes@intel.com> ++ */ ++#ifndef DRM_FB_HELPER_H ++#define DRM_FB_HELPER_H ++ ++struct drm_fb_helper_crtc { ++ uint32_t crtc_id; ++ struct drm_mode_set mode_set; ++}; ++ ++ ++struct drm_fb_helper_funcs { ++ void (*gamma_set)(struct drm_crtc *crtc, u16 red, u16 green, ++ u16 blue, int regno); ++}; ++ ++/* mode specified on the command line */ ++struct drm_fb_helper_cmdline_mode { ++ bool specified; ++ bool refresh_specified; ++ bool bpp_specified; ++ int xres, yres; ++ int bpp; ++ int refresh; ++ bool rb; ++ bool interlace; ++ bool cvt; ++ bool margins; ++}; ++ ++struct drm_fb_helper_connector { ++ struct drm_fb_helper_cmdline_mode cmdline_mode; ++}; ++ ++struct drm_fb_helper { ++ struct drm_framebuffer *fb; ++ struct drm_device *dev; ++ struct drm_display_mode *mode; ++ int crtc_count; ++ struct drm_fb_helper_crtc *crtc_info; ++ struct drm_fb_helper_funcs *funcs; ++ int conn_limit; ++ struct list_head kernel_fb_list; ++}; ++ ++int drm_fb_helper_single_fb_probe(struct drm_device *dev, ++ int (*fb_create)(struct drm_device *dev, ++ uint32_t fb_width, ++ uint32_t fb_height, ++ uint32_t surface_width, ++ uint32_t surface_height, ++ uint32_t surface_depth, ++ uint32_t surface_bpp, ++ struct drm_framebuffer **fb_ptr)); ++int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count, ++ int max_conn); ++void drm_fb_helper_free(struct drm_fb_helper *helper); ++int drm_fb_helper_blank(int blank, struct fb_info *info); ++int drm_fb_helper_pan_display(struct fb_var_screeninfo *var, ++ struct fb_info *info); ++int drm_fb_helper_set_par(struct fb_info *info); ++int drm_fb_helper_check_var(struct fb_var_screeninfo *var, ++ struct fb_info *info); ++int drm_fb_helper_setcolreg(unsigned regno, ++ unsigned red, ++ unsigned green, ++ unsigned blue, ++ unsigned transp, ++ struct fb_info *info); ++ ++void drm_fb_helper_restore(void); ++void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb, ++ uint32_t fb_width, uint32_t fb_height); ++void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch); ++ ++int drm_fb_helper_add_connector(struct drm_connector *connector); ++int drm_fb_helper_parse_command_line(struct drm_device *dev); ++ ++#endif +diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h +index f833207..62329f9 100644 +--- a/include/drm/drm_mm.h ++++ b/include/drm/drm_mm.h +@@ -37,6 +37,9 @@ + * Generic range manager structs + */ + #include <linux/list.h> ++#ifdef CONFIG_DEBUG_FS ++#include <linux/seq_file.h> ++#endif + + struct drm_mm_node { + struct list_head fl_entry; +@@ -96,4 +99,8 @@ static inline struct drm_mm *drm_get_mm(struct drm_mm_node *block) + return block->mm; + } + ++#ifdef CONFIG_DEBUG_FS ++int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm); ++#endif ++ + #endif +diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h +index ae304cc..1f90841 100644 +--- a/include/drm/drm_mode.h ++++ b/include/drm/drm_mode.h +@@ -68,10 +68,11 @@ + #define DRM_MODE_DPMS_OFF 3 + + /* Scaling mode options */ +-#define DRM_MODE_SCALE_NON_GPU 0 +-#define DRM_MODE_SCALE_FULLSCREEN 1 +-#define DRM_MODE_SCALE_NO_SCALE 2 +-#define DRM_MODE_SCALE_ASPECT 3 ++#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or ++ software can still scale) */ ++#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ ++#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ ++#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ + + /* Dithering mode options */ + #define DRM_MODE_DITHERING_OFF 0 +@@ -141,6 +142,7 @@ struct drm_mode_get_encoder { + #define DRM_MODE_SUBCONNECTOR_Composite 5 + #define DRM_MODE_SUBCONNECTOR_SVIDEO 6 + #define DRM_MODE_SUBCONNECTOR_Component 8 ++#define DRM_MODE_SUBCONNECTOR_SCART 9 + + #define DRM_MODE_CONNECTOR_Unknown 0 + #define DRM_MODE_CONNECTOR_VGA 1 +@@ -155,6 +157,7 @@ struct drm_mode_get_encoder { + #define DRM_MODE_CONNECTOR_DisplayPort 10 + #define DRM_MODE_CONNECTOR_HDMIA 11 + #define DRM_MODE_CONNECTOR_HDMIB 12 ++#define DRM_MODE_CONNECTOR_TV 13 + + struct drm_mode_get_connector { + +diff --git a/include/drm/drm_sysfs.h b/include/drm/drm_sysfs.h +new file mode 100644 +index 0000000..1d8e033 +--- /dev/null ++++ b/include/drm/drm_sysfs.h +@@ -0,0 +1,12 @@ ++#ifndef _DRM_SYSFS_H_ ++#define _DRM_SYSFS_H_ ++ ++/** ++ * This minimalistic include file is intended for users (read TTM) that ++ * don't want to include the full drmP.h file. ++ */ ++ ++extern int drm_class_device_register(struct device *dev); ++extern void drm_class_device_unregister(struct device *dev); ++ ++#endif +diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h +index 2ba61e1..3b9932a 100644 +--- a/include/drm/radeon_drm.h ++++ b/include/drm/radeon_drm.h +@@ -802,11 +802,12 @@ struct drm_radeon_gem_create { + uint32_t flags; + }; + +-#define RADEON_TILING_MACRO 0x1 +-#define RADEON_TILING_MICRO 0x2 +-#define RADEON_TILING_SWAP 0x4 +-#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface +- * when mapped - i.e. front buffer */ ++#define RADEON_TILING_MACRO 0x1 ++#define RADEON_TILING_MICRO 0x2 ++#define RADEON_TILING_SWAP_16BIT 0x4 ++#define RADEON_TILING_SWAP_32BIT 0x8 ++#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface ++ * when mapped - i.e. front buffer */ + + struct drm_radeon_gem_set_tiling { + uint32_t handle; +@@ -899,6 +900,7 @@ struct drm_radeon_cs { + #define RADEON_INFO_DEVICE_ID 0x00 + #define RADEON_INFO_NUM_GB_PIPES 0x01 + #define RADEON_INFO_NUM_Z_PIPES 0x02 ++#define RADEON_INFO_ACCEL_WORKING 0x03 + + struct drm_radeon_info { + uint32_t request; +diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h +index cd22ab4..4911461 100644 +--- a/include/drm/ttm/ttm_bo_api.h ++++ b/include/drm/ttm/ttm_bo_api.h +@@ -155,6 +155,7 @@ struct ttm_buffer_object { + * Members constant at init. + */ + ++ struct ttm_bo_global *glob; + struct ttm_bo_device *bdev; + unsigned long buffer_start; + enum ttm_bo_type type; +@@ -245,14 +246,15 @@ struct ttm_buffer_object { + * premapped region. + */ + ++#define TTM_BO_MAP_IOMEM_MASK 0x80 + struct ttm_bo_kmap_obj { + void *virtual; + struct page *page; + enum { +- ttm_bo_map_iomap, +- ttm_bo_map_vmap, +- ttm_bo_map_kmap, +- ttm_bo_map_premapped, ++ ttm_bo_map_iomap = 1 | TTM_BO_MAP_IOMEM_MASK, ++ ttm_bo_map_vmap = 2, ++ ttm_bo_map_kmap = 3, ++ ttm_bo_map_premapped = 4 | TTM_BO_MAP_IOMEM_MASK, + } bo_kmap_type; + }; + +@@ -522,8 +524,7 @@ extern int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type); + static inline void *ttm_kmap_obj_virtual(struct ttm_bo_kmap_obj *map, + bool *is_iomem) + { +- *is_iomem = (map->bo_kmap_type == ttm_bo_map_iomap || +- map->bo_kmap_type == ttm_bo_map_premapped); ++ *is_iomem = !!(map->bo_kmap_type & TTM_BO_MAP_IOMEM_MASK); + return map->virtual; + } + +diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h +index a68829d..e8cd6d2 100644 +--- a/include/drm/ttm/ttm_bo_driver.h ++++ b/include/drm/ttm/ttm_bo_driver.h +@@ -32,6 +32,7 @@ + + #include "ttm/ttm_bo_api.h" + #include "ttm/ttm_memory.h" ++#include "ttm/ttm_module.h" + #include "drm_mm.h" + #include "linux/workqueue.h" + #include "linux/fs.h" +@@ -161,7 +162,7 @@ struct ttm_tt { + long last_lomem_page; + uint32_t page_flags; + unsigned long num_pages; +- struct ttm_bo_device *bdev; ++ struct ttm_bo_global *glob; + struct ttm_backend *be; + struct task_struct *tsk; + unsigned long start; +@@ -364,24 +365,73 @@ struct ttm_bo_driver { + void (*fault_reserve_notify)(struct ttm_buffer_object *bo); + }; + +-#define TTM_NUM_MEM_TYPES 8 ++/** ++ * struct ttm_bo_global_ref - Argument to initialize a struct ttm_bo_global. ++ */ ++ ++struct ttm_bo_global_ref { ++ struct ttm_global_reference ref; ++ struct ttm_mem_global *mem_glob; ++}; + +-#define TTM_BO_PRIV_FLAG_MOVING 0 /* Buffer object is moving and needs +- idling before CPU mapping */ +-#define TTM_BO_PRIV_FLAG_MAX 1 + /** +- * struct ttm_bo_device - Buffer object driver device-specific data. ++ * struct ttm_bo_global - Buffer object driver global data. + * + * @mem_glob: Pointer to a struct ttm_mem_global object for accounting. +- * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver. +- * @count: Current number of buffer object. +- * @pages: Current number of pinned pages. + * @dummy_read_page: Pointer to a dummy page used for mapping requests + * of unpopulated pages. +- * @shrink: A shrink callback object used for buffre object swap. ++ * @shrink: A shrink callback object used for buffer object swap. + * @ttm_bo_extra_size: Extra size (sizeof(struct ttm_buffer_object) excluded) + * used by a buffer object. This is excluding page arrays and backing pages. + * @ttm_bo_size: This is @ttm_bo_extra_size + sizeof(struct ttm_buffer_object). ++ * @device_list_mutex: Mutex protecting the device list. ++ * This mutex is held while traversing the device list for pm options. ++ * @lru_lock: Spinlock protecting the bo subsystem lru lists. ++ * @device_list: List of buffer object devices. ++ * @swap_lru: Lru list of buffer objects used for swapping. ++ */ ++ ++struct ttm_bo_global { ++ ++ /** ++ * Constant after init. ++ */ ++ ++ struct kobject kobj; ++ struct ttm_mem_global *mem_glob; ++ struct page *dummy_read_page; ++ struct ttm_mem_shrink shrink; ++ size_t ttm_bo_extra_size; ++ size_t ttm_bo_size; ++ struct mutex device_list_mutex; ++ spinlock_t lru_lock; ++ ++ /** ++ * Protected by device_list_mutex. ++ */ ++ struct list_head device_list; ++ ++ /** ++ * Protected by the lru_lock. ++ */ ++ struct list_head swap_lru; ++ ++ /** ++ * Internal protection. ++ */ ++ atomic_t bo_count; ++}; ++ ++ ++#define TTM_NUM_MEM_TYPES 8 ++ ++#define TTM_BO_PRIV_FLAG_MOVING 0 /* Buffer object is moving and needs ++ idling before CPU mapping */ ++#define TTM_BO_PRIV_FLAG_MAX 1 ++/** ++ * struct ttm_bo_device - Buffer object driver device-specific data. ++ * ++ * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver. + * @man: An array of mem_type_managers. + * @addr_space_mm: Range manager for the device address space. + * lru_lock: Spinlock that protects the buffer+device lru lists and +@@ -399,32 +449,21 @@ struct ttm_bo_device { + /* + * Constant after bo device init / atomic. + */ +- +- struct ttm_mem_global *mem_glob; ++ struct list_head device_list; ++ struct ttm_bo_global *glob; + struct ttm_bo_driver *driver; +- struct page *dummy_read_page; +- struct ttm_mem_shrink shrink; +- +- size_t ttm_bo_extra_size; +- size_t ttm_bo_size; +- + rwlock_t vm_lock; ++ struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES]; + /* + * Protected by the vm lock. + */ +- struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES]; + struct rb_root addr_space_rb; + struct drm_mm addr_space_mm; + + /* +- * Might want to change this to one lock per manager. +- */ +- spinlock_t lru_lock; +- /* +- * Protected by the lru lock. ++ * Protected by the global:lru lock. + */ + struct list_head ddestroy; +- struct list_head swap_lru; + + /* + * Protected by load / firstopen / lastclose /unload sync. +@@ -640,6 +679,9 @@ extern int ttm_bo_pci_offset(struct ttm_bo_device *bdev, + unsigned long *bus_offset, + unsigned long *bus_size); + ++extern void ttm_bo_global_release(struct ttm_global_reference *ref); ++extern int ttm_bo_global_init(struct ttm_global_reference *ref); ++ + extern int ttm_bo_device_release(struct ttm_bo_device *bdev); + + /** +@@ -657,7 +699,7 @@ extern int ttm_bo_device_release(struct ttm_bo_device *bdev); + * !0: Failure. + */ + extern int ttm_bo_device_init(struct ttm_bo_device *bdev, +- struct ttm_mem_global *mem_glob, ++ struct ttm_bo_global *glob, + struct ttm_bo_driver *driver, + uint64_t file_page_offset, bool need_dma32); + +diff --git a/include/drm/ttm/ttm_memory.h b/include/drm/ttm/ttm_memory.h +index d8b8f04..6983a7c 100644 +--- a/include/drm/ttm/ttm_memory.h ++++ b/include/drm/ttm/ttm_memory.h +@@ -32,6 +32,7 @@ + #include <linux/spinlock.h> + #include <linux/wait.h> + #include <linux/errno.h> ++#include <linux/kobject.h> + + /** + * struct ttm_mem_shrink - callback to shrink TTM memory usage. +@@ -60,34 +61,33 @@ struct ttm_mem_shrink { + * @queue: Wait queue for processes suspended waiting for memory. + * @lock: Lock to protect the @shrink - and the memory accounting members, + * that is, essentially the whole structure with some exceptions. +- * @emer_memory: Lowmem memory limit available for root. +- * @max_memory: Lowmem memory limit available for non-root. +- * @swap_limit: Lowmem memory limit where the shrink workqueue kicks in. +- * @used_memory: Currently used lowmem memory. +- * @used_total_memory: Currently used total (lowmem + highmem) memory. +- * @total_memory_swap_limit: Total memory limit where the shrink workqueue +- * kicks in. +- * @max_total_memory: Total memory available to non-root processes. +- * @emer_total_memory: Total memory available to root processes. ++ * @zones: Array of pointers to accounting zones. ++ * @num_zones: Number of populated entries in the @zones array. ++ * @zone_kernel: Pointer to the kernel zone. ++ * @zone_highmem: Pointer to the highmem zone if there is one. ++ * @zone_dma32: Pointer to the dma32 zone if there is one. + * + * Note that this structure is not per device. It should be global for all + * graphics devices. + */ + ++#define TTM_MEM_MAX_ZONES 2 ++struct ttm_mem_zone; + struct ttm_mem_global { ++ struct kobject kobj; + struct ttm_mem_shrink *shrink; + struct workqueue_struct *swap_queue; + struct work_struct work; + wait_queue_head_t queue; + spinlock_t lock; +- uint64_t emer_memory; +- uint64_t max_memory; +- uint64_t swap_limit; +- uint64_t used_memory; +- uint64_t used_total_memory; +- uint64_t total_memory_swap_limit; +- uint64_t max_total_memory; +- uint64_t emer_total_memory; ++ struct ttm_mem_zone *zones[TTM_MEM_MAX_ZONES]; ++ unsigned int num_zones; ++ struct ttm_mem_zone *zone_kernel; ++#ifdef CONFIG_HIGHMEM ++ struct ttm_mem_zone *zone_highmem; ++#else ++ struct ttm_mem_zone *zone_dma32; ++#endif + }; + + /** +@@ -146,8 +146,13 @@ static inline void ttm_mem_unregister_shrink(struct ttm_mem_global *glob, + extern int ttm_mem_global_init(struct ttm_mem_global *glob); + extern void ttm_mem_global_release(struct ttm_mem_global *glob); + extern int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, +- bool no_wait, bool interruptible, bool himem); ++ bool no_wait, bool interruptible); + extern void ttm_mem_global_free(struct ttm_mem_global *glob, +- uint64_t amount, bool himem); ++ uint64_t amount); ++extern int ttm_mem_global_alloc_page(struct ttm_mem_global *glob, ++ struct page *page, ++ bool no_wait, bool interruptible); ++extern void ttm_mem_global_free_page(struct ttm_mem_global *glob, ++ struct page *page); + extern size_t ttm_round_pot(size_t size); + #endif +diff --git a/include/drm/ttm/ttm_module.h b/include/drm/ttm/ttm_module.h +index d1d4338..cf416ae 100644 +--- a/include/drm/ttm/ttm_module.h ++++ b/include/drm/ttm/ttm_module.h +@@ -32,6 +32,7 @@ + #define _TTM_MODULE_H_ + + #include <linux/kernel.h> ++struct kobject; + + #define TTM_PFX "[TTM] " + +@@ -54,5 +55,6 @@ extern void ttm_global_init(void); + extern void ttm_global_release(void); + extern int ttm_global_item_ref(struct ttm_global_reference *ref); + extern void ttm_global_item_unref(struct ttm_global_reference *ref); ++extern struct kobject *ttm_get_kobj(void); + + #endif /* _TTM_MODULE_H_ */ diff --git a/sys-kernel/thinkpad-sources/files/2.6.28/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch b/sys-kernel/thinkpad-sources/files/2.6.31/linux-phc-0.3.2-2.6.31.patch index 4a4db8b..e48f4a0 100644 --- a/sys-kernel/thinkpad-sources/files/2.6.28/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch +++ b/sys-kernel/thinkpad-sources/files/2.6.31/linux-phc-0.3.2-2.6.31.patch @@ -1,14 +1,15 @@ -diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c linux-source-2.6.26-rc9-custom8/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c ---- linux-source-2.6.26-rc9_orig/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c 2008-07-09 16:59:37.000000000 +0200 -+++ linux-source-2.6.26-rc9-custom8/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c 2008-07-09 12:41:37.000000000 +0200 +diff --new-file -a --unified=5 --recursive linux-source-2.6.31_orig/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c linux-source-2.6.31_phc/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c +--- linux-source-2.6.30_orig/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c 2009-07-14 09:15:09.864904000 +0200 ++++ linux-source-2.6.30_phc/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c 2009-07-18 09:31:50.687906676 +0200 + @@ -23,10 +23,14 @@ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. * * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ -+/* This file has been patched with Linux PHC: http://phc.athousandnights.de -+ * Patch version: linux-phc-0.3.1-kernel-vanilla-2.6.26.patch ++/* This file has been patched with Linux PHC: www.linux-phc.org ++ * Patch version: linux-phc-0.3.2 + */ + #include <linux/kernel.h> @@ -16,7 +17,7 @@ diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x8 #include <linux/init.h> #include <linux/smp.h> #include <linux/sched.h> -@@ -56,17 +60,22 @@ +@@ -59,16 +63,21 @@ SYSTEM_IO_CAPABLE, }; @@ -25,12 +26,11 @@ diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x8 +#define INTEL_MSR_VID_MASK (0x00ff) +#define INTEL_MSR_FID_MASK (0xff00) +#define INTEL_MSR_FID_SHIFT (0x8) -+#define PHC_VERSION_STRING "0.3.2:1" ++#define PHC_VERSION_STRING "0.3.2:2" struct acpi_cpufreq_data { struct acpi_processor_performance *acpi_data; struct cpufreq_frequency_table *freq_table; - unsigned int max_freq; unsigned int resume; unsigned int cpu_feature; + acpi_integer *original_controls; @@ -38,8 +38,8 @@ diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x8 static DEFINE_PER_CPU(struct acpi_cpufreq_data *, drv_data); - /* acpi_perf_data is a pointer to percpu data. */ -@@ -102,17 +111,18 @@ + struct acpi_msr_data { +@@ -108,17 +117,18 @@ } static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) @@ -52,7 +52,7 @@ diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x8 + fid = msr & INTEL_MSR_FID_MASK; perf = data->acpi_data; - for (i=0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { + for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { - if (msr == perf->states[data->freq_table[i].index].status) + if (fid == (perf->states[data->freq_table[i].index].status & INTEL_MSR_FID_MASK)) return data->freq_table[i].frequency; @@ -60,7 +60,7 @@ diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x8 return data->freq_table[0].frequency; } -@@ -740,10 +750,12 @@ +@@ -776,10 +786,12 @@ if (data) { cpufreq_frequency_table_put_attr(policy->cpu); per_cpu(drv_data, policy->cpu) = NULL; @@ -73,15 +73,12 @@ diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x8 return 0; } -@@ -757,12 +769,477 @@ +@@ -793,12 +805,474 @@ data->resume = 1; return 0; } -+ -+ -+ +/* sysfs interface to change operating points voltages */ + +static unsigned int extract_fid_from_control(unsigned int control) @@ -540,8 +537,8 @@ diff --new-file -a --unified=5 --recursive linux-source-2.6.26-rc9_orig/arch/x8 + static struct freq_attr *acpi_cpufreq_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, -+ &cpufreq_freq_attr_phc_version, + &cpufreq_freq_attr_scaling_available_freqs, ++ &cpufreq_freq_attr_phc_version, + &cpufreq_freq_attr_vids, + &cpufreq_freq_attr_default_vids, + &cpufreq_freq_attr_fids, diff --git a/sys-kernel/thinkpad-sources/files/2.6.28/01-mac80211_2.6.28-rc4-wl_frag+ack_v2.patch b/sys-kernel/thinkpad-sources/files/2.6.31/mac80211.compat08082009.wl_frag+ack_v1.patch index cd33cf2..8b7add3 100644 --- a/sys-kernel/thinkpad-sources/files/2.6.28/01-mac80211_2.6.28-rc4-wl_frag+ack_v2.patch +++ b/sys-kernel/thinkpad-sources/files/2.6.31/mac80211.compat08082009.wl_frag+ack_v1.patch @@ -2,7 +2,7 @@ diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c index 0855cac..221bed6 100644 --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c -@@ -611,11 +611,19 @@ ieee80211_tx_h_sequence(struct ieee80211_tx_data *tx) +@@ -677,11 +677,19 @@ int tid; /* * Packet injection may want to control the sequence @@ -15,9 +15,9 @@ index 0855cac..221bed6 100644 + * FIXME This may break hostapd and some other injectors. + * This should be done using a radiotap flag. */ -- if (unlikely(!info->control.vif)) -+ if (unlikely(info->flags & IEEE80211_TX_CTL_INJECTED) && -+ !(tx->sdata->u.mntr_flags & MONITOR_FLAG_COOK_FRAMES)) { +- if (unlikely(info->control.vif->type == NL80211_IFTYPE_MONITOR)) ++ if (unlikely((info->flags & IEEE80211_TX_CTL_INJECTED) && ++ !(tx->sdata->u.mntr_flags & MONITOR_FLAG_COOK_FRAMES))) { + if (!ieee80211_has_morefrags(hdr->frame_control)) + info->flags |= IEEE80211_TX_CTL_NO_ACK; return TX_CONTINUE; diff --git a/sys-kernel/thinkpad-sources/files/2.6.31/thinkpad-acpi-0.23-20090920-fix1.patch.gz b/sys-kernel/thinkpad-sources/files/2.6.31/thinkpad-acpi-0.23-20090920-fix1.patch.gz Binary files differnew file mode 100644 index 0000000..433f8fa --- /dev/null +++ b/sys-kernel/thinkpad-sources/files/2.6.31/thinkpad-acpi-0.23-20090920-fix1.patch.gz diff --git a/sys-kernel/thinkpad-sources/files/configs/config-for-core-2.6.27 b/sys-kernel/thinkpad-sources/files/configs/config-for-core-2.6.27 deleted file mode 100644 index dfe476a..0000000 --- a/sys-kernel/thinkpad-sources/files/configs/config-for-core-2.6.27 +++ /dev/null @@ -1,2393 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-thinkpad -# Mon Dec 1 13:16:10 2008 -# -# CONFIG_64BIT is not set -CONFIG_X86_32=y -# CONFIG_X86_64 is not set -CONFIG_X86=y -CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig" -# CONFIG_GENERIC_LOCKBREAK is not set -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_FAST_CMPXCHG_LOCAL=y -CONFIG_MMU=y -CONFIG_ZONE_DMA=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_HWEIGHT=y -# CONFIG_GENERIC_GPIO is not set -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -# CONFIG_RWSEM_GENERIC_SPINLOCK is not set -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -# CONFIG_GENERIC_TIME_VSYSCALL is not set -CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_HAVE_SETUP_PER_CPU_AREA=y -# CONFIG_HAVE_CPUMASK_OF_CPU_MAP is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ZONE_DMA32 is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -# CONFIG_AUDIT_ARCH is not set -CONFIG_ARCH_SUPPORTS_AOUT=y -CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_X86_SMP=y -CONFIG_X86_32_SMP=y -CONFIG_X86_HT=y -CONFIG_X86_BIOS_REBOOT=y -CONFIG_X86_TRAMPOLINE=y -CONFIG_KTIME_SCALAR=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -# CONFIG_TASKSTATS is not set -CONFIG_AUDIT=y -CONFIG_AUDITSYSCALL=y -CONFIG_AUDIT_TREE=y -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_CGROUPS is not set -CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -# CONFIG_EMBEDDED is not set -CONFIG_UID16=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y -# CONFIG_COMPAT_BRK is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_CLK is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y -CONFIG_STOP_MACHINE=y -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -CONFIG_LSF=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_BLK_DEV_INTEGRITY=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_CLASSIC_RCU=y - -# -# Processor type and features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_SMP=y -CONFIG_X86_FIND_SMP_CONFIG=y -CONFIG_X86_MPPARSE=y -CONFIG_X86_PC=y -# CONFIG_X86_ELAN is not set -# CONFIG_X86_VOYAGER is not set -# CONFIG_X86_GENERICARCH is not set -# CONFIG_X86_VSMP is not set -# CONFIG_X86_RDC321X is not set -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_PARAVIRT_GUEST is not set -# CONFIG_MEMTEST is not set -# CONFIG_M386 is not set -# CONFIG_M486 is not set -# CONFIG_M586 is not set -# CONFIG_M586TSC is not set -# CONFIG_M586MMX is not set -# CONFIG_M686 is not set -# CONFIG_MPENTIUMII is not set -# CONFIG_MPENTIUMIII is not set -# CONFIG_MPENTIUMM is not set -CONFIG_MPENTIUM4=y -# CONFIG_MK6 is not set -# CONFIG_MK7 is not set -# CONFIG_MK8 is not set -# CONFIG_MCRUSOE is not set -# CONFIG_MEFFICEON is not set -# CONFIG_MWINCHIPC6 is not set -# CONFIG_MWINCHIP2 is not set -# CONFIG_MWINCHIP3D is not set -# CONFIG_MGEODEGX1 is not set -# CONFIG_MGEODE_LX is not set -# CONFIG_MCYRIXIII is not set -# CONFIG_MVIAC3_2 is not set -# CONFIG_MVIAC7 is not set -# CONFIG_MPSC is not set -# CONFIG_MCORE2 is not set -# CONFIG_GENERIC_CPU is not set -# CONFIG_X86_GENERIC is not set -CONFIG_X86_CPU=y -CONFIG_X86_CMPXCHG=y -CONFIG_X86_L1_CACHE_SHIFT=7 -CONFIG_X86_XADD=y -CONFIG_X86_WP_WORKS_OK=y -CONFIG_X86_INVLPG=y -CONFIG_X86_BSWAP=y -CONFIG_X86_POPAD_OK=y -CONFIG_X86_INTEL_USERCOPY=y -CONFIG_X86_USE_PPRO_CHECKSUM=y -CONFIG_X86_TSC=y -CONFIG_X86_CMOV=y -CONFIG_X86_MINIMUM_CPU_FAMILY=4 -CONFIG_X86_DEBUGCTLMSR=y -CONFIG_HPET_TIMER=y -CONFIG_HPET_EMULATE_RTC=y -CONFIG_DMI=y -# CONFIG_IOMMU_HELPER is not set -CONFIG_NR_CPUS=2 -# CONFIG_SCHED_SMT is not set -CONFIG_SCHED_MC=y -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -# CONFIG_PREEMPT_RCU is not set -CONFIG_X86_LOCAL_APIC=y -CONFIG_X86_IO_APIC=y -CONFIG_X86_MCE=y -# CONFIG_X86_MCE_NONFATAL is not set -# CONFIG_X86_MCE_P4THERMAL is not set -CONFIG_VM86=y -# CONFIG_TOSHIBA is not set -# CONFIG_I8K is not set -# CONFIG_X86_REBOOTFIXUPS is not set -# CONFIG_MICROCODE is not set -# CONFIG_X86_MSR is not set -# CONFIG_X86_CPUID is not set -# CONFIG_NOHIGHMEM is not set -CONFIG_HIGHMEM4G=y -# CONFIG_HIGHMEM64G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_SPARSEMEM_STATIC=y -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_VIRT_TO_BUS=y -CONFIG_HIGHPTE=y -# CONFIG_X86_RESERVE_LOW_64K is not set -# CONFIG_MATH_EMULATION is not set -CONFIG_MTRR=y -CONFIG_MTRR_SANITIZER=y -CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 -CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 -CONFIG_X86_PAT=y -# CONFIG_EFI is not set -# CONFIG_IRQBALANCE is not set -CONFIG_SECCOMP=y -# CONFIG_HZ_100 is not set -# CONFIG_HZ_250 is not set -CONFIG_HZ_300=y -# CONFIG_HZ_1000 is not set -CONFIG_HZ=300 -CONFIG_SCHED_HRTICK=y -# CONFIG_KEXEC is not set -# CONFIG_CRASH_DUMP is not set -CONFIG_PHYSICAL_START=0x100000 -# CONFIG_RELOCATABLE is not set -CONFIG_PHYSICAL_ALIGN=0x100000 -CONFIG_HOTPLUG_CPU=y -# CONFIG_COMPAT_VDSO is not set -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP_SMP=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_HIBERNATION=y -CONFIG_PM_STD_PARTITION="/dev/sda5" -CONFIG_TOI_CORE=y - -# -# Image Storage (you need at least one allocator) -# -CONFIG_TOI_FILE=y -CONFIG_TOI_SWAP=y - -# -# General Options -# -CONFIG_TOI_DEFAULT_PRE_HIBERNATE="" -CONFIG_TOI_DEFAULT_POST_HIBERNATE="" -CONFIG_TOI_CRYPTO=y -CONFIG_TOI_USERUI=y -CONFIG_TOI_USERUI_DEFAULT_PATH="/usr/local/sbin/tuxonice_fbsplash" -# CONFIG_TOI_KEEP_IMAGE is not set -CONFIG_TOI_REPLACE_SWSUSP=y -# CONFIG_TOI_IGNORE_LATE_INITCALL is not set -CONFIG_TOI_CHECKSUM=y -CONFIG_TOI_DEFAULT_WAIT=25 -CONFIG_TOI_DEFAULT_EXTRA_PAGES_ALLOWANCE=15300 -# CONFIG_TOI_PAGEFLAGS_TEST is not set -CONFIG_TOI=y -CONFIG_ACPI=y -CONFIG_ACPI_SLEEP=y -CONFIG_ACPI_PROCFS=y -CONFIG_ACPI_PROCFS_POWER=y -CONFIG_ACPI_SYSFS_POWER=y -CONFIG_ACPI_PROC_EVENT=y -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -CONFIG_ACPI_BUTTON=y -CONFIG_ACPI_VIDEO=y -CONFIG_ACPI_FAN=y -CONFIG_ACPI_DOCK=y -CONFIG_ACPI_BAY=m -CONFIG_ACPI_PROCESSOR=y -CONFIG_ACPI_HOTPLUG_CPU=y -CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_WMI=y -# CONFIG_ACPI_ASUS is not set -# CONFIG_ACPI_TOSHIBA is not set -# CONFIG_ACPI_CUSTOM_DSDT is not set -CONFIG_ACPI_BLACKLIST_YEAR=0 -# CONFIG_ACPI_DEBUG is not set -CONFIG_ACPI_EC=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_POWER=y -CONFIG_ACPI_SYSTEM=y -CONFIG_X86_PM_TIMER=y -CONFIG_ACPI_CONTAINER=y -# CONFIG_ACPI_SBS is not set -# CONFIG_APM is not set - -# -# CPU Frequency scaling -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y - -# -# CPUFreq processor drivers -# -CONFIG_X86_ACPI_CPUFREQ=y -# CONFIG_X86_POWERNOW_K6 is not set -# CONFIG_X86_POWERNOW_K7 is not set -# CONFIG_X86_POWERNOW_K8 is not set -# CONFIG_X86_GX_SUSPMOD is not set -# CONFIG_X86_SPEEDSTEP_CENTRINO is not set -CONFIG_X86_SPEEDSTEP_ICH=y -CONFIG_X86_SPEEDSTEP_SMI=y -# CONFIG_X86_P4_CLOCKMOD is not set -# CONFIG_X86_CPUFREQ_NFORCE2 is not set -# CONFIG_X86_LONGRUN is not set -# CONFIG_X86_LONGHAUL is not set -# CONFIG_X86_E_POWERSAVER is not set - -# -# shared options -# -# CONFIG_X86_ACPI_CPUFREQ_PROC_INTF is not set -CONFIG_X86_SPEEDSTEP_LIB=y -# CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y - -# -# Bus options (PCI etc.) -# -CONFIG_PCI=y -# CONFIG_PCI_GOBIOS is not set -# CONFIG_PCI_GOMMCONFIG is not set -# CONFIG_PCI_GODIRECT is not set -# CONFIG_PCI_GOOLPC is not set -CONFIG_PCI_GOANY=y -CONFIG_PCI_BIOS=y -CONFIG_PCI_DIRECT=y -CONFIG_PCI_MMCONFIG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCIEPORTBUS=y -CONFIG_HOTPLUG_PCI_PCIE=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEBUG is not set -CONFIG_ARCH_SUPPORTS_MSI=y -CONFIG_PCI_MSI=y -CONFIG_PCI_LEGACY=y -# CONFIG_PCI_DEBUG is not set -CONFIG_HT_IRQ=y -CONFIG_ISA_DMA_API=y -CONFIG_ISA=y -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SCx200 is not set -# CONFIG_OLPC is not set -CONFIG_PCCARD=y -# CONFIG_PCMCIA_DEBUG is not set -CONFIG_PCMCIA=y -CONFIG_PCMCIA_LOAD_CIS=y -CONFIG_PCMCIA_IOCTL=y -CONFIG_CARDBUS=y - -# -# PC-card bridges -# -CONFIG_YENTA=y -CONFIG_YENTA_O2=y -CONFIG_YENTA_RICOH=y -CONFIG_YENTA_TI=y -CONFIG_YENTA_ENE_TUNE=y -CONFIG_YENTA_TOSHIBA=y -# CONFIG_PD6729 is not set -# CONFIG_I82092 is not set -# CONFIG_I82365 is not set -# CONFIG_TCIC is not set -CONFIG_PCMCIA_PROBE=y -CONFIG_PCCARD_NONSTATIC=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_FAKE is not set -# CONFIG_HOTPLUG_PCI_COMPAQ is not set -CONFIG_HOTPLUG_PCI_IBM=y -CONFIG_HOTPLUG_PCI_ACPI=y -# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set - -# -# Executable file formats / Emulations -# -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_AOUT=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_MULTIPLE_TABLES is not set -# CONFIG_IP_ROUTE_MULTIPATH is not set -# CONFIG_IP_ROUTE_VERBOSE is not set -# CONFIG_IP_PNP is not set -CONFIG_NET_IPIP=y -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=y -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y -# CONFIG_IP_VS is not set -CONFIG_IPV6=y -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -CONFIG_IPV6_MIP6=y -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=y -CONFIG_NETFILTER_NETLINK_QUEUE=y -CONFIG_NETFILTER_NETLINK_LOG=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -# CONFIG_NF_CT_PROTO_DCCP is not set -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -# CONFIG_NF_CT_PROTO_UDPLITE is not set -# CONFIG_NF_CONNTRACK_AMANDA is not set -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -# CONFIG_NF_CONNTRACK_SANE is not set -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XTABLES=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=y -CONFIG_NETFILTER_XT_MATCH_DSCP=m -# CONFIG_NETFILTER_XT_MATCH_ESP is not set -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=y -CONFIG_NETFILTER_XT_MATCH_SCTP=y -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TCPMSS=y -# CONFIG_NETFILTER_XT_MATCH_TIME is not set -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV4=m -# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set -CONFIG_IP_NF_QUEUE=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_RECENT=y -CONFIG_IP_NF_MATCH_ECN=y -# CONFIG_IP_NF_MATCH_AH is not set -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_MATCH_ADDRTYPE=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_TARGET_LOG=y -CONFIG_IP_NF_TARGET_ULOG=y -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_PROTO_SCTP=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -# CONFIG_NF_NAT_AMANDA is not set -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_TARGET_ECN=y -CONFIG_IP_NF_TARGET_TTL=y -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RT=y -CONFIG_IP6_NF_MATCH_OPTS=y -CONFIG_IP6_NF_MATCH_FRAG=y -CONFIG_IP6_NF_MATCH_HL=y -CONFIG_IP6_NF_MATCH_IPV6HEADER=y -# CONFIG_IP6_NF_MATCH_AH is not set -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_LOG=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_TARGET_HL=y -CONFIG_IP6_NF_RAW=y -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -# CONFIG_NET_SCH_CBQ is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_NETEM is not set - -# -# Classification -# -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_TCINDEX is not set -# CONFIG_NET_CLS_ROUTE4 is not set -CONFIG_NET_CLS_ROUTE=y -# CONFIG_NET_CLS_FW is not set -# CONFIG_NET_CLS_U32 is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_CLS_FLOW is not set -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_SCH_FIFO=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -# CONFIG_BT_BNEP is not set -CONFIG_BT_HIDP=m - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=m -# CONFIG_BT_HCIUART is not set -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBPA10X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIDTL1 is not set -# CONFIG_BT_HCIBT3C is not set -# CONFIG_BT_HCIBLUECARD is not set -# CONFIG_BT_HCIBTUART is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_AF_RXRPC is not set - -# -# Wireless -# -CONFIG_CFG80211=m -CONFIG_NL80211=y -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_MAC80211=m - -# -# Rate control algorithm selection -# -CONFIG_MAC80211_RC_PID=y -CONFIG_MAC80211_RC_DEFAULT_PID=y -CONFIG_MAC80211_RC_DEFAULT="pid" -CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_RFKILL=y -CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_LEDS=y -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -CONFIG_PARPORT=y -CONFIG_PARPORT_PC=y -# CONFIG_PARPORT_SERIAL is not set -# CONFIG_PARPORT_PC_FIFO is not set -# CONFIG_PARPORT_PC_SUPERIO is not set -# CONFIG_PARPORT_PC_PCMCIA is not set -# CONFIG_PARPORT_GSC is not set -# CONFIG_PARPORT_AX88796 is not set -# CONFIG_PARPORT_1284 is not set -CONFIG_PNP=y -# CONFIG_PNP_DEBUG is not set - -# -# Protocols -# -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set -CONFIG_PNPACPI=y -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_UB is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_MISC_DEVICES=y -# CONFIG_IBM_ASM is not set -# CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_ACER_WMI is not set -# CONFIG_ASUS_LAPTOP is not set -# CONFIG_FUJITSU_LAPTOP is not set -# CONFIG_TC1100_WMI is not set -# CONFIG_HP_WMI is not set -# CONFIG_MSI_LAPTOP is not set -# CONFIG_COMPAL_LAPTOP is not set -# CONFIG_SONY_LAPTOP is not set -CONFIG_THINKPAD_ACPI=m -# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set -# CONFIG_THINKPAD_ACPI_DEBUG is not set -# CONFIG_THINKPAD_ACPI_BAY is not set -# CONFIG_THINKPAD_ACPI_VIDEO is not set -CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y -CONFIG_INTEL_MENLOW=m -# CONFIG_EEEPC_LAPTOP is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set -# CONFIG_SCSI_DH is not set -CONFIG_ATA=y -# CONFIG_ATA_NONSTANDARD is not set -CONFIG_ATA_ACPI=y -# CONFIG_SATA_PMP is not set -CONFIG_SATA_AHCI=y -# CONFIG_SATA_SIL24 is not set -CONFIG_ATA_SFF=y -# CONFIG_SATA_SVW is not set -CONFIG_ATA_PIIX=y -# CONFIG_SATA_MV is not set -# CONFIG_SATA_NV is not set -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set -# CONFIG_SATA_PROMISE is not set -# CONFIG_SATA_SX4 is not set -# CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set -# CONFIG_SATA_INIC162X is not set -CONFIG_PATA_ACPI=y -# CONFIG_PATA_ALI is not set -# CONFIG_PATA_AMD is not set -# CONFIG_PATA_ARTOP is not set -# CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CS5520 is not set -# CONFIG_PATA_CS5530 is not set -# CONFIG_PATA_CS5535 is not set -# CONFIG_PATA_CS5536 is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_ATA_GENERIC is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_LEGACY is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_OLDPIIX is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_NS87415 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_OPTIDMA is not set -CONFIG_PATA_PCMCIA=m -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_QDI is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RZ1000 is not set -# CONFIG_PATA_SC1200 is not set -# CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set -# CONFIG_PATA_WINBOND_VLB is not set -# CONFIG_PATA_SCH is not set -# CONFIG_MD is not set -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# Enable only one of the two stacks, unless you know what you are doing -# -# CONFIG_FIREWIRE is not set -# CONFIG_IEEE1394 is not set -# CONFIG_I2O is not set -# CONFIG_MACINTOSH_DRIVERS is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -CONFIG_TUN=y -# CONFIG_VETH is not set -# CONFIG_NET_SB1000 is not set -# CONFIG_ARCNET is not set -# CONFIG_NET_ETHERNET is not set -CONFIG_MII=m -CONFIG_NETDEV_1000=y -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -CONFIG_E1000=m -CONFIG_E1000_DISABLE_PACKET_SPLIT=y -CONFIG_E1000E=m -# CONFIG_IP1000 is not set -CONFIG_IGB=m -# CONFIG_IGB_LRO is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_QLA3XXX is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -# CONFIG_PCMCIA_RAYCS is not set -# CONFIG_IPW2100 is not set -# CONFIG_IPW2200 is not set -# CONFIG_LIBERTAS is not set -# CONFIG_AIRO is not set -# CONFIG_HERMES is not set -# CONFIG_ATMEL is not set -# CONFIG_AIRO_CS is not set -# CONFIG_PCMCIA_WL3501 is not set -# CONFIG_PRISM54 is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set -# CONFIG_RTL8180 is not set -# CONFIG_RTL8187 is not set -# CONFIG_ADM8211 is not set -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_P54_COMMON is not set -CONFIG_ATH5K=m -# CONFIG_ATH5K_DEBUG is not set -CONFIG_ATH9K=m -CONFIG_IWLWIFI=m -CONFIG_IWLCORE=m -CONFIG_IWLWIFI_LEDS=y -CONFIG_IWLWIFI_RFKILL=y -# CONFIG_IWLWIFI_DEBUG is not set -CONFIG_IWLAGN=m -CONFIG_IWLAGN_SPECTRUM_MEASUREMENT=y -CONFIG_IWLAGN_LEDS=y -# CONFIG_IWL4965 is not set -CONFIG_IWL5000=y -CONFIG_IWL3945=m -CONFIG_IWL3945_RFKILL=y -CONFIG_IWL3945_SPECTRUM_MEASUREMENT=y -CONFIG_IWL3945_LEDS=y -# CONFIG_IWL3945_DEBUG is not set -# CONFIG_HOSTAP is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -# CONFIG_ZD1211RW is not set -# CONFIG_RT2X00 is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -CONFIG_USB_HSO=m -CONFIG_NET_PCMCIA=y -CONFIG_PCMCIA_3C589=m -CONFIG_PCMCIA_3C574=m -CONFIG_PCMCIA_FMVJ18X=m -CONFIG_PCMCIA_PCNET=m -CONFIG_PCMCIA_NMCLAN=m -CONFIG_PCMCIA_SMC91C92=m -CONFIG_PCMCIA_XIRC2PS=m -CONFIG_PCMCIA_AXNET=m -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -CONFIG_PPP=m -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -CONFIG_PPPOL2TP=m -# CONFIG_SLIP is not set -CONFIG_SLHC=m -# CONFIG_NET_FC is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=m - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1400 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=1050 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_INPORT is not set -# CONFIG_MOUSE_LOGIBM is not set -# CONFIG_MOUSE_PC110PAD is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_PCSPKR is not set -# CONFIG_INPUT_APANEL is not set -# CONFIG_INPUT_WISTRON_BTNS is not set -# CONFIG_INPUT_ATLAS_BTNS is not set -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -CONFIG_INPUT_UINPUT=m - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PARKBD is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CKO=y -CONFIG_VT_PRINTK_EMERG_COLOR=0x09 -CONFIG_VT_PRINTK_ALERT_COLOR=0x01 -CONFIG_VT_PRINTK_CRIT_COLOR=0x05 -CONFIG_VT_PRINTK_ERR_COLOR=0x07 -CONFIG_VT_PRINTK_WARNING_COLOR=0x0B -CONFIG_VT_PRINTK_NOTICE_COLOR=0x02 -CONFIG_VT_PRINTK_INFO_COLOR=0x04 -CONFIG_VT_PRINTK_DEBUG_COLOR=0x07 -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_NOZOMI=m - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_CONSOLE is not set -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_PNP=y -CONFIG_SERIAL_8250_CS=m -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -CONFIG_PRINTER=y -# CONFIG_LP_CONSOLE is not set -# CONFIG_PPDEV is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -CONFIG_NVRAM=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set - -# -# PCMCIA character devices -# -# CONFIG_SYNCLINK_CS is not set -# CONFIG_CARDMAN_4000 is not set -# CONFIG_CARDMAN_4040 is not set -# CONFIG_IPWIRELESS is not set -# CONFIG_MWAVE is not set -# CONFIG_PC8736x_GPIO is not set -# CONFIG_NSC_GPIO is not set -# CONFIG_CS5535_GPIO is not set -# CONFIG_RAW_DRIVER is not set -CONFIG_HPET=y -CONFIG_HPET_MMAP=y -# CONFIG_HANGCHECK_TIMER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set -CONFIG_DEVPORT=y -CONFIG_I2C=m -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_ALGOBIT=m - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Graphics adapter I2C/DDC channel drivers -# -# CONFIG_I2C_VOODOO3 is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set -# CONFIG_SCx200_ACB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_AT24 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ABITUGURU3 is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_K8TEMP is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set -# CONFIG_SENSORS_FSCHMD is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -CONFIG_SENSORS_CORETEMP=y -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_HDAPS is not set -# CONFIG_SENSORS_APPLESMC is not set -# CONFIG_HWMON_DEBUG_CHIP is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -# CONFIG_WATCHDOG is not set - -# -# Sonics Silicon Backplane -# -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m -# CONFIG_VIDEO_ALLOW_V4L1 is not set -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_VIDEO_SAA7146=m -CONFIG_VIDEO_SAA7146_VV=m -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_DMA_SG=m -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_BTCX=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -CONFIG_VIDEO_IR_I2C=m -CONFIG_VIDEO_TVAUDIO=m -CONFIG_VIDEO_TDA7432=m -CONFIG_VIDEO_TDA9875=m -CONFIG_VIDEO_MSP3400=m -CONFIG_VIDEO_CS53L32A=m -CONFIG_VIDEO_WM8775=m -CONFIG_VIDEO_OV7670=m -CONFIG_VIDEO_SAA711X=m -CONFIG_VIDEO_TVP5150=m -CONFIG_VIDEO_CX25840=m -CONFIG_VIDEO_CX2341X=m -CONFIG_VIDEO_VIVI=m -CONFIG_VIDEO_BT848=m -# CONFIG_VIDEO_BT848_DVB is not set -CONFIG_VIDEO_SAA6588=m -CONFIG_VIDEO_SAA5246A=m -CONFIG_VIDEO_SAA5249=m -CONFIG_VIDEO_SAA7134=m -# CONFIG_VIDEO_SAA7134_ALSA is not set -CONFIG_VIDEO_SAA7134_DVB=m -CONFIG_VIDEO_HEXIUM_ORION=m -CONFIG_VIDEO_HEXIUM_GEMINI=m -CONFIG_VIDEO_CX88=m -# CONFIG_VIDEO_CX88_ALSA is not set -CONFIG_VIDEO_CX88_BLACKBIRD=m -CONFIG_VIDEO_CX88_DVB=m -CONFIG_VIDEO_CX88_VP3054=m -# CONFIG_VIDEO_CX23885 is not set -# CONFIG_VIDEO_AU0828 is not set -# CONFIG_VIDEO_CX18 is not set -CONFIG_VIDEO_CAFE_CCIC=m -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -# CONFIG_USB_GSPCA is not set -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_USB_ET61X251=m -CONFIG_USB_SN9C102=m -CONFIG_USB_ZC0301=m -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -# CONFIG_USB_S2255 is not set -CONFIG_SOC_CAMERA=m -CONFIG_SOC_CAMERA_MT9M001=m -CONFIG_SOC_CAMERA_MT9V022=m -# CONFIG_SOC_CAMERA_PLATFORM is not set -# CONFIG_VIDEO_SH_MOBILE_CEU is not set -# CONFIG_RADIO_ADAPTERS is not set -CONFIG_DVB_CAPTURE_DRIVERS=y - -# -# Supported SAA7146 based PCI Adapters -# -# CONFIG_TTPCI_EEPROM is not set -# CONFIG_DVB_AV7110 is not set -# CONFIG_DVB_BUDGET_CORE is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -# CONFIG_DVB_USB_DW2102 is not set -# CONFIG_DVB_USB_ANYSEE is not set -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m -CONFIG_DVB_CINERGYT2=m -# CONFIG_DVB_CINERGYT2_TUNING is not set -# CONFIG_DVB_SIANO_SMS1XXX is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_DVB_B2C2_FLEXCOP_PCI=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set - -# -# Supported BT878 Adapters -# -CONFIG_DVB_BT8XX=m - -# -# Supported Pluto2 Adapters -# -CONFIG_DVB_PLUTO2=m - -# -# Supported DVB Frontends -# - -# -# Customise DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set - -# -# DVB-S (satellite) frontends -# -CONFIG_DVB_CX24110=m -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA8083=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_VES1X93=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_TUA6100=m - -# -# DVB-T (terrestrial) frontends -# -CONFIG_DVB_SP8870=m -CONFIG_DVB_SP887X=m -CONFIG_DVB_CX22700=m -CONFIG_DVB_CX22702=m -# CONFIG_DVB_DRX397XD is not set -CONFIG_DVB_L64781=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m - -# -# DVB-C (cable) frontends -# -CONFIG_DVB_VES1820=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m - -# -# ATSC (North American/Korean Terrestrial/Cable DTV) frontends -# -CONFIG_DVB_NXT200X=m -CONFIG_DVB_OR51211=m -CONFIG_DVB_OR51132=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_AU8522=m -CONFIG_DVB_S5H1411=m - -# -# Digital terrestrial only tuners/PLL -# -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m - -# -# SEC control devices for DVB-S -# -CONFIG_DVB_LNBP21=m -CONFIG_DVB_ISL6405=m -CONFIG_DVB_ISL6421=m -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -# CONFIG_FB is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -# CONFIG_LCD_ILI9320 is not set -CONFIG_LCD_PLATFORM=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_CORGI is not set -# CONFIG_BACKLIGHT_PROGEAR is not set -# CONFIG_BACKLIGHT_MBP_NVIDIA is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -CONFIG_VGA_CONSOLE=y -# CONFIG_VGACON_SOFT_SCROLLBACK is not set -# CONFIG_VIDEO_SELECT is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_VMASTER=y -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ISA is not set -CONFIG_SND_PCI=y -# CONFIG_SND_AD1889 is not set -# CONFIG_SND_ALS300 is not set -# CONFIG_SND_ALS4000 is not set -# CONFIG_SND_ALI5451 is not set -# CONFIG_SND_ATIIXP is not set -# CONFIG_SND_ATIIXP_MODEM is not set -# CONFIG_SND_AU8810 is not set -# CONFIG_SND_AU8820 is not set -# CONFIG_SND_AU8830 is not set -# CONFIG_SND_AW2 is not set -# CONFIG_SND_AZT3328 is not set -# CONFIG_SND_BT87X is not set -# CONFIG_SND_CA0106 is not set -# CONFIG_SND_CMIPCI is not set -# CONFIG_SND_OXYGEN is not set -# CONFIG_SND_CS4281 is not set -# CONFIG_SND_CS46XX is not set -# CONFIG_SND_CS5530 is not set -# CONFIG_SND_CS5535AUDIO is not set -# CONFIG_SND_DARLA20 is not set -# CONFIG_SND_GINA20 is not set -# CONFIG_SND_LAYLA20 is not set -# CONFIG_SND_DARLA24 is not set -# CONFIG_SND_GINA24 is not set -# CONFIG_SND_LAYLA24 is not set -# CONFIG_SND_MONA is not set -# CONFIG_SND_MIA is not set -# CONFIG_SND_ECHO3G is not set -# CONFIG_SND_INDIGO is not set -# CONFIG_SND_INDIGOIO is not set -# CONFIG_SND_INDIGODJ is not set -# CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_ENS1370 is not set -# CONFIG_SND_ENS1371 is not set -# CONFIG_SND_ES1938 is not set -# CONFIG_SND_ES1968 is not set -# CONFIG_SND_FM801 is not set -CONFIG_SND_HDA_INTEL=m -# CONFIG_SND_HDA_HWDEP is not set -# CONFIG_SND_HDA_CODEC_REALTEK is not set -CONFIG_SND_HDA_CODEC_ANALOG=y -# CONFIG_SND_HDA_CODEC_SIGMATEL is not set -# CONFIG_SND_HDA_CODEC_VIA is not set -# CONFIG_SND_HDA_CODEC_ATIHDMI is not set -# CONFIG_SND_HDA_CODEC_CONEXANT is not set -# CONFIG_SND_HDA_CODEC_CMEDIA is not set -# CONFIG_SND_HDA_CODEC_SI3054 is not set -# CONFIG_SND_HDA_GENERIC is not set -CONFIG_SND_HDA_POWER_SAVE=y -CONFIG_SND_HDA_POWER_SAVE_DEFAULT=5 -# CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set -# CONFIG_SND_HIFIER is not set -# CONFIG_SND_ICE1712 is not set -# CONFIG_SND_ICE1724 is not set -# CONFIG_SND_INTEL8X0 is not set -# CONFIG_SND_INTEL8X0M is not set -# CONFIG_SND_KORG1212 is not set -# CONFIG_SND_MAESTRO3 is not set -# CONFIG_SND_MIXART is not set -# CONFIG_SND_NM256 is not set -# CONFIG_SND_PCXHR is not set -# CONFIG_SND_RIPTIDE is not set -# CONFIG_SND_RME32 is not set -# CONFIG_SND_RME96 is not set -# CONFIG_SND_RME9652 is not set -# CONFIG_SND_SIS7019 is not set -# CONFIG_SND_SONICVIBES is not set -# CONFIG_SND_TRIDENT is not set -# CONFIG_SND_VIA82XX is not set -# CONFIG_SND_VIA82XX_MODEM is not set -# CONFIG_SND_VIRTUOSO is not set -# CONFIG_SND_VX222 is not set -# CONFIG_SND_YMFPCI is not set -# CONFIG_SND_USB is not set -# CONFIG_SND_PCMCIA is not set -# CONFIG_SND_SOC is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set -CONFIG_USB_HIDDEV=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG is not set -# CONFIG_USB_MON is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -CONFIG_USB_UHCI_HCD=m -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -CONFIG_USB_PRINTER=y -# CONFIG_USB_WDM is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# may also be needed; see USB_STORAGE Help for more information -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set -CONFIG_USB_SERIAL=m -# CONFIG_USB_EZUSB is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP2101 is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -CONFIG_USB_SERIAL_FTDI_SIO=m -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_GADGET is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_CLEVO_MAIL is not set -# CONFIG_LEDS_PCA955X is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -# CONFIG_EDAC is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -CONFIG_RTC_DRV_CMOS=y -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -CONFIG_DMADEVICES=y - -# -# DMA Devices -# -# CONFIG_INTEL_IOATDMA is not set -CONFIG_AUXDISPLAY=y -# CONFIG_KS0108 is not set -# CONFIG_UIO is not set - -# -# Firmware Drivers -# -# CONFIG_EDD is not set -CONFIG_FIRMWARE_MEMMAP=y -# CONFIG_DELL_RBU is not set -# CONFIG_DCDBAS is not set -CONFIG_DMIID=y -# CONFIG_ISCSI_IBFT_FIND is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4DEV_FS=y -CONFIG_EXT4DEV_FS_XATTR=y -CONFIG_EXT4DEV_FS_POSIX_ACL=y -CONFIG_EXT4DEV_FS_SECURITY=y -CONFIG_JBD=y -CONFIG_JBD2=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y -# CONFIG_XFS_DEBUG is not set -# CONFIG_OCFS2_FS is not set -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=y -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=850 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFSD=y -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=y -# CONFIG_SMB_NLS_DEFAULT is not set -CONFIG_CIFS=y -CONFIG_CIFS_STATS=y -# CONFIG_CIFS_STATS2 is not set -CONFIG_CIFS_WEAK_PW_HASH=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -# CONFIG_CIFS_DEBUG2 is not set -CONFIG_CIFS_EXPERIMENTAL=y -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf8" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=y -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=y -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -CONFIG_UNUSED_SYMBOLS=y -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -# CONFIG_DETECT_SOFTLOCKUP is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_HIGHMEM is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -CONFIG_DEBUG_MEMORY_INIT=y -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_FRAME_POINTER is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SYSPROF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_STRICT_DEVMEM is not set -# CONFIG_X86_VERBOSE_BOOTUP is not set -CONFIG_EARLY_PRINTK=y -# CONFIG_DEBUG_STACKOVERFLOW is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -# CONFIG_X86_PTDUMP is not set -# CONFIG_DEBUG_RODATA is not set -# CONFIG_DEBUG_NX_TEST is not set -# CONFIG_4KSTACKS is not set -CONFIG_DOUBLEFAULT=y -# CONFIG_MMIOTRACE is not set -CONFIG_IO_DELAY_TYPE_0X80=0 -CONFIG_IO_DELAY_TYPE_0XED=1 -CONFIG_IO_DELAY_TYPE_UDELAY=2 -CONFIG_IO_DELAY_TYPE_NONE=3 -CONFIG_IO_DELAY_0X80=y -# CONFIG_IO_DELAY_0XED is not set -# CONFIG_IO_DELAY_UDELAY is not set -# CONFIG_IO_DELAY_NONE is not set -CONFIG_DEFAULT_IO_DELAY_TYPE=0 -# CONFIG_CPA_DEBUG is not set -# CONFIG_OPTIMIZE_INLINING is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_GF128MUL=m -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=y -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -CONFIG_CRYPTO_XCBC=y - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_AES_586=y -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_CAMELLIA=y -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=y -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SALSA20_586 is not set -# CONFIG_CRYPTO_SEED is not set -CONFIG_CRYPTO_SERPENT=y -# CONFIG_CRYPTO_TEA is not set -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_TWOFISH_COMMON=y -# CONFIG_CRYPTO_TWOFISH_586 is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_LZF=y -# CONFIG_CRYPTO_HW is not set -CONFIG_HAVE_KVM=y -# CONFIG_VIRTUALIZATION is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_CRC_CCITT=m -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_AUDIT_GENERIC=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=m -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=y -CONFIG_TEXTSEARCH_BM=y -CONFIG_TEXTSEARCH_FSM=y -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y diff --git a/sys-kernel/thinkpad-sources/files/configs/config-for-core-2.6.28-r1 b/sys-kernel/thinkpad-sources/files/configs/config-for-core-2.6.31 index dfe7ef6..bb4166c 100644 --- a/sys-kernel/thinkpad-sources/files/configs/config-for-core-2.6.28-r1 +++ b/sys-kernel/thinkpad-sources/files/configs/config-for-core-2.6.31 @@ -1,12 +1,13 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.28-thinkpad-r1 -# Fri Jan 9 09:55:32 2009 +# Linux kernel version: 2.6.31-thinkpad +# Sat Oct 3 11:24:22 2009 # # CONFIG_64BIT is not set CONFIG_X86_32=y # CONFIG_X86_64 is not set CONFIG_X86=y +CONFIG_OUTPUT_FORMAT="elf32-i386" CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig" CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y @@ -33,6 +34,7 @@ CONFIG_ARCH_HAS_CPU_RELAX=y CONFIG_ARCH_HAS_DEFAULT_IDLE=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_HAVE_DYNAMIC_PER_CPU_AREA=y # CONFIG_HAVE_CPUMASK_OF_CPU_MAP is not set CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y @@ -40,17 +42,19 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y # CONFIG_AUDIT_ARCH is not set CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_X86_SMP=y CONFIG_USE_GENERIC_SMP_HELPERS=y CONFIG_X86_32_SMP=y CONFIG_X86_HT=y -CONFIG_X86_BIOS_REBOOT=y CONFIG_X86_TRAMPOLINE=y +CONFIG_X86_32_LAZY_GS=y CONFIG_KTIME_SCALAR=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -60,36 +64,53 @@ CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y # CONFIG_TASKSTATS is not set CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y CONFIG_AUDIT_TREE=y + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_CGROUPS is not set CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y CONFIG_GROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_RT_GROUP_SCHED is not set CONFIG_USER_SCHED=y # CONFIG_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_IPC_NS is not set # CONFIG_USER_NS is not set # CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set # CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y @@ -101,20 +122,27 @@ CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y -# CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +CONFIG_PERF_COUNTERS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set +CONFIG_SLUB_DEBUG=y +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set @@ -125,10 +153,16 @@ CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -136,13 +170,10 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -CONFIG_LSF=y -# CONFIG_BLK_DEV_BSG is not set +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_INTEGRITY=y # @@ -157,7 +188,6 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_CLASSIC_RCU=y CONFIG_FREEZER=y # @@ -168,15 +198,11 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_SMP=y -CONFIG_X86_FIND_SMP_CONFIG=y +# CONFIG_SPARSE_IRQ is not set CONFIG_X86_MPPARSE=y -CONFIG_X86_PC=y -# CONFIG_X86_ELAN is not set -# CONFIG_X86_VOYAGER is not set -# CONFIG_X86_GENERICARCH is not set -# CONFIG_X86_VSMP is not set -# CONFIG_X86_RDC321X is not set -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +# CONFIG_X86_BIGSMP is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y # CONFIG_PARAVIRT_GUEST is not set # CONFIG_MEMTEST is not set # CONFIG_M386 is not set @@ -188,7 +214,7 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_MPENTIUMII is not set # CONFIG_MPENTIUMIII is not set # CONFIG_MPENTIUMM is not set -CONFIG_MPENTIUM4=y +# CONFIG_MPENTIUM4 is not set # CONFIG_MK6 is not set # CONFIG_MK7 is not set # CONFIG_MK8 is not set @@ -202,12 +228,14 @@ CONFIG_MPENTIUM4=y # CONFIG_MVIAC3_2 is not set # CONFIG_MVIAC7 is not set # CONFIG_MPSC is not set -# CONFIG_MCORE2 is not set +CONFIG_MCORE2=y # CONFIG_GENERIC_CPU is not set # CONFIG_X86_GENERIC is not set CONFIG_X86_CPU=y +CONFIG_X86_L1_CACHE_BYTES=64 +CONFIG_X86_INTERNODE_CACHE_BYTES=64 CONFIG_X86_CMPXCHG=y -CONFIG_X86_L1_CACHE_SHIFT=7 +CONFIG_X86_L1_CACHE_SHIFT=6 CONFIG_X86_XADD=y CONFIG_X86_WP_WORKS_OK=y CONFIG_X86_INVLPG=y @@ -222,7 +250,7 @@ CONFIG_X86_DEBUGCTLMSR=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_CYRIX_32=y CONFIG_CPU_SUP_AMD=y -CONFIG_CPU_SUP_CENTAUR_32=y +CONFIG_CPU_SUP_CENTAUR=y CONFIG_CPU_SUP_TRANSMETA_32=y CONFIG_CPU_SUP_UMC_32=y # CONFIG_X86_DS is not set @@ -230,18 +258,25 @@ CONFIG_HPET_TIMER=y CONFIG_HPET_EMULATE_RTC=y CONFIG_DMI=y # CONFIG_IOMMU_HELPER is not set +# CONFIG_IOMMU_API is not set CONFIG_NR_CPUS=2 # CONFIG_SCHED_SMT is not set CONFIG_SCHED_MC=y # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y -# CONFIG_PREEMPT_RCU is not set CONFIG_X86_LOCAL_APIC=y CONFIG_X86_IO_APIC=y +# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set CONFIG_X86_MCE=y -# CONFIG_X86_MCE_NONFATAL is not set -# CONFIG_X86_MCE_P4THERMAL is not set +# CONFIG_X86_OLD_MCE is not set +CONFIG_X86_NEW_MCE=y +CONFIG_X86_MCE_INTEL=y +# CONFIG_X86_MCE_AMD is not set +# CONFIG_X86_ANCIENT_MCE is not set +CONFIG_X86_MCE_THRESHOLD=y +# CONFIG_X86_MCE_INJECT is not set +CONFIG_X86_THERMAL_VECTOR=y CONFIG_VM86=y # CONFIG_TOSHIBA is not set # CONFIG_I8K is not set @@ -249,6 +284,7 @@ CONFIG_VM86=y # CONFIG_MICROCODE is not set # CONFIG_X86_MSR is not set # CONFIG_X86_CPUID is not set +# CONFIG_X86_CPU_DEBUG is not set # CONFIG_NOHIGHMEM is not set CONFIG_HIGHMEM4G=y # CONFIG_HIGHMEM64G is not set @@ -267,12 +303,13 @@ CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPARSEMEM_STATIC=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_HIGHPTE=y # CONFIG_X86_CHECK_BIOS_CORRUPTION is not set # CONFIG_X86_RESERVE_LOW_64K is not set @@ -284,6 +321,7 @@ CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 CONFIG_X86_PAT=y # CONFIG_EFI is not set CONFIG_SECCOMP=y +# CONFIG_CC_STACKPROTECTOR is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set CONFIG_HZ_300=y @@ -292,7 +330,7 @@ CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set -CONFIG_PHYSICAL_START=0x100000 +CONFIG_PHYSICAL_START=0x1000000 # CONFIG_RELOCATABLE is not set CONFIG_PHYSICAL_ALIGN=0x100000 CONFIG_HOTPLUG_CPU=y @@ -309,6 +347,7 @@ CONFIG_PM_SLEEP_SMP=y CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y +CONFIG_HIBERNATION_NVS=y CONFIG_HIBERNATION=y CONFIG_PM_STD_PARTITION="/dev/sda5" CONFIG_TOI_CORE=y @@ -322,8 +361,6 @@ CONFIG_TOI_SWAP=y # # General Options # -CONFIG_TOI_DEFAULT_PRE_HIBERNATE="" -CONFIG_TOI_DEFAULT_POST_HIBERNATE="" CONFIG_TOI_CRYPTO=y CONFIG_TOI_USERUI=y CONFIG_TOI_USERUI_DEFAULT_PATH="/usr/local/sbin/tuxonice_fbsplash" @@ -349,14 +386,10 @@ CONFIG_ACPI_DOCK=y CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_WMI=y -# CONFIG_ACPI_ASUS is not set -# CONFIG_ACPI_TOSHIBA is not set # CONFIG_ACPI_CUSTOM_DSDT is not set CONFIG_ACPI_BLACKLIST_YEAR=0 # CONFIG_ACPI_DEBUG is not set # CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_SYSTEM=y CONFIG_X86_PM_TIMER=y CONFIG_ACPI_CONTAINER=y # CONFIG_ACPI_SBS is not set @@ -401,7 +434,6 @@ CONFIG_X86_SPEEDSTEP_SMI=y # # shared options # -# CONFIG_X86_ACPI_CPUFREQ_PROC_INTF is not set CONFIG_X86_SPEEDSTEP_LIB=y # CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK is not set CONFIG_CPU_IDLE=y @@ -421,16 +453,21 @@ CONFIG_PCI_BIOS=y CONFIG_PCI_DIRECT=y CONFIG_PCI_MMCONFIG=y CONFIG_PCI_DOMAINS=y +# CONFIG_DMAR is not set CONFIG_PCIEPORTBUS=y CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_PCIEAER=y +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIEAER_INJECT is not set CONFIG_PCIEASPM=y # CONFIG_PCIEASPM_DEBUG is not set CONFIG_ARCH_SUPPORTS_MSI=y CONFIG_PCI_MSI=y CONFIG_PCI_LEGACY=y # CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set CONFIG_HT_IRQ=y +# CONFIG_PCI_IOV is not set CONFIG_ISA_DMA_API=y CONFIG_ISA=y # CONFIG_EISA is not set @@ -488,9 +525,11 @@ CONFIG_UNIX=y CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set +CONFIG_XFRM_MIGRATE=y # CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y @@ -506,10 +545,10 @@ CONFIG_NET_IPIP=y # CONFIG_IP_MROUTE is not set # CONFIG_ARPD is not set CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=y CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m @@ -574,6 +613,8 @@ CONFIG_NETFILTER_XTABLES=y CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=y +CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_MARK=y CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y @@ -583,6 +624,7 @@ CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=y CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m @@ -593,6 +635,7 @@ CONFIG_NETFILTER_XT_MATCH_DSCP=m # CONFIG_NETFILTER_XT_MATCH_ESP is not set CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=y CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_LENGTH=y CONFIG_NETFILTER_XT_MATCH_LIMIT=y @@ -615,6 +658,7 @@ CONFIG_NETFILTER_XT_MATCH_STRING=y CONFIG_NETFILTER_XT_MATCH_TCPMSS=y # CONFIG_NETFILTER_XT_MATCH_TIME is not set CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_NETFILTER_XT_MATCH_OSF=m # CONFIG_IP_VS is not set # @@ -671,11 +715,11 @@ CONFIG_IP6_NF_MATCH_HL=y CONFIG_IP6_NF_MATCH_IPV6HEADER=y CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_TARGET_HL=y CONFIG_IP6_NF_TARGET_LOG=y CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_TARGET_HL=y CONFIG_IP6_NF_RAW=y # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set @@ -692,6 +736,8 @@ CONFIG_IP6_NF_RAW=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y # @@ -709,6 +755,7 @@ CONFIG_NET_SCHED=y # CONFIG_NET_SCH_GRED is not set # CONFIG_NET_SCH_DSMARK is not set # CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set # # Classification @@ -725,6 +772,7 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set # # Network testing @@ -755,34 +803,35 @@ CONFIG_BT_HCIBTUSB=m # CONFIG_BT_HCIBTUART is not set # CONFIG_BT_HCIVHCI is not set # CONFIG_AF_RXRPC is not set -# CONFIG_PHONET is not set CONFIG_WIRELESS=y CONFIG_CFG80211=m -CONFIG_NL80211=y +# CONFIG_CFG80211_REG_DEBUG is not set # CONFIG_WIRELESS_OLD_REGULATORY is not set CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set CONFIG_MAC80211=m +CONFIG_MAC80211_DEFAULT_PS=y +CONFIG_MAC80211_DEFAULT_PS_VALUE=1 # # Rate control algorithm selection # -CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT="pid" -CONFIG_MAC80211_MESH=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +CONFIG_WIMAX=y +CONFIG_WIMAX_DEBUG_LEVEL=8 CONFIG_RFKILL=y -CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y # CONFIG_NET_9P is not set # @@ -842,30 +891,22 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_MISC_DEVICES=y # CONFIG_IBM_ASM is not set # CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set -# CONFIG_ACER_WMI is not set -# CONFIG_ASUS_LAPTOP is not set -# CONFIG_FUJITSU_LAPTOP is not set -# CONFIG_TC1100_WMI is not set -# CONFIG_HP_WMI is not set # CONFIG_ICS932S401 is not set -# CONFIG_MSI_LAPTOP is not set -# CONFIG_PANASONIC_LAPTOP is not set -# CONFIG_COMPAL_LAPTOP is not set -# CONFIG_SONY_LAPTOP is not set -CONFIG_THINKPAD_ACPI=m -# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set -# CONFIG_THINKPAD_ACPI_DEBUG is not set -# CONFIG_THINKPAD_ACPI_BAY is not set -# CONFIG_THINKPAD_ACPI_VIDEO is not set -CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y -CONFIG_INTEL_MENLOW=m -# CONFIG_EEEPC_LAPTOP is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set # CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -889,10 +930,6 @@ CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -905,11 +942,13 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set # CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_ATA_ACPI=y @@ -985,7 +1024,11 @@ CONFIG_PATA_PCMCIA=m # # -# Enable only one of the two stacks, unless you know what you are doing +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set @@ -1009,7 +1052,7 @@ CONFIG_E1000=m CONFIG_E1000E=m # CONFIG_IP1000 is not set CONFIG_IGB=m -# CONFIG_IGB_LRO is not set +CONFIG_IGBVF=m # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -1020,9 +1063,11 @@ CONFIG_IGB=m # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set +# CONFIG_CNIC is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set # CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -1033,18 +1078,11 @@ CONFIG_IGB=m # CONFIG_WLAN_PRE80211 is not set CONFIG_WLAN_80211=y # CONFIG_PCMCIA_RAYCS is not set -# CONFIG_IPW2100 is not set -CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_RADIOTAP=y -CONFIG_IPW2200_PROMISCUOUS=y -CONFIG_IPW2200_QOS=y -# CONFIG_IPW2200_DEBUG is not set # CONFIG_LIBERTAS is not set # CONFIG_LIBERTAS_THINFIRM is not set # CONFIG_AIRO is not set -# CONFIG_HERMES is not set # CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set # CONFIG_AIRO_CS is not set # CONFIG_PCMCIA_WL3501 is not set # CONFIG_PRISM54 is not set @@ -1054,30 +1092,50 @@ CONFIG_IPW2200_QOS=y # CONFIG_RTL8187 is not set # CONFIG_ADM8211 is not set # CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set # CONFIG_P54_COMMON is not set +CONFIG_ATH_COMMON=m CONFIG_ATH5K=m # CONFIG_ATH5K_DEBUG is not set CONFIG_ATH9K=m +# CONFIG_ATH9K_DEBUG is not set +CONFIG_AR9170_USB=m +CONFIG_AR9170_LEDS=y +# CONFIG_IPW2100 is not set +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +# CONFIG_IPW2200_DEBUG is not set +CONFIG_LIBIPW=m +# CONFIG_LIBIPW_DEBUG is not set CONFIG_IWLWIFI=m -CONFIG_IWLCORE=m CONFIG_IWLWIFI_LEDS=y -CONFIG_IWLWIFI_RFKILL=y +CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT=y # CONFIG_IWLWIFI_DEBUG is not set CONFIG_IWLAGN=m -CONFIG_IWLAGN_SPECTRUM_MEASUREMENT=y -CONFIG_IWLAGN_LEDS=y CONFIG_IWL4965=y CONFIG_IWL5000=y CONFIG_IWL3945=m -CONFIG_IWL3945_RFKILL=y CONFIG_IWL3945_SPECTRUM_MEASUREMENT=y -CONFIG_IWL3945_LEDS=y -# CONFIG_IWL3945_DEBUG is not set # CONFIG_HOSTAP is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_ZD1211RW is not set # CONFIG_RT2X00 is not set +# CONFIG_HERMES is not set + +# +# WiMAX Wireless Broadband devices +# +CONFIG_WIMAX_I2400M=m + +# +# Enable MMC support to see WiMAX SDIO drivers +# +CONFIG_WIMAX_I2400M_USB=m +CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 # # USB Network Adapters @@ -1143,11 +1201,12 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y @@ -1164,6 +1223,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_LOGIBM is not set # CONFIG_MOUSE_PC110PAD is not set # CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -1233,6 +1293,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_CORE=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 CONFIG_PRINTER=y @@ -1264,10 +1325,11 @@ CONFIG_HPET_MMAP=y # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set CONFIG_DEVPORT=y -CONFIG_I2C=m +CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y # # I2C Hardware Bus support @@ -1322,19 +1384,20 @@ CONFIG_I2C_HELPER_AUTO=y # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set -# CONFIG_AT24 is not set -# CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set @@ -1342,7 +1405,9 @@ CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set # CONFIG_PDA_POWER is not set # CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set # CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_ABITUGURU is not set @@ -1358,8 +1423,10 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_K8TEMP is not set # CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ATK0110 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -1369,6 +1436,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_FSCHER is not set # CONFIG_SENSORS_FSCPOS is not set # CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_G760A is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set CONFIG_SENSORS_CORETEMP=y @@ -1384,10 +1452,14 @@ CONFIG_SENSORS_CORETEMP=y # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set @@ -1395,6 +1467,7 @@ CONFIG_SENSORS_CORETEMP=y # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set @@ -1426,45 +1499,103 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set # CONFIG_REGULATOR_FIXED_VOLTAGE is not set # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -# CONFIG_DAB is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support # # CONFIG_AGP is not set -# CONFIG_DRM is not set +CONFIG_DRM=m +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +CONFIG_DRM_RADEON=m +# CONFIG_DRM_MGA is not set +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set # CONFIG_VGASTATE is not set CONFIG_VIDEO_OUTPUT_CONTROL=y -# CONFIG_FB is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +CONFIG_FB_BACKLIGHT=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VESA is not set +# CONFIG_FB_N411 is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_MATROX is not set +CONFIG_FB_RADEON=y +CONFIG_FB_RADEON_I2C=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_GEODE is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_ILI9320 is not set CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_CORGI is not set +CONFIG_BACKLIGHT_GENERIC=y # CONFIG_BACKLIGHT_PROGEAR is not set # CONFIG_BACKLIGHT_MBP_NVIDIA is not set # CONFIG_BACKLIGHT_SAHARA is not set @@ -1472,7 +1603,11 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # # Display device support # -# CONFIG_DISPLAY_SUPPORT is not set +CONFIG_DISPLAY_SUPPORT=m + +# +# Display hardware drivers +# # # Console display driver support @@ -1481,11 +1616,23 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FB_CON_DECOR is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=y CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y -CONFIG_SND_TIMER=m +CONFIG_SND_TIMER=y CONFIG_SND_PCM=m +CONFIG_SND_JACK=y CONFIG_SND_SEQUENCER=m # CONFIG_SND_SEQ_DUMMY is not set CONFIG_SND_OSSEMUL=y @@ -1493,12 +1640,19 @@ CONFIG_SND_MIXER_OSS=m CONFIG_SND_PCM_OSS=m CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y # CONFIG_SND_DYNAMIC_MINORS is not set CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set CONFIG_SND_VMASTER=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set # CONFIG_SND_DRIVERS is not set # CONFIG_SND_ISA is not set CONFIG_SND_PCI=y @@ -1521,6 +1675,7 @@ CONFIG_SND_PCI=y # CONFIG_SND_CS46XX is not set # CONFIG_SND_CS5530 is not set # CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set # CONFIG_SND_DARLA20 is not set # CONFIG_SND_GINA20 is not set # CONFIG_SND_LAYLA20 is not set @@ -1533,6 +1688,8 @@ CONFIG_SND_PCI=y # CONFIG_SND_INDIGO is not set # CONFIG_SND_INDIGOIO is not set # CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set # CONFIG_SND_EMU10K1 is not set # CONFIG_SND_EMU10K1X is not set # CONFIG_SND_ENS1370 is not set @@ -1543,13 +1700,17 @@ CONFIG_SND_PCI=y CONFIG_SND_HDA_INTEL=m # CONFIG_SND_HDA_HWDEP is not set CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_JACK=y # CONFIG_SND_HDA_CODEC_REALTEK is not set CONFIG_SND_HDA_CODEC_ANALOG=y # CONFIG_SND_HDA_CODEC_SIGMATEL is not set # CONFIG_SND_HDA_CODEC_VIA is not set # CONFIG_SND_HDA_CODEC_ATIHDMI is not set # CONFIG_SND_HDA_CODEC_NVHDMI is not set +CONFIG_SND_HDA_CODEC_INTELHDMI=y +CONFIG_SND_HDA_ELD=y # CONFIG_SND_HDA_CODEC_CONEXANT is not set +# CONFIG_SND_HDA_CODEC_CA0110 is not set # CONFIG_SND_HDA_CODEC_CMEDIA is not set # CONFIG_SND_HDA_CODEC_SI3054 is not set # CONFIG_SND_HDA_GENERIC is not set @@ -1563,6 +1724,7 @@ CONFIG_SND_HDA_POWER_SAVE_DEFAULT=5 # CONFIG_SND_INTEL8X0 is not set # CONFIG_SND_INTEL8X0M is not set # CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set # CONFIG_SND_MAESTRO3 is not set # CONFIG_SND_MIXART is not set # CONFIG_SND_NM256 is not set @@ -1598,29 +1760,39 @@ CONFIG_USB_HIDDEV=y # # Special HID drivers # -# CONFIG_HID_COMPAT is not set CONFIG_HID_A4TECH=y CONFIG_HID_APPLE=y CONFIG_HID_BELKIN=y -CONFIG_HID_BRIGHT=y CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y CONFIG_HID_CYPRESS=y -CONFIG_HID_DELL=y +CONFIG_HID_DRAGONRISE=y +# CONFIG_DRAGONRISE_FF is not set CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y CONFIG_HID_GYRATION=y +CONFIG_HID_KENSINGTON=y CONFIG_HID_LOGITECH=y # CONFIG_LOGITECH_FF is not set # CONFIG_LOGIRUMBLEPAD2_FF is not set CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y CONFIG_HID_PANTHERLORD=y # CONFIG_PANTHERLORD_FF is not set CONFIG_HID_PETALYNX=y CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_SMARTJOYPLUS=y +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y # CONFIG_THRUSTMASTER_FF is not set +CONFIG_HID_WACOM=m +CONFIG_HID_ZEROPLUS=y # CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -1647,9 +1819,11 @@ CONFIG_USB_WUSB_CBAF=y # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_OHCI_HCD is not set @@ -1658,28 +1832,28 @@ CONFIG_USB_UHCI_HCD=m # CONFIG_USB_R8A66597_HCD is not set CONFIG_USB_WHCI_HCD=y # CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set # # USB Device Class drivers # -# CONFIG_USB_ACM is not set +CONFIG_USB_ACM=m CONFIG_USB_PRINTER=y CONFIG_USB_WDM=m # CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # -# see USB_STORAGE Help for more information +# also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set @@ -1709,7 +1883,7 @@ CONFIG_USB_SERIAL=m # CONFIG_USB_SERIAL_CH341 is not set # CONFIG_USB_SERIAL_WHITEHEAT is not set # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP2101 is not set +# CONFIG_USB_SERIAL_CP210X is not set # CONFIG_USB_SERIAL_CYPRESS_M8 is not set # CONFIG_USB_SERIAL_EMPEG is not set CONFIG_USB_SERIAL_FTDI_SIO=m @@ -1733,15 +1907,19 @@ CONFIG_USB_SERIAL_FTDI_SIO=m # CONFIG_USB_SERIAL_NAVMAN is not set # CONFIG_USB_SERIAL_PL2303 is not set # CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set # CONFIG_USB_SERIAL_SPCP8X5 is not set # CONFIG_USB_SERIAL_HP4X is not set # CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -1758,7 +1936,6 @@ CONFIG_USB_SERIAL_FTDI_SIO=m # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set @@ -1769,7 +1946,45 @@ CONFIG_USB_SERIAL_FTDI_SIO=m # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set -# CONFIG_USB_GADGET is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +CONFIG_USB_GADGET_M66592=y +CONFIG_USB_M66592=m +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=m + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set CONFIG_UWB=y # CONFIG_UWB_HWA is not set CONFIG_UWB_WHCI=y @@ -1782,10 +1997,12 @@ CONFIG_LEDS_CLASS=m # # LED drivers # +# CONFIG_LEDS_ALIX2 is not set # CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_HP_DISK is not set +# CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_CLEVO_MAIL is not set # CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set # # LED Triggers @@ -1795,6 +2012,10 @@ CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set # CONFIG_EDAC is not set @@ -1829,6 +2050,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers @@ -1860,7 +2082,34 @@ CONFIG_DMADEVICES=y # CONFIG_INTEL_IOATDMA is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set + +# +# TI VLYNQ +# # CONFIG_STAGING is not set +CONFIG_X86_PLATFORM_DEVICES=y +# CONFIG_ACER_WMI is not set +# CONFIG_ACERHDF is not set +# CONFIG_ASUS_LAPTOP is not set +# CONFIG_DELL_WMI is not set +# CONFIG_FUJITSU_LAPTOP is not set +# CONFIG_TC1100_WMI is not set +# CONFIG_HP_WMI is not set +# CONFIG_MSI_LAPTOP is not set +# CONFIG_PANASONIC_LAPTOP is not set +# CONFIG_COMPAL_LAPTOP is not set +# CONFIG_SONY_LAPTOP is not set +CONFIG_THINKPAD_ACPI=m +# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set +# CONFIG_THINKPAD_ACPI_DEBUG is not set +# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set +# CONFIG_THINKPAD_ACPI_VIDEO is not set +CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y +CONFIG_INTEL_MENLOW=m +# CONFIG_EEEPC_LAPTOP is not set +CONFIG_ACPI_WMI=y +# CONFIG_ACPI_ASUS is not set +# CONFIG_ACPI_TOSHIBA is not set # # Firmware Drivers @@ -1881,6 +2130,7 @@ CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT2_FS_XIP=y CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y @@ -1896,13 +2146,16 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y # CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1911,6 +2164,13 @@ CONFIG_QUOTACTL=y # CONFIG_AUTOFS_FS is not set CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set # # CD-ROM/DVD Filesystems @@ -1940,36 +2200,17 @@ CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set +CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLBFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set CONFIG_NFSD=y CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y @@ -1982,7 +2223,6 @@ CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=y @@ -2061,11 +2301,14 @@ CONFIG_UNUSED_SYMBOLS=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set CONFIG_TIMER_STATS=y # CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set CONFIG_DEBUG_PREEMPT=y # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set @@ -2086,6 +2329,8 @@ CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y # CONFIG_FRAME_POINTER is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set @@ -2095,40 +2340,38 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SYSPROF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_STACK_TRACER is not set +CONFIG_HAVE_FTRACE_SYSCALLS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set +CONFIG_HAVE_ARCH_KMEMCHECK=y +# CONFIG_KMEMCHECK is not set # CONFIG_STRICT_DEVMEM is not set # CONFIG_X86_VERBOSE_BOOTUP is not set CONFIG_EARLY_PRINTK=y # CONFIG_EARLY_PRINTK_DBGP is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set # CONFIG_X86_PTDUMP is not set # CONFIG_DEBUG_RODATA is not set # CONFIG_DEBUG_NX_TEST is not set # CONFIG_4KSTACKS is not set CONFIG_DOUBLEFAULT=y -# CONFIG_MMIOTRACE is not set +# CONFIG_IOMMU_STRESS is not set +CONFIG_HAVE_MMIOTRACE_SUPPORT=y CONFIG_IO_DELAY_TYPE_0X80=0 CONFIG_IO_DELAY_TYPE_0XED=1 CONFIG_IO_DELAY_TYPE_UDELAY=2 @@ -2148,6 +2391,7 @@ CONFIG_DEFAULT_IO_DELAY_TYPE=0 # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_IMA is not set CONFIG_CRYPTO=y # @@ -2156,18 +2400,21 @@ CONFIG_CRYPTO=y # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_GF128MUL=m -# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set # @@ -2191,7 +2438,7 @@ CONFIG_CRYPTO_PCBC=y # # Hash modes # -# CONFIG_CRYPTO_HMAC is not set +CONFIG_CRYPTO_HMAC=m CONFIG_CRYPTO_XCBC=y # @@ -2201,7 +2448,6 @@ CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32C_INTEL is not set CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_LZF=y CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set @@ -2239,7 +2485,8 @@ CONFIG_CRYPTO_TWOFISH_COMMON=y # # Compression # -# CONFIG_CRYPTO_DEFLATE is not set +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=y # @@ -2248,7 +2495,9 @@ CONFIG_CRYPTO_LZO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set CONFIG_HAVE_KVM=y +CONFIG_HAVE_KVM_IRQCHIP=y # CONFIG_VIRTUALIZATION is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines @@ -2256,6 +2505,7 @@ CONFIG_HAVE_KVM=y CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -2272,7 +2522,7 @@ CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=y CONFIG_TEXTSEARCH_BM=y CONFIG_TEXTSEARCH_FSM=y -CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.27-r2.ebuild b/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.27-r2.ebuild deleted file mode 100644 index 8f16d0d..0000000 --- a/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.27-r2.ebuild +++ /dev/null @@ -1,70 +0,0 @@ -# Copyright 1999-2009 Gentoo Foundation -# Distributed under the terms of the GNU General Public License v2 -# $Header: sys-kernel/thinkpad-sources/thinkpad-sources-2.6.27-r2.ebuild 2009 01 09 - -ETYPE="sources" -K_WANT_GENPATCHES="base extras" -K_GENPATCHES_VER="9" -inherit kernel-2 -detect_version -detect_arch - -KEYWORDS="~amd64 ~x86" -IUSE="" -HOMEPAGE="http://dev.gentoo.org/~dsd/genpatches http://www.tuxonice.net http://ibm-acpi.sourceforge.net/" - -DESCRIPTION="TuxOnIce + Gentoo patches + Latest THINKPAD-Acpi + PCI-E ASPM + Colored Printk + Libata Powermanagement + Bay Fixes + hdaps + phc + ipw2200 inject" - -TUXONICE_VERSION="3.0-rc8" -TUXONICE_TARGET="2.6.27" -TUXONICE_SRC="tuxonice-${TUXONICE_VERSION}-for-${TUXONICE_TARGET}" -TUXONICE_URI="http://www.tuxonice.net/downloads/all/${TUXONICE_SRC}.patch.bz2" - -THINKPAD_ACPI_VERSION="0.21-20081111" -THINKPAD_ACPI_TARGET="2.6.27.5" -THINKPAD_ACPI_SRC="thinkpad-acpi-${THINKPAD_ACPI_VERSION}_v${THINKPAD_ACPI_TARGET}.patch.gz" -THINKPAD_ACPI_URI="mirror://sourceforge/ibm-acpi/${THINKPAD_ACPI_SRC}" - - -UNIPATCH_LIST="" - -MY_PV="${PV}" -UNIPATCH_LIST="${UNIPATCH_LIST} - ${FILESDIR}/${MY_PV}/colored-printk-2.6.26.patch - ${FILESDIR}/${MY_PV}/01-disk-protect-for-2.6.27.2.patch - ${FILESDIR}/${MY_PV}/02-ipw2200-inject-for-2.6.27.patch - ${FILESDIR}/${MY_PV}/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch - ${DISTDIR}/${THINKPAD_ACPI_SRC} - ${DISTDIR}/${TUXONICE_SRC}.patch.bz2 - ${FILESDIR}/${MY_PV}/power-off-unused-ports.patch -" - - -UNIPATCH_STRICTORDER="yes" -SRC_URI="${KERNEL_URI} ${GENPATCHES_URI} ${ARCH_URI} ${TUXONICE_URI} ${THINKPAD_ACPI_URI} ${IEEE80211_URI} ${HRT_URI}" - - -RDEPEND="${RDEPEND} - >=sys-apps/tuxonice-userui-0.7.3 - >=sys-power/hibernate-script-1.99" - -pkg_postinst() { - kernel-2_pkg_postinst - einfo "For more info on this patchset, and how to report problems, see:" - einfo "${HOMEPAGE}" - einfo "AND send a mail to linux-thinkpad mailinglist," - einfo "so the patch could be retested and rerated" - einfo "In files dir is an example config suitable for T60" - einfo "and hopefully all pci-express driven Thinkpads" - einfo "but at all you should try for all Thinkpads" - einfo "to NOT alter the given storage device controller configuration" - einfo "for powersaving i recommend to append these kernel options:" - einfo "usbcore.autosuspend=1 pcie_aspm.policy=powersave" - einfo "additional powertweaks possible (depending on your hardware):" - einfo "snd_hda_intel.power_save=1" - einfo "echo 7 > /sys/bus/pci/drivers/iwl3945/0000\:03\:00.0/power_level" - einfo "echo min_power > /sys/class/scsi_host/host0/link_power_management_policy" - einfo "echo 5 >/proc/sys/vm/laptop_mode" - einfo "echo 1500 >/proc/sys/vm/dirty_writeback_centisecs" - einfo "echo 1 >/sys/devices/system/cpu/sched_mc_power_savings" -} diff --git a/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.28-r1.ebuild b/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.31-r1.ebuild index 6f67549..f20f127 100644 --- a/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.28-r1.ebuild +++ b/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.31-r1.ebuild @@ -1,27 +1,28 @@ # Copyright 1999-2009 Gentoo Foundation # Distributed under the terms of the GNU General Public License v2 -# $Header: sys-kernel/thinkpad-sources/thinkpad-sources-2.6.28-r1.ebuild 2009 01 09 +# $Header: sys-kernel/thinkpad-sources/thinkpad-sources-2.6.28-r2.ebuild 2009 01 19 ETYPE="sources" K_WANT_GENPATCHES="base extras" -K_GENPATCHES_VER="1" +K_GENPATCHES_VER="2" inherit kernel-2 detect_version detect_arch -KEYWORDS="~amd64 ~x86" +#KEYWORDS="~amd64 ~x86" +KEYWORDS="" IUSE="" HOMEPAGE="http://dev.gentoo.org/~dsd/genpatches http://www.tuxonice.net http://ibm-acpi.sourceforge.net/" DESCRIPTION="TuxOnIce + Gentoo patches + Latest THINKPAD-Acpi + PCI-E ASPM + Colored Printk + Libata Powermanagement + Bay Fixes + hdaps + phc + ipw2200 inject" -TUXONICE_VERSION="3.0-rc8" -TUXONICE_TARGET="2.6.28" -TUXONICE_SRC="tuxonice-${TUXONICE_VERSION}-for-${TUXONICE_TARGET}" -TUXONICE_URI="http://www.tuxonice.net/downloads/all/${TUXONICE_SRC}.patch.bz2" +TUXONICE_VERSION="20090911" +TUXONICE_TARGET="2.6.31" +TUXONICE_SRC="current-tuxonice-for-${TUXONICE_TARGET}.patch-${TUXONICE_VERSION}-v1.bz2" +TUXONICE_URI="http://www.tuxonice.net/downloads/all/${TUXONICE_SRC}" -THINKPAD_ACPI_VERSION="0.21-20081111" -THINKPAD_ACPI_TARGET="2.6.28-rc7" +THINKPAD_ACPI_VERSION="0.23-20090920" +THINKPAD_ACPI_TARGET="2.6.31" THINKPAD_ACPI_SRC="thinkpad-acpi-${THINKPAD_ACPI_VERSION}_v${THINKPAD_ACPI_TARGET}.patch.gz" THINKPAD_ACPI_URI="mirror://sourceforge/ibm-acpi/${THINKPAD_ACPI_SRC}" @@ -30,14 +31,15 @@ UNIPATCH_LIST="" MY_PV="${PV}" UNIPATCH_LIST="${UNIPATCH_LIST} - ${FILESDIR}/${MY_PV}/colored-printk-2.6.26.patch - ${FILESDIR}/${MY_PV}/01-mac80211_2.6.28-rc4-wl_frag+ack_v2.patch - ${FILESDIR}/${MY_PV}/02-ipw2200-inject-for-2.6.27.patch - ${FILESDIR}/${MY_PV}/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch + ${FILESDIR}/${MY_PV}/drm-next.patch + ${FILESDIR}/${MY_PV}/colored-printk-2.6.30.patch + ${FILESDIR}/${MY_PV}/linux-phc-0.3.2-2.6.31.patch ${DISTDIR}/${THINKPAD_ACPI_SRC} - ${DISTDIR}/${TUXONICE_SRC}.patch.bz2 - ${FILESDIR}/${MY_PV}/power-off-unused-ports.patch + ${FILESDIR}/${MY_PV}/thinkpad-acpi-0.23-20090920-fix1.patch.gz + ${DISTDIR}/${TUXONICE_SRC} " +# ${FILESDIR}/${MY_PV}/02-ipw2200-inject-for-2.6.27.patch +# ${FILESDIR}/${MY_PV}/mac80211.compat08082009.wl_frag+ack_v1.patch UNIPATCH_STRICTORDER="yes" @@ -46,7 +48,7 @@ SRC_URI="${KERNEL_URI} ${GENPATCHES_URI} ${ARCH_URI} ${TUXONICE_URI} ${THINKPAD_ RDEPEND="${RDEPEND} >=sys-apps/tuxonice-userui-0.7.3 - >=sys-power/hibernate-script-1.99" + >=sys-power/hibernate-script-1.99-r1" pkg_postinst() { kernel-2_pkg_postinst diff --git a/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.28-r2.ebuild b/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.31.ebuild index 87306c2..958ea38 100644 --- a/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.28-r2.ebuild +++ b/sys-kernel/thinkpad-sources/thinkpad-sources-2.6.31.ebuild @@ -15,14 +15,14 @@ HOMEPAGE="http://dev.gentoo.org/~dsd/genpatches http://www.tuxonice.net http://i DESCRIPTION="TuxOnIce + Gentoo patches + Latest THINKPAD-Acpi + PCI-E ASPM + Colored Printk + Libata Powermanagement + Bay Fixes + hdaps + phc + ipw2200 inject" -TUXONICE_VERSION="3.0-rc8" -TUXONICE_TARGET="2.6.28" -TUXONICE_SRC="tuxonice-${TUXONICE_VERSION}-for-${TUXONICE_TARGET}" -TUXONICE_URI="http://www.tuxonice.net/downloads/all/${TUXONICE_SRC}.patch.bz2" +TUXONICE_VERSION="20090911" +TUXONICE_TARGET="2.6.31" +TUXONICE_SRC="current-tuxonice-for-${TUXONICE_TARGET}.patch-${TUXONICE_VERSION}-v1.bz2" +TUXONICE_URI="http://www.tuxonice.net/downloads/all/${TUXONICE_SRC}" -THINKPAD_ACPI_VERSION="0.22" -THINKPAD_ACPI_TARGET="2.6.28" -THINKPAD_ACPI_SRC="thinkpad-acpi-${THINKPAD_ACPI_VERSION}_v${THINKPAD_ACPI_TARGET}.gz" +THINKPAD_ACPI_VERSION="0.23-20090920" +THINKPAD_ACPI_TARGET="2.6.31" +THINKPAD_ACPI_SRC="thinkpad-acpi-${THINKPAD_ACPI_VERSION}_v${THINKPAD_ACPI_TARGET}.patch.gz" THINKPAD_ACPI_URI="mirror://sourceforge/ibm-acpi/${THINKPAD_ACPI_SRC}" @@ -30,14 +30,14 @@ UNIPATCH_LIST="" MY_PV="${PV}" UNIPATCH_LIST="${UNIPATCH_LIST} - ${FILESDIR}/${MY_PV}/colored-printk-2.6.26.patch - ${FILESDIR}/${MY_PV}/01-mac80211_2.6.28-rc4-wl_frag+ack_v2.patch - ${FILESDIR}/${MY_PV}/02-ipw2200-inject-for-2.6.27.patch - ${FILESDIR}/${MY_PV}/linux-phc-0.3.2-kernel-vanilla-2.6.26.patch + ${FILESDIR}/${MY_PV}/colored-printk-2.6.30.patch + ${FILESDIR}/${MY_PV}/linux-phc-0.3.2-2.6.31.patch ${DISTDIR}/${THINKPAD_ACPI_SRC} - ${DISTDIR}/${TUXONICE_SRC}.patch.bz2 - ${FILESDIR}/${MY_PV}/power-off-unused-ports.patch + ${FILESDIR}/${MY_PV}/thinkpad-acpi-0.23-20090920-fix1.patch.gz + ${DISTDIR}/${TUXONICE_SRC} " +# ${FILESDIR}/${MY_PV}/02-ipw2200-inject-for-2.6.27.patch +# ${FILESDIR}/${MY_PV}/mac80211.compat08082009.wl_frag+ack_v1.patch UNIPATCH_STRICTORDER="yes" |