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| author |   Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:53:54 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:53:54 +0100 |
| commit | f11ad6bc0fc44b94c6970115bb6984b497b967e7 (patch) | |
| tree | c2b10c53bb44b45c5b34bdbc415e942caffbcfcf /opcodes/aarch64-tbl.h | |
| parent | [AArch64][SVE 20/32] Add support for tied operands (diff) | |
| download | binutils-gdb-f11ad6bc0fc44b94c6970115bb6984b497b967e7.tar.gz binutils-gdb-f11ad6bc0fc44b94c6970115bb6984b497b967e7.tar.bz2 binutils-gdb-f11ad6bc0fc44b94c6970115bb6984b497b967e7.zip | |
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 8f1c9b237d9..9dbe0c0ec5d 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2819,4 +2819,40 @@ struct aarch64_opcode aarch64_opcode_table[] = Y(SYSTEM, prfop, "PRFOP", 0, F(), \ "a prefetch operation specifier") \ Y (SYSTEM, hint, "BARRIER_PSB", 0, F (), \ - "the PSB option name CSYNC") + "the PSB option name CSYNC") \ + Y(PRED_REG, regno, "SVE_Pd", 0, F(FLD_SVE_Pd), \ + "an SVE predicate register") \ + Y(PRED_REG, regno, "SVE_Pg3", 0, F(FLD_SVE_Pg3), \ + "an SVE predicate register") \ + Y(PRED_REG, regno, "SVE_Pg4_5", 0, F(FLD_SVE_Pg4_5), \ + "an SVE predicate register") \ + Y(PRED_REG, regno, "SVE_Pg4_10", 0, F(FLD_SVE_Pg4_10), \ + "an SVE predicate register") \ + Y(PRED_REG, regno, "SVE_Pg4_16", 0, F(FLD_SVE_Pg4_16), \ + "an SVE predicate register") \ + Y(PRED_REG, regno, "SVE_Pm", 0, F(FLD_SVE_Pm), \ + "an SVE predicate register") \ + Y(PRED_REG, regno, "SVE_Pn", 0, F(FLD_SVE_Pn), \ + "an SVE predicate register") \ + Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \ + "an SVE predicate register") \ + Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \ + "an SVE vector register") \ + Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \ + "an SVE vector register") \ + Y(SVE_REG, regno, "SVE_Zd", 0, F(FLD_SVE_Zd), \ + "an SVE vector register") \ + Y(SVE_REG, regno, "SVE_Zm_5", 0, F(FLD_SVE_Zm_5), \ + "an SVE vector register") \ + Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \ + "an SVE vector register") \ + Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \ + "an SVE vector register") \ + Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \ + "an indexed SVE vector register") \ + Y(SVE_REG, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \ + "a list of SVE vector registers") \ + Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \ + "an SVE vector register") \ + Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ + "a list of SVE vector registers") |