Get Gentoo!
gentoo.org sites
gentoo.org Wiki Bugs Forums Packages
Planet Archives Sources
Infra Status
aboutsummaryrefslogtreecommitdiff
path: root/opcodes/aarch64-asm-2.c
Commit message (Expand)AuthorAgeFilesLines
* Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina2018-05-151-59/+60
* Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton2018-03-281-56/+57
* Add support for the AArch64's CSDB instruction.James Greenhalgh2018-01-091-105/+106
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2017-11-091-88/+94
* [AArch64] Additional SVE instructionsRichard Sandiford2017-02-241-72/+81
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2016-12-131-2/+2
* [AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy2016-11-181-506/+510
* [AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy2016-11-181-318/+318
* [AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy2016-11-181-306/+306
* [AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy2016-11-181-324/+326
* [AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy2016-11-111-406/+406
* [AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2016-11-111-399/+400
* [AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy2016-11-111-389/+389
* [AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy2016-11-111-127/+140
* [AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford2016-09-211-0/+119
* [AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2016-09-211-10/+16
* [AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2016-09-211-25/+32
* [AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2016-09-211-38/+62
* [AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2016-09-211-18/+27
* [AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2016-09-211-19/+57
* [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2016-09-211-6/+8
* [AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford2016-09-211-5/+7
* [AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford2016-09-211-0/+20
* [AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford2016-09-211-1/+2
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab2015-12-141-304/+304
* [AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab2015-12-141-316/+316
* [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab2015-12-141-304/+304
* [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab2015-12-141-344/+344
* [AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab2015-12-141-343/+343
* [AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab2015-12-141-308/+308
* [AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab2015-12-141-343/+343
* [AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab2015-12-141-308/+308
* [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab2015-12-141-332/+332
* [AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab2015-12-141-304/+304
* [AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab2015-12-141-328/+328
* [AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab2015-12-111-6/+9
* [AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab2015-12-101-6/+7
* [AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab2015-11-271-211/+211
* [AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab2015-11-271-255/+259
* [AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab2015-11-271-285/+286
* [AArch64] Let aliased instructions be their preferred form.Matthew Wahab2015-11-271-0/+95
* [AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab2015-06-021-190/+190
* [AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab2015-06-021-125/+125
* [AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang2015-03-101-161/+125
* ChangeLog rotatation and copyright year updateAlan Modra2015-01-021-1/+1
* [PATCH/AArch64] Implement LSE featureJiong Wang2014-09-031-51/+195
* Update copyright yearsAlan Modra2014-03-051-1/+1