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path: root/opcodes/i386-opc.tbl
Commit message (Expand)AuthorAgeFilesLines
* x86: fold MOV to/from segment register templatesJan Beulich2018-06-011-10/+4
* x86: don't emit REX.W for SLDT and STRJan Beulich2018-06-011-2/+2
* x86/Intel: accept "oword ptr" for INVPCIDJan Beulich2018-06-011-2/+2
* x86: Remove Disp<N> from movidir{i,64b}H.J. Lu2018-05-091-3/+3
* Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu2018-05-071-0/+9
* x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu2018-05-071-10/+10
* Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist2018-04-271-10/+0
* Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist2018-04-261-0/+10
* x86: fold various non-memory operand AVX512VL templatesJan Beulich2018-04-261-228/+148
* x86: drop VexImmExtJan Beulich2018-04-261-70/+70
* x86: drop redundant AVX512VL shift templatesJan Beulich2018-04-251-6/+0
* Enable Intel CLDEMOTE instruction.Igor Tsimbalist2018-04-171-0/+6
* x86: Allow 32-bit registers for tpause and umwaitH.J. Lu2018-04-151-4/+2
* Enable Intel WAITPKG instructions.Igor Tsimbalist2018-04-111-0/+13
* x86: drop VecESizeJan Beulich2018-03-281-543/+543
* x86: convert broadcast insn attribute to booleanJan Beulich2018-03-281-1085/+1085
* x86: fold to-scalar-int conversion insnsJan Beulich2018-03-281-43/+21
* x86: drop pointless VecESizeJan Beulich2018-03-221-477/+477
* x86: drop remaining redundant DispNJan Beulich2018-03-221-75/+75
* x86: fix swapped operand handling for BNDMOVJan Beulich2018-03-221-2/+2
* x86/Intel: fix fallout from earlier template foldingJan Beulich2018-03-221-10/+15
* x86: fold a few XOP templatesJan Beulich2018-03-221-16/+8
* x86-64: Also optimize "clr reg64"H.J. Lu2018-03-081-1/+1
* x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu2018-03-081-8/+0
* x86: fold several AVX512VL templatesJan Beulich2018-03-081-185/+90
* x86: fold certain AVX512 rotate and shift templatesJan Beulich2018-03-081-84/+45
* x86: fold VEX-encoded GFNI templatesJan Beulich2018-03-081-8/+3
* x86: fold a few AVX512F templatesJan Beulich2018-03-081-24/+12
* x86: fold LWP templatesJan Beulich2018-03-081-8/+4
* x86: fold FMA and FMA4 templatesJan Beulich2018-03-081-120/+60
* x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich2018-03-081-1/+1
* x86: drop bogus NoAVXJan Beulich2018-03-081-7/+7
* x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich2018-03-081-2/+2
* x86: drop FloatDJan Beulich2018-03-081-10/+10
* x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich2018-03-081-2/+2
* x86: fold AVX vcvtpd2ps memory formsJan Beulich2018-03-081-2/+1
* x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu2018-03-011-12/+12
* x86: Add -O[2|s] assembler command-line optionsH.J. Lu2018-02-271-32/+33
* x86: Add {rex} pseudo prefixH.J. Lu2018-02-221-0/+1
* Enable Intel PCONFIG instruction.Igor Tsimbalist2018-01-231-0/+6
* Enable Intel WBNOINVD instruction.Igor Tsimbalist2018-01-231-0/+6
* Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist2018-01-171-15/+15
* Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist2018-01-111-12/+0
* x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich2018-01-101-2/+2
* x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich2018-01-101-48/+48
* x86: Properly encode vmovd with 64-bit memeoryH.J. Lu2018-01-081-4/+2
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* x86: fold certain AVX and AVX2 templatesJan Beulich2017-12-181-328/+164
* x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich2017-12-181-7/+7
* x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich2017-12-181-21/+42