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gentoo/binutils-2.43
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path:
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/
opcodes
/
riscv-opc.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.
Jim Wilson
2019-11-12
1
-60
/
+60
*
RISC-V: Gate opcode tables by enum rather than string.
Jim Wilson
2019-09-17
1
-658
/
+658
*
RISC-V: Fix minor issues with FP csr instructions.
Jim Wilson
2019-07-30
1
-16
/
+16
*
Kito's 5-part patch set to improve .insn support.
Jim Wilson
2019-07-05
1
-4
/
+26
*
RISC-V: Compress 3-operand beq/bne against x0.
Jim Wilson
2019-02-08
1
-0
/
+2
*
Update year range in copyright notice of binutils files
Alan Modra
2019-01-01
1
-1
/
+1
*
RISC-V: Fix 4-arg add parsing.
Jim Wilson
2018-12-07
1
-1
/
+1
*
RISC-V: Add missing c.unimp instruction.
Jim Wilson
2018-11-29
1
-1
/
+2
*
RISC-V: Add .insn CA support.
Jim Wilson
2018-11-27
1
-2
/
+7
*
RISC-V: Add fence.tso instruction
Palmer Dabbelt
2018-10-02
1
-0
/
+1
*
RISC-V: bge[u] should get higher priority than ble[u].
Jim Wilson
2018-09-17
1
-2
/
+2
*
RISC-V: Correct the requirement of compressed floating point instructions
Jim Wilson
2018-08-31
1
-16
/
+16
*
RISC-V: Allow instruction require more than one extension
Jim Wilson
2018-08-30
1
-629
/
+629
*
RISC-V: Set insn info fields correctly when disassembling.
Jim Wilson
2018-07-30
1
-178
/
+178
*
RISC-V: Accept constant operands in la and lla
Sebastian Huber
2018-06-20
1
-2
/
+2
*
RISC-V: Add missing hint instructions from RV128I.
Jim Wilson
2018-05-08
1
-9
/
+45
*
RISC-V: Add .insn support.
Jim Wilson
2018-03-14
1
-0
/
+74
*
RISC-V: Fix bug in prior addi/c.nop patch.
Jim Wilson
2018-01-17
1
-1
/
+1
*
RISC-V: Add support for addi that compresses to c.nop.
Jim Wilson
2018-01-15
1
-0
/
+8
*
Update year range in copyright notice of binutils files
Alan Modra
2018-01-03
1
-1
/
+1
*
RISC-V: Add compressed instruction hints, and a few misc cleanups.
Jim Wilson
2017-12-20
1
-13
/
+35
*
Add missing RISC-V fsrmi and fsflagsi instructions.
Jim Wilson
2017-12-13
1
-0
/
+4
*
RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0
Andrew Waterman
2017-10-24
1
-7
/
+23
*
Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...
Nick Clifton
2017-09-27
1
-0
/
+5
*
RISC-V: Mark "c.nop" as an alias
Palmer Dabbelt
2017-08-22
1
-1
/
+1
*
RISC-V: Fix SLTI disassembly
Andrew Waterman
2017-06-23
1
-2
/
+2
*
RISC-V: Change CALL macro to use ra as the temporary address register
Michael Clark
2017-05-02
1
-1
/
+1
*
RISC-V: Fix assembler for c.li, c.andi and c.addiw
Kito Cheng
2017-03-15
1
-3
/
+3
*
RISC-V: Fix assembler for c.addi, rd can be x0
Kito Cheng
2017-03-15
1
-1
/
+1
*
RISC-V: Fix [dis]assembly of srai/srli
Andrew Waterman
2017-03-14
1
-4
/
+4
*
Add SFENCE.VMA instruction
Andrew Waterman
2017-02-15
1
-0
/
+3
*
Add support for the Q extension to the RISCV ISA.
Kito Cheng
2017-01-03
1
-0
/
+60
*
Update year range in copyright notice of all files.
Alan Modra
2017-01-02
1
-1
/
+1
*
Avoid creating symbol table entries for registers
Andrew Waterman
2016-12-22
1
-2
/
+2
*
Correct assembler mnemonic for RISC-V aqrl AMOs
Andrew Waterman
2016-12-20
1
-22
/
+22
*
Fix disassembly of RISC-V CSR instructions under -Mno-aliases
Andrew Waterman
2016-12-20
1
-22
/
+22
*
Add canonical JALR for RISC-V
Andrew Waterman
2016-12-20
1
-0
/
+3
*
Formatting changes for RISC-V
Andrew Waterman
2016-12-20
1
-8
/
+6
*
Add support for RISC-V architecture.
Nick Clifton
2016-11-01
1
-0
/
+624