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| author |   Zhuojia Shen <chaosdefinition@hotmail.com> | 2021-01-26 14:00:58 -0800 |
|---|---|---|
| committer | Zhuojia Shen <chaosdefinition@hotmail.com> | 2021-01-26 14:00:58 -0800 |
| commit | 8cef45517e47af7c81dd6504fa52ce98e21a6208 (patch) | |
| tree | dd346c7c8f2da5d83705e3925ed507361b40f4db /llvm/lib/Target/ARM/ARMInstrThumb2.td | |
| parent | [NewPM] Add ExtraVectorizerPasses support (diff) | |
| download | llvm-project-8cef45517e47af7c81dd6504fa52ce98e21a6208.tar.gz llvm-project-8cef45517e47af7c81dd6504fa52ce98e21a6208.tar.bz2 llvm-project-8cef45517e47af7c81dd6504fa52ce98e21a6208.zip | |
[ARM] Fix STRT/STRHT/STRBT input/output operands.
STRT, STRHT, and STRBT are store instructions and their source register
$Rt should be treated as an input operand instead of an output operand.
This should fix things (e.g., liveness tracking in LivePhysRegs) if
these instructions were used in CodeGen.
Differential Revision: https://reviews.llvm.org/D95074
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrThumb2.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index f83807d27f88..5642cab32e7c 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -1724,7 +1724,7 @@ def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), // only. // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 class T2IstT<bits<2> type, string opc, InstrItinClass ii> - : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, + : T2Ii8<(outs), (ins rGPR:$Rt, t2addrmode_imm8:$addr), ii, opc, "\t$Rt, $addr", []>, Sched<[WriteST]> { let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; |