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path: root/llvm/lib/Target/ARM/ARMInstrThumb2.td
Commit message (Expand)AuthorAgeFilesLines
* [MC][ARM] add .w suffixes for RSB/RSBS T1Nick Desaulniers2021-04-011-2/+9
* [MC][ARM] add .w suffixes for ORN/ORNS T1Nick Desaulniers2021-04-011-0/+6
* [ARM] Move t2DoLoopStart reg alloc hintDavid Green2021-03-111-1/+0
* [ARM] Improve WLS loweringDavid Green2021-03-111-2/+34
* [ARM] Use 0, not ZR during ISel for CSINC/INV/NEGDavid Green2021-03-021-6/+15
* [MC][ARM] add .w suffixes for BL (T1) and DBGNick Desaulniers2021-02-241-0/+3
* [THUMB2] add .w suffixes for ldr/str (immediate) T4Nick Desaulniers2021-02-231-0/+17
* [Thumb2] support `movs pc, lr` alias for `subs pc, lr, #0`/`eret`Nick Desaulniers2021-02-101-6/+12
* [ARM] Fix STRT/STRHT/STRBT input/output operands.Zhuojia Shen2021-01-261-1/+1
* [ARM] Implement harden-sls-retbr for Thumb modeKristof Beyls2020-12-191-0/+9
* [ARM] Make t2DoLoopStartTP a terminatorDavid Green2020-12-111-0/+1
* [ARM][RegAlloc] Add t2LoopEndDecDavid Green2020-12-101-0/+4
* [ARM] Introduce t2DoLoopStartTPDavid Green2020-11-101-0/+3
* [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LRDavid Green2020-11-101-0/+1
* [ARM] Alter t2DoLoopStart to define lrDavid Green2020-11-101-2/+6
* [ARM] Removed hasSideEffects from signed/unsigned saturatesMeera Nakrani2020-10-011-1/+0
* [ARM] Added more patterns to generate SSAT/USAT with shiftMeera Nakrani2020-09-281-2/+10
* [ARM] Generated SSAT and USAT instructions with shiftMeera Nakrani2020-08-041-0/+9
* [ARM] CSEL generationDavid Green2020-07-161-0/+1
* [ARM] Mark more integer instructions as not having side effects.David Green2020-06-231-4/+8
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2020-05-281-3/+6
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2020-05-221-6/+3
* [llvm] NFC: Fix trivial typo in rst and td filesKazuaki Ishizaki2020-04-231-2/+2
* [ARM] Fix qdadd operand orderDavid Green2020-03-311-2/+2
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2020-03-111-3/+6
* [ARM][Thumb2] support .w assembler qualifier for dmb/dsb/isbStefan Agner2020-02-281-0/+6
* [ARM][Thumb2] Support .w assembler qualifier for pld/pldw/pliStefan Agner2020-02-281-8/+46
* Revert "[ARM] Add CPSR as an implicit use of t2IT"Sam Parker2020-02-271-1/+1
* [ARM] Add CPSR as an implicit use of t2ITSam Parker2020-02-271-1/+1
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2020-02-081-6/+3
* [ARM] Correct syntax of the CLRM insnMomchil Velikov2020-02-051-1/+1
* [ARM][MVE] Tail Predicate IsSafeToRemoveSam Parker2020-01-171-0/+1
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-141-39/+154
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-101-154/+39
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-101-39/+154
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2020-01-071-3/+6
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2019-12-201-6/+3
* [ARM][MVE] Fixes for tail predication.Sam Parker2019-12-201-4/+6
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2019-12-191-3/+6
* [ARM] Generate CMSE instructions from CMSE intrinsicsMomchil Velikov2019-11-251-4/+12
* [ARM] Extra qdadd patternsDavid Green2019-10-211-0/+4
* [ARM] Add qadd lowering from a sadd_satDavid Green2019-10-211-0/+4
* [ARM] Lower sadd_sat to qadd8 and qadd16David Green2019-10-211-0/+9
* [ARM] Cortex-M4 schedule additionsDavid Green2019-09-291-1/+2
* [ARM] Ensure we do not attempt to create lsll #0David Green2019-09-251-1/+2
* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-24/+24
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-24/+24
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-24/+24
* [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.David Green2019-09-031-0/+19
* [ARM] Reject CSEL instructions with invalid operandsMikhail Maltsev2019-07-311-1/+1