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| author |   Monk Chiang <monk.chiang@sifive.com> | 2020-12-17 13:45:52 +0800 |
|---|---|---|
| committer |   Hsiangkai Wang <kai.wang@sifive.com> | 2020-12-18 10:24:24 +0800 |
| commit | ee2cb90e3bbe5cc6d027b1f821458eb267da516f (patch) | |
| tree | 6be951aba416e882e39f9e9c7b561aaa3bb707a8 /llvm/lib/Target/RISCV/RISCVRegisterInfo.td | |
| parent | [DAGCombiner] Improve shift by select of constant (diff) | |
| download | llvm-project-ee2cb90e3bbe5cc6d027b1f821458eb267da516f.tar.gz llvm-project-ee2cb90e3bbe5cc6d027b1f821458eb267da516f.tar.bz2 llvm-project-ee2cb90e3bbe5cc6d027b1f821458eb267da516f.zip | |
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.
We work with @rogfer01 from BSC to come out this patch.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Co-Authored-by: Monk Chiang <monk.chiang@sifive.com>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D93366
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVRegisterInfo.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index a9575f6cd42c..b87658fea59a 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -379,6 +379,7 @@ let RegAltNameIndices = [ABIRegAltName] in { def VTYPE : RISCVReg<0, "vtype", ["vtype"]>; def VL : RISCVReg<0, "vl", ["vl"]>; + def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>; } class RegisterTypes<list<ValueType> reg_types> { |