Get Gentoo!
gentoo.org sites
gentoo.org Wiki Bugs Forums Packages
Planet Archives Sources
Infra Status
aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Support inline asm for vector instructions.Hsiangkai Wang2021-03-151-8/+15
* [RISCV] Use XLenRI alias for RegInfoByHwMode instancesJessica Clarke2021-02-181-21/+10
* [RISCV] Fix bugs in pseudo instructions for masked segment load.Hsiangkai Wang2021-02-181-11/+24
* Support a list of CostPerUse valuesChristudasan Devadasan2021-01-291-2/+2
* [RISCV] Correct DWARF number for vector registers.Hsiangkai Wang2021-01-221-1/+1
* [RISCV] Implement vlseg intrinsics.Hsiangkai Wang2021-01-201-9/+92
* [RISCV] Correct alignment settings for vector registers.Hsiangkai Wang2021-01-161-3/+2
* [NFC][RISCV] Remove useless code in RISCVRegisterInfo.td.Hsiangkai Wang2021-01-151-4/+0
* [RISCV] Define the remaining vector fixed-point arithmetic intrinsics.Monk Chiang2020-12-201-0/+1
* [RISCV] Remove NoVReg to avoid compile warning messages.Hsiangkai Wang2020-12-181-3/+0
* [RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.Monk Chiang2020-12-181-0/+1
* [RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.Hsiangkai Wang2020-12-151-0/+3
* [RISCV][NFC] Define scalable vectors for half types.Hsiangkai Wang2020-12-151-6/+15
* [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.Hsiangkai Wang2020-12-151-0/+13
* [RISCV] Initial infrastructure for code generation of the RISC-V V-extensionCraig Topper2020-12-041-37/+108
* [RISCV] Support Zfh half-precision floating-point extension.Hsiangkai Wang2020-12-031-35/+57
* [RISCV] Remove unused VM register classCraig Topper2020-11-231-7/+0
* [RISCV] Put RV32 before RV64 in the ValueTypeByHwMode and RegInfoByHwMode lis...Craig Topper2020-11-201-16/+16
* [RISCV] Remove RV32 HwMode. Use DefaultMode for RV32Craig Topper2020-11-201-16/+16
* [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.Hsiangkai Wang2020-10-021-1/+10
* [RISCV] Assemble/Disassemble v-ext instructions.Hsiangkai Wang2020-06-281-0/+99
* [RISCV] Rename FPRs and use Register arithmeticLuis Marques2019-09-271-47/+47
* [RISCV] Add support for RVC HINT instructionsLuis Marques2019-08-211-0/+6
* [RISCV] Allow fp as an alias of s0Alex Bradbury2019-03-111-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-0/+13
* [RISCV] Set CostPerUse for registersSameer AbuAsal2018-05-231-0/+11
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-131-0/+23
* [RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury2017-12-071-0/+30
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-071-0/+27
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+52
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-4/+9
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-191-68/+47
* [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.tdAlex Bradbury2016-11-011-0/+90