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path: root/llvm/lib/CodeGen/MachineCSE.cpp
Commit message (Expand)AuthorAgeFilesLines
* [CodeGen] Use llvm::append_range (NFC)Kazu Hirata2021-01-211-4/+2
* [NFC] Use [MC]Register in CSE & LICMGaurav Jain2020-10-281-17/+17
* MachineCSE.cpp - use auto const& iterators in for-range loops to avoid copies...Simon Pilgrim2020-09-261-2/+2
* MachineCSE.cpp - use auto const& iterator in for-range loop to avoid copies. ...Simon Pilgrim2020-09-211-2/+2
* DomTree: Remove getChildren() accessorNicolai Hähnle2020-07-061-5/+3
* [MachineCSE] Don't carry the wrong location when hoistingDavide Italiano2020-04-061-0/+7
* Sink all InitializePasses.h includesReid Kleckner2019-11-131-0/+1
* [DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locationsJeremy Morse2019-09-021-3/+5
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-9/+9
* [MachineCSE][NFC] Use 'profitable' rather than 'beneficial' to name method.Kai Luo2019-08-071-8/+8
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-13/+11
* [MachineCSE][MachinePRE] Avoid hoisting code from code regions into hot BBs.Kai Luo2019-07-191-0/+25
* [MIR] Skip hoisting to basic block which may throw exception or returnAnton Afanasyev2019-06-121-0/+2
* [MIR] Add simple PRE pass to MachineCSEAnton Afanasyev2019-06-091-9/+118
* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-051-1/+1
* Revert r361356: "[MIR] Add simple PRE pass to MachineCSE"David L. Jones2019-05-271-113/+9
* [MIR] Add simple PRE pass to MachineCSEAnton Afanasyev2019-05-221-9/+113
* Revert "[MIR] Add simple PRE pass to MachineCSE"Anton Afanasyev2019-05-031-117/+9
* [MIR] Add simple PRE pass to MachineCSEAnton Afanasyev2019-05-031-9/+117
* [Codegen] Remove dead flags on Physical Defs in machine cseDavid Green2019-02-201-19/+24
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)Roman Tereshin2018-10-201-1/+16
* [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal.Carlos Alberto Enciso2018-10-011-6/+2
* [DWARF] Missing location debug information with -O2.Carlos Alberto Enciso2018-08-301-0/+8
* [MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs()Roman Tereshin2018-06-121-2/+1
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-8/+9
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-2/+2
* [MachineCSE] Rewrite a loop checking if a block is in a set of blocks without...Michael Zolotukhin2018-05-041-7/+5
* GlobalISel: Make MachineCSE runnable in the middle of the GlobalISelJustin Bogner2018-01-181-7/+6
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-4/+4
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-5/+5
* [MachineCSE] Add new callback for is caller preserved or constant physregsTony Jiang2017-11-201-2/+2
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-3/+3
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko2017-08-241-11/+36
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* CodeGen: Rename DEBUG_TYPE to match passnamesMatthias Braun2017-05-251-4/+4
* MachineCSE: Respect interblock physreg livenessMikael Holmen2017-05-241-2/+2
* [codegen] Add generic functions to skip debug values.Florian Hahn2016-12-161-2/+1
* MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFCMatthias Braun2016-10-281-1/+1
* [CodeGen] Rename MachineInstr::isInvariantLoad to isDereferenceableInvariantL...Justin Lebar2016-09-101-1/+1
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-4/+3
* Re-commit optimization bisect support (r267022) without new pass manager supp...Andrew Kaylor2016-04-221-1/+1
* Revert "Initial implementation of optimization bisect support."Vedant Kumar2016-04-221-1/+1
* Initial implementation of optimization bisect support.Andrew Kaylor2016-04-211-1/+1
* [SSP, 2/2] Create llvm.stackguard() intrinsic and lower it to LOAD_STACK_GUARDTim Shen2016-04-191-0/+6
* rangify; NFCISanjay Patel2016-01-061-24/+14
* [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatibleChandler Carruth2015-09-091-3/+3
* MachineCSE: Add a target query for the LookAheadLimit heurisiticTom Stellard2015-05-091-2/+3