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path: root/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
Commit message (Expand)AuthorAgeFilesLines
* [AMDGPU] Don't check for VMEM hazards on GFX10Jay Foad2021-03-041-9/+9
* [AMDGPU] gfx90a supportStanislav Mekhanoshin2021-02-171-4/+423
* [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargetsdfukalov2021-01-201-1/+2
* [AMDGPU] Add _e64 suffix to VOP3 InstsJoe Nash2021-01-121-17/+17
* [NFC][AMDGPU] Reduce include files dependency.dfukalov2021-01-071-16/+1
* [AMDGPU] Rename pseudo S_WAITCNT_IDLE to S_WAIT_IDLE. NFC.Jay Foad2020-11-181-1/+1
* [NFC] Use Register/MCRegisterMircea Trofin2020-11-041-3/+3
* [AMDGPU] Use pseudo instructions for readlane/writelaneJay Foad2020-10-291-1/+0
* [AMDGPU] Simplify insertNoops functions. NFC.Jay Foad2020-10-291-7/+3
* [AMDGPU] Add Reset function to GCNHazardRecognizerAustin Kerbow2020-10-281-0/+4
* [AMDGPU] Fix inserting combined s_nop in bundlesAustin Kerbow2020-10-281-6/+15
* [AMDGPU] Avoid inserting noops during schedulingAustin Kerbow2020-10-201-18/+26
* [AMDGPU] Fix mai hazard VALU to LD/STAustin Kerbow2020-10-081-5/+6
* [AMDGPU] Enable scheduling around FP MODE-setting instructionsJay Foad2020-09-161-1/+8
* AMDGPU: Skip all meta instructions in hazard recognizerMatt Arsenault2020-09-091-1/+1
* [AMDGPU] Fix MAI ld/st hazard handlingStanislav Mekhanoshin2020-08-141-2/+6
* [AMDGPU] Fixed formatting in GCNHazardRecognizer.cpp. NFC.Stanislav Mekhanoshin2020-07-291-2/+3
* [AMDGPU] prefer non-mfma in post-RA scheduleStanislav Mekhanoshin2020-07-291-0/+24
* [AMDGPU] Removed s_mov_regrd and mov_fed opcodesDmitry Preobrazhensky2020-07-171-32/+1
* [AMDGPU] Update VMEM scalar write hazard mitigation sequenceCarl Ritson2020-07-161-3/+7
* [AMDGPU] Don't implement GCNHazardRecognizer::PreEmitNoops(SUnit *)Jay Foad2020-05-061-5/+0
* [AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizerJay Foad2020-05-051-1/+9
* Make more use of MachineInstr::mayLoadOrStore.Jay Foad2019-12-191-2/+2
* AMDGPU: Fix SMEM WAR hazard for gfx10 readlaneAustin Kerbow2019-10-181-0/+1
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-10/+10
* AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXECNicolai Haehnle2019-07-171-1/+1
* [AMDGPU] gfx908 hazard recognizerStanislav Mekhanoshin2019-07-111-1/+228
* [AMDGPU] hazard recognizer for fp atomic to s_denorm_modeStanislav Mekhanoshin2019-06-211-0/+41
* AMDGPU: Consolidate some getGeneration checksMatt Arsenault2019-06-191-5/+4
* [AMDGPU] gfx1010 premlane instructionsStanislav Mekhanoshin2019-06-121-0/+44
* [AMDGPU] gfx1010 Avoid SMEM WAR hazard for some s_waitcnt valuesCarl Ritson2019-05-201-6/+22
* [AMDGPU] Check MI bundles for hazardsAustin Kerbow2019-05-071-11/+56
* [AMDGPU] Fixed asan error after D61536Stanislav Mekhanoshin2019-05-041-1/+1
* AMDGPU] gfx1010 hazard recognizerStanislav Mekhanoshin2019-05-041-3/+262
* AMDGPU: Remove unnecessary subtarget getMatt Arsenault2019-04-031-1/+0
* [AMDGPU] Omit KILL instructions from hazard recognizerDavid Stuttard2019-03-051-3/+2
* [AMDGPU] Fixed hazard recognizer to walk predecessorsStanislav Mekhanoshin2019-01-211-25/+113
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Add llvm.amdgcn.ds.ordered.add & swapMarek Olsak2019-01-161-4/+18
* [AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer...Carl Ritson2018-09-101-2/+9
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-4/+4
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-1/+1
* [AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecogn...Mark Searles2017-12-071-17/+60
* AMDGPU: Move hazard avoidance out of waitcnt pass.Matt Arsenault2017-11-171-37/+54
* AMDGPU: Replace list of SMEM buffer opcodesMatt Arsenault2017-11-171-10/+1
* AMDGPU: Fix breaking SMEM clausesMatt Arsenault2017-11-171-25/+29
* AMDGPU: Handle s_buffer_load_dword hazard on SIMarek Olsak2017-10-261-0/+27
* AMDGPU: Make worst-case assumption about the wait states in inline assemblyNicolai Haehnle2017-09-061-1/+2
* AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait statesNicolai Haehnle2017-09-011-4/+9