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path: root/llvm/utils/TableGen/InstrInfoEmitter.cpp
Commit message (Expand)AuthorAgeFilesLines
* [M68k][TableGen](1/8) TableGen related changesMin-Yih Hsu2021-03-081-0/+191
* [llvm] Drop unnecessary make_range (NFC)Kazu Hirata2021-01-091-1/+1
* [MCInstrDesc] [TableGen] Reduce size of MCOperandInfo instances.Paul C. Anagnostopoulos2020-12-221-3/+2
* [TableGen] Slim down the data structures in xxxGenInstrInfo.inc, step 1Paul C. Anagnostopoulos2020-12-161-4/+14
* [TableGen] Cache the vectors of records returned by getAllDerivedDefinitions().Paul C. Anagnostopoulos2020-12-091-0/+10
* [TableGen] Indentation and whitespace fixes in generated code. NFC.Jay Foad2020-11-061-2/+2
* TableGen: Don't reconstruct CodeGenDAGTargetMatt Arsenault2020-05-231-1/+1
* [MC] Move deprecation infos from MCTargetDesc to MCInstrInfoBenjamin Kramer2020-03-291-20/+75
* Make llvm::StringRef to std::string conversions explicit.Benjamin Kramer2020-01-281-3/+3
* [tablegen] Emit string literals instead of char arraysLuke Drummond2020-01-271-3/+2
* Revert "[tablegen] Emit string literals instead of char arrays"Sergej Jaskiewicz2020-01-231-1/+1
* [tablegen] Emit string literals instead of char arraysLuke Drummond2020-01-231-1/+1
* [AArch64] Add isAuthenticated predicate to MCInstDescVedant Kumar2020-01-101-0/+1
* [ms] [X86] Use "P" modifier on all branch-target operands in inline X86 assem...Eric Astor2020-01-091-0/+5
* GlobalISel: Add target pre-isel instructionsMatt Arsenault2019-10-071-0/+1
* [TableGen] Emit OperandType enums for RegisterOperands/RegisterClassesAditya Nandakumar2019-09-231-7/+18
* [TableGen] Correct comments for end of namespace. NFCBjorn Pettersson2019-08-251-13/+13
* [TableGen] Generate offsets into a flat array for getOperandTypeJustin Bogner2019-07-161-25/+38
* [TableGen] Add "getOperandType" to get operand types from opcode/opidxJustin Bogner2019-07-161-4/+57
* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-051-0/+1
* [tablegen] Add locations to many PrintFatalError() callsDaniel Sanders2019-02-121-2/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [TableGen] Improve the formatting of the emitted predicates (NFC)Evandro Menezes2018-12-041-8/+7
* [TableGen] Fix typo in emitted comment (NFC)Evandro Menezes2018-12-041-1/+1
* [ARM][MC] Move information about variadic register defs into tablegenOliver Stannard2018-12-031-0/+1
* [TableGen] Refactor macro names (NFC)Evandro Menezes2018-11-271-10/+10
* [tblgen][PredicateExpander] Add the ability to describe more complex constrai...Andrea Di Biagio2018-10-311-5/+25
* [WebAssembly] Add isEHScopeReturn instruction propertyHeejin Ahn2018-08-211-0/+1
* [Tablegen][MCInstPredicate] Removed redundant template argument from class TI...Andrea Di Biagio2018-08-141-11/+10
* [Tablegen] Replace uses of formatted_raw_ostream with raw_ostream in the pred...Andrea Di Biagio2018-08-131-26/+29
* [MC][PredicateExpander] Extend the grammar to support simple switch and retur...Andrea Di Biagio2018-08-091-6/+4
* [cfi-verify] Support AArch64.Joel Galenson2018-07-131-0/+1
* [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling cla...Andrea Di Biagio2018-05-251-0/+55
* [RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.Andrea Di Biagio2018-05-251-3/+32
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-231-0/+1
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-3/+6
* [Targets] Don't automatically include the scheduler class enum from *GenInstr...Craig Topper2017-12-131-1/+9
* [TableGen] Use StringRef instead of std::string for CodeGenInstruction namesp...Craig Topper2017-07-071-6/+6
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What Yo...Eugene Zelenko2016-12-121-10/+14
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-1/+2
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-0/+1
* Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2016-09-131-1/+0
* This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2016-09-131-0/+1
* XRay: Add entry and exit sledsDean Michael Berris2016-07-141-3/+3
* [TableGen] Use range-based for loop. NFCCraig Topper2016-02-161-2/+2
* [TableGen] Don't call emitSourceFileHeader a second time in the middle of the...Craig Topper2016-02-111-3/+1
* [TableGen] Whitespace cleanup in output file. NFCCraig Topper2016-02-111-14/+14
* [TableGen] Simplify code slightly. NFCCraig Topper2016-02-111-6/+3
* [TableGen] Store result of getInstructionsByEnumValue in an ArrayRef instead ...Craig Topper2016-02-011-6/+6
* [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ...Craig Topper2016-01-171-2/+2