diff options
| author |   fijal <unknown> | 2021-03-01 14:23:45 +0200 |
|---|---|---|
| committer | fijal <unknown> | 2021-03-01 14:23:45 +0200 |
| commit | c56a590e68e1c3aee07627c58908da7344edc3b7 (patch) | |
| tree | b97465a5845284a23e72a0bdbea76014fa0090e1 | |
| parent | seems sometimes we have mc sometimes we dont (diff) | |
| download | pypy-c56a590e68e1c3aee07627c58908da7344edc3b7.tar.gz pypy-c56a590e68e1c3aee07627c58908da7344edc3b7.tar.bz2 pypy-c56a590e68e1c3aee07627c58908da7344edc3b7.zip | |
use the real way to do it
| -rw-r--r-- | rpython/jit/backend/aarch64/assembler.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py index 1c973a8af3..0212d6dd7d 100644 --- a/rpython/jit/backend/aarch64/assembler.py +++ b/rpython/jit/backend/aarch64/assembler.py @@ -1122,7 +1122,7 @@ class AssemblerARM64(ResOpAssembler): # stack->value = my sp self.mc.STR_ri(r.sp.value, r.sp.value, WORD) # stack->kind = VMPROF_JITTED_TAG - self.mc.MOV_ri(r.ip0.value, VMPROF_JITTED_TAG) + self.mc.gen_load_int(r.ip0.value, VMPROF_JITTED_TAG) self.mc.STR_ri(r.ip0.value, r.sp.value, WORD * 2) # save in vmprof_tl_stack the new eax self.mc.STR_ri(r.sp.value, tloc.value, offset) |