Fix compilation with gcc-4.3 by Devils-Hawk <dev AT stuffit DOT at>; bug #206076

Package-Manager: portage-2.1.5_rc7

4 files changed, 192 insertions, 7 deletions

diff --git a/sci-electronics/iverilog/ChangeLog b/sci-electronics/iverilog/ChangeLog
index 196953c0ca30..4269365869fd 100644
--- a/sci-electronics/iverilog/ChangeLog
+++ b/sci-electronics/iverilog/ChangeLog
@@ -1,6 +1,11 @@
 # ChangeLog for sci-electronics/iverilog
-# Copyright 2002-2007 Gentoo Foundation; Distributed under the GPL v2
-# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/ChangeLog,v 1.20 2007/11/30 09:11:22 calchan Exp $
+# Copyright 2002-2008 Gentoo Foundation; Distributed under the GPL v2
+# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/ChangeLog,v 1.21 2008/05/07 01:49:12 halcy0n Exp $
+
+  07 May 2008; Mark Loeser <halcy0n@gentoo.org> +files/iverilog-gcc43.patch,
+  iverilog-0.8.6.ebuild:
+  Fix compilation with gcc-4.3 by Devils-Hawk <dev AT stuffit DOT at>; bug
+  #206076
 
 *iverilog-0.8.6 (30 Nov 2007)
 
diff --git a/sci-electronics/iverilog/Manifest b/sci-electronics/iverilog/Manifest
index 1aabf443b1d1..43de155f761d 100644
--- a/sci-electronics/iverilog/Manifest
+++ b/sci-electronics/iverilog/Manifest
@@ -1,4 +1,5 @@
 AUX iverilog-0.8.2-gcc-4.10.patch 520 RMD160 0c5a5add0bce6e1d28ddd3bb08b62357dedd4258 SHA1 36856aa13041ed1d7d0e62a29b206eada1eedb2f SHA256 73765dbafbb7b0f46e2ce66424bb138569f47862279921e426edb75f16dd22fd
+AUX iverilog-gcc43.patch 5851 RMD160 7b62580712893d0997ee7f5170d9bd514a5182ea SHA1 4edcd74164c45f321ab74677a375034e06b03b45 SHA256 b64aa2030dc8b7cc9dffbe4d78bfb918e89164d95b221dba429acc6af2df38d8
 DIST verilog-0.8.2.tar.gz 1526676 RMD160 4e233941068d3a38f6036700614a21404e7287d4 SHA1 ab6966cf85976160c2f6974b7836336271044f71 SHA256 c0df02855d547b0b73d3c020f4cc884319fde8f449ab216abcb685639ff69f08
 DIST verilog-0.8.3.tar.gz 1568131 RMD160 b45c7b9811f99ad833e6bf8e5508a72472b7b8f7 SHA1 c3fd64bcdc51d44bde1fd5e168cdff761057c798 SHA256 799a20a193ba34d74a14128f1f4494714619a035adad967283dc51c7b994079d
 DIST verilog-0.8.4.tar.gz 1531959 RMD160 de305cab49a4ffd6eaab876f8c06a19085f7a311 SHA1 0f16dec7d7970c8a2e4d0b9208bcf486f5d8f7b7 SHA256 f20839c806ce566f1e74f0707f5bb38be04539a6e800f07f0baabea7e48a6c21
@@ -6,6 +7,6 @@ DIST verilog-0.8.6.tar.gz 1537422 RMD160 11ebb11ff99cb23aff481ddcd274eb50d117ee8
 EBUILD iverilog-0.8.2.ebuild 1043 RMD160 7b157e4ab48e80dc64cc408978d46dd1e4c8e1d3 SHA1 63e2d49ffc9110d9e149efc946d4d98352ccc3eb SHA256 d1b4141016aeb4512208f3e7fec5248e428de2b18600e2154ce83854145b5afb
 EBUILD iverilog-0.8.3.ebuild 1175 RMD160 b15d1961932134341ac0160eb91dc35f6fecd308 SHA1 6877541aab864c9306b232e79eeec1e57498a374 SHA256 aabbf9911e6ad611ed5d0c91c5eb5388876dc6288e743d05e1bc3b2089b363bf
 EBUILD iverilog-0.8.4.ebuild 1188 RMD160 2f9b83f8c0b9635a8b31018f46132cfcf7b960fe SHA1 bd94bc5834d664d87b500629bec01565011ab630 SHA256 c27f4ee14444d28f54a3dce2e29317066ec3f80fbe8982af8b8c8beb9fef4c2b
-EBUILD iverilog-0.8.6.ebuild 1015 RMD160 123cd64167259040ffc2b37c24d571ec6c91fc7e SHA1 9ccb9475135e5748b309d3aaf5ae08670599d659 SHA256 9977539778a1f01d406c5d6e8c2e4adc6983a7246a83fbc22d5a645d6c88bb56
-MISC ChangeLog 4329 RMD160 aa1e839e3ac541e699ac4ed7be11e6c595e92eab SHA1 9704fa2be634c225daadb87c0b946b9977fa49c2 SHA256 014785e9f35c4dbbf5e2f85774b3833305c657a46ed900924dfe521f3c696d1b
+EBUILD iverilog-0.8.6.ebuild 1066 RMD160 7df2c6fab1e9bbe0a72e4a8107acf30b557f9555 SHA1 f78a4904b13249623ae96d9049ca86d7eb1b4d6a SHA256 c165537daf79bf7f1007ef8abde02f394baf3116e0e6c1f33ef5759bd518893c
+MISC ChangeLog 4517 RMD160 6b3e8c5b84f711fa5490b40dca00e2276fec7be5 SHA1 b99c9dedbb3d200eeaefd69d49feccc0c665b59e SHA256 71698635ad87c66b3a1e756e86b0149a51bbb3876036e186c6a9bc1bdff1af7d
 MISC metadata.xml 506 RMD160 48a23b4bf81a7ab0c7e00ed9c3f4e264dc6e4b78 SHA1 bedb493b0943f337c3e2e4af267ee00b56fdf1de SHA256 d1f9a885eabf83550648f0a80a1302bcdd56b36d3d0572f0a91fb5bd9ade0b84
diff --git a/sci-electronics/iverilog/files/iverilog-gcc43.patch b/sci-electronics/iverilog/files/iverilog-gcc43.patch
new file mode 100644
index 000000000000..960ba01c8dc2
--- /dev/null
+++ b/sci-electronics/iverilog/files/iverilog-gcc43.patch
@@ -0,0 +1,177 @@
+diff -rup verilog-0.8.6/elab_net.cc verilog-0.8.6-devel/elab_net.cc
+--- verilog-0.8.6/elab_net.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/elab_net.cc	2008-01-16 12:02:42.000000000 +0100
+@@ -28,6 +28,7 @@
+ # include  "compiler.h"
+ 
+ # include  <iostream>
++# include  <cstring>
+ 
+ /*
+  * This is a state flag that determines whether an elaborate_net must
+diff -rup verilog-0.8.6/elab_scope.cc verilog-0.8.6-devel/elab_scope.cc
+--- verilog-0.8.6/elab_scope.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/elab_scope.cc	2008-01-16 12:03:34.000000000 +0100
+@@ -24,6 +24,7 @@
+ # include  "compiler.h"
+ # include  <iostream>
+ # include  <stdio.h>
++# include  <cstring>
+ 
+ /*
+  * Elaboration happens in two passes, generally. The first scans the
+diff -rup verilog-0.8.6/elab_sig.cc verilog-0.8.6-devel/elab_sig.cc
+--- verilog-0.8.6/elab_sig.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/elab_sig.cc	2008-01-16 12:04:05.000000000 +0100
+@@ -23,6 +23,7 @@
+ # include "config.h"
+ 
+ # include  <iostream>
++# include  <cstdlib>
+ 
+ # include  "Module.h"
+ # include  "PExpr.h"
+diff -rup verilog-0.8.6/emit.cc verilog-0.8.6-devel/emit.cc
+--- verilog-0.8.6/emit.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/emit.cc	2008-01-16 12:04:40.000000000 +0100
+@@ -32,6 +32,7 @@
+ # include  "netlist.h"
+ # include  <typeinfo>
+ # include  <cassert>
++# include  <cstring>
+ 
+ bool NetNode::emit_node(struct target_t*tgt) const
+ {
+diff -rup verilog-0.8.6/load_module.cc verilog-0.8.6-devel/load_module.cc
+--- verilog-0.8.6/load_module.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/load_module.cc	2008-01-16 12:05:21.000000000 +0100
+@@ -31,6 +31,8 @@
+ # include  <dirent.h>
+ # include  <ctype.h>
+ # include  <assert.h>
++# include  <cstdlib>
++# include  <cstring>
+ 
+ /*
+  * The module library items are maps of key names to file name within
+diff -rup verilog-0.8.6/net_design.cc verilog-0.8.6-devel/net_design.cc
+--- verilog-0.8.6/net_design.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/net_design.cc	2008-01-16 12:05:46.000000000 +0100
+@@ -33,6 +33,7 @@
+ # include  "util.h"
+ # include  "compiler.h"
+ # include  <sstream>
++# include  <cstring>
+ 
+ Design:: Design()
+ : errors(0), nodes_(0), procs_(0), lcounter_(0)
+diff -rup verilog-0.8.6/net_link.cc verilog-0.8.6-devel/net_link.cc
+--- verilog-0.8.6/net_link.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/net_link.cc	2008-01-16 12:06:28.000000000 +0100
+@@ -27,6 +27,7 @@
+ # include  "netlist.h"
+ # include  <sstream>
+ # include  <string>
++# include  <cstring>
+ # include  <typeinfo>
+ #ifdef HAVE_MALLOC_H
+ # include  <malloc.h>
+diff -rup verilog-0.8.6/net_scope.cc verilog-0.8.6-devel/net_scope.cc
+--- verilog-0.8.6/net_scope.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/net_scope.cc	2008-01-16 12:06:56.000000000 +0100
+@@ -25,6 +25,7 @@
+ 
+ # include  "netlist.h"
+ # include  <sstream>
++# include  <cstring>
+ 
+ /*
+  * The NetScope class keeps a scope tree organized. Each node of the
+diff -rup verilog-0.8.6/pform.h verilog-0.8.6-devel/pform.h
+--- verilog-0.8.6/pform.h	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/pform.h	2008-01-16 11:58:59.000000000 +0100
+@@ -37,6 +37,8 @@
+ # include  <string>
+ # include  <list>
+ # include  <stdio.h>
++# include  <cstring>
++# include  <cstdlib>
+ 
+ /*
+  * These classes implement the parsed form (P-form for short) of the
+diff -rup verilog-0.8.6/synth2.cc verilog-0.8.6-devel/synth2.cc
+--- verilog-0.8.6/synth2.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/synth2.cc	2008-01-16 12:11:00.000000000 +0100
+@@ -28,6 +28,7 @@
+ #include <cassert>
+ #include "NetLatch.h"
+ #include <climits>
++#include <cstdlib>
+ 
+ #include <new> // standard operator new
+ using std::bad_alloc;
+diff -rup verilog-0.8.6/sys_funcs.cc verilog-0.8.6-devel/sys_funcs.cc
+--- verilog-0.8.6/sys_funcs.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/sys_funcs.cc	2008-01-16 12:07:31.000000000 +0100
+@@ -23,6 +23,8 @@
+ # include  "config.h"
+ # include  "compiler.h"
+ # include  <stdio.h>
++# include  <cstdlib>
++# include  <cstring>
+ 
+ /*
+  * Manage the information about system functions. This information is
+diff -rup verilog-0.8.6/t-dll.cc verilog-0.8.6-devel/t-dll.cc
+--- verilog-0.8.6/t-dll.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/t-dll.cc	2008-01-16 12:11:25.000000000 +0100
+@@ -31,7 +31,8 @@
+ #ifdef HAVE_MALLOC_H
+ # include  <malloc.h>
+ #endif
+-# include  <stdlib.h>
++# include  <cstdlib>
++# include  <cstring>
+ 
+ #include <new> // standard operator new
+ using std::bad_alloc;
+diff -rup verilog-0.8.6/t-dll-expr.cc verilog-0.8.6-devel/t-dll-expr.cc
+--- verilog-0.8.6/t-dll-expr.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/t-dll-expr.cc	2008-01-16 12:11:54.000000000 +0100
+@@ -30,7 +30,8 @@
+ #ifdef HAVE_MALLOC_H
+ # include  <malloc.h>
+ #endif
+-# include  <stdlib.h>
++# include  <cstdlib>
++# include  <cstring>
+ 
+ /*
+  * This is a little convenience function for converting a NetExpr
+diff -rup verilog-0.8.6/t-dll-proc.cc verilog-0.8.6-devel/t-dll-proc.cc
+--- verilog-0.8.6/t-dll-proc.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/t-dll-proc.cc	2008-01-16 12:12:29.000000000 +0100
+@@ -32,7 +32,8 @@
+ #ifdef HAVE_MALLOC_H
+ # include  <malloc.h>
+ #endif
+-# include  <stdlib.h>
++# include  <cstdlib>
++# include  <cstring>
+ 
+ 
+ bool dll_target::process(const NetProcTop*net)
+diff -rup verilog-0.8.6/verireal.cc verilog-0.8.6-devel/verireal.cc
+--- verilog-0.8.6/verireal.cc	2007-11-26 19:55:13.000000000 +0100
++++ verilog-0.8.6-devel/verireal.cc	2008-01-16 12:07:58.000000000 +0100
+@@ -24,7 +24,8 @@
+ 
+ # include  "verireal.h"
+ # include  "verinum.h"
+-# include  <stdlib.h>
++# include  <cstdlib>
++# include  <cstring>
+ # include  <ctype.h>
+ # include  <iostream>
+ # include  <math.h>
+
diff --git a/sci-electronics/iverilog/iverilog-0.8.6.ebuild b/sci-electronics/iverilog/iverilog-0.8.6.ebuild
index 7736bc3429c5..0fb491fe36ae 100644
--- a/sci-electronics/iverilog/iverilog-0.8.6.ebuild
+++ b/sci-electronics/iverilog/iverilog-0.8.6.ebuild
@@ -1,8 +1,8 @@
-# Copyright 1999-2007 Gentoo Foundation
+# Copyright 1999-2008 Gentoo Foundation
 # Distributed under the terms of the GNU General Public License v2
-# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/iverilog-0.8.6.ebuild,v 1.1 2007/11/30 09:11:22 calchan Exp $
+# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/iverilog-0.8.6.ebuild,v 1.2 2008/05/07 01:49:12 halcy0n Exp $
 
-inherit multilib
+inherit eutils multilib
 
 S="${WORKDIR}/verilog-${PV}"
 
@@ -22,6 +22,8 @@ src_unpack() {
 	unpack ${A}
 	cd "${S}"
 
+	epatch "${FILESDIR}"/iverilog-gcc43.patch
+
 	# Fix for bug #172919
 	sed -i -e '/#  include <asm\/page.h>/d' vvp/main.cc || die "sed failed"
 }