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path: root/opcodes/aarch64-tbl.h
Commit message (Expand)AuthorAgeFilesLines
* Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu2018-06-081-2/+16
* Fix disassembly mask for vector sdot on AArch64.Tamar Christina2018-05-161-2/+2
* Implement Read/Write constraints on system registers on AArch64Tamar Christina2018-05-151-3/+3
* Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina2018-04-251-2/+2
* Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton2018-03-281-0/+26
* Add support for the AArch64's CSDB instruction.James Greenhalgh2018-01-091-0/+1
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* Correct disassembly of dot product instructions.Tamar Christina2017-12-191-2/+2
* Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2017-11-161-2/+2
* Correct AArch64 crypto dependencies.Tamar Christina2017-11-161-4/+6
* Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina2017-11-161-1/+60
* Add the operand encoding types for the new Armv8.2-a back-ported instructions...Tamar Christina2017-11-091-0/+90
* Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2017-11-091-2/+10
* Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina2017-11-091-0/+27
* Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton2017-11-081-17/+28
* [AArch64] Add dot product support for AArch64 to binutilsTamar Christina2017-06-281-0/+24
* Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L...Nick Clifton2017-04-211-8/+8
* [AArch64] Additional SVE instructionsRichard Sandiford2017-02-241-96/+230
* [AArch64] Add a "compnum" featureRichard Sandiford2017-02-241-6/+8
* [AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy2017-01-041-3/+8
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2016-12-131-6/+6
* [AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy2016-11-181-0/+30
* [AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy2016-11-181-0/+3
* [AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy2016-11-181-0/+10
* [AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy2016-11-181-0/+11
* [AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy2016-11-111-0/+12
* [AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2016-11-111-0/+3
* [AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy2016-11-111-0/+18
* [AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy2016-11-111-0/+18
* [AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang2016-09-301-4/+4
* [AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford2016-09-211-0/+1269
* [AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2016-09-211-0/+8
* [AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2016-09-211-0/+8
* [AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2016-09-211-0/+39
* [AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2016-09-211-0/+18
* [AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2016-09-211-1/+88
* [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2016-09-211-0/+2
* [AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford2016-09-211-0/+4
* [AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford2016-09-211-1/+37
* [AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford2016-09-211-16/+16
* [AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford2016-09-211-1/+1
* [AArch64] Add V8_2_INSN macroRichard Sandiford2016-08-231-2/+4
* [AArch64] Make more use of CORE/FP/SIMD_INSNRichard Sandiford2016-08-231-67/+67
* [AArch64] Add OP parameter to aarch64-tbl.h macrosRichard Sandiford2016-08-231-722/+722
* Fix generation of AArhc64 instruction table.Szabolcs Nagy2016-05-031-2/+6
* Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton2016-04-281-1332/+1191
* Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.Nick Clifton2016-03-181-1/+1
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab2015-12-141-0/+14